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United States Patent7251759
Turner , ; et al.July 31, 2007
Title
Method and apparatus to compare pointers associated with asynchronous clock domains
Abstract
A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are not synchronized. One or more guard bits can be associated with the single-bit write pointer and/or the single-bit read pointer. The single-bit write pointer and the single-bit read pointer can be compared. According to an embodiment, an error can be detected in response to comparing the single-bit write pointer and the single-bit read pointer.
Inventors:Turner; Tony (Foothill Ranch, CA), Lupienski; John  (Phoenix, AZ)
Assignee:Broadcom Corporation (Irvine, CA)
Appl. No.:10/918,408
Filed:August 16, 2004
PCT Pub Date:July 31, 2007
Current U.S. Class:714/719 714/718 
Current International Class:G11C 29/18 (20060101) G11C 29/14 (20060101)
Field of Search:714/719,718,25,48,715,3
U.S. Patent Documents
20020194401December 2002Sakugawa
4959836September 1990Berard et al.
6161160December 2000Niu et al.
6173386January 2001Key et al.
6225933May 2001Salter et al.
6243728June 2001Farooqui et al.
6987953January 2006Morris et al.
Primary Examiner: Lamarre; Guy
Assistant Examiner: Gandhi; Dipakkumar
Attorney, Agent or Firm:Sterne, Kessler, Goldstein & Fox PLLC
Claims

What is claimed is:
1. A method, comprising: converting a multi-bit write pointer that is associated with a first clock to a single-bit write pointer represented by a first plurality of bits, each bit of the first plurality of bits corresponding to a respective address, wherein converting the multi-bit write pointer includes setting a bit of the first plurality of bits that corresponds to an address specified by the multi-bit write pointer; converting a multi-bit read pointer that is associated with a second clock not synchronized with the first clock to a single-bit read pointer represented by a second plurality of bits, each bit of the second plurality of bits corresponding to a respective address, wherein converting the multi-bit read pointer includes setting a bit of the second plurality of bits that corresponds to an address specified by the multi-bit read pointer; and comparing the single-bit write pointer and the single-bit read pointer to determine whether a read error occurs.

2. The method of claim 1, wherein comparing the single-bit write pointer and the single-bit read pointer includes comparing the single-bit write pointer and the single-bit read pointer using a bitwise logical AND operation.

3. The method of claim 1, wherein comparing the single-bit write pointer and the single-bit read pointer includes comparing the single-bit write pointer and the single-bit read pointer using a bitwise logical AND operation to provide a plurality of bits, and the method further comprises comparing the plurality of bits using a logical OR operation.

4. The method of claim 1, wherein at least one of the first plurality of bits and the second plurality of bits includes a guard bit.

5. The method of claim 1, wherein comparing the single-bit write pointer and the single-bit read pointer includes comparing a write address of the single-bit write pointer and a read address of the single-bit read pointer.

6. The method of claim 5, wherein converting the multi-bit write pointer includes converting the multi-bit write pointer having an address that is represented using a binary notation to the single-bit write pointer having the write address that is represented using a linear progression notation.

7. The method of claim 5, wherein converting the multi-bit read pointer includes converting the multi-bit read pointer having an address that is represented using a binary notation to the single-bit read pointer having the read address that is represented using a linear progression notation.

8. A method, comprising: representing a multi-bit write pointer that is associated with a first clock using a single bit of a first plurality of bits, each bit of the first plurality of bits being relevant to representing the multi-bit write pointer; representing a multi-bit read pointer that is associated with a second clock not synchronized with the first clock using a single bit of a second plurality of bits, each bit of the second plurality of bits being relevant to representing the multi-bit read pointer; and bitwise comparing the first plurality of bits and the second plurality of bits to determine whether a read error occurs.

9. The method of claim 8, wherein bitwise comparing the first plurality of bits and the second plurality of bits includes bitwise comparing the first plurality of bits and the second plurality of bits using a logical AND operation.

10. The method of claim 8, wherein bitwise comparing the first plurality of bits and the second plurality of bits includes bitwise comparing the first plurality of bits and the second plurality of bits using a logical AND operation to provide a third plurality of bits.

11. The method of claim 10, further comprising individually comparing the third plurality of bits using a logical OR operation.

12. The method of claim 8, wherein at least one of the first plurality of bits and the second plurality of bits includes a guard bit.

13. The method of claim 8, further comprising determining that a read error occurs, based on the single bit of the first plurality of bits or a guard bit of the first plurality of bits having a bit address that is the same as a bit address of the single bit of the second plurality of bits or a guard bit of the second plurality of bits.

14. An apparatus, comprising: means for converting a multi-bit write pointer that is associated with a first clock to a single-bit write pointer represented by a first plurality of bits. each bit of the first plurality of bits corresponding to a respective address, wherein converting the multi-bit write pointer includes setting a bit of the first plurality of bits that corresponds to an address specified by the multi-bit write pointer means for converting a multi-bit read pointer that is associated with a second clock not synchronized with the first clock to a single-bit read pointer represented by a second plurality of bits, each bit of the second plurality of bits corresponding to a respective address, wherein converting the multi-bit read pointer includes setting a bit of the second plurality of bits that corresponds to an address specified by the multi-bit read pointer; and means for comparing the single-bit write pointer and the single-bit read pointer to determine whether a read error occurs.

15. The apparatus of claim 14, wherein the means for comparing the single-bit write pointer and the single-bit read pointer compare the single-bit write pointer and the single-bit read pointer using a bitwise logical AND operation.

16. The apparatus of claim 14, wherein the means for comparing the single-bit write pointer and the single-bit read pointer compare the single-bit write pointer and the single-bit read pointer using a bitwise logical AND operation to provide a plurality of bits, and the apparatus further comprises means for comparing the plurality of bits using a logical OR operation.

17. The apparatus of claim 14, wherein at least one of the first plurality of bits and the second plurality of bits includes a guard bit.

18. The apparatus of claim 14, wherein the means for comparing the single-bit write pointer and the single-bit read pointer compare a write address of the single-bit write pointer and a read address of the single-bit read pointer.

19. The apparatus of claim 18, wherein the means for converting the multi-bit write pointer convert the multi-bit write pointer having an address that is represented using a binary notation to the single-bit write pointer having the write address that is represented using a linear progression notation.

20. The apparatus of claim 18, wherein the means for converting the multi-bit read pointer convert the multi-bit read pointer having an address that is represented using a binary notation to the single-bit read pointer having the read address that is represented using a linear progression notation.

21. An apparatus, comprising: means for representing a multi-bit write pointer that is associated with a first clock using a single bit of a first plurality of bits, each bit of the first plurality of bits being relevant to representing the multi-bit write pointer; means for representing a multi-bit read pointer that is associated with a second clock not synchronized with the first clock using a single bit of a second plurality of bits, each bit of the second plurality of bits being relevant to representing the multi-bit read pointer; and means for bitwise comparing the first plurality of bits and the second plurality of bits to determine whether a read error occurs.

22. The apparatus of claim 21, wherein the means for bitwise comparing the first plurality of bits and the second plurality of bits bitwise compare the first plurality of bits and the second plurality of bits using a logical AND operation.

23. The apparatus of claim 21, wherein the means for bitwise comparing the first plurality of bits and the second plurality of bits bitwise compare the first plurality of bits and the second plurality of bits using a logical AND operation to provide a third plurality of bits, and the apparatus further comprises means for comparing the third plurality of bits using a logical OR operation.

24. The apparatus of claim 21, wherein at least one of the first plurality of bits and the second plurality of bits includes a guard bit.

25. The apparatus of claim 21, further comprising means for determining that a read error occurs, based on the single bit of the first plurality of bits or a guard bit of the first plurality of bits having a bit address that is the same as a bit address of the single bit of the second plurality of bits or a guard bit of the second plurality of bits.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to asynchronous clock technology, and more specifically to pointers associated with asynchronous clock domains.

2. Background

An electronic device generally performs operations based on a clock. The clock is often generated internally by the device, though the clock can be based on an external clock, such as a clock of another device. Clocks of different devices can be synchronized or unsynchronized. Unsynchronized clocks are known as "asynchronous clocks". Asynchronous clocks need not operate at different frequencies. For instance, the phase of one clock can differ from the phase of another clock having the same frequency.

Information is often temporarily stored in a memory, such as a register, when being transferred between devices having asynchronous clocks. A first device can write the information to the register, and a second device can read the information from the register. The first device uses a write pointer to specify the address of the register at which the information is to be written. The second device uses a read pointer to specify the address of the register at which the information is to be read. The addresses of the register are typically multi-bit addresses.

The address of the write pointer and the address of the read pointer are often compared to determine whether the read pointer is properly aligned to read the information written by the first device. Comparing the multiple-bit pointers typically requires multiple clock cycles. However, at high frequencies, the addresses of the pointers can change at every clock cycle. The pointers can become unstable because the addresses of the pointers cannot be accurately determined.

What is needed is a method and apparatus to compare pointers associated with asynchronous clock domains.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a method and apparatus to compare pointers associated with asynchronous clock domains. A multi-bit write pointer is associated with a first clock. A multi-bit read pointer is associated with a second clock that is not synchronized with the first clock. A first bit can represent the multi-bit write pointer. A second bit can represent the multi-bit read pointer. A first plurality of bits can include the first bit. A second plurality of bits can include the second bit. The first plurality of bits and/or the second plurality of bits can include one or more guard bits. The first plurality of bits and the second plurality of bits can be compared. According to an embodiment, an error can be detected in response to comparing the first plurality of bits and the second plurality of bits.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left most digit(s) of a reference number identifies the drawing in which the reference number first appears.

FIG. 1 illustrates a system having asynchronous clocks according to an embodiment of the present invention.

FIG. 2 illustrates a register having a plurality of memory locations according to an embodiment of the present invention.

FIG. 3 illustrates a flowchart of a first method of comparing pointers associated with asynchronous clock domains according to an embodiment of the present invention.

FIG. 4 illustrates a flowchart of a second method of comparing pointers associated with asynchronous clock domains according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a system having asynchronous clocks according to an embodiment of the present invention. A first device 110 has a first clock. A second device 120 has a second clock that is not synchronized with the first clock. The first device 110 or the second device 120 can be a video camera, a personal video recorder, a settop box, a server, a barcode reader or scanner, a Moving Pictures Experts Group Audio Layer 3 (MP3) player or storage device, or a computer, to provide some examples.

The first and second clocks can have substantially the same frequency, though the scope of the invention is not limited in this respect. For example, the first and second clocks can each have a frequency of 480 MHz.+-.500 ppm, or 480 MHz.+-.240
kHz. The first clock can have a first frequency in the range of 479.76 MHz and 480.24 MHz, and the second clock can have a second frequency in the range of 479.76 MHz and 480.24 MHz. In this example, the first and second clocks are within 480 kHz of each other.

In a first example, the first device 110 includes a device controller 130a to which the first device 110 writes information. For example, the device controller 130a generally includes a first register 140a to temporarily store the information written by the first device 110, so that the information can be read by another device, such as the second device 120. The second device 120 can read the information from the first register 140a.

In a second example, the second device 120 includes a host controller 130b to which the second device 120 writes information. The host controller 130b typically includes a second register 140b to temporarily store the information written by the second device 120, so that the information can be read by the first device 110. The first device 110 can read the information from the second register 140b.

In a third example, the second device 120 writes information to the first register 140a of the first device 110. The first register 140a can temporarily store the information written by the second device 120, so that the first device 110 can read the information.

In a fourth example, the first device 110 writes information to the second register 140b of the second device 120. The second device 120 can read the information from the second register 140b.

The first device 110 and the second device 120 generally communicate via a path 150, such as a serial bus or a wireless link. The first and second devices 110 and 120 can communicate in accordance with a universal serial bus (USB) 2.0 standard or an Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, to provide some examples.

Information can be transmitted via path 150 using packets. A packet often includes multiple (e.g., eight, sixty-four, 1024) bits of information. A controller 130 can determine whether the second device 120 successfully reads a packet written by the first device 110. If the controller 130 determines that an error occurs with respect to the reading operation performed by the second device 120, the controller 130 can set an error flag of the packet. Generally, an error flag having a value of "1" indicates that the error flag is set. The error flag can be a sideband signal of the packet. According to an embodiment, the error flag is defined by the USB 2.0 Transceiver Macrocell Interface (UTMI) specification, which is incorporated herein by reference. The controller 130 can disregard the packet in response to detecting that the error flag is set. If the controller disregards the packet, the controller 130 can request the packet again.

According to the fourth embodiment described above, the host controller 130b can receive the information written by the first device 110 as a serial stream of bits via path 150 at a frequency of approximately 480 MHz. For example, the second device 120 can read one bit of the serial stream of bits per read operation at a frequency of approximately 480 MHz. In another example, the second device 120 can read multiple bits (e.g., eight bits) of the information per read operation at a frequency that is inversely proportional to the number of bits read per read operation. For instance, if the clock associated with the second device 120 operates at a frequency of 480 MHz, the second device 120 can read eight bits of the stream of bits per read operation at a frequency of approximately 60 MHz (e.g., 480 MHz/8=60 MHz). The host controller 130b can be used as a serial-to-parallel converter.

The second device 120 can process the information written by the first device 110. For instance, the host controller 130b of the second device 120 often processes the information. The host controller 130b can perform non-return-to-zero inverted (NRZI) coding/decoding with respect to the bits. The host controller 130b can remove one or more stuff bits from the stream of bits.

FIG. 2 illustrates a register 140 having a plurality of memory locations 250 according to an embodiment of the present invention. Each memory location 250 has an address that can be used by the first device 110 to write information to the memory location 250 and by the second device 120 to read the information from the memory location 250. For example, the first device 110 can write information to the register 140 using a write pointer 210. The second device 120 can read the information from the register 140 using a read pointer 220. The write pointer 210 is associated with a write address, which is the address of the register 140 to which the write pointer 210 writes information during a particular clock cycle of the first device 110 in this example. The read pointer 220 is associated with a read address, which is the address of the register 140 from which the read pointer 220 reads during a corresponding clock cycle of the second device 120 according to this example.

The write pointer 210 generally begins writing to the register 140 at a memory location 250 other than the first memory location 250a of the register 140 to reduce the likelihood of the read pointer 220 reading from a memory location 250 before the write pointer 210 finishes writing to the memory location 250. For instance, the write pointer 210 can begin writing at memory location 250n to facilitate an accurate reading by the read pointer 220. The write pointer 210 typically writes to the next consecutive memory location 250 at the next clock cycle of the first device 110.

According to an embodiment, the write pointer 210 writes in a first direction. For instance, the write pointer 210 can write to memory location 250b at the next clock cycle after writing to memory location 250a. The write pointer 210 can write to memory location 250c at the next clock cycle after writing to memory location 250b, and so on. When the write pointer 210 reaches the end of the register 140, memory location 250bb in this example, the write pointer 210 typically returns to the other end of the register 140 to continue writing. For example, the write pointer 210 can write to memory location 250a at the next clock cycle after writing to memory location 250bb.

An error can occur when the write address and the read address are the same. This common address can be referred to as the "read/write address". For instance, the clock cycle of the first device 110 can be shifted in time with respect to the clock cycle of the second device 120, such that the read pointer 220 reads from the read/write address before the write pointer 210 finishes writing to the read/write address. The information stored at the read/write address can be in a state of transition or can be previously stored information when the read pointer 220 reads from the read/write address. For instance, the second device 120 can receive information that is different from the information provided by the first device 110.

According to an embodiment, the register 140 is a first-in, first-out (FIFO) register. For example, the read pointer 220 can read information from the register 140 in the order that the write pointer 210 writes the information. The write pointer 210 and the read pointer 220 are typically capable of writing and reading, respectively, from both ends of the register 140.

The size of the write pointer 210 or the read pointer 220 is usually based on the size of the register 140. For instance, an N-bit pointer can be used if the register 140 has 2.sup.N or fewer memory locations 250. For instance, a 5-bit pointer can be used if the register 140 has no more than thirty-two memory locations 250. A 4-bit pointer can be used if the register 140 has no more than sixteen memory locations 250, and so on.

In the embodiment of FIG. 2, the register 140 has twenty-eight memory locations 250, and the write pointer 210 is a 5-bit write pointer. The write pointer 210 can be generated based on positive clock edges, negative clock edges, or positive and negative clock edges. For instance, the first device 110 can generate the write pointer 210, based on positive and negative edges of the clock of the first device 110, using the following verilog write pointer generation algorithm:

TABLE-US-00001 always @ (posedge rclk480 or negedge resetb_480 ) begin if (
 
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