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United States Patent7210159
Roop , ; et al.April 24, 2007
Title
System and method for transmitting and utilizing electronic programs guide information
Abstract
Television schedule information transmission and utilization systems transmit TV schedule data and associated network control messages provided by computer as packets via the Video Blanking Interval (VBI) lines in the TV signal from various television program providers. This data is acquired by regional data processing systems and forwarded by the regional data processing systems to subscriber units and used to construct an internal database. This internal database can be accessed by the subscriber unit to display a TV schedule for the channels that are received by the user's TV.
Inventors:Roop; John H. (Palo Alto, CA), Ebright; Alan R.  (Los Gatos, CA), Kochy; Jeffrey J.  (San Jose, CA), Warden; David P.  (Redwood City, CA), Sokolik; Konstantine  (Redwood City, CA), Alegiani; Giambattista A.  (San Francisco, CA)
Assignee:Starsight Telecast, Inc. (Fremont, CA)
Appl. No.:09/741,301
Filed:December 19, 2000
PCT Pub Date:May 2, 2007
Current U.S. Class:725/54 348/467 348/473 348/734 725/40 725/44 725/48 725/50 
Current International Class:G06F 3/00 (20060101) G06F 13/00 (20060101) H04N 11/00 (20060101) H04N 5/445 (20060101) H04N 7/00 (20060101)
Field of Search:725/40,44,48,50,54 348/467,473,734
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Primary Examiner: Miller; John
Assistant Examiner: Hoye; Michael W.
Attorney, Agent or Firm:Fish & Neave IP Group of Ropes & Gray LLP
Parent Case Text


ORIGIN OF THE INVENTION

This application is a continuation of U.S. patent application Ser. No. 09/096,269, filed Jun. 11, 1998 now U.S. Pat. No. 6,216,265, which is a continuation of application Ser. No. 08/239,225 filed May 4, 1994, now U.S. Pat. No. 5,790,198, issued Aug. 4, 1998, which is a continuation-in-part of application Ser. No. 08/198,538 filed Feb. 18, 1994, now U.S. Pat. No. 5,479,268, issued Dec. 26, 1995, and entitled "User Interface for Television Schedule System," which is in turn a file wrapper continuing application of U.S. patent application Ser. No. 07/579,555, filed Sep. 10, 1990, now abandoned, all of which are incorporated fully herein by reference.
Claims

The invention claimed is:
1. A method of displaying and updating television schedule information data in a television schedule information transmission system having a central data processing system and a plurality of subscriber systems, the method comprising the steps of: receiving via a television telecast signal commands that instruct the plurality of subscriber systems and which include command data and the television schedule information data used by the commands; responsive to receiving a command, reading the command data from the command to determine the instructions of the command; responsive to the command instructions, extracting a portion of the television schedule information data included in the command from the television telecast signal; responsive to the command instructions, storing the portion of the television schedule information data in a memory at the plurality of subscriber systems; responsive to the command instructions, preparing portions of the television schedule information data; and displaying the portions of the television schedule information data on a display monitor.

2. The method of claim 1, wherein the television schedule information data is received by a subscriber system if the commands are addressed to that subscriber system.

3. The method of claim 2, wherein a batch number as part of a command is used as a group address to send the command to at least one subscriber system sharing the same batch number.

4. The method of claim 2, wherein the command instructions contain an authorization command authorizing the subscriber system to begin collecting and displaying the television schedule information data.

5. The method of claim 1, wherein at least one of the commands received is private to at least one of the subscriber systems.

6. The method of claim 1, wherein the television schedule information data is received in the blanking interval of the television telecast signal.

7. The method of claim 1, wherein the receiving step comprises the step of decrypting an encrypted command.

8. The method of claim 1, wherein the preparing step comprises the steps of: executing at least one command instruction of the command; determining if certain of the television schedule information has already been received by the subscriber system; and receiving the certain of the television schedule information if it has not already been received.

9. The method of claim 1, further comprising the steps of: receiving a daylight change command instruction defining when a next daylight change will occur; and adding a time-zone offset to a local time to show the correct adjusted local time when the next daylight change occurs.

10. The method of claim 1, wherein the preparing step comprises the steps of: receiving a command including channel ID numbers and television scheduling information; matching the received channel ID numbers to a list of channel ID numbers stored in the memory representing the valid channels in the subscriber system; and compiling the television scheduling information on the channels for which the channel ID number in the list stored in the memory representing the valid channel matches that of the received channel ID number.

11. The method of claim 10, further comprising the steps of: receiving a second command providing at least 24 hours of television scheduling information data.

12. The method of claim 10, further comprising the steps of: receiving a show title command containing a name of a television program; comparing the name of the television program to a show list maintained in the memory; saving the show title command in the database if there is a match between the name of the television program and any entry in the show list; and ignoring the show title command in the memory if there is not a match between the name of the television program and any entry in the show list.

13. The method of claim 12, wherein the name of a television program is compressed text.

14. The method of claim 1, wherein the storing step comprises the steps of: periodically running a garbage collection process to collect unused memory blocks; recombining the unused memory blocks into larger memory blocks; and making the larger memory blocks accessible by the computer program.

15. The method of claim 1, wherein the portion of the television schedule information data is stored in a database as database items in the memory.

16. The method of claim 15, wherein the database items are arranged hierarchically in descending order as a list of channels and a list of show titles, show description, show start time and show durations for each channel.

17. The method of claim 16, wherein the database items are further arranged hierarchically in descending order as a theme table defining theme categories, theme sub-table defining theme sub-categories, and theme show table defining themes of a selected list of shows.

18. A system for displaying and updating television schedule information data in a subscriber system included in a television schedule information transmission system having a central data processing system and a plurality of subscriber systems, comprising of: a microprocessor at each of the plurality of subscriber systems; a decoder at each of the plurality of subscriber systems for receiving via a television telecast signal commands that instruct the microprocessor and which include command data and the television schedule information data used by the commands; means for reading the command data from a command to determine the instructions of the command responsive to receiving the command; means for extracting at least a portion of the television schedule information data included in the command from the television telecast signal responsive to the command instructions; a memory for storing the at least a portion of the television schedule information data responsive to the command instructions; code for the microprocessor for preparing portions of the television schedule information data responsive to the command instructions; and a display for displaying the portions of the television schedule information data on the display monitor.

19. The system of claim 18, wherein the television schedule information data is received by a subscriber system if the commands are directed to that subscriber system.

20. The system of claim 19, further comprising a batch number as part of a command for a group address to direct the command to at least one subscriber system sharing the same batch number.

21. The system of claim 19, wherein the command instructions contain an authorization command authorizing the subscriber system to begin collecting and displaying the television schedule information data.

22. The system of claim 18, wherein at least one of the commands received is private to at least one of the subscriber system.

23. The system of claim 18, wherein the television schedule information data is received in the blanking interval of the television telecast signal.

24. The system of claim 18, wherein at least one of the received commands is an encrypted command.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a system and method for broadcasting, receiving and using television schedule information. More particularly, it relates to such a system and method in which the television schedule information is broadcast in, e.g., the vertical blanking interval (VBI) of a television broadcast, a schedule of television programs for a user's broadcast area or cable system is compiled from the broadcast, and the schedule is displayed on the user's television set for interactive use. As used herein, the term "broadcast" is used in a brad sense to include such transmission modes as cable and telephonic transmission.

2. Description of the Prior Art

It is known in the art to provide an interactive television program schedule system utilizing broadcast schedule information. For example, such a schedule system is disclosed in commonly assigned Young, U.S. Pat. No. 4,706,121, issued Nov.
10, 1987 and the above referenced Young et al. pending application.

In the design of such a schedule system, only a limited amount of memory and data processing capability can be provided in the user's equipment that receives the schedule information broadcast, compiles the schedule for the user's broadcast area or cable system, displays the schedule on the user's television set and interacts with the user, while enabling that equipment to be provided at a low enough price for mass marketing. This memory and data processing limitation was recognized by Hallenbeck, U.S. Pat. No. 5,038,211, issued Aug. 6, 1991. The solution proposed by Hallenbeck is to subdivide the schedule information into prioritized categories, store the highest priority category, and as much of the lower priority categories as possible in the amount of memory available. A significant problem with this approach is that less information may be provided about programs in the schedule when there are more programs in the schedule and the need for more information is greatest. Further development in light of the memory and processor limitations of consumer electronics is therefore required.

When schedule information is transmitted as part of a program broadcast signal and a prior art subscriber unit acquires the schedule information from the program broadcast signal, a potential problem arises when previously broadcast programs have been recorded on a VCR and are played back The prior art subscriber unit lacks any ability to distinguish a video signal generated from a recorded program from a video signal received in real time from a broadcast As a result, the subscriber unit may overwrite more recent program schedule information acquired from a real time broadcast with older program schedule information coming from a video tape.

Proposals to transmit television schedule information with television broadcast signals often use a low bandwidth transmission mode, such as one or more lines in the vertical blanking interval (VBI) of the television broadcast signals. The use of such low bandwidth transmission modes means that the format and management of the transmissions must be carefully planned in order to avoid practical problems. For example, when a schedule update is to be transmitted, unless special provisions are made for such updates, worst case transmission delay until the update is received and entered in a user's subscriber unit could amount to five hours, the time for transmission of a complete schedule for a week in an NTSC television broadcast signal using one line of the VBI for the schedule information. In the case of last minute schedule changes, such a delay would be unacceptable.

Data encryption is essential for a subscription-based broadcast television schedule system Without data encryption, the schedule information could be acquired and used by pirate user equipment without payment of the subscription fee. However, decryption of encoded data is a processor intensive. A conventional approach of encrypting the entire schedule information transmission requires a faster and more expensive microprocessor than would otherwise be suitable for the subscriber units.

When implementing a television schedule system on a national or even international basis, provision must be made for different time zones. Adjusting times in the schedule for the different time zones in the process of transmitting the schedule adds substantial overhead to the data transmission. It would be desirable to eliminate the need for such adjustments in the transmission.

It may be desirable in the operation of a television schedule system to provide the schedule information embedded at different places in the television signal at different parts of the system in order to avoid the necessity of imposing uniformity throughout the system. To do so, it is necessary to provide a way for recipients of the schedule information to identify it in the television signal.

In the operation of a broadcast television schedule system, acquisition of new schedule information by the subscriber units consumes a substantial proportion of available microprocessor processing time. When obsolete schedule information is deleted and new schedule information is acquired, a substantial portion of the new information, such as program titles, duplicates information already present in stored schedule information or to be deleted with the obsolete schedule information. Avoiding the deletion of information that will form part of new schedule information would help to minimize the amount of processor time devoted to the acquisition of new schedule information.

Because of the severe memory limitations in consumer electronic products, it is necessary to use the memory efficiently in order to provide as much information and as much functionality in the subscriber unit as possible with the available memory.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide an interactive television program schedule system and method that can be implemented with low cost microprocessors and memory in subscriber data processing systems.

It is another object of the invention to provide an interactive television program schedule system and method in which television program schedule data is transmitted and stored in a manner that allows a low cost microprocessor suitable for use in a mass produced consumer product to carry out subset searching of the television program schedule data.

It is a further object of the invention to provide such a system and method in which television program schedule information is transmitted in an efficient manner.

It is still another object of the invention to provide such a system and method in which the television program schedule information is acquired by the subscriber data processing systems in an efficient manner.

It is a still further object of the invention to provide such a system and method in which fast schedule updates to accommodate schedule updates can be provided with a low bandwidth transmission system.

It is yet another object of the invention to provide such a system and method that will be able to distinguish between currently broadcast schedule information and older schedule information included with a broadcast that was recorded.

It is yet a further object of the invention to provide such a system and method in which schedule update information is given priority treatment.

It is another object of the invention to provide such a system and method in which the schedule information transmission is selectively encrypted.

It is a further object of the invention to provide such a system and method in which a single system time is employed in schedule information transmission portions of the system and compensation for local time is carried out in the subscriber units.

It is still another object of the invention to provide such a system and method in which the subscriber units are able to identify schedule information provided in different locations of a television broadcast signal.

It is still another object of the invention to provide such a system and method in which portions of schedule information already acquired by a subscriber unit and which duplicate portions of new schedule information are retained, so that such schedule information portions need not be acquired again by the subscriber unit.

It is yet another object of the invention to provide such a system and method in which data compression is employed in a unique way to make most efficient use of available memory.

The attainment of these and related objects may be achieved through use of the novel television schedule information transmission and utilization system and method herein disclosed. In one aspect, a television schedule information transmission and utilization system in accordance with this invention has a central data processing system. A means is connected to the central data processing system for providing schedule information data for a predetermined territory to the central data processing system. The central data processing system includes means for formatting the schedule information data for the predetermined territory into a predetermined schedule information transmission formal A means is coupled to the central data processing system for transmitting the schedule information data for the predetermined territory in the predetermined schedule information transmission formats. A plurality of regional data processing systems, each located in a region of the predetermined territory, include means for receiving the schedule information data for the predetermined territory, means for selecting the schedule information data for the region in which each of the plurality of regional data processing systems is located and means for transmitting the schedule information data for the region. A plurality of subscriber data processing systems are in each of the regions. Each of the plurality of subscriber data processing systems include means for receiving at least a portion of the schedule information data for the region, means for storing the schedule information data received by the subscriber data processing system, means for assembling portions of the schedule information data received by the subscriber data processing system for display to a user of the subscriber data processing system and a display connected to the means for assembling portions of the schedule information data to display the portions of the schedule information data.

In another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and subscriber data processing systems in the predetermined territory. The system is improved with a plurality of regional data processing systems, each located in a region of the predetermined territory. The plurality of regional data processing systems each include means for receiving the schedule information data for the predetermined territory, means for selecting the schedule information data for the region in which each of said plurality of regional data processing systems is located and means for transmitting the schedule information data for the region to a plurality of the subscriber data processing systems in each of the regions.

In a further improvement of the television schedule transmission system, the means for transmitting the schedule information data for the region in each of said plurality of regional data processing systems has an ability to transmit the schedule information data for the region in different places of a television broadcast signal. Each of the subscriber data processing systems includes a means for locating the schedule information data in the television broadcast signal.

In a further aspect of the invention, a method in a television schedule information transmission system includes transmitting schedule information data for a predetermined territory to a plurality of regional data processing systems each located in a region of the territory. The schedule information data for each region is selected with its regional data processing system. The schedule information data for each region is transmitted with its regional data processing system to a plurality of subscriber data processing systems in each region. Portions of the schedule information data received by each subscriber data processing system are assembled for display to a user of each subscriber data processing system. The portions of the schedule information data are displayed to the user.

The method further desirably includes having at least some of the plurality of regional data processing systems transmit the schedule information data in different places of a television broadcast signal. Each of the plurality of subscriber data processing systems locates the schedule information data in the television broadcast signal.

In still another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. The system is improved by providing means in the central data processing system for transmitting the television schedule data as commands. The commands include instructions for the plurality of subscriber data processing systems in the system and television schedule information in elemental form used by the commands in the plurality of subscriber data processing systems to assemble and display a television schedule.

In a still further aspect of the invention, a method in a television schedule information transmission system includes transmitting commands from a central data processing system to a plurality of subscriber data processing systems. The commands include instructions for the plurality of subscriber data processing systems in the system and television schedule information used by the commands in the plurality of subscriber data processing systems to assemble and display a television schedule. The television schedule is assembled from the television schedule information in each of the plurality of subscriber data processing systems. The television schedule is displayed to a user of each of the plurality of subscriber data processing systems.

In a still further aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. The system is improved with means in the central data processing system for transmitting a predetermined character string comprising a portion of the schedule information to the plurality of subscriber data processing systems. A means in each of the plurality of subscriber data processing systems determines whether the predetermined character string has been acquired by that subscriber data processing system. A means in each of the plurality of subscriber data processing systems stores the predetermined character string in that subscriber data processing system if it has not already been acquired.

In yet another aspect of the invention, a method in a television schedule information transmission system includes transmitting a predetermined character string comprising a portion of the schedule information to a plurality of subscriber data processing systems in the system. Whether the predetermined character string has been acquired by a particular subscriber data processing system is determined. The predetermined character string is stored in that subscriber data processing system if it has not already been acquired.

In a further aspect of the invention, a television schedule information transmission system includes a direct broadcast satellite. A central data processing system has means for transmitting television schedule data for the direct broadcast satellite to the direct broadcast satellite. Subscriber data processing systems have means for receiving the television schedule data for the direct broadcast satellite from the direct broadcast satellite. The system is improved with a plurality of regional data processing systems, each located in a region of a predetermined territory. The plurality of regional data processing systems each include means for receiving the schedule information data for the predetermined territory. Means selects the schedule information data for the region in which each of the plurality of regional data processing systems is located. Means transmits the schedule information data for the region to a plurality of the subscriber data processing systems in each of the regions.

In another aspect of the invention, a method in a television schedule transmission system includes transmitting television schedule data for a direct broadcast satellite to the direct broadcast satellite. The television schedule data for the direct broadcast satellite is received from the direct broadcast satellite at a subscriber data processing system. Schedule information data for a predetermined territory is received in a regional data processing system located in a region of the predetermined territory. The schedule information data for the region in which the regional data processing system is located is selected in the regional data processor. The schedule information data for the region is transmitted to the subscriber data processing system.

In still another aspect of the invention, a television schedule information transmission system includes a central data processing system having means for transmitting television schedule data. A subscriber data processing system has means for receiving at least some of the television schedule data transmitted by the central data processing system. The system is improved by providing a subscriber data processing system including a memory for efficiently storing database items comprising the television schedule information. Each of the database items has a handle as an index into a handle table identifying memory locations corresponding to the handle. This allows physical movement of database items from one memory location to another for garbage collection. This allows holes in the database memory which arise as data ages and is discarded to be recovered and concatenated into large useful memory blocks. This trades "free" microcontroller cycles for memory, which is expensive.

In a still further aspect of the invention, a method in a television schedule information transmission system includes transmitting television schedule data. At least some of the television schedule data is received at a subscriber data processing system as database items comprising the television schedule information. Each of the database items has a handle. The handle is used as an index into a handle table identifying memory locations corresponding to the handle.

In another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory including updates of television schedule data previously transmitted. There are a plurality of subscriber data processing systems in the predetermined territory. Each of the plurality of subscriber data processing systems includes a receiver for television schedule data and a memory for storing television schedule data The memory is coupled to the receiver. The system is improved by including means in the central data processing system for assigning a transmission priority for the updates of television schedule data previously transmitted relative to other television schedule data.

In a further aspect of the invention, a method in a television schedule information transmission system includes establishing a relative priority for transmission of the television schedule information between updates of originally transmitted television schedule information and originally transmitted schedule information. The television schedule information is transmitted in accordance with the relative priority. At least some of the transmitted television schedule information is received at a subscriber data processing system.

In yet another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. Each of the plurality of subscriber data processing systems includes a receiver for television schedule data. A memory for storing television schedule data is coupled to the receiver. The system is improved by including means in the central data processing system for identifying the transmitted television schedule data by time relative to other transmitted television schedule data. Means in the subscriber data processing system determines if television schedule data received by the subscriber data processing system has a time identification later than a time identification of television schedule data stored in the memory.

In yet a further aspect of the invention, a method in a television schedule transmission system includes transmitting television schedule data with an identification of the transmitted television schedule data by time relative to other transmitted television schedule data. The transmitted television schedule data is received with a subscriber data processing system. The television schedule data is stored in a memory of the subscriber data processing system. Television schedule data is subsequently supplied including an identification by time relative to other television schedule data The identification by time of the subsequently supplied television schedule data is compared with the identification by time of the television schedule data stored in the memory. The stored television schedule data is replaced with the subsequently supplied television schedule data if the identification by time of the subsequently supplied television schedule data is later than the identification by time of the stored television schedule data The stored television schedule data is maintained in the memory if the identification by time of the stored television schedule data is later than the identification by time of the subsequently supplied television schedule data.

In still another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. Each of the plurality of subscriber data processing systems includes a receiver for television schedule data. A memory for storing television schedule data is coupled to the receiver. The system is improved by including means in the central data processing system for encrypting a selected portion of the television schedule data required by the subscriber data processing system to assemble a television schedule for display. Means in the subscriber data processing system decrypts the selected portion of the television schedule data.

In a still further aspect of the invention, a method in a television schedule transmission system includes selectively encrypting a portion of television schedule data necessary to assemble a television schedule for display. The television schedule data including the encrypted portion is transmitted. The television schedule data is received in a subscriber data processing system. The encrypted portion of the television schedule data is decrypted. The television schedule data, including the now decrypted portion, is used to assemble a television schedule for display.

In another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. Each of the plurality of subscriber data processing systems includes a receiver for television schedule data. A memory for storing television schedule data is coupled to the receiver. The system is improved by including a real time clock in the central data processing system for establishing a single system time for the transmission system. The means for transmitting television schedule data includes means for transmitting the single system time. The receiver includes means for receiving the single system time. The memory has a stored value for calculating local real time from the single system time.

In a further aspect of the invention, a method in a television schedule transmission system includes establishing a single system time related to real time. The single system time is transmitted to a subscriber data processing system. Television schedule data expressed in the single system time is transmitted to the subscriber data processing system. A value is provided to the subscriber data processing system for calculating local real time from the single system time. Local times are calculated for a television schedule from the schedule data expressed in the single system time using the value.

In still another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. Each of the plurality of subscriber data processing systems includes a receiver for television schedule data. A memory for storing television schedule data is coupled to the receiver. The system is improved by having the means for transmitting television schedule data configured to transmit the television schedule data as a show list for each day in the television schedule. The subscriber data processing system is configured to maintain show lists for a rolling window comprising a plurality of days extending from present time into future time.

In a still further aspect of the invention, a method in a television schedule information transmission system includes transmitting television schedule data as a show list for each day in the television schedule. Show lists are maintained for a rolling window comprising a plurality of days extending from present time into future time.

In yet another aspect of the invention, a television schedule information transmission system includes a central data processing system for a predetermined territory having means for transmitting television schedule data for the predetermined territory and a plurality of subscriber data processing systems in the predetermined territory. Each of said plurality of subscriber data processing systems includes a receiver for television schedule data A memory for storing television schedule data is coupled to the receiver. The system is improved by having the subscriber data processing systems configured to store the television schedule data in compressed form in the memory. A read only memory in the data processing system stores fixed text for the system The fixed text is stored in said read only memory in compressed form.

In yet a further aspect of the invention, a method in a television schedule information transmission system includes storing television schedule data in compressed form in a memory of the system. Fixed text for the system is stored in a read only memory, also in compressed form.

The attainment of the foregoing and related objects, advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the invention, taken together with the drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 5 are block diagrams of television schedule information transmission and utilization systems in accordance with the invention.

Appendix A attached to and forming a part of this application contains more detailed block diagrams of portions of the television schedule information. transmission and utilization systems of FIGS. 1 5.

FIGS. 6 25 are schematic representations of message formats used in the systems of FIGS. 1 5.

FIGS. 26 60 are schematic representations of data structures, flow charts and display formats used in the systems of FIGS. 1 5.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to the drawings, more particularly to FIGS. 1 4, there is shown television schedule information transmission and utilization systems 50A 50D. The systems 50A 50D transmit TV schedule data and associated network control messages as packets via the Video Blanking Interval (VBI) lines in the TV signal from various television program providers 51, such as PBS, MTV or Showtime. This data is acquired by StarSight Subscriber Units 52 and used to construct an internal database. This internal database can be accessed by the Subscriber Unit 52 to display a TV schedule for the channels that are received by the user's TV.

Since access to the network systems 50A 50D is via a subscription service, certain messages are encrypted by a security computer 53 to prevent access by nonsubscribers. Essentially any encryption system can be used with the invention, but an encryption system as disclosed in U.S. Pat. Nos. 4,531,020 and 4,531,021 is preferred.

Packets contain error detection information and system overhead bytes for finding the head of a packet. The information embedded in a Packet is termed a Message. Messages consist of one or more Commands. There are various types of Commands, each type distinguished by a unique code number. Commands contain the different types of information necessary to construct and maintain a TV schedule database, time markers, and user authorization information.

The systems 50A 50D are data networks that deliver specially formatted data to subscribers 52 located throughout the USA. This data is used to build an "on screen program guide" that enables the system subscribers to interactively view television program listings on their TV screen. The information for this network is derived from a database that is built by a computer program running on a UNIX computer 54. To build this database a data provider (DP) 56 is required to supply the computer 54 with program listing files called Show list files.

The Show list files are transferred electronically to the file system in computer 54 through a router connected to the DPs Ethernet and a digital leased line 58, using the standard TCP/IP program, FTP, or other file transfer protocol standard mutually agreed upon. The files may require compression, due to the bulk of data being transferred using a mutually agreed upon data compression algorithm compatible with the UNIX file system in computer 54. The operating speed of the leased line 58
will be sufficient to transfer all data files in a reasonable length of time.

The files are transferred to the computer 54 on a daily basis 7 days a week, with the file transfer completed by 0800 hours PST. The daily file transfer will be into the home directory corresponding to the login name used to perform the file transfer.

The "Main" file download to the computer 54 will always be for the date 12 days into the future. Thus if today is the 10th, todays data download would be for start times beginning at 0000 hours GMT on the 22nd.

Since the data files are sent on a daily basis some mechanism must be in place to allow for the updating of a program listing that has already been transferred. This is accomplished via the "Update" file. An Update file contains records of all changes that have been made since the last Update file was produced, which modify any of the data for any date which is still "active". An "active" date is defined as the dates beginning with today's date, and spanning the 11 days following (that is, all dates from today to the date covered by today's "Main" file, but not including that date.

Last minute schedule changes require "Flash Updates", which provide a "Flash Update" file within 5 minutes after entry of any change. Such files "trickle" across the leased line 58 to the computer 54 throughout the day.

Details of the subscriber units 52 are provided in FIG. 5. The following description is in terms of a subscriber unit 52 for a TV Receive Only (TVRO) system (see also FIG. 4). With appropriate modifications, the subscriber unit 52 can also be incorporated in a cable decoder box for use with cable systems. The subscriber unit can also be built into televisions or VCRs or provided as a separate stand alone unit.

This description is for the electronic hardware of the StarSight Telecast "TVRO Subscriber Unit" 52. TVRO customers are people who have home satellite dishes for television viewing. TVRO stands for "TV Receive Only". The TVRO Subscriber Unit
52 will hook up to the customers TVRO Satellite system and will enable the customer to subscribe to StarSight's Electronic Program Guide Service. The TVRO Subscriber Unit 52 is a fully self contained, separate unit, that is installed in series with the existing customer TVRO equipment.

The Subscriber Unit receives Baseband Video from the customer TVRO system. The Program guide display screens are merged with the customer video in the Subscriber Unit. The customer has the options of Baseband Video out or Channel 3/4 RF out.

The Subscriber Unit formats and displays TV program schedule information in real time, overlaid on top of the TV viewing screen. The TV schedule information is transmitted in one of the Vertical Blanking Interval (VBI) lines of a conventional TV broadcast. The Subscriber Unit stores this information in local on board memory. The information is displayed in the form of a "Grid Guide" on the TV screen when the customer presses a button on the remote control.

The Subscriber Unit 52 consists of the following subsections: Inexpensive 8 bit Microprocessor 100. 64K Bytes of code ROM 101. 512K of RAM 102 for program data storage. Custom gate array 103. Segmented Base Registers 104 for fast memory data manipulation. Security logic 106 for decoding incoming encrypted data. Serial "I.M." Bus 108 for display controller interface. Serial "StarSight" Bus 110 for inter processor communications. (ISB) Watchdog timer 112 for error recovery. IR input 113. Infrared Receiver circuits 114. Infrared Transmitter circuits 116 for TV, VCR control. IR output 117. CRC-32 encoding and decoding logic 118. On board power supply 120. Power down RAM data retention 122. Video Input 123. On Screen Display Controller and Formatter 124. Custom Color Converter 126 for overlay display. RF Modulator 127. Choice of Baseband Video or RF outputs 128 or 130.

The heart of the TVRO Subscriber Unit 52 is an "8032, 8 bit Microprocessor" 100. This microprocessor controls all sections of the Subscriber Unit. A brief description of this processor will be given for reference. For more detail, refer to the
8032 data books from Intel or Signetics.

The 8032 has an 8 bit Data Bus and a 16 bit Address Bus. The upper 8 bits of the address bus are always present. The lower 8 bits of the Address Bus are time multiplexed with the Data Bus and an External Address Latch is required to de-multiplex this bus. This latch is located inside of the DBE 1200 Gate Array 103. The 8032 has two address spaces, the "CODE" space and the "DATA" space. The DATA space is further divided into the RAM Memory area and the I/O area. "CODE" refers to any access to Program ROM. The Program CODE space is 64K bytes long and the 8032 can only "READ" from this space. All Code access uses the "PSEN" (Program Store ENable) line. The -WR and -RD lines do not assert during CODE accesses. +ALE is the control signal used to de-multiplex the Address Bus. The falling edge of +ALE will latch the lower 8 bits of the address. -PSEN will then assert to start the ROM read. The current design has the EPROM -CS line always tied to ground. This makes the EPROM "OE ACCESS" time the determining spec for ROM reads. By today's standards, this microprocessor bus timing is very slow and this allows for the use of inexpensive ROMs.

"DATA" refers to any access to external RAM 102. Special additional hardware has been added to the TVRO Subscriber Unit so that the DATA area can extend past the 64K addressing limit. This is done via segmenting "BASE REGISTERS" 104 and will be discussed later. The 8032 -RD strobe will assert for RAM Data Reads and the -WR strobe will assert for RAM Data Writes. PSEN will not assert during Data accesses. The RAM Data accesses can only take place via the "MOVX" instruction. No other 8032
instruction will cause -RD or -WR to assert. Once again, +ALE is used to latch the address, then -RD or -WR will assert to start the data transfer. Read data must be valid just before -RD negates. The Write data is valid the entire time that -WR is asserted.

Along with the RAM Data Space, there is also a "64K I/O SPACE". This I/O space occupies the same first 64K segment as the DATA RAM. There is a signal called +DRAM_ENABLE that is used to determine which area will be accessed. The I/O space is where the system control registers are located. There are 18 write registers and 13 read registers. These registers air used to control the various subsystems in the Subscriber Unit. Features like clock frequency selection, serial bus control, I.R. status and control, etc . . . , are all controlled through this register set. There are other control registers located in the peripheral chips. The 8032 uses two serial Busses to communicate and control these peripheral chips. The "IM BUS" 108 is a
3 wire serial bus used to talk to the transaction processing unit (TPU 2740) 124. The TPU 2740 collects the incoming VBI data and also formats and displays the various StarSight overlay screens.

The Software Serial Bus 110 is used to talk to the Security Microprocessor 106 and also to the IR Blaster Chip 116. This is a two wire bus with a unique serial timing protocol.

The first 64K of 8032 Address Space has three separate overlapping functions. 1. If -PSEN is asserted, then the CODE ROM will be accessed. 2. If +DRAM_ENABLE=logic `0`, then the I/O registers will be accessed. 3. If +DRAM_ENABLE=logic `2`, then the first 64K of RAM will be accessed. The area above 64K is always RAM and the total length is 512K bytes. 8032 SIGNAL SUMMARY

Table I summarizes the input and output signals of the 8032 microprocessor:

TABLE-US-00001 TABLE I Signal Direc- Name FUNCTION tion +ALE Latches the low 8 bits of the Address Bus. Output -PSEN Enables Op-Code read fetches from ROM. Output -WR Asserts to Write to external DATA RAM Output -RD Asserts to Read from external DATA RAM Output -INT0 Interrupt 0-Indicates the ISB circuit requesting service. Input -INTl Interrupt1 -- Indicates that power is about to fail. Input PORT 0 8 bit Multiplexed 8032 Data and Address Bus. I/O PORT 1 Various system control bits. I/O PORT 2 Upper 8 bits of the Address Bus Output PORT 3 8032 control bits. I/O

Base Register Description

The 8032 Data Address space is only 64K bytes long. The TVRO Subscriber Unit however, is required to store more than 64K bytes of TV program data The "READ and WRITE BASE REGISTERS" allow the 8032 to access additional memory above the 64K limit

The 8032 uses an internal 16 bit register called the "Data Pointer Register" (DPTR) to hold the address of the external DATA location. The Base Registers (located in the DBE 1200 Gate Array) hold another 16 bit value that is added to the Data Pointer value to form the actual RAM address. The Base Register contents is shifted 4 bits left with respect to the Data Pointer so that the RAM address becomes 20 bits long. 20 bits allows for a 1 Megabyte total Data RAM size. The 8032 can access any
64K byte chunk of the external RAM starting at the address written in the Base Registers. (Since the base register is shifted 4 bits left, the 8032 can access any 64K byte segment starting on even 16 byte boundaries.) There are two base registers so that Memory Block Moves can be performed quickly. It would be very slow and cumbersome to the software if the value of the DPTR had to be changed for each read and then changed again before a write during block moves. The dual Base Registers allow you to put the starting address of the Read (Source) Block into the Read Base Register, and the starting address of the Write (Destination) block into the Write Base Register. A software loop can then be written that does a read followed by a write to the same DPTR address. The DPTR is then incremented and the process repeated. This allows software to quickly move blocks of Data anywhere in external RAM.

A provision has also been added to quickly disable the Base Registers. The signal +ENABLE_BASE will force the outputs of both Base Registers to all zeros. This is done without altering the contents of the Base Registers. This feature provides a quick method of accessing the first 64K segment of RAM. Both RAM Reads and Writes will go to the same location. Processor related data will be stored in the first 64K segment (Register Images, Software Counter Values, System Parameters etc . . . ). The upper segments are used to store TV program information.

Table II below tries to show how the DPTR is added to the Base Register to form the 20 bit RAM address.

TABLE-US-00002 TABLE II Base Reg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +8032 Addr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 =20 bit Addr 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +DRAM_EN must = 1 to access the external memory area Note: Base Reg shifted 4 bits left with respect to Address bus.

As an example: The READ BASE REGISTER is set to 0001 Hex. The WRITE BASE REGISTER is set to 1080 Hex. The Data Pointer (DPTR) is set to 382A Hex. An 8032 Read (MOVX A,@DPTR), will access address 0383A Hex (note: 20 bits!). An 8032 Write (MOVX @DPTR,A), will access address 1403A Hex (note: 20 bits!). +DRAM_EN must=0 to access the I/O area. Data RAM Description

As previously mentioned, the DATA RAM 102 stores the TV program guide information. This RAM is currently available in 3 sizes, 128K bytes, 256K bytes or 512K bytes. The TVRO product uses 512K bytes. The Data RAM uses "PSRAM" chips. "PS" stands for Pseudo Static. The PSRAM is a standard DRAM that has been packaged with STATIC RAM pinouts. Extra logic is added so that DRAM refreshes are simplified. These PSRAMs also have a power down data retention feature that works down to 3 Volts.

There are four modes of PS RAM operation in this product. They are:

1. Sequence Up Mode.

2. Normal Data Transfer Mode.

3. Sequence Down Mode.

4. Power Down Data Retention Mode.

There are two sizes of PSRAM that can be used in this design. The 128K by 8 chip or the 512K by 8 chip. There is a provision to use two of the 128K by 8 parts to obtain 256K bytes of total memory.

These two parts have slightly different pin outs and operate in slightly different methods. Circuitry has been added to compensate for these differences. There is a bit called +512KRAM that must be set by the software depending on which chip is used.

Also the PSRAMs must go through a "Sequence Up" state after power on and a "Sequence Down" state just prior to power off.

PSRAM Operation (Sequence Up Operation)

After initial power up, the PSRAMs must be "SEQUENCED UP" before any reads or writes can be done. The Sequence Up procedure is slightly different for 128K and 512K parts. This procedure was added to insure that logic and timing specifications of the PSRAM are maintained when the PSRAMs are in the power down data retention mode. There is a provision to use a large Capacitor or a Battery to keep the PSRAMs powered up when the system power is lost. In order to preserve PSRAM data when the power is off, certain of the PSRAM inputs must be held in a known logic state. On top of this, these pins must follow defined timing constraints when they are put into the known logic states. The pins and logic levels are different for the 128K and the
512K parts.

For the 128K parts:

+Chip_Enable 2 (Pin 30) and -REFRESH (Pin 1) must both be held at logic `0` when the power is removed to insure data retention. When going from data retention mode to normal operation, -REFRESH (Pin 1) must go high at least 225 nS before +CHIP_ENABLE (Pin 30) goes high.

For the 512K parts:

-Chip_Enable (Pin 22) must be held at logic `1`and -OE/-REFRESH (Pin 24) must be held at logic `0` when the power is removed to insure data retention. When going from data retention mode to normal operation, -Chip_Enable (Pin 22) must go high at least 50 nS before -OE/-REFRESH (Pin 24) goes high.

There is also a timing constraint as to how soon after normal PSRAM REFRESH the above sequences can occur. The Sequence Up logic in the DBE 1200 Gate Array controls the above timing. After a Power On Reset (POR) sequence is finished, the Microprocessor toggles a bit called +SEQUENCE_UP [Wr Addr 7400Hex, bit 5]. (Be sure to always return this bit to logic `0`). Toggling the +SEQUENCE_UP bit will start the Sequence Up State Machine. This State Machine will wait for the end of the next normal Refresh Pulse and then it will remove the forced logic levels using the correct timing as mentioned above. The refresh pulses occur about every 11 uS and the Sequence Up process takes about 1 uS. Software should wait at least 15 uS from the time that +SEQUENCE_UP is set till when the first PSRAM access is attempted.

PSRAM Operation (Normal Operation)

Normal PSRAM operation is very straightforward. Refreshes are automatic and transparent to the microprocessor. The PSRAM must be Refreshed at least once every 15 uS. The Refresh address is generated inside the PSRAM and is transparent to the user. In order to do a Refresh, the Refresh pin on the PSRAM must be held low for a minimum time. For ease of circuit design, the Refresh Request is generated by the internal clock divided by 256. With a 24 MHz clock, this happens about every 10.7 uS.

The Refresh Pulse to the PSRAM chip must not occur at the same time as a PSRAM read or write access. Since the Refresh Request and any PSRAM access are asynchronous, the -PSEN line is used to start a Refresh. When the Refresh Request is detected, the Refresh circuit waits until the next -PSEN falling edge. -PSEN falls at the beginning of a CODE access to ROM. CODE accesses to ROM happen all the time as the 8032 fetches OP-CODES. During this time, it is impossible for the 8032 to access PSRAM. The Refresh is very fast and it will be finished before the -PSEN CODE fetch is complete.

CAUTION: This system must have -PSEN toggling in order to refresh PSRAM. In normal operation this will happen all of the time. Be careful if you use an 8032 emulator. The refreshes will stop if you ever break and stop the emulator. Most emulators have an option to insure that -PSEN still asserts even when an emulator breakpoint occurs.

PSRAM Operation (Sequence Down Operation)

Sequence Down is the opposite of Sequence Up. The system has an "Early Warning Power Fail Detector" that will interrupt the 8032 before the supply voltage starts to drop. The 8032 responds to this interrupt by saving any critical PSRAM data and then asserting the +SEQUENCE_DOWN bit. Sequence Down will force the PS RAM critical inputs to their correct state and will do so insuring that the timing specification is maintained. The Sequence Down logic will not start until the end of the next Refresh to insure proper timing. The SEQUENCE DOWN rules are shown below.

For the 128K parts:

+Chip_Enable2 (Pin 30) must go to logic `0` at least 60 nS before -REFRESH (Pin 1) is forced to logic `0`. After the power dies, external components should hold these lines at logic `0` as the gate array outputs will be undefined.

For the 512K parts:

-Chip_Enable (Pin 22) must be forced to logic `1` at least 50 nS before -OE/-REFRESH (Pin 24) is forced to logic `0`.

PSRAM Operation (Power Down Data Retention)

As long as the critical input pins are held at their power down levels (See Above) and the voltage to the PSRAM chips stays above 3.0 Volts, the data will be retained.

PSRAM Power Down Latch

There is a very low current J-K Flip Flop that is powered by the same backup capacitor that powers the PSRAMs. This flip flop lets the software know if the voltage dropped below the minimum voltage specification during a power off period.

At initial power on, this latch should power up to logic `0`. The microprocessor can read the state of this latch on the +RAMV_OK line. If the latch is `0`, then it should be assumed that the voltage dropped below the PSRAM minimum data retention specification and all RAM data is invalid. If the latch =1, then the PSRAM data is still valid from before the power down.

If +RAMV_OK is logic `0`, then the microprocessor can set it to logic `1` after self test diagnostics pass. Once this latch is set to logic `1`, it will stay set until the PSRAM Vdd Voltage drops below about 3.1 Volts.

Five conditions are necessary to set this latch. 1. The PSRAM voltage must be greater than 3.1 Volts. (This releases the J-K Flip Flop Reset Pin). 2. The PCB +5 Volt supply must be greater than about 4.5 Volts. (This releases system POR).
3. The -ENBLAT line must be set to logic `0`. 4. The +BAND0 line must be set to logic `1`. 5. The +LAT_CLK line must be toggled to logic `0` and then to logic `1`.

The -ENBLAT and +LAT_CLK lines are driven by 8032 microprocessor PORT pins. These pins will be initialized to logic `1` by 8032 hardware at POR time. The +BAND0 line comes from the DBE 1200 gate array and is reset to logic `0` at POR time.

By requiring all of these conditions, it is hoped that the latch will not be able to be set by spurious noise glitches at power up. It would not be a bad idea to have checksum locations in PSRAM to verify that the data is valid if the latch reads a logic `1`. (Just in case the latch can be set by a noise glitch.)

The MC14xxx series CMOS devices were chosen for the latch circuit because this family guaranteed very low worst case current drain.

DBE 1200 Gate Array 103

The Gate Array 103 is packaged in an 84 pin PLCC package. The Gate Array terminology is slightly different from the PCB terminology. The PCB uses "+" in front of a signal name to indicate "active high". The Gate Array dropped the "+" and just uses the signal name when the signal is "active high". The PCB uses "-" in front of a signal name to indicate "active low". The Gate Array adds the letter "X" in front of a signal name when it is "active low".

The following abbreviations for addresses and bits will be used.

(6000W.5)=Write Address 6000 hex, bit 5.

(6COOR.3) =Read Address 6COO hex, bit 3.

Address Decoding

The address decoders are shown on pages 1 and 9 of Appendix A. 74F138 type 1 of 8 decoders are used with the 8032 -RD or -WR strobe used for an enable. The outputs of the 74F138 will be valid only when the proper address is written or read.

The following tables show the Write and Read addresses that are decoded. The page number refers to the page of the Gate Array schematic of Appendix A that the register can be found on. The "Gate Array Name" is the name of the decoded signal on the schematic. Table III below shows the I/O Write register decodes and Table IV shows the I/O read register decodes.

+DRAM_EN must =0 to access these registers.

TABLE-US-00003 TABLE III 8032 I/O WRITE REGISTERS WRITE WRITE Gate Array ADDRESS Pg REGISTER ACCESSED Name 8032 PORT 1 X VARIOUS OUTPUT CONTROL BITS 8032 PORT 3 X VARIOUS CONTROL AND I/O BITS 0000H 3 READ_BASE_REGISTER_LOW XRBASELO 0400H 3
READ_BASE_REGISTER_HIGH XRBASEHI 0800H 3 WRITE_BASE_REGISTER_LOW XWBASELO 0C00H 3 WRITE_BASE_REGISTER_HIGH XWBASEHI 1000H 10 PWM_CONTROL_REGISTER_LOW XPWM_LO 1400H 10 PWM_CONTROL_REGISTER_HI XPWM_HI 2000H 12 I.M. BUS ADDRESS REGISTER XL_IM_AD 2400H 12
I.M. WRITE DATA 1 REGISTER XL_IM_Dl 2800H 12 I.M. WRITE DATA 2 REGISTER XL_IM_D2 2C00H 12 I.M. BUS START TRANSFER REGISTER XSTRT_IM 3000H 9 IM BUS CONTROL REGISTER XIM_CTRL 3C00H 9 SECURITY CHIP CLOCK FREQ REGISTER XCLK_REG 6000H 9 OUTPUT CONTROL REGISTER XCNTRL_1 6400H 13 REFRESH WATCHDOG REGISTER XWDOG_CS 6800H 18 CRC-32 DATA REGISTER XWR_CRC 6C00H 29 ISB CONTROL REGISTER XISBCTRL 7000H 24 ISB TRANSMIT DATA REGISTER XISBXM1T 7400H 31 RAM SEQUENCE AND GATE ARRAY XWR_TEST TEST REGISTER

TABLE-US-00004 TABLE IV 8032 I/O READ REGISTERS READ AD- READ Gate Array DRESS Pg REGISTER ACCESSED Name 0400H 31 READ TEST MULTIPLEXER REGISTER XRD_MUX 0800H 5 I.R. RECEIVE DATA REGISTER XIRR_REG 0C00H 6 ISB INTERRUPT STATUS REGISTER XRD_STAT
1000H 12 I.M. READ DATA BYTE #1 XRD_BYT1 1400H 12 I.M. READ DATA BYTE #2 XRD_BYT2 1800H 6 I.M. STATUS AND CHIP I.D. REGISTER XSW_LO 1C00H 6 I.R. RECEIVER STATUS REGISTER XSW_HI 6800H 24 ISB RECEIVE DATA REGISTER XRRECREG 6C00H 29 ISB STATUS REGISTER
2 XISB_ST2 7000H 16 CRC-32 READ REGISTER 3 XRDCRC3 7400H 16 CRC-32 READ REGISTER 2 XRDCRC2 7800H 17 CRC-32 READ REGISTER 1 XRDCRC1 7C00H 17 CRC-32 READ REGISTER 0 XRDCRC0

PSRAM Control

The PSRAM Control logic is shown on Page 2 of Appendix A. This logic consists of simple gates that route the control signals to their proper pins depending on the mode the chip is in. The chip has two memory size modes, 128K and 512K. There is also a Sequence Up mode and Sequence Down mode.

PSRAM Control Signals

XRFSH_18 (-ReFreSH or address_bit_18)

This is a dual purpose signal that should be tied to pin 1 of the PSRAM chips. When Sequenced Up, this signal is mode dependent.

In 128K mode, the -REFRESH signal is routed to this pin.

In 512K mode, Bit 18 from the Address Mux is routed to this pin. When Sequenced Down, this signal is forced to logic "0".

XRAM_OE0 (-RAM Output Enable 0)

This is a dual purpose signal that should be tied to pin 24 of the lower PSRAM chip. When Sequenced Up, this signal is mode dependent.

In 128K mode, this is the PSRAM read output enable line for the lower 128K PSRAM chip. It can only assert (active low) if the address is to the lower 128K and the 8032 -RD line asserts.

In 512K mode, this is the PSRAM read output enable AND the Refresh input. If this signal asserts by itself, then a refresh happens. If it asserts along with the -Chip Select pin, then a PSRAM read takes place. When Sequenced Down, this signal is forced to logic "0".

XRAM_WE0 (-RAM Write Enable 0)

This signal should tie to pin 29 of the low order PSRAM chip. A PSRAM write will be done when this signal asserts along with a valid chip select When Sequenced Up, this signal is the Write Enable to the PSRAMs in both modes. When Sequenced Down, this signal is a don't care.

XRAM_OE1 (-RAM Output Enable 1)

This is a dual purpose signal that should be tied to pin 24 of the upper PSRAM chip. When Sequenced Up, this signal is the Output Enable control for reads from the upper PSRAM chip in 128K mode. This signal is not used in 512K mode as there is no upper chip installed. When Sequenced Down, this signal is a don't care.

XRAM_WE1 (-RAM Write Enable 1)

This signal should tie to pin 29 of the high order PSRAM chip. A PSRAM write will be done when this signal asserts along with a valid chip select When Sequenced Up, this signal is the Write Enable to the upper PSRAM in 128K mode. (Note: The current design does not use an "upper" chip in 512K mode.) When Sequenced Down, this signal is a don't care.

XCE1 (-Chip Enable 1)

This is a dual purpose signal that should be tied to pin 22 of the PSRAM chips. When Sequenced Up, this signal enables the PSRAM chips to read and write in both modes. When Sequenced Down, this signal is forced to logic "1". The 512K PSRAM chip requires this line to be forced to logic "1" during power down data retention mode. This line is a don't care on 128K PSRAMs. CE2_A17 (+Chip Enable 2 or Address_bit_17)

This is a dual purpose signal that should be tied to pin 30 of the PSRAM chips. When Sequenced Up, this signal is mode dependent

In 128K mode, this signal is tied to +Chip Enable and it is always logic "1".

In 512K mode, Bit 17 from the Address Mux is routed to this pin.

XWRSTROB (-WRite STROBe)

During write, this is a shorter version of the 8032 write strobe. XWRSTROB is the timing signal used to write to PSRAMS. Data is written to PSRAM at the rising edge of XWRSTROB. This rising edge hits before the rising edge of the 8032 -WR to insure that any PSRAM data hold times are met.

Base Registers and Address Multiplexer

Pages 3 and 4 of the Gate Array schematics in Appendix A show the Base Registers and the PSRAM address Multiplexer. See above for a description of the Base Register functions. This section will deal with the circuitry.

The Base Registers are shown at the left of Page 2. The outputs of these registers pass through "AND" gates before going into the Adders. The AND gates allow the base register outputs to be quickly forced to all zeros at the Adder inputs.

The outputs of the Adders feed over to the MUX. This MUX places the results of the READ ADDERS on the PSRAM address pins most of the time by default. There is no way to know that the 8032 is going to do a write until the -WR strobe asserts. When -WR asserts, a flip flop switches the MUX over to the WRITE ADDER output. The read adder was chosen for the default value because RAM reads take a little longer than writes. The dual adders are there so that the write address is stable as soon as the -WR strobe asserts.

I.R. Receive Circuit

The I.R. Receive circuit has various modes of operation depending on whether the button on the remote is released or if it is continuously held down. This circuit is on page 5 of Appendix A.

When a valid code is clocked into the I.R. RECEIVE DATA REGISTER (0800R), the +IRR_VAL (IR Receive Valid) bit and the +VALTILRD (VALid TIL RD) bits will set. The +IRR_VAL bit will remain set until the remote button is released. There are 2
ways to clear the +VALTILRD bit. 1. Reading the I.R. RECEIVE DATA REGISTER will clear +VALTILRD. 2. If the remote button is released and then pressed again, then +VALTILRD will clear when the button is re-pressed.

+IRR_NC (I.R. RECEIVER NO CHANGE) will set the first time that the I.R. RECEIVE DATA REGISTER is read. It will remain set until the remote button is released.

+IRR_RDY goes high as soon as the remote button is pressed and stays set until released.

Security Clock Generator

The Security Clock Generator is at the lower middle of page 9 in Appendix A. This is a programmable clock generator for the Motorola Security Chip. The original spec for this clock was 5 MHz To allow for changing oscillator frequencies, this clock was made programmable.

Both the high time and the low time of this clock period can be programmed independently by writing to I/O address 3C00hex. The high time is set with the upper nibble while the lower nibble sets the low time. This time is in multiples of the input oscillator frequency.

The circuit works by loading the program nibbles into 74F169 type counters. These counters are set up as "down counters" and only one of them will decrement at any one time. After one counter reaches zero, the output will toggle, the counter will re-load and then the other counter will decrement. The inverters at the output of the program register set the initial value to "divide-by-7".

I.M. Serial Bus Circuit

The I.M. Bus is used to talk to the TPU 2740 chip. The I.M. bus circuit is shown in Figures. Refer to the I.M. bus specification for a detailed explanation of this bus. Briefly, the I.M. bus is a 3 wire serial communication bus. The 3
lines are called I.M._CLOCK, I.M._DATA and I.M._IDENTIFY. The DBE 1200 gate array is always the I.M. Bus Master and therefore always drives the I.M._CLOCK line. The I.M._DATA line is a bi-directional data line (Open Drain with an external pull up resistor). The I.M._IDENTIFY line is an output used to identify the "I.M. Address" and also to terminate the transfer. An "IM BUS WRITE" is a transfer out of the 8032 to the IM Slave. An "IM BUS READ" is into the 8032 from the IM Slave device.

I.M. bus transfers always start with a 1 byte address and then 1 or 2 bytes of data. . A bit called I1BYTE (3000W.0) determines how many data bytes to transfer. Another bit called WXR_BIT (3000W.1) determines if the transfer will be a read or a write. Page 11 of Appendix A shows the I.M. counter and control logic and Page 12 shows the I.M. Data Shift Registers.

I.M. Circuit Overview

The I.M. circuit is operated via the control and data registers. Here is a quick summary:

I.M. BUS ADDRESS REGISTER (2000W page 12 XL_IM_AD). The 8032 writes the 8 bit address of the slave device that communication should be established with here. This address is latched in the 74HCT273 in Figure and is transferred to the shift register when the transfer begins. It is not necessary to reload this register if the same address is accessed on two successive I.M. transfers. The byte written to this register will always be the first byte written out of the Gate Array for all I.M. transfers.

I.M. WRITE DATA 1 REGISTER (2400W page 12 XL_IM_D1). The byte contained in this register will be the 2nd byte shifted out onto the I.M. bus during I.M. Writes. This register must be reloaded after each transfer.

I.M. WRITE DATA 2 REGISTER (2800W page 12 XL_IM_D2). The byte contained in this register will be the 3rd byte shifted out during I.M. Writes, but only if the transfer length is set to 2 bytes. This register must be reloaded after each transfer.

I.M. READ DATA BYTE 1 (1000R page 12 XRD_BYT1). After a read transfer, this register will contain the incoming data byte. If it is a 1 byte read transfer, then the data will be in this register. If it is a 2 byte read transfer, then the second byte received will be in this register.

I.M. READ DATA BYTE 2 (1400R page 12 XRD_BYT2). After a 2 byte read transfer, this register will contain the first incoming data byte. During a I byte read transfer, the outgoing address will wrap back and end up in this register. This wrap feature can be used for error checking or diagnostics.

I.M. BUS CONTROL REGISTER. (3000W page 9 XIM_CTRL) Bit 1 of this register determines whether the transfer is read or write. Bit 0 of this register determines if 1 or 2 data bytes will be transferred.

I.M. BUS START TRANSFER REGISTER. (2C00W page 11 XSTRT_IM) Writing any value to this register will start the I.M. bus hardware.

I.M. BUS STATUS REGISTER. (1800R page 6 XSW_LO) Bit 7 of this register contains the +IM_BUSY line. This line will be high during the I.M. transfer.

I.M. Circuit Operation

The logic on page 11 controls the I.M. Bus transfers. The I.M. clock (IM_P_CK) and the 8032 input oscillator clk (OSC_2) are both derived from the 24 MHz oscillator. The 8032 does not specify any timing with respect to the input oscillator and the timing that is specified is very loose with respect to a 12 MHz input clock. For this reason, it must be assumed that the Start Transfer Pulse from the 8032 and the IM_P_CK are asynchronous. The first 3 flip flops at the lower left of Figure are used to re-synchronize these signals and to start the I.M. transfer.

After the transfer is started, the 74F269 counter on page 11 will start to count up from zero. The EN_IMCK line will allow the IM_P_CK to gate out to the I.M. bus clock pin 14. The first 8 clocks will clock out the address and the I.M._IDENTIFY line will assert during this time. When the counter reaches a count of 8, the I.M._IDENTIFY line will negate.

If an I.M. Write is in progress, then the I.M._DATA line will continue to be an output for the rest of the transfer. If an I.M. Read is in progress, the I.M._DATA line will switch from an output to an input after the 8th count. The transfer will abort after count 16 or count 24 depending on the state of the I1BYTE (3C00W.0) bit.

After all of the clocks have completed, the I.M._IDENTIFY line will briefly pulse low one more time to indicate that the transfer is complete. During this entire time, the IM_BUSY bit will be asserted and available to the 8032 as status. The IM_P_CLK is created by dividing the 24 MHz oscillator by 32. This yields a clock edge at about every 1.3 uS. A full 24 clock transfer takes about 32 uS.

Watchdog Timer

The Watchdog Timer is on page 13 of the Gate Array Schematic, Appendix A. This timer can be turned on and off with the bit EN_WDOG (3000W.7). The Watchdog is reset in normal operation by writing to address 6400W. The data written to this address is "don't care".

The Watchdog timer is 16 bits long and it is clocked by the OSC.sub.--256 clock. This timer was made out of synchronous counter blocks (I_SCBR) provided by the Gate Array vendor. The Watchdog starts at Zero and counts up. If it is allowed to overflow, then the reset line to the 8032 will assert. The Power on Reset line to the Gate Array will also assert. The 8032 reset line will assert about 256 clocks before the Gate Array POR internal reset asserts. The 8032 requires that a fixed number of Clocks be provided while the reset line is asserted in order to properly reset. The internal Gate Array POR line completely resets the Watchdog circuit, so it is necessary to delay these events for proper 8032 reset timing. NOTE: The Gate Array internal POR line completely resets the chip to a known state except for the OSC divider clocks on page 9 and the IM Read data registers on page 12.

CRC 32 Polynomial Circuit

The CRC-32 circuit is on pages 15 18 of the Gate Array Schematic. This circuit can be used to Check or Generate the CRC-32 Polynomial. This polynomial is four bytes long and is used to verify data integrity.

The circuit has two modes of operation, CRC-32 on and CRC-32 off. The bit X_EN_XOR (6000W.4) determines the mode. When this bit is logic "0", the CRC-32 logic is enabled and any data written to the CRC registers will be multiplied by the CRC-32
polynomial. When this bit is logic "1", the CRC-32 polynomial is disabled and the data shifts into the CRC-32 registers unaltered.

The circuit consists of four 8 bit Read Data Registers, one Write Data Register, the above mentioned control bit and control logic. Here is a summary of the registers.

CRC-32 READ REGISTER 3 (7000R)

CRC-32 READ REGISTER 2 (7400R)

CRC-32 READ REGISTER 1 (7800R)

CRC-32 READ REGISTER 0 (7C00R)

CRC-32 WRITE DATA REGISTER (6800W)

X_EN_XOR Control bit (6000W.4)

CRC 32 CIRCUIT OPERATION

Data is entered into the CRC circuit one byte at a time. This is done by writing the byte to the CRC-32 Write Data Register (6800W). After the 8032 completes the write, a hardware state machine will take the byte and shift it into the CRC circuit (This shift takes about 1.5 uS if the OSC is at 24 MHz.) When all of the bytes have been shifted in, the resultant can be read out of the four CRC-32 Read Registers. The CRC circuit can be turned off in order to initialize the four registers to a known value.

The CRC-32 Write Data Register is on page 18. This is a parallel in, serial out shift register. The end of the 8032-WR strobe will start the shift logic in page 15. This logic will synchronize the shift start to the OSC_2 clock A 3 bit counter will count out exactly 8 clocks, then shut the circuit off.

The X_EN_XOR bit can be used to initialize the CRC-32 circuit to a known value. Some CRC schemes start with all 32 bits set zero, others start with all bits set to one. When X_EN_XOR is set to logic "1", the CRC-32 circuit Exclusive-OR gates are all disabled. This allows the data written to the CRC-32 Write Data Register to enter the CRC-32 flip flop chain unaltered. This feature also allows for breaks in the CRC calculation. When a break occurs, the software could read and store the data in the four CRC-32 READ REGISTERS. At a later time, this data can then be reloaded back into these registers.

The CRC-32 polynomial is: x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. Gate Array Pinouts

Table V shows pinouts for the gate array

TABLE-US-00005 TABLE V shows the pinouts for the gate array PIN NO. PIN NAME PIN TYPE SPECIAL NOTES 1 GND1 POWER 2 VDD1 POWER 3 PRAM_A15 OUTPUT_2 drives psram address line 4 PRAM_Al6 OUTPUT_2 drives psram address line 5 PXRFSHI8 OUTPUT_2 drives psram rfsh in l28K mode, Al8 in 512K mode. 6 PTESTOUT OUTPUT_2 TEST OUTPUT 7 PBAND1 OUTPUT_1 output digital control bit. 8 PBAND0 OUTPUT_1 output digital control bit. 9 PIRR_DTA INPUT_1 IR input 10 PIRR_CLK INPUT_1 IR input 11 PIRR_RDY INPUT_1 IR input 12 P_XRESET INPUT_1 SYSTEM POWER ON RESET 13 P_IM_DTA I/O_1 IM bus data line, open drain 14 PIM_CLK OUTPUT_4 IM bus clk line, output only 15 PIM_IDEN OUTPUT_4 IM bus identify line 16 PXRAMWE1 OUTPUT_3 PSRAM #1 R/W line 17 PXRAMWE0 OUTPUT_3 PSRAM #0
R/W line 18 PRAM_A13 OUTPUT 2 drives psram address line 19 PRAM_A8 OUTPUT_2 drives psram address line 20 PRAM_A6 OUTPUT_2 drives psram address line 21 PRAM_A9 OUTPUT_2 drives psram address line 22 GND2 POWER 23 VDD2 POWER 24 PRAM_A5 OUTPUT_2 drives psram address line 25 PRAM_A11 OUTPUT_2 drives psram address line 26 PRAM_A4 OUTPUT 2 drives psram address line 27 PRAM_A10 OUTPUT 2 drives psram address line 28 PXRAMOE0 OUTPUT_3 PSRAM #0 output enable line 29 PXRAMOE1 OUTPUT_3 PSRAM #1 output enable line 30
PXCE1 OUTPUT_3 PSRAM chip select 31 P6805CLK OUTPUT_4 Security Micro Clock 32 POSC_2 OUTPUT_4 8032 microprocessor clock 33 P_XWR INPUT_1 8032 write strobe 34 P_XRD INPUT_1 8032 read strobe 35 PXISBINT OUTPUT_3 ISB interrupt line to 8032 36 PUPRESET OUTPUT_3 active high reset to 8032 37 PDRAM_EN INPUT_2 RAM enable bit 38 PXENBASE INPUT_2 Base Register enable bit 39 P_AD0 I/O_2 8032 data bus 40 P_AD1 I/O_2 8032 data bus 41 P_AD2 I/O_2 8032 data bus 42 P_AD3 I/O_2 8032 data bus 43 GND3 POWER 44 VDD3
POWER 45 P_AD4 I/O_2 8032 data bus 46 P_AD5 I/O_2 8032 data bus 47 P_AD6 I/O_2 8032 data bus 48 P_AD7 I/O_2 8032 data bus 49 P_ALE INPUT_1 8032 address latch enable 50 P_XPSEN INPUT_1 8032 program store enable 51 P_A15 INPUT_2 8032 upper address bus bit
52 P_A14 INPUT_2 8032 upper address bus bit 53 P_A13 INPUT_2 8032 upper address bus bit 54 P_A12 INPUT_2 8032 upper address bus bit 55 P_A11 INPUT_2 8032 upper address bus bit 56 P_A10 INPUT_2 8032 upper address bus bit 57 P_A9 INPUT_2 8032 upper address bus bit 58 P_A8 INPUT_2 8032 upper address bus bit 59 PIR_XCLK OUTPUT_4 2 or 4 MHz clk for IR transmitter 60 P_A0 OUTPUT_3 demultiplexed 8032 lower address bus bit 61 P_Al OUTPUT_3 demultiplexed 8032 lower address bus bit 62 P_A2 OUTPUT_3 demultiplexed
8032 lower address bus bit 63 P_A3 OUTPUT_3 demuluplexed 8032 lower address bus bit 64 GND4 POWER 65 VDD4 POWER 66 PXTAL1 OSC INPUT external crystal oscillator pin 67 PXTAL2 OSC OUT external crystal oscillator pin 68 P_A4 OUTPUT_3 demultiplexed 8032
lower address bus bit 69 P_A5 OUTPUT_3 demultiplexed 8032 lower address bus bit 70 P_A6 OUTPUT_3 demultiplexed 8032 lower address bus bit 71 P_A7 OUTPUT_3 demultiplexed 8032 lower address bus bit 72 PISB_CLK I/O_1 ISB clk line 73 PISB_DTA I/O_1 ISB data line 74 PBAND2 OUTPUT_1 output digital control bit. 75 P1378_IN INPUT_1 divide by 2275 clk input for MC1378 76 P13780UT OUTPUT_4 divide by 2275 output for MC1378 77 PPWM_OUT OUTPUT_4 Pulse Width Modulator output 78 PRF_SEL2 OUTPUT_ output digital control bit. 79 PRF_SELl OUTPUT_1 output digital control bit. 80 PRF_SEL0 OUTPUT_1 output digital control bit. 81 PRAM_A7 OUTPUT_2 drives psram address line 82 PRAM_A12 OUTPUT_2 drives psram address line 83 PCE2_A17 OUTPUT_2 PSRAM CE2 in 128K mode, A17 in 512K mode 84 PRAM_A14 OUTPUT_2 drives psram address line OUTPUT_1 = 4mA, NORMAL SPEED, (OUTPUT PORT CONTROL BITS) OUTPUT_2 = 2mA,, SLOW (10nS) RISE AND FALL TIMES. (PSRAM ADDRESS OUTPUTS) OUTPUT_3 = 2mA NORMAL SPEED OUTPUT. OUTPUT_4 = 4mA NORMAL SPEED OUTPUT. (Used for CLOCKS). Note: Outputs 1 and 2 grouped differently so output bit current can easily be changed between groups. INPUT_1 = TTL INPUT LEVELS WITH SCHMITT TRIGGER. INPUT_2 = TTL INPUT LEVELS. I/O_1 = 2mA OUTPUT DRIVER (with active high enable), OPEN DRAIN OR TRISTATABLE. INPUT IS TTL LEVEL I/O_2 = 2mA OUTPUT DRIVER (with active high enable). INPUT IS TTL LEVEL [data bus]

TPU 2740 Onscreen Controller 124

The TPU 2740 124 functions as an On Screen Display (OSD) controller and also as a Closed Caption Data (CCD) VBI Data Slicer. This device has two functionally separate sections, the OSD and the CCD VBI data slicer. The TPU 2740 contains a RISC based processor called the Fast Processor (FP) that is used to collect the VBI data, communicate with the serial bus, and control the OSD. Some of the internal TPU 2740 circuits are running at four times the input clock frequency (This is 72 MHz on the TVRO board with an 18 MHz input clock). Communications between the 8032 and the TPU2740 are via the 3 wire IM Serial Bus 108.

The TPU 2740 is a fully digital chip, Baseband Video data must first be digitized before the TPU can use it. A 6 bit Analog to Digital converter (uPC660) does this digitizing.

The uPC660 is shown on page 1 of the TVRO schemtics in Appendix A. The input video signal is about 1 Volt P-P and this signal must be "clamped" to a known DC level before it can be digitized. The "VIDEO CLAMP AND FILTER" on page 1 does this using a "Back Porch Clamp" method. This clamp will bias the video signal into the A/D converter so that the "Back Porch" area will be at about 3.69 Volts DC. (The "Back Porch" is the area where the color burst sits.) The resistor network on page 1
comprised of R15, R16, R17 and R18 sets the voltage levels for the clamp and the A/D circuits. The A/D upper reference (pin 11) is set to about 4.52 Volts and the lower reference (pin 13) is set to about 3.35 Volts. If the input video signal back porch area is biased to 3.69 Volts DC (at pin 12), then the maximum peak to peak swing of the video signal should always be between the voltages at the reference pins. The TPU only uses the incoming video signal to strip off VBI Closed Caption Data. There is no need for the entire 4 MHz video bandwidth so R7 and C6 form a low pass filter that rolls off the TPU video at about 1 MHz. (Note: The ratios of the clamp voltages are the same as the expected video signal IRE values.)

Circuitry in the TPU detects vertical and horizontal sync from the digitized video. The OSD and VBI data slicers use these signals for timing functions. A programmable comparator is used to detect vertical and horizontal sync pulses. It is important that the video clamp function correctly in order for this comparator to accurately detect sync. The FP reads the output of the sync detection circuitry and is able to count horizontal lines, thus is able to read VBI data from a particular VBI line and start the graphic on screen display at the correct video scan line. When a VBI signal that contains the proper lead in and framing data is detected, the VBI circuitry on the TPU will load the VBI data into internal registers that the FP may read. The FP reads this data and inserts it into a buffer. At a later time the VBI data may be read by the 8032 via the IM Bus.

The TPU requires good digitized video and a stable horizontal timing reference on pin 27. The horizontal rate signal is +Burst Gate from the MC1378 and is fed into the TPU at pin 27. If either of these signals is missing or poor, then the TPU will not be able to create a stable overlay.

The OSD portion of the TPU consists of cache memory, character memory, timing functions, and an external 256K by 4 bit DRAM (U9). The FP reads high level graphic commands from the IM Bus and stores the graphic information in the external DRAM memory. In conjunction with the cache memory, timing circuitry, and the character generation hardware, the TPU FP outputs the graphic data on the R, G, B, and FBLOUT lines. 8 colors may be generated using the R, G, and B outputs. The FBLOUT (Fast BLanking OUT) signal determines if the video output should contain the R, G, B data from the TPU, or if the incoming live video should be passed through.

The TPU has a 256K.times.4 DRAM (U9) for storing overlay screens and data. This is a fast page mode DRAM and refresh logic is avoided by constantly reading out the screen data, even when there is no overlay on the screen.

R,G,B Color Converter.

The StarSight Telecast graphic display requires 8 colors, black, white, gray, yellow, light yellow, light green, and red. These colors are not the standard 8 NTSC saturated colors that the TPU puts out. A "Color Converter Circuit" is required to translate the TPU saturated digital colors into the StarSight graphic display "pleasing" colors. This circuit is on page 2 of the PCB schematic. The Color Converter if made from three "8 into 1 analog switches". There is one switch for each of the R,G,B outputs. There is a precision voltage divider that creates the desired R,G,B voltages. The analog switches route the proper voltage to their outputs based on the 3 bit digital R,G,B signal from the TPU. The TPU R,G,B outputs are programmed to be open drain so that a full TTL level swing is available to the multiplexing analog switches. R14 and C18 on page 2 form an inexpensive R-C delay for the Fast Blanking Signal to compensate for delays in the R,G,B channel.

Overlay Generator and Video Synchronizer

The Motorola MC1378 is used as a main building block for the Video Synchronizer. The MC1378 operates in REMOTE MODE (pin 1 is set HIGH). In this mode, external video is required to create the synchronizing timing signals. See page 3 of the TVRO Schematic of Appendix A for a block diagram of the 1378.

A 1 volt peak to peak NTSC video signal must be fed into pin 24 to provide timing information for both the 1378 and the TPU.

The signal at pin 24 is the called the "Remote Video Signal". This signal is internally clamped in the 1378 and then Composite sync is separated out. Composite Sync is used to separate out Vertical Sync and also to lock the 4.03 MHz Horizontal Phase Locked Loop. Both Composite Sync (pin 39) and Vertical Sync (pin 38) are externally available for debug and timing.

The separated composite sync is used to lock the 4.03 MHz PLL (using PD1). The VCO in this PLL is formed around a 4.03 MHz ceramic resonator. The free running frequency of this ceramic resonator must be adjusted with C39. The best way to adjust this VCO is to use a frequency counter and adjust C39 until the frequency at U1 5 is 15,750 Hz. This adjustment is made with the Video In signal disconnected so that the VCO is free running.

The 4.03 MHz VCO output is divided by 256 to obtain horizontal frequency, and then further decoded to create "BURST GATE". Burst Gate (MC1378 pin 5) is about 4 uS wide and is centered around the 3.58 MHz color burst. This signal is the main timing reference for the overlay display. It is used extensively by both the 1378 and TPU 2740. The TPU uses Burst Gate to decide when to start the overlay. There is a programmable counter in the TPU that sets the delay from Burst Gate to the overlay start. (The overlay starts when +FBLOUT goes low.) Any jitter on Burst Gate will cause an annoying side to side motion on the overlay.

The color burst from the remote video is used to lock the 4X color sub carrier oscillator using PD3 which is gated by burst gate.

Phase of the locally generated composite video from the encoder section is compared against the same sub carrier reference used to lock PD3. This is done by means of PD4 so that the sub carrier phases of both the local and the remote signals are made essentially equal.

Phase detector operation summary:

1. PD1--compares and locks the internally counted down 4.03 MHz VCO to the incoming remote horizontal sync. It is fast acting to follow VCR source fluctuation. Its PLL filter network consists of C24, C38, and R19. 2. PD2--is not used in this design. 3. PD3--a gated phase detector, which locks the crystal oscillator frequency divided by four to the incoming remote signal burst. 4. PD4--controls the internal phase shifter to assure that the outgoing local color burst has the same phase as the incoming remote burst at PD3. 5. PD5--not used in this mode of operation Video paths inside the MC1378

The remote video is AC coupled and fed in through pin 24 and clamped to proper DC level (blanking is at 0 V). The clamped video is fed to the Fast Video Switch where switching between the local and the remote video occurs controlled by Overlay Enable at pin 25. The second path leads to the PD3 where the remote video burst is compared against crystal oscillator frequency divided by four. The third path leads to Identity Detector which determines whether incoming signal is PAL or NTSC.

The local video is generated from R, G, and B signals which are direct coupled, 1 volt peak to peak inputs at pins 14, 15, and 16. After that follows the Color Difference and Luma Matrix which produces B-Y, R-Y, and the luminance-Y signals. The B-Y and R-Y signals are clamped and sent to their respective modulators. Modulated B-Y and R-Y signals are summed together thus making 3.58 MHz NTSC chroma signal which is fed out pin 18. This chroma signal is filtered by a 3.58 MHz band-pass filter consisting of C33, C34, C35, R22, R13, and T1. The filtered chroma signal is fed back in at pin 20. At this point the chroma signal is added to the luminance signal which passes through a 400 nS delay line. The need for this delay line arises because of the longer path for the chroma signal through the modulators and the band-pass filter. The delay line should have at least 4 MHz bandwidth, and good linearity through its entire bandwidth as well as linear group delay. The chroma and luma signals combined make the composite NTSC video signal which is then clamped by the local video clamp and fed to the fast video switch to be mixed with the remote video at the output pin 27.

To keep the local video amplitude correct in respect to the remote video amplitude the two burst amplitudes are compared in the ACC detector and made equal using a variable gain ACC amplifier in the locally generated chroma path.

The absolute burst amplitude of the remote signal is detected by the kill detector, the chroma of the locally generated signal being tuned off when the remote burst falls below a predetermined level. The kill level can be adjusted by changing the value of the resistor R3 at pin 31. 470K kills at about 10 20 mVp-p remote burst. Normal burst is 286 mVp-p.

Power Supply

The system requires 5 VDC digital, 5 VDC analog, and possibly 12 VDC analog (for certain RF Modulators).

The current requirements are:

TABLE-US-00006 5 VDC Digital 550 mA 5 VDC Analog l50 mA 12 VDC Analog 80 mA

It is very important that the microprocessor -PWRBAD line is set to zero at least 10 mS before the 5 VDC Digital supply drops below 4.75 volts. This allows the microprocessor to complete any pending database transactions and do an orderly shutdown of the DRAM. This is accomplished by monitoring the unregulated power with the Seiko S80731AN power supervisor IC (U2). After the unregulated supply drops below about 8 volts, the S80731AN will assert -PWRBAD. This causes an interrupt in the microprocessor which will initiate power down subroutines. U3 monitors the 5VDC supply and controls the -RESET line into the DBE 1200. This generates a clean reset signal during power up and power down.

I.R. Transmitter 116.

The I.R. Transmitter 116 function is done with a MC68HC05C9 microprocessor. This microprocessor is programmed to interface with the software serial bus 110 for communication with the 8032. This microprocessor can generate pulses on its output pin that simulate IR signals for most VCR's. The ROM in the MC68HC05C9 contains the executable program and the codes and sequences to control a VCR via Infrared. . Port B on the MC68HC05C9 is used to set the serial address that it will respond to. The clock signal is generated by a programmable clock divider in the DBE1200 gate array.

FIG. 6 illustrates how packets 300, messages 302 and commands 304 are related FIG. 7 provides further details of packets 300. Unless otherwise noted, all fields are binary 2's complement numbers. All undefined bits within fields are reserved, and initialized to zero. All multi-byte variables are stored most significant byte first (big endian format), unless otherwise noted. Notable exceptions are the CRC16 and CRC32 fields, which are stored in reverse order, least significant byte first (little endian format).

All viewable text strings are comprised exclusively of printable characters, where printable is defined as any character with ASCII values in the range of 32 (20H) to 122 (07 AH), inclusive. Both upper and lower case letters are supported. All fixed fields which contain ASCII strings that do not fill the field are to padded with NULL (ASCII value 0) characters. Unless otherwise specified, strings which do fill the field are not NULL terminated.

Packets 300

Packets 300 consist of error detection information and information to be operated on by a subscriber unit. The packet fields shown in FIG. 7 have the following descriptions, as shown in Table VI:

TABLE-US-00007 TABLE VI Field Description sync Code number indicating the start of a Packet. Used to locate the start of a Packet when transmission errors occur. Value is always 2C(hex). size Is the total size of the packet, in bytes. This includes the `sync`, `size` `packet time stamp, `CRCl`, `Message`, and `CRC32` fields. There is no official maximum size for packets. All units which listen to packet streams should be prepared to ignore any packet that exceeds the maximum packet size the unit can handle. First generation Subscriber Units ignore any packet that is greater than 2048 Bytes in length, total. packet time stamp Is the four byte time stamp of the minute the packet was transmitted. This field is used by subscriber units to differentiate data streams on recoided mediums (such as VCR tapes) from live data streams. The time is encoded as minutes since January 1, 1992, rounded to the nearest minute boundary. Since packet headers are not guaranteed to be transmitted on minute boundaries, the maximum error of this field is up to +/-30 seconds. vbi Stream ID Is a two byte number identifying the unique ID of the VBI stream the command has been transmitted on. This field may be used by subscriber units to identify their assigned "home" data stream, where their key distribution message will be broadcast. CRCl Least significant word (16 bits) of the 32 bit cyclic redundancy code (CRC-32) value for the Packet header . The CRC is computed over the `sync` and `size` fields. This field is stored least significant byte first (little endian format). Message Information bearing portion of a Packet. Contains one or more Commands. Command An entity that contains information pertaining to a specific portion of the database, or time markers, or user authorization information. Each type of Command contains a unique code number and a length field. CRC32 32 bit cyclic redundancy check (CRC-32) value. The CRC is computed over the `sync`, `size`, `CRCl`, and `Message` fields. The CRC32 generator polynomial is x.sup.32 + x.sup.26 + x.sup.23 + x.sup.22 + x.sup.16 + x.sup.12 + x.sup.11 + x.sup.l0 + x.sup.8 + x.sup.7 + x.sup.5 + x.sup.4 + x.sup.2 + x.sup.1 + 1. This field is stored least significant byte first (little endian format).

Messages 302

Messages 302 are the information bearing portion of a Packet 300. As shown in FIG. 8, they consist of one or more Commands 304. Messages contain an integral number of Commands and Commands are not split between Messages. The `size` field in the packet header is used to determine when all Commands have been processed. The optimal size of the Message field is 250 bytes or less. Commands that are larger than 250 bytes should be contained singly in a packet. The bytes following the last byte in the last command is always the first byte of the CRC32 field.

Commands 304

Commands 304 are the elements of the StarSight Data Transmission Network requited to build a TV schedule database, maintain the current time of day, and handle user authorization and security issues.

The different Commands are distinguished by a unique value known as the `Cmd type`. It is contained in the least significant 6 bits of the Command's first byte. A total of 64 unique command types are possible. The second field is `Cmd length`, used to determine the byte size of the Command. The size includes the `Cmd type` and `Cmd length` fields. The `Cmd length` field may be a one or two byte quantity. Table 11 lists all commands and specifies the size of the `Cmd length` fields. Also included in this table is the encryption offset for the command. This concept is discussed in the section that follows this table.

TABLE-US-00008 TABLE VII COMMAMD SIZE FIELD ENCRYPTION COMMAND NAME CODE SIZE OFFSET Time Command 1 1 2 Daylight Saving Time Change Command 2 1 2 Region Command 3 2 10 (0AH) Channel Data Command 4 1 5 Show list Command 5 2 11 (0BH) Show Title Command 6 1 5 Reserved 7 1 2 Show Description Command 8 1 5 Reserved 9 1 2 Reserved 10(0AH) 1 2 Theme Category Command 11(0BH) 2 5 Theme Sub-Category Command 12(0CH) 2 5 Subscriber Unit Reset Command 13(0DH) 1 8 Authorization Command 14(0EH) 1 2 Reserved
15(0FH) 1 2 Reserved 16(10H) 1 2 Key Distribution Command 17(11H) 1 2 Reserved 18(12H) 1 2 Reserved 19(13H) 1 2 Sequence Number Command 20(14H) 1 2 Station Node Status Command 21(15H) 2 3 Long Assign IR Codes Command 22(16H) 2 18 (22H) Reserved 23(17H) 2
3 Subscriber Unit Command 24(18H) 2 9 Reserved 25(19H) 1 2 Reserved 26(1AH) 1 2 Reserved 27(1BH) 1 2 Reserved 28(1CH) 1 2 Reserved 29(1DH) 2 3 All Future Command Definitions 30 63(lEH 3FH) 2 3

Subscriber units that do not recognize a command type (as will happen in the future when new commands are implemented) must compute the Command length and skip over/ignore the command.

The most significant bit of the Command's first byte is a flag that signals whether the command is encrypted or not. When set, the command is encrypted, when clear, not encrypted. It is probable that the only commands which are passed to the Subscriber Unit in an encrypted format are Show list, Authorization, and Key Distribution Commands. The Subscriber Unit should however be prepared to decrypt any command.

The starting offset of the encrypted portion of the command is also listed in the previous table. Most commands leave a portion of their contents in the clear so that network entities which process the packet stream may filter out unneeded commands without decrypting the guts of the command. (Note that the encryption offset for future commands may be changed when the commands are actually implemented.)

The second most significant bit of the command's first byte indicates which of two program keys are to be used when decrypting the command When the bit is clear, decryption program key 0 is used, when set, key is to be used.

Since it is necessary to add an initialization vector and pad characters, the process of encrypting a command increases the amount of memory necessary for storing the command. The initialization vector is an 8 byte field that is always prepended to the start of the encrypted byte stream. The padding is appended to the byte stream before it is encrypted. The purpose of the padding is to help the Security Module determine if the encrypted data has been "tame" with. Enough pad characters are added to make the length of the raw data stream a multiple of eight. If the length begins as a multiple of eight, 8 pad characters are added. The value of the pad characters are the number of fill bytes that have been added; i.e., if 3 extra bytes are added to the command then each fill byte will have the value 3. The encrypted data within the Command is stored as shown in FIG. 9.

Future revisions of this command set may append field definitions onto existing commands. Command processors should be prepared to ignore all data that follows the last recognized field.

Some commands are addressed to particular units or groups of units. Units are addressed using a logical address that is comprised of two parts; the four byte batch number and the one byte unit number. The batch number is used as the group address, directing the command to a group of units that share the same batch number. A batch number of zero has a reserved meaning; it addresses all units. All other possible batch numbers are valid addresses. (i.e. a command transmitted with batch number=0 is intended as a system wide broadcast, while a command with batch address 23456 is directed towards units in batch group 23456 only. Units in other batch groups should ignore the latter command).

The unit number is used to identify a particular unit within the batch group. Up to 255 units may be contained within a batch group. The unit number of zero has the reserved meaning of addressing all unit's within a batch group. (i.e. a logical address with batch number=23456, unit number=0 is directed to all units within the batch group 23456).

Commands required to build the subscriber unit database are typically sent repetitively, in the order shown in Table VIII:

Theme Categories Always acquired (if not already acquired).

Theme Subcategories Always acquired (if not already acquired).

TABLE-US-00009 TABLE VIII Regions Region's list of channels is acquired if the unit has been authorized. Channel Channel data is acquired if the channel is in the region's list Data of channels. Show Show list is acquired if it is applicable to an active channel in lists the region's list of channels. Show lists give the schedule data for a single channel for a single day. The current day's data is sent more often than succeeding day's data. Show Show title is acquired if it is referenced in some acquired Titles Show list and the subscriber unit does not already have it. Show Show description is acquired if it is referenced in some Descrip- acquired Show list and the subscriber unit does not already tions have it. Key Key distribution commands are always processed, if the Distri- batch address of the command matches the unit's assigned butions batch address.

Other messages are interspersed in this cyclic stream on a random basis as required. Note that transmission errors can cause missing messages and commands can therefore be received out of order. Note especially that there can be gaps in the Show lists. Subscriber units must be able to handle missing and out of order messages.

The following sections describe each command. Commands are shown in their non-encrypted form, but the reader must be aware that the above mentioned modifications due to encryption may be made to any command.

Time Command

Time Commands (FIG. 10) specify the current time of day and date. They are sent periodically, at a predetermined rate. Subscriber Units 52 (FIGS. 1 4) should reset their current time of day and date to agree with the value received in this message.