Electronic design for integrated circuits based process related variations


United States Patent		7200823
White , ; et al.		April 3, 2007

	*Title*

Electronic design for integrated circuits based process related variations

	*Abstract*

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.



Inventors:	White; David (Cambridge, MA), Smith; Taber H. (San Jose, CA)
Assignee:	Praesagus, Inc. (Cambridge, MA)
Appl. No.:	10/321,290
Filed:	December 17, 2002
PCT Pub Date:	April 3, 2007

Current U.S. Class:			716/4 716/5 716/19 716/21
Current International Class:			G06F 17/50 (20060101)
Field of Search:			716/4-5,19-21 430/5 438/14

	U.S. Patent Documents
20010031506	October 2001	Plat et al.
20010052107	December 2001	Anderson et al.
20020045110	April 2002	Ohnuma
20020083401	June 2002	Breiner et al.
20020106837	August 2002	Cleeves et al.
20020157076	October 2002	Asakawa
20020162082	October 2002	Cwynar et al.
20030084416	May 2003	Dai et al.
20030107134	June 2003	Lee
20030199150	October 2003	Permana et al.
20030228714	December 2003	Smith et al.
20030229410	December 2003	Smith
20030229479	December 2003	Smith et al.
20030229875	December 2003	Smith et al.
20040044984	March 2004	Keogan et al.
20040058255	March 2004	Jessen et al.
20040076896	April 2004	Kim et al.
20040107410	June 2004	Misaka et al.
20050037522	February 2005	Smith et al.
20050132306	June 2005	Smith et al.
20050196964	September 2005	Smith et al.
20050235246	October 2005	Smith et al.
20050289500	December 2005	Misaka et al.
5124927	June 1992	Hopewell
5581475	December 1996	Majorss
5597668	January 1997	Nowak et al.
5663076	September 1997	Rostoker et al.
5705301	January 1998	Garza et al.
5763955	June 1998	Findley et al.
5798298	August 1998	Yang et al.
5821621	October 1998	Jeng
5854125	December 1998	Harvey
5861342	January 1999	Gabriel et al.
5903469	May 1999	Ho
5920487	July 1999	Reich et al.
5923563	July 1999	Lavin et al.
5923947	July 1999	Sur
5948573	September 1999	Takahashi
5972541	October 1999	Sugasawara et al.
6049789	April 2000	Frison et al.
6081272	June 2000	Morimoto
6093631	July 2000	Jaso
6109775	August 2000	Tripathi et al.
6118137	September 2000	Fulford et al.
6124197	September 2000	Fulford
6157947	December 2000	Watanabe et al.
6176992	January 2001	Talieh
6230299	May 2001	McSherry et al.
6249904	June 2001	Cobb
6255125	July 2001	Schmidt et al.
6259115	July 2001	You et al.
6263476	July 2001	Browen et al.
6289499	September 2001	Rieger et al.
6309956	October 2001	Chiang et al.
6323113	November 2001	Gabriel et al.
6327555	December 2001	Shimizu et al.
6328872	December 2001	Talieh et al.
6343370	January 2002	Taoka et al.
6344409	February 2002	Jaso et al.
6352623	March 2002	Volodarsky et al.
6355387	March 2002	Fujinaga et al.
6380087	April 2002	Gupta et al.
6396158	May 2002	Travis
6486066	November 2002	Cleeves et al.
6539321	March 2003	Bruce et al.
6550041	April 2003	McBride
6556884	April 2003	Miller et al.
6556947	April 2003	Scheiner et al.
6562639	May 2003	Minvielle et al.
6567964	May 2003	Shin et al.
6578174	June 2003	Zizzo
6578188	June 2003	Pang et al.
6611045	August 2003	Travis et al.
6613688	September 2003	Brown et al.
6625801	September 2003	Pierrat et al.
6651226	November 2003	Plew et al.
6665856	December 2003	Pierrat et al.
6691297	February 2004	Misaka et al.
6704920	March 2004	Brill et al.
6708129	March 2004	Pasadyn et al.
6708318	March 2004	Satoh et al.
6742165	May 2004	Lev et al.
6751785	June 2004	Oh
6781570	August 2004	Arrigo et al.
6866974	March 2005	Kim et al.
6873720	March 2005	Cal et al.
6893800	May 2005	Jessen et al.
6904581	June 2005	Oh

	Foreign Patent Documents
0 453 753	Oct., 1991	EP
03/079240	Sep., 2003	WO
2003/079240	Sep., 2003	WO

	Other References
Conrad et al., "Model Considerations, Calibration Issues, and Metrology Methods for Resist-Bias Models", in Metrology, Inspection, and Process Control for Microlithography XIII, ed. by B. Singh, Proc. SPIE 3677, pp. 940-955 (1999). cited by other . Baker, "Using Calibre In A Design for Manufacturing Environment", Deep Submicron Technical Publication, Mentor Graphics, Sep. 2001. cited by oth- er . Ouma et al., "An Integrated Characterization and Modeling Methodology for CMP dielectric Planarization," Proc. Of Interconnect Technology Conference, pp. 67-69, Feb. 1998. cited by other . Lee et al., "Analyzing The Effects of Floating Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Extraction," Proc. Of IEDM 2001, Dec. 2001. cited by other . Slide Presentation Exhibit A. cited by other . Slide Presentation Exhibit B1. cited by other . Slide Presentation Exhibit B2. cited by other . Praesagus Business Plan, Exhibit C. cited by other . Boning, Duane et al., "Statistical metrology of interlevel dielectric thickness variation," Proceedings of the SPIE Symposium on Microelectronic Manufacturing, Oct. 1994, SPIE vol. 2334, pp. 316-327. cited by other . Boning, Duane et al., "Models for Pattern Dependencies: Capturing Effects in Oxide, STI, and Copper CMP," Jul. 17, 2001, Semicon West. cited by oth- er . Boning, D. et al, "Pattern Dependent Modeling for CMP Optimization and Control," MRS Spring Meeting, Proc. Symposium P: Chemical Mechanical Polishing, San Francisco, CA, Apr. 1999. cited by other . Boning, Duane S. et al., "A General Semiconductor Process Modeling Framework," IEEE Transactions on Semiconductor Manufacturing, vol. 5, No. 4, Nov. 1992, pp. 266-280. cited by other . Chen, Yu et al., "Monte-Carlo Algorithms for Layout Density Control," Asia and South Pacific Design Automation Conference, Jan. 2002, pp. 523-528. cited by other . Chen, Yu et al., "Hierarchical Dummy Fill for Process Uniformity," Asia and South Pacific Design Automation Conference, Jan. 2001, pp. 139-144. cited by other . Chen, Yu et al., "Practical Iterated Fill Synthesis for CMP Uniformity," ACM/IEEE Design Automation Conference, Jun. 2000, pp. 671-674. cited by other . Davis, Joseph C. et al., "Automatic Synthesis of Equipment Recipes from Specified Wafer-State Transitions," IEEE Transactions on Semiconductor Manufacturing, vol. 11, No. 4, Nov. 1998, pp. 527-536. cited by other . Hosack, Harold H. et al., "Recent Advances in Process Synthesis for Semiconductor Devices" IEEE Transactions on Electron Devices, vol. 45, No. 3, Mar. 1998, pp. 626-633. cited by other . Kahng, Andrew B. et al., "New and Exact Filling Algorithms for Layout Density Control," UCLA Department of Computer Science, Los Angeles, CA, 1999. cited by other . Kahng, Andrew B. et al., "Filling and Slotting: Analysis and Algorithms," International Symposium of Physical Design, Monterey, CA, 1998, pp. 95-102. cited by other . Kahng, Andrew B. et al., "New Multilevel and Hierarchical Algorithms for Layout Density Control," UCLA Department of Computer Science, Los Angeles, CA, 1999. cited by other . Kahng, Andrew B. et al., "Filling Algorithms and Analyses for Layout Density Control," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 4, Apr. 1999, pp. 445-462. cited by other . Kim, Yoo-Hyon et al., "CHAMPS (CHemicAl-Mechanical Planarization Simulator)," International Conference on Simulation of Semiconductor Processes and Devices, Seattle, WA, Sep. 6-8, 2000. cited by other . Lee, Keun-Ho, "Analyzing the Effects of Floating Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Extraction," Samsung Electronics Co., Ltd, Korea, 2001. cited by other . Lee, Brian et al., "Using Smart Dummy Fill and Selective Reverse Etchback for Pattern Denisty Equalization," Proc. CMP-MIC, Santa Clara, CA, Mar. 2000, pp. 255-258. cited by other . McGhee, John et al., "The MMST Computer-Integrated Manufacturing System Framework," IEEE Transactions of Semiconductor Manufacturing, vol. 7, No. 2, May 1994, pp. 107-116. cited by other . Mehrotra, V. and Duane Boning, "Technology Scaling Impact of Variation on Clock Skew and Interconnect Delay," International Interconnect Technology Conference (IITC), San Francisco, CA, Jun. 2001. cited by other . Mehrotra, V. et al., "A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance," Design Automation Conference, Los Angeles, CA, Jun. 2000. cited by other . Mehrotra, V. et al., "Modeling the Effects of Manufacturing Variation on High-Speed Microprocessor Interconnect Performance," Annual ACM IEEE Design Automation Conference, Los Angeles, CA, 2000, pp. 168-171. cited by other . Moyne, William Patrick, "Enhancing MEMS Design Using Statistical Process Information," Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, Apr. 7, 2000. cited by other . Ouma, Dennis et al., "An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization," International Interconnect Technology Conference, San Francisco, CA, Jun. 1998. cited by other . Park, Jin-Kun, "An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing an Efficient Field Solving Algorithm," International Conference on Simulation of Semiconductor Processes and Devices, 2000, pp. 98-101. cite- d by other . Park, Tae H. et al., "Pattern Dependent Modeling of Electroplated Copper Profiles," International Interconnect Technology Conference (IITC), Jun. 2001. cited by other . Park, T. et al., "Electrical Characterization of Copper Chemical Mechanical Polishing," SEMATECH, Austin, TX, Feb. 1999. cited by other . Park, T. et al., "Pattern and Process Dependencies in Copper Damascene Chemical Mechanical Polishing Processes," VLSI Multilevel Interconnect Conference (VMIC), Santa Clara, CA, Jun. 1998. cited by other . Peters, Laura, "Removing Barriers to Low-k Dielectric Adoption," Semiconductor International, May 1, 2002. cited by other . Sakurai, Takayasu, "Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's," IEEE Transactions on Electron Devices, vol. 40, No. 1, Jan. 1993. cited by other . Saxena et al., "A methodology for the top-down synthesis of semiconductor process flows," Proc. 3rd IEEE/SEMI Int. Symp. Semiconductor Manufacturing, pp. 36-40, 1995. cited by other . Singer, Peter, "Progress in Copper: A Look Ahead," Semiconductor International, May 1, 2002. cited by other . Smith, Taber H., Thesis entitled "Device Independent Process Control of Dielectric Chemical Mechanical Polishing", MIT, Sep. 27, 1999. cited by other . Smith, Taber H. et al., "A CMP Model Combining Density and Time Dependencies," Proc. CMP-MIC, Santa Clara, CA, Feb. 1999. cited by other . Stine, Brian E., Thesis entitled "A General Methodology for Assessing and Characterizing Variation in Semiconductor Manufacturing", MIT, Sep. 1997. cited by other . Stine, Brian E. and Rakes Vallishayee, "On the Impact of Dishing in Metal CMP Processes on Circuit Performance," International Workshop on Statistical Metrology Technical Papers, 1998, pp. 64-67. cited by other . Stine, Brian E. et al., "A Simulation Methodology for Assessing the Impact of Spatial/Pattern Dependent Interconnect Parameter Variation on Circuit Performance," 1997 International Electron Devices Meeting, Washington, D.C., Dec. 1997, pp. 133-136. cited by other . Stine, B. et al, "A Closed-From Analytic Model for ILD Thickness Variation in CMP Processes," Proc. CMP-MIC, Santa Clara, CA, Feb. 1997. cited by other . Stine, Brian E. et al., "The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes," IEEE Transactions of Electron Devices, vol. 45, No. 3, Mar. 1998, pp. 665-679. cited by other . Tugbawa, Tamba et al., "A Mathematical Model of Pattern Dependencies in Cu CMP Processes," CMP Symposium, ELectrochemical Society Meeting, Honolulu, HA, Oct. 1999. cited by other . Tugbawa, Tamba E. et al., "Integrated Chip-Scale Simulation of Pattern Dependencies in Copper Electroplating and Copper Chemical Mechanical Polishing Processes," International Interconnect Technology Conference, San Francisco, CA, Jun. 2002. cited by other . Tugbawa, Tamba et al., "Framework for Modeling of Pattern Dependencies in Multi-Step Cu CMP Processes," SEMICON West 2000, Jul. 11, 2000. cited by other . Tugbawa, Tamba et al., "Modeling of Pattern Dependencies for Multi-Level Copper Chemical-Mechanical Polishing Processes," Materials Research Society Spring Meeting, San Francisco, CA, Apr. 2001. cited by other . Tuinhout, Hans P. and Maarten Vertregt, "Characterization of Systematic MOSFET Current Factor Mismatch Caused by Metal CMP Dummy Structures," IEEE Transactions on Semiconductor Manufacturing, vol. 14, No. 4, Nov. 2001, pp. 302-312. cited by other . Zaman, Mohammed H. et al., "Automatic Generation of Thin Film Process Flows--Part I: Basic Algorithms," IEEE Transactions on Semiconductor Manufacturing, vol. 12, No. 1, Feb. 1999, pp. 116-128. cited by other . Zaman, Mohammed H. et al., "Automatic Generation of Thin Film Process Flows--Part II: Recipe Generation, Flow Evaluation, and System Framework," IEEE Transactions on Semiconductor Manufacturing, vol. 12, No. 1, Feb. 1999, pp. 129-138. cited by other . "MIT Statistical Metrology," Publications List, http://www-mtl.mit.edu/Metrology/PAPERS/, 1994-2003. cited by other . Tian et al., "Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability", Proceedings of the 37.sup.th Design Automation Conference, pp. 667-670, 2000. cited by other . U.S. Appl. No. 10/615,214, filed Jun. 7, 2002, Lynne Ann Gurley, Awaiting Action. cited by other . U.S. Appl. No. 10/946,810, filed Sep. 22, 2004, Continuation of 10/165,214; Awaiting Action. cited by other . U.S. Appl. No. 10/947,500, filed Sep. 22, 2004, Continuation of 10/165,214; Awaiting Action. cited by other . U.S. Appl. No. 10/947,195, filed Sep. 22, 2004, Continuation of 10/165,214; Awaiting Action. cited by other . U.S. Appl. No. 10/164,844, filed Jun. 7, 2002, Sun J. Lin, Pending. cited by other . U.S. Appl. No. 10/164,847, filed Jun. 7, 2002, Evan Pert, Allowed. cited by other . U.S. Appl. No. 10/164,842, filed Jun. 7, 2002, Stacy Whitmore, Abandoned in Favor Cont. 11/142,606. cited by other . U.S. Appl. No. 11/142,606, filed May 31, 2005, Awaiting Action. cited by other . U.S. Appl. No. 10/200,660, Jul. 22, 2002, Paul Rodriguez, Pending. cited by other . U.S. Appl. No. 10/321,283, filed Dec. 17, 2002, Awaiting Action. cited by other . U.S. Appl. No. 10/321,298, filed Dec. 17, 2002, Sun J. Lin, Allowed. cited by other . U.S. Appl. No. 10/321,281, filed Dec. 17, 2002, Stacy Whitmore, Allowed. cited by other . U.S. Appl. No. 10/321,777, filed Dec. 17, 2002, Binh C. Tat, Awaiting Action. cited by other . U.S. Appl. No. 10/321,290, filed Dec. 17, 2002, Awaiting Action. cited by other . U.S. Appl. No. 11/005,651, filed Dec. 6, 2004, Awaiting Action. cited by other.~


Primary Examiner:	Dinh; Paul
Attorney, Agent or Firm:	Bingham McCutchen LLP


	*Parent Case Text*

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation in part of, and claims the benefit of priority of, U.S. patent application Ser. Nos. 10/165,214, 10/164,844 now U.S. Pat. No. 7,124,386, 10/164,847, and 10/164,842 now abandoned, all filed Jun. 7, 2002, and Ser. No. 10/200,660, filed Jul. 22, 2002, all assigned to the same assignee as this patent application. The contents of those patent applications are incorporated by reference here.


	*Claims*

The invention claimed is: 1. A method comprising enabling a generation of an electronic design using a pattern-dependent model to predict thickness or topographical variation within an integrated circuit that is to be fabricated in accordance with the electronic design by a method that includes (a) a fabrication process that will impart thickness or topographical variation with respect to the integrated circuit, and (b) a lithography or etch process that will form shapes or patterns of conductive and/or non-conductive features corresponding to the electronic design on a surface and making the predicted thickness or topographical variation available to the pattern-dependent model for predicting width variation in features that correspond to the electronic design for use in evaluating or adjusting the electronic design, in which the width variation comprises at least one of the shapes or patterns having an intended width dimension which corresponds to a predicted different width dimension based upon interaction between the lithography or etch process and the thickness or topographical variation at different locations on a die. 2. The method of claim 1 in which enabling the generation also includes using optical proximity correction to adjust the design for optical interference effects. 3. The method of claim 1 in which the electronic design is associated with electrical characteristics that include at least one of sheet resistance, capacitance, drive current, signal integrity, power distribution, and timing closure. 4. The method of claim 1 in which the feature width variations are associated with at least one of printed feature widths, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss. 5. The method of claim 1 also including using a place and route tool to create the electronic design. 6. The method of claim 1 also including using a resistance and capacitance (RC) extraction tool in connection with adjusting the electronic design. 7. The method of claim 1 also including using an electronic design automation simulation tool in connection with creating the electronic design. 8. The method of claim 1 also including verifying the electronic design using a physical verification tool. 9. The method of claim 1 also including adjusting the electronic design based on use of an optical proximity correction (OPC) tool. 10. The method of claim 1 also including verifying the electronic design using a signal integrity tool. 11. The method of claim 1 also including ensuring the manufacturability of the electronic design. 12. The method of claim 1 also including improving the electrical performance of an electronic representation of the integrated circuit. 13. The method of claim 1 also including improving the electrical performance of an electronic design layout of the integrated circuit. 14. The method of claim 1 also including modifying a formatted file of the electronic design, the file format conforming to a file format used by an EDA tool. 15. The method of claim 14 in which the file format comprises a Graphical Data Stream (GDS) format. 16. The method of claim 1 also including adjusting the electronic design to improve manufacturability of the integrated circuit. 17. The method of claim 1 also including adjusting the electronic design based on the predicted width variation to improve circuit performance. 18. The method of claim 1 in which enabling the generation of the electronic design includes predicting topographical variations with respect to an interconnect level. 19. The method of claim 1 in which enabling the generation of the electronic design includes predicting topographical variations for multiple levels to electrically characterize or simulate multiple interconnect levels. 20. The method of claim 1 also including determining placement of dummy fill or slotting structures based on the predictions. 21. The method of claim 1 also including determining the placement of electrical components in the integrated circuit. 22. The method of claim 1 also including determining the routing of interconnect regions between electrical components of the integrated circuit. 23. The method of claim 1 in which the integrated circuit comprises a system-on-chip (SoC) device and the method also includes determining the routing of interconnect regions in the SoC device. 24. The method of claim 1 also including determining geometry of electrical features, interconnect lines, or vias in the design of the integrated circuit. 25. The method of claim 1 also including using an electronics design automation (EDA) tool in conjunction with the predicting. 26. The method of claim 1 in which the generation is enabled as a service in a network. 27. The method of claim 26 in which the network comprises an intranet, an extranet, or an internet, and the generating is provided in response to user requests. 28. The method of claim 1 also including enabling a use of an RC extraction tool in conjunction with the electronic design. 29. The method of claim 28 in which the generating is performed on sub-portions of the circuit. 30. The method of claim 28 in which the width variations are associated with at least one of printed feature width, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss. 31. The method of claim 28 in which the electronic design is associated with at least one of sheet resistance, capacitance, drive current, signal integrity, power distribution and, timing closure. 32. The method of claim 28 in which the generation is enabled as a service in a network. 33. The method of claim 32 in which the network comprises an intranet, an extranet, or an internet, and the generation is enabled in response to user requests. 34. The method of claim 1 also including adjusting the electronic design based on the width variation prediction.


	*Description*

BACKGROUND This description relates to lithography mask creation for integrated circuits (ICs). Lithography mask creation and printing assume that projection is done on a film, within a predetermined depth of focus range. However pattern dependencies between the process by which the ICs are fabricated and the pattern that is being created often cause processed films to have significant variation in thickness across a surface, resulting in variation in feature dimensions (e.g. line widths) of integrated circuits (ICs) that are patterned using the mask. As successive non-conformal layers are deposited and polished, the variation becomes worse. Because interconnect lines and connections on higher layers carry power to portions of the chip, the variations can increase the sheet resistance and thus affect the power effectiveness of the chip. One way to reduce the variations in fabricated chips is to make physical measurements on manufactured wafers containing initial designs of devices and use these measurements to adjust the mask design. Other methods to reduce variation include optical proximity correction (OPC) where subwavelength distortions due to patterned features are identified and corrected. SUMMARY In general, in one aspect, the invention features a method comprising generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit, the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. Implementations of the invention may include one or more of the following features. The generating includes using optical proximity correction to adjust the design for optical interference effects. The electronic design is associated with electrical characteristics that include at least one of sheet resistance, capacitance, drive current, signal integrity, power distribution, and timing closure. The feature dimension variations are associated with at least one of printed feature widths, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss. A place and route tool is used to create the electronic design. A resistance and capacitance (RC) extraction tool is used in connection with adjusting the electronic design. An electronic design automation simulation tool is used in connection with creating the electronic design. The electronic design is verified using a physical verification tool. The electronic design is adjusted based on use of an optical proximity correction (OPC) tool. The electronic design is verified using a signal integrity tool. The manufacturability of the electronic design is ensured. The electrical performance of an electronic representation of the integrated circuit is improved. The electrical performance of an electronic design layout of the integrated circuit is improved. A formatted file is modified based on the adjusting of the electronic design, the file format conforming to a file format used by an EDA tool. The file format comprises a Graphical Data Stream (GDS) format. The adjusting of the electronic design includes improving manufacturability of the integrated circuit. The adjusting of the electronic design includes modifying the design to improve circuit performance. The generating of the electronic design includes predicting topographical variations with respect to an interconnect level. The generating of the electronic design includes predicting topographical variations for multiple levels to electrically characterize or simulate multiple interconnect levels. The placement of dummy fill or slotting structures is determined based on the determining of the impact. The placement of electrical components in the integrated circuit is determined. The routing of interconnect regions between electrical components of the integrated circuit is determined. The integrated circuit comprises a system-on-chip (SoC) device and the method also includes determining the routing of interconnect regions in the SoC device. The geometry of electrical features, interconnect lines, or vias in the design of the integrated circuit is determined. An electronics design automation (EDA) tool is used in conjunction with the predicting and the determining. The generating is provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the generating is provided in response to user requests. In general, in another aspect, the invention features a method comprising generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit, the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model, and using an RC extraction tool in conjunction with generating and adjusting the electronic design. In general, in another aspect, the invention features a method comprising generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit, the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model, and using an RC extraction tool in conjunction with generating and adjusting the electronic design. Implementations of the invention may include one or more of the following features. The generating is performed on sub-portions of the circuit. The feature dimensions are associated with at least one of printed feature width, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss. The electrical characteristics comprise at least one of sheet resistance, capacitance, drive current, signal integrity, power distribution and, timing closure. The generating is provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the generating is provided in response to user requests. In general, in another aspect, the invention features a method comprising generating an electronic design for an integrated circuit that is to be fabricated in accordance with a design by a process that will impart feature dimension variations to the integrated circuit, using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process. In general, in another aspect, the invention features using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process, and determining placement attributes for elements of the integrated circuit based on the predicted characteristics. Implementations of the invention may include one or more of the following features. The placement attributes comprise attributes of buffer regions for interconnect vias and lines determined during a place and route step in the design. The predicted characteristics comprise width variation or topographical variation, and the placement attributes comprise the placement locations of electrically active features or components. The predicted characteristics comprise width variation or geographical variation, and the placement attributes comprise the routing of interconnect features across the integrated circuit. The predicted characteristics comprise placement of dummy or slotting structures. The predicted characteristics comprise geometries of dummy or slotting structures. In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict electrical feature geometries of an integrated circuit that is to be fabricated in accordance with a design by a process, the prediction of electrical feature geometries being based on width variations or topographical variations produced by the process. Implementations of the invention may include one or more of the following features. The design is modified to improve circuit performance of the electrical features or to improve structural or reliability characteristics of the electrical features. Other advantages and features of the invention will become apparent from the following description and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates how lithography works. FIG. 2 describes the process for using IC designs and patterns to create lithography masks. FIG. 3 illustrates a case in which the focal distance to an alignment key is proper; but chip-level variation is outside the depth of focus limits. FIG. 4 shows where lithography fits within a damascene process. FIG. 5 illustrates pattern dependencies for electroplated copper deposition (ECD). FIG. 6A illustrates film thickness variation that results from oxide chemical mechanical polishing (CMP). FIG. 6B illustrates erosion, dishing and corner rounding effects associated with a CMP step used in a process of forming of shallow trench isolation (STI). FIG. 6C illustrates copper dishing, dielectric erosion and residual copper effects associated with a copper CMP step used in damascene processes. FIG. 7A illustrates a top-down view of different density features within a squareregion. FIG. 7B illustrates the variation in oxide thickness for features within a region. FIG. 8 illustrates how surface topography may affect printed feature dimensions. FIG. 9 illustrates how feature density may affect printed feature dimensions. FIG. 10A provides a high-level flow diagram of a method. FIG. 10B provides a high-level flow diagram of a method for design verification FIG. 10C provides a high-level flow diagram of a method for mask correction FIG. 11 describes an application in which designs are modified to meet desired printed or etched feature dimensions. FIG. 12 describes an application in which designs are not modified to meet desired printed or etched feature dimensions. FIG. 13A describes steps commonly used for layout generation. FIG. 13B describes steps commonly used for layout generation when design verification is inserted into the design flow. FIG. 14A illustrates the steps involved in layout extraction. FIG. 14B illustrates a continuation of the steps involved in layout extraction. FIG. 14C illustrates a continuation of the steps involved in layout extraction. FIG. 15 illustrates the relationship between spatial regions across the chip and the creation of a layout extraction table. FIG. 16 describes a process model component. FIG. 17A illustrates the use of product wafers in calibrating a tool for a particular recipe. FIG. 17B illustrates the use of test wafers in calibrating a tool for a particular recipe. FIG. 18 illustrates how a calibration is used to map layout features to film thickness variation. FIG. 19A illustrates the use of a calibration mapping to predict film thickness variation for an IC design. FIG. 19B illustrates how wafer-state parameters, such as film thickness variation, can be used to predict electrical parameters. FIG. 20 illustrates steps in a calibration process. FIG. 21A illustrates steps in a prediction of full-chip topography. FIG. 21B illustrates a continuation of the steps in prediction of chip topography. FIG. 21C illustrates a continuation of the steps in prediction of chip topography. FIG. 21D illustrates a continuation of the steps in prediction of chip topography FIG. 22A illustrates an overview of a prediction of feature dimensions (e.g. line widths) resulting from lithography process steps or flows. FIG. 22B illustrates a mapping provided by a etch prediction component FIG. 23 illustrates a mapping provided by a lithography prediction component FIG. 24 illustrates steps in generating a feature dimension variation prediction with regard to variation in chip topography FIG. 25 illustrates steps in generating a feature dimension variation prediction with regard to variation in chip feature density FIG. 26A illustrates the use of test wafers to calibrate a lithography model to a particular tool and recipe. FIG. 26B illustrates the use of calibrated lithography models to predict feature dimension variation. FIG. 27 illustrates steps in using calibrated lithography models to predict feature dimension variation. FIG. 28 illustrates an overview of a verification and correction component. FIG. 29A illustrates steps in verification option A. FIG. 29B illustrates steps in verification option B. FIG. 29C illustrates steps in verification option C. FIG. 29D illustrates steps in verification option D. FIG. 30 illustrates an overview of a correction component. FIG. 31 illustrates steps to compute modifications to a layout. FIG. 32 illustrates the steps to compute modifications to a layout using test wafer data. FIG. 33A illustrates a relationship between process model predictions of surface topography and a prediction of feature dimension using a lithography model component. FIG. 33B illustrates a use of errors in predicted versus desired dimensions to modify features in a layout to improve printed feature dimensions. FIG. 34A illustrates a process for computing relationships among feature width, feature space, density or height. FIG. 34B illustrates how surface topography is related to design parameters, such as feature width, feature space and density before input into a lithography model. FIG. 34C illustrates how test wafers may be used to compute mathematical relationships between feature width, feature space, and density for a given height or thickness. FIG. 35 illustrates how a process may be used iteratively to do multi-layer verification and correction. FIG. 36A illustrates steps in using a lithography test wafer. FIG. 36B shows an example of a table relating test wafer parameters. FIG. 37A shows a stack for a lithography test wafer. FIG. 37B shows metal level 1 of a lithography test wafer. FIG. 37C shows via level 1 of a lithography test wafer. FIG. 37D shows the metal level 2 of a lithography test wafer. FIG. 38 illustrates a section of varying line widths and line spaces in metal level 1. FIG. 39 illustrates a sub-section of fixed line widths and line spaces in metal level 1. FIG. 40 illustrates a same sub-section with varied line widths and line spaces for metal level 2. FIG. 41A illustrates patterns in metal level 1 and metal level 2. FIG. 41B illustrates metal level 2 superimposed on metal level 1. FIG. 42 illustrates varying array structures in metal level 1. FIG. 43 illustrates a large array of vias in via level 1. FIG. 44A illustrates patterns in metal level 1 and via level 1. FIG. 44B illustrates via level 1 pattern superimposed on metal level 1 pattern. FIG. 45A illustrates three areas of slotting structures in metal level 1. FIG. 45B illustrates slotting patterns for three areas in metal level 1. FIG. 45C illustrates a via pattern in the via level 1 superimposed on metal level 1 slotting structures. FIG. 45D illustrates a metal level 2 pattern superimposed on via level 1 and metal level 1 patterns. FIG. 46A illustrates an application of a method to address surface topography. FIG. 46B depicts an impact of a method when surface topography occurs. FIG. 47A illustrates an application of a method to address feature density. FIG. 47B depicts an impact of a method when feature density occurs. FIG. 48 illustrates an application of a stepper mechanism to address wafer-level surface variation. FIG. 49 illustrates a stepper mechanism with a proper focal distance to an alignment key and including imaged areas within the chip that are outside of the depth of focus FIG. 50 illustrates an application of a method to a chip-level stepper mechanism. FIG. 51 illustrates an implementation of a method using computer hardware, software and networking equipment. FIG. 52A illustrates an implementation of a method where client and server reside or are bundled with other software on a single computer. FIG. 52B illustrates an implementation of a method where the client and server communicate via a network. FIG. 53 illustrates an implementation of the method where the client communicates with a server and web services via a network. FIG. 54 illustrates an implementation of a method within an electronic design automation (EDA tool). FIG. 55 illustrates a use of the implementation within an EDA tool. FIG. 56 illustrates a use of the implementation communicating with an EDA tool via a network. FIG. 57 illustrates use of the method within a design for manufacturing system. FIG. 58 illustrates use of the method within a design for manufacturing system for choosing lithography related tool settings, recipes or consumable sets. FIG. 59 illustrates a GUI for managing layout extractions from multiple designs. FIG. 60A illustrates results from a feature width extraction from a chip layout. FIG. 60B illustrates results from extraction binning based upon feature width. FIG. 61 illustrates a GUI for a design for lithography system embedded within a design for manufacturing system. FIG. 62 illustrates a GUI for managing tools and tool recipes within a design for lithography or design for manufacturing system. DETAILED DESCRIPTION In what follows, we describe approaches that are useful to identify and correct, in advance of lithographic mask creation, areas of an integrated circuit (IC) that are likely to be problematic due to variations in film thickness, surface topography uniformity, and electrical impact that arise in the manufacture of an integrated circuit. The identifications or corrections may be based on predicted or modeled physical and electrical properties of a manufactured IC, arising from dependencies between predefined circuit layout patterns and the characteristics of the processes used in the manufacture of the integrated circuit. These approaches are applicable to (a) high-density plasma (HDP) and chemical-mechanical polishing (CMP) processes used in the formation of shallow trench isolation (STI) structures; (b) lithographic, high-density plasma (HDP), electroplated copper deposition (ECD), and chemical mechanical polishing (CMP) processes used in the formation of single- and multi-level interconnect structures for integrated circuit (IC) devices; (c) processes and flows used to create oxide and low-k dielectric layers; (d) plasma-etch processes and the measurement of critical feature dimensions; (e) lithographic process flows that may include pre and post photo resist deposition and removal steps and a subsequent plasma etch step used to physically etch the patterned features into the wafer; (f) photoresist deposition and photoresist material selection, (g) any step or steps in damascene process flows; and (h) computation of corrections to mask dimensions to achieve desired critical IC dimensions. In fabricating integrated circuits, the degree of interconnect film uniformity (in terms of both thickness and surface topography) is dependent on characteristics of circuit layout patterns (e.g. material density, line widths, line spaces, and other feature dimensions). Surface and thickness non-uniformities often lead to subsequent manufacturability and process integration issues. Pattern dependencies often cause processed films to have significant variation. The variation becomes worse as subsequent non-conformal layers are deposited and polished. An integrated circuit (IC) typically includes multiple levels of materials that have been deposited, planarized, and selectively etched to reproduce circuitry defined by a computer-generated design. Lithography is a frequently repeated process step during the manufacture of ICs in which a pattern that defines the dimensions of the circuitry is transferred to a silicon wafer. The patterns are subsequently used with the etch process to physically etch the features into the wafer surface or other thin films deposited on the wafer surface. The terms feature dimensions or feature size refer to dimensions of the geometries within the circuit. Examples include: the width of a line, the spacing between structures (e.g. the spacing between two lines in an array of lines or a buffer distance between working circuitry and dummy fill structures), the critical dimension (CD) of a circuit (i.e. the smallest dimension of any geometry in the circuit), widths of arrays of lines or other repeating structures, as well as the metrics (e.g. minimum, maximum, and average) on individual geometries or on groups of geometries (e.g. an array of lines). Feature dimensions may also include vertical and other dimensions, including sidewall angle, feature height (e.g. trench depth). Lithography equipment includes mechanisms (e.g. steppers) used to project images of patterns onto wafers and pattern transfer tools (e.g., masks and reticles) used to transfer circuitry patterns onto wafers coated with a photosensitive film. Etch equipment includes mechanisms to selectively remove materials (e.g. oxide) from a wafer surface or thin films on the wafer surface patterned with lithography equipment. A basic projection lithography process is illustrated in FIG. 1. A light source (e.g., a lamp or laser) 10 is used to project light 12 through a condenser lens 14, which directs light through a mask or reticle 16 that contains a pattern that represents the printed circuit features. The light 12 then passes through a reduction lens, which focuses the image onto a wafer 22. The minimum feature size that can be imaged can be defined using the Rayleigh equations as: .times..times..times..lamda..times..times. ##EQU00001## where .lamda. is the exposing wavelength and NA is the numerical aperture of the optics. The parameter k.sub.1, normally between 0.65 and 0.4 for deep ultraviolet (DUV) imaging systems, is a process and system dependent variable that includes effects such as resist, process improvements, light source, and reticle characteristics. FIG. 2 describes the process of how a lithography mask may be created from an IC design. A computer-aided-design (CAD) system 36 is used to translate a functional circuit design to an electronic layout design file that represents a physical device, layer-by-layer. The result is a design layout that describes each level of the device from the lowest level, for example a transistor level, up to higher levels, for example interconnect layers that transmit signals among transistors and supply power to the components on the chip. The electronic design files are used during so-called tape-out to generate specifications for making a mask 37. The masks are then manufactured 38 and used with the lithography tool to transfer circuit features to a wafer 39. Many projection systems use step-and-repeat mechanisms that expose only a sub-area of the wafer or a die, also referred to as the optical field, and then repeat the process until the entire wafer is imaged. The stepper may be controlled to accommodate wafer-level variation that occurs across the wafer as a result of, for example, warp or bow. This is normally used to accommodate variability that occurs from die to die, but not variability that occurs within each die. To ensure that the printed circuit is within a depth-of-focus associated with the optics, the stepper may adjust the focal length of the optics based on measurements of test keys or alignment marks, which are formed on a surface of the wafer, to accommodate variation in the thickness of the photosensitive film or photoresist. Underlying film thickness variation in materials below the photoresist often causes the variation. FIG. 3 illustrates that while the stepper can account for die-to-die variation, it may not adequately address within-die variation caused by IC pattern dependencies. The reduction lens 18 of FIG. 1 is shown above the die surface 30 in FIG. 3. The projection system adjusts so that the focal length 24 matches the measured distance to a test key or alignment mark 26. The depth of focus 28 determines what features along the optical axis can be reproduced with the desired resolution M.sub.fs. Using the Rayleigh equations, depth of focus D.sub.f 28 can be expressed as: .+-..times..lamda..times..times. ##EQU00002## where .lamda. is the exposing wavelength and NA is the numerical aperture of the optics. The parameter k.sub.2 (normally around one for deep ultraviolet or DUV imaging systems) is a scaling factor based upon process related characteristics. During deposition of copper material via ECD or through the CMP of oxide or copper, for example, process related pattern dependencies often cause within-die variation 30 across the chip. If the chip-level variation exceeds the depth of focus, then the printed features 32 may not accurately represent the critical dimensions of the IC design as patterned on the mask and the errors, as imaged on the wafer, may negatively impact the performance of the device. As explained below, it is possible to adapt the mask design so that the printed IC dimensions better match the designed dimensions. The next few paragraphs describe the cause and result of process-related IC pattern dependencies. The lithography process is repeated throughout the manufacture of a semiconductor device as each subsequent layer is created. One area where the techniques described here may be particularly helpful is during a damascene process in which metal lines, that connect device components (called interconnect), are created. Multiple layers of connections are used to transmit signals and power among device components. The damascene process flow for a given interconnect layer is described in FIG. 4. The flow begins with a post-CMP planarized surface 40 of the prior interconnect level (level N-1). A dielectric material (e.g. oxide or low-k material) is deposited 42 to electrically isolate the previous and current interconnect layers N-1 and N. (The dielectric forms what is called an inter-level dielectric or ILD layer. Although pattern dependencies due to underlying features may require a CMP planarization step on the ILD, that step is optional and is not shown in this flow example.) A photosensitive film (e.g. photoresist) is deposited on the ILD wafer surface 44. A lithography system images the wafer 46 to define circuit features for the current interconnect layer using a process similar to that illustrated in FIG. 1. A developer is used to selectively remove photoresist 48. Plasma etch is used to remove selective oxide areas 50 and the remaining photoresist is subsequently removed 52. A barrier material is then deposited 54 and subsequently ECD is used to deposit metal, for example copper 56. CMP is used to polish away selective copper areas and remove the barrier material 58. This completes the formation of metal interconnects for level N. Often pattern-related non-uniformity is transferred from underlying levels to overlying interconnect levels resulting in variations in the ILD and photoresist thickness that is imaged during lithography. As described in FIG. 5, electroplated copper deposition (ECD) is a process step in a copper damascene flow that is used to deposit copper material within the interconnect structures. The goal is to completely fill an etched trench region in a void-free manner while minimizing a variation in the deposited copper thickness and minimizing a variation in surface topography. There exist pattern-dependencies in ECD that result in plated surface variation. FIG. 5 shows, for example, the difference in post-plated thickness T.sub.diff84 commonly observed between the deposited copper thickness T.sub.narrow 70 that occurs over narrow line widths 72 and the deposited copper thickness T.sub.wide 82 that occurs over a wide line width or trench 86. Film thickness variation in chemical mechanical polishing (CMP) processes can be separated into various components: lot-to-lot, wafer-to-wafer, wafer-level, and die-level. Often, the most significant component is the pattern dependent die-level component. Die-level fill thickness variation is often due to differences in layout patterns on the chip. For example, in the CMP process, differences in the underlying metal pattern result in large long-range variation in the post CMP film thickness, even though a locally planar surface topography is achieved. This variation occurs in copper, oxide, and shallow trench isolation (STI) CMP and is described in following figures. For oxide polishing, the major source of variation is caused by within-die pattern density variation 102, shown as two groups of metal lines in FIG. 6A. The metal lines 106 on the left side of FIG. 6A have a lower density in the direction of the plane of the integrated circuit than do the metal lines 108 on the right side of the figure. Pattern density, in this case, is defined as the ratio of raised oxide area 110 divided by the total area of the region. The region may be taken as a square with the length of the sides equal to some length, for example, the planarization length. The planarization length is usually determined by process factors such as the type of polishing pad, CMP tool, slurry chemistry, etc. FIG. 7A illustrates an example of how the underlying feature density affects the film thickness variation. FIG. 7B plots the film thickness variation corresponding to each density type. For a given square area defined by planarization length 132, the higher underlying feature density leads to larger film thickness variation 134. The lower underlying feature density leads to a reduced film thickness 135. Designers often try to maintain density tightly around 50% 133 to promote planarity. The effective pattern density may be computed for each location on the die by filtering the designed layout densities, often by using various two-dimensional filters of densities around the given location. FIG. 6A illustrates how the underlying features 106 and 108 cause variation in local surface topography (step height) 104 and global non-planarity 102. In creating shallow trench isolation (STI) structures (examples are shown in FIG. 6B), SiO.sub.2 112 is deposited in a trench etched in silicon 111 and planarized using CMP to electrically isolate devices. As with oxide inter-level dielectric (ILD) polishing, the underlying pattern of isolated trenches results in unwanted variation in the deposited SiO.sub.2. Problematic areas often are created as a result of CMP such as nitride erosion 114 (where the nitride barrier is removed and possibly exposes the underlying Si to contaminants and damage), corner rounding 116 and oxide dishing 118. The corner rounding has the effect of potentially widening the trench and where the exposure of Si 110 destroys the device. The oxide dishing results in topography variation that impacts subsequent lithography. In STI polishing, pattern density is an important feature with regard to topographical variation and other CMP effects. FIG. 6C illustrates the effects of polishing metal features (e.g., copper lines 122 and 126) entrenched in a dielectric (e.g., SiO.sub.2) 120, during a damascene CMP process. For metal polishing, computation of pattern density is important to characterizing full-chip pattern dependencies; however determining other physical layout effects, such as the line width and line space, may also be required. Two unwanted effects known as dishing and erosion result from metal damascene CMP. Dishing 124 is measured as the difference in metal thickness at the edge of a line and its center. Erosion 128 is defined as the difference in oxide thickness above a metal line, typically within an array of lines, to the oxide thickness in an adjacent unpatterned region. Another unwanted effect is residual copper 130 that is has not been removed from dielectric field (or up areas) of the chip and remains on the wafer after polishing is complete. It is common for process engineers to set polish times such that all residual copper is removed. For those patterned areas where copper is cleared first, dishing and erosion continue to occur, thereby increasing the non-uniformity of the wafer surface. Each of the described CMP processes contribute to surface level non-uniformity and thus may negatively impact lithography. While the techniques described here are applicable to any process related pattern dependencies, ECD and CMP are two processes that cause specific concern regarding non-uniformity. Although these processes will be used to illustrate the methods, the methods are applicable to pattern dependencies related to any process. The impact of process related pattern dependency on lithography is illustrated in FIG. 8. For the sake of clarity, the mask 184 and wafer 192 are shown and the related optics are not shown. As a matter of terminology used throughout, feature width (FW) is taken to be the smallest dimension of any given object. This term encompasses various types of layout objects, such as lines, rectangles, polygons, etc. Also, the critical dimension (CD) is understood to be the smallest dimension of any feature on the layout, i.e. the smallest FW. A mask 184 is shown with two features with the same feature width, (w), 180 and 182 to be printed onto a wafer surface 192. When lithography is performed, the within-die non-uniformity 192 due to process-related pattern dependencies (as illustrated in FIGS. 5, 6, and 7) may result in a film thickness difference (.DELTA.h) 186 across the chip between the two printed line widths w.sub.2 188 and w.sub.1 190. In this case 194, the printed line width w.sub.1 190 is much larger than w.sub.2 188. Although both line widths 180 and 182 have been designed and created on the mask with the same dimensions, surface level non-uniformity may result in significantly different dimensions in the printed features 188 and 190, which subsequently affects the performance of the manufactured IC. Process related pattern-dependencies may also occur within the lithography process itself where the density of features often affect how well the printed features reproduce those designed. In FIG. 9, a mask 214 is shown with two sets of features: one with higher density 210 and one with lower density 212. As features on the chip are placed closer to each other (i.e. feature density increases), the diffraction patterns associated with them change often resulting in a feature dimension that varies from that designed. Even with a perfectly planar wafer surface across the chip 216, the printed feature dimensions (e.g. line widths) (w+.DELTA.1) 218 and (w+.DELTA.2) 219 may vary 220 from the dimensions designed and patterned on the mask. Topographical variation may occur over all components within a chip and thus a full-chip characterization or prediction may be useful. In some cases, it is useful to focus on critical components or circuit areas call sub-networks or sub-nets. Within this context, full-chip prediction is meant to include any focus on topographical variation within a critical sub-net. IC pattern dependent relationships can be used to verify whether feature dimensions produced by lithography match the dimensions as they were designed, and, if not, to modify the design layout and masks to yield the designed features. Lithography models may be combined with etch models to predict the physical feature dimensions created within the wafer. Electrical extraction and simulator components may also be used to assess the electrical impact of variations in features (e.g. width, height, depth, sidewall angle) across the chip and fine-tune the specified tolerances for the chip. The following paragraphs describe an embodiment of the method, which is depicted in FIG. 10A. Sub-blocks (310, 400, 600 and 800) within FIG. 10A will be described in greater detail below. An IC design is commonly represented electronically, e.g., in a Graphical Data Stream (GDS) format, in a library of files that define structures and their locations at each level of an integrated circuit 280. These files are typically large, although the features that are relevant to process variation may be described more efficiently. A process of layout extraction 310 involves summarizing discrete grids (sub-portions) of IC designs in a compact set of parameters such as feature width, feature space, and density for each grid. Layout extraction is not required but may be helpful where computation resources are constrained. A description of how to perform layout extraction is described in section a below. In the prediction component (P.sub.r) 300, the layout features 280 of the design are mapped 310 to parameters of wafer topography (.DELTA.h) 580, such as film thickness, dishing, erosion, and total copper loss. This information may be used by a process model (e.g., a CMP model) or a set of process models M.sub.p (e.g., ECD and a multi-step CMP process or a more complex process flow) 400 to predict or simulate the manufacturing results and corresponding variation that will occur when the design represented by the layout features is manufactured on the modeled process. The variation of the resulting fabricated device can be measured physically, such as by optical measurement of the film thickness or surface profiling of the wafer surface to determine actual topography (e.g. dishing or step height and erosion or array height). The chip-level surface topography and associated electrical parameters 580, relevant for comparison to the desired specifications 750, are computed for the full-chip, both within die and for multiple dies across the wafer. The predicted chip-level topography 580 is input into a lithography modeling M.sub.L step 600 that maps the variation in wafer surface height 580 to the variation in printed feature dimensions 680 for the particular lithography tool. This mapping may use the tool specifications and equations for minimum feature size (M.sub.fs) and depth of focus (D.sub.f) to compute the feature dimension variation with respect to surface topography (as shown in FIG. 8) and an optical proximity correction tool (e.g., existing commercial versions) to compute the feature dimension variation with regard to feature density (as shown in FIG. 9). Another approach is to utilize test wafers and a calibration process described in FIGS. 36A and 36B and section f. to capture pattern dependencies with regard to surface topography and feature density. The result of these approaches is the predicted variation in feature dimensions and line widths across the full-chip 680 for one or multiple dies across a wafer that has been processed using lithography process or flow 680. One option is to use models in which the lithography process flow 600 is defined to include not only the lithography process step but may also include pre and post photoresist deposition and subsequent plasma etch. This may be useful if the actual physical feature dimensions are desired, as an alternative to the patterned feature dimensions that lithography models alone provide. It is recommended to use a pattern dependent etch model that provides additional feature dimensions such as sidewall angle and trench profiles. This step concludes the prediction component P.sub.r 300. The predicted feature dimension variation 680 and the desired feature dimension specification and tolerances 750 are input into a verification and correction component 800 which identifies any features that will exceed or approach the tolerances. This component also may be used to correct the dimensions of the identified features within the design layout and in subsequent mask creation so as to achieve the designed (or desired) feature dimensions across the chip. Once these modifications are made to the IC design, dummy fill may be reinserted or adjusted and a new layout generated. Dummy fill is a method of improving film thickness uniformity in integrated circuits through the addition of the structures or the removal of existing structures. Adding metal dummy fill increases the pattern density since density is defined as the amount of metal divided by the total area within a given region. Conversely, adding oxide dummy (also called slotting) removes sections of the copper line and decreases the pattern density. Tile addition of fill can also alter other parameters such as line width and line space. If dummy metal is inserted between two parallel lines, the line space changes for both of those lines. Similarly, if oxide dummy is inserted within a wire, its effective line width is changed. By modifying the existing layout through the addition of dummy fill, physical parameters such as pattern density, line width, and line space are changed. The new layout is then input into the prediction component to ensure that the new design meets not only the lithography related feature dimension requirements but also the design and electrical rules and specifications as well. This will likely be an iterative process until the criteria are met across all concerns. FIG. 10A describes the basic flow for design verification and for mask correction. FIGS. 10B and 10C provide more detailed flows for design verification and mask correction, respectively. The motivation behind design verification is to predict feature width and topographical variations and to use electrical simulations to verify that a given design meets the desired criteria. As such, it is important to modify the design file to reflect the feature dimensions that will result for each interconnect level. As shown in FIG. 10B, the first step is to generate the layout for an interconnect level (e.g. level N). The full-chip design, a critical sub-portion of the circuit design or an extraction from the layout is used to predict feature width variation 222 due to the lithography (and optionally, plasma etch as well) process. This is similar to the prediction component 300 shown in FIG. 10A. The original design file is stored 223 for future use because if the design passes verification, the original design will be used to create the masks. A temporary design file is modified 224 to reflect the feature width variation that will result from the lithography (and optionally, the plasma etch) process. The electrical impact of feature width variation can be evaluated 225 by performing full-chip or critical circuit network simulation using resistance-capacitance (RC) extraction and other electrical simulation tools. This allows for examination of issues, related to interconnect feature width variation such as coupling capacitance, noise and timing. The physical characteristics (e.g. total copper loss, dishing and erosion) and electrical characteristics (e.g. sheet rho variation, timing closure, signal integrity, power grid and overall performance) are checked 226 against specifications for the device. The verification step weighs the results and either passes or rejects this design level. If the design passes, the original design file is used for mask creation 228. If the design is rejected or fails to pass, both the feature width and topographical variation results are provided to the designer or may be input into a design or mask correction component 229, such as the mask correction approach described here. Approaches for both design verification and mask correction components are described in Section e. A mask correction technique is shown in FIG. 10C and may be integrated with an electronic design automation (EDA) tool (as shown in FIGS. 54 and 55 ) or used separately (FIG. 56). The first step is generate the layout for an interconnect level (e.g. level N) 231. The layout is normally generated using an EDA tool that places circuit components and routes wiring for interconnect levels. Often dummy fill is added 232 to promote uniformity. The dummy fill may be performed at this stage or performed during the prediction step in 235 when the topographical variation due to pattern dependencies is computed. The next step 233 is physical verification in which the design is checked to make sure that it meets all the design rules and parameters that are specified by manufacturing (e.g., a foundry). Physical verification is often part of the normal EDA tool flow that includes steps 231, 232, 233 and electrical simulation 234. Normally optical proximity correction (OPC) is done, as part of physical verification, to adapt features to compensate for sub-wavelength distortions. However it is recommended that this component be made inactive in any design flow and that OPC methods be used in step 235 instead. If both are used, then the design is adapted for mask creation before the topographical effects on lithography can be properly evaluated. The next recommended step is electrical simulation, which is used to verify that the feature widths, as designed, meet the electrical specifications 234. The full-chip design, a sub-network of the circuit or an extraction from the design layout is then input into the feature width prediction component that characterizes the impact of pattern dependencies on the lithography process (and optionally, the etch process as well) 235. This is similar to the prediction component 300 shown in FIG. 10A. Optical proximity correction (OPC) 236 may be performed within the prediction step, as shown in 640 FIG. 22A, or separately, as shown in 236, using an existing commercial tool. The next step is correction 237 where the design file is modified so that the mask features compensate for width variation. It is recommended that any modifications to the design files 237 by these components (235 and 236) be coordinated. These steps may be repeated 230 for each interconnect level until the highest interconnect level is reached. When modifications to design files, to be used for mask tape-out for each interconnect level, are complete, the electronic files are sent out for creating the masks. It is important to maintain separate design files though The design files that have been modified to compensate for the width variation are only useful for mask creation. The masks if properly modified will result in feature dimensions that closely resemble those designed in the original design files. As such, any further simulation or analysis should use the original design files, whose dimensions will be accurately represented in the manufactured circuit. Two examples of how the techniques may be applied to damascene process flows are provided in FIGS. 11 and 12, which will be referred to as modes A and B respectively. The damascene process flow is a good example because non-uniformity may propagate from level 1 to level 2 and so on until the final level N is reached, and the following figures illustrate the iterative nature of the approach. To simplify the process flow descriptions, pre and post wafer treatments that do not significantly affect wafer topography are ignored. Also, to simplify the example to a generic damascene flow, the term interconnect level is used as a global reference to include both metal and via levels; any additional oxide deposition or etch steps to form vias are not shown. The damascene flows illustrated can be easily extended to dual-damascene and other damascene process flows. Also, the process flows shown in FIGS. 11 and 12 are for the case where plasma etch is not included in the lithography process module 600 and is computed separately. If the option to predict etched or physically created feature dimensions is used, the etch model 250 is used within a lithography process flow component 600 before comparison 246 or modification 260. The difference between the two approaches is that in mode A, the design is modified before mask creation and tape-out to produce the desired dimensions and thus the original design and extraction reflect the actual printed circuit dimensions (if one uses the corrections to the mask to produce the originally designed features). The layout extraction for the original design still reflects the processed feature dimensions or may be close enough to assume the designed widths are used in subsequent ECD process steps. In mode B, the design is modified to reflect the impact of width variation due to lithography. The variation in feature dimensions at each level needs to be reflected in subsequent steps that have pattern dependencies. As such, the design file is adapted, another layout extraction may be performed and the variation is propagated to the next interconnect level to examine multi-layer effects. Mode A is oriented toward mask correction to yield minimal feature size variation. Mode B is useful for characterizing lithography process impact, for a given design, within the flow. This is also useful in determining measurement plans for feature dimension variation impact--perhaps for existing production device flows where the masks have already been made and being used in production. As such, the full-chip feature dimension variation has to be taken into consideration for subsequent process impact and the design appropriately modified to generate a new layout extraction for downstream process prediction. Also if the full physical and electrical impact of lithography variation is to be examined the changes to feature dimensions should be modified before simulation (perhaps using RC extractor or EDA tool) as well. That allows for the electrical impact of lithography variation to be characterized as well. FIG. 11 describes mode A in which the design is modified to yield minimal feature dimension variation after each lithography prediction. Please note that further details on each step will be provided in subsequent sections and these descriptions are to indicate the flow and operation of the components in FIG. 10. The sample application begins with interconnect level 1, the layout is generated 280 for levels 1 through the final level N, the process model component 401 is used to extract layout parameters 240, and the ILD process model 242 is used to predict the full-chip dielectric thickness, also referred to as .DELTA.h in FIG. 10. The lithography model component 600 is used to predict the feature dimension variation .DELTA.FW. One option is to import feature width variation to electrical simulation tools to characterize the electrical impact and transfer the electrical characterization of feature width variation to the verification component 246 as well. The verification component 246 compares the prediction and specifications and identifies problematic areas. The correction component 248 modifies the design so that the lithography process yields the desired feature dimension levels. Since the printed features now match (or are sufficiently close within some acceptable threshold) the original layout extraction parameters 240, a new layout extraction is probably not required unless the feature specifications have been set too broad. This is a way in which the techniques may be used to modify design rules to be less conservative, once lithography variation has been minimized. To generate the lithography prediction for interconnect level 2, the underlying topography for all the process steps between the two lithography steps should be addressed. To compute the incoming wafer topography .DELTA.h for level 2, the prediction component M.sub.p Level 2 402 must use the predicted ILD topography from 242, the etch model prediction 250, the ECD model predicted wafer topography, and the CMP model predicted topography 252 from interconnect level 1 and the subsequent ILD topography 256 from interconnect level 2. The pattern that is imaged during interconnect level 2 lithography is the level 2 design, which is extracted 254 and input into the lithography model. Finally, the feed-forward propagation through the model flow yields the incoming topographical variation 256 that is input into the lithography model along with the level 2 extraction parameters 254 for predicting the interconnect level 2 feature variation 600. One option for the use outlined in FIG. 11 is to transfer feature width variation computed in 600 and 250 and the topographical variation computed in 252 into electrical simulations to characterize the electrical performance for interconnect level 1 and this may be repeated for each interconnect level. FIG. 12 describes mode B. The mode B approach may be used to determine the impact of chip and wafer level pattern dependencies on the lithography process for multiple interconnect levels or the entire chip. In this approach, the printed or etched feature dimensions that result from a lithography process flow may not be the same as the desired feature dimensions and as such any pattern dependencies in subsequent process steps would be based on the printed or etched dimensions. Given that circuit dimensions may be significantly different, it is recommended that the design or extraction be updated to the predicted variation. When the design is updated to reflect the variation, another extraction may need to be performed and forwarded to subsequent model prediction steps. Further details on each step will be provided in subsequent sections and this description is to indicate the flow and operation of the components in FIG. 10. The key difference in the steps described in FIG. 11 and FIG. 12 is that in FIG. 12 the lithography model prediction of feature dimension variation 600 is used to modify the layout 260 so that it accurately represents the full-chip printed feature width that will actually be printed on the wafer surface. The existing extraction may be modified or a new extraction 262 may be run and fed into the subsequent etch process step 250. In the option where etch models are used within lithography process flow in 600, the resulting variation in features are used to update the layout and a new extraction is ran and fed into the subsequent ECD step 252. The verification, mode B, operation may be used with existing process flows to determine measurement and sampling plans to measure problematic areas where feature dimension variation is a concern. An option for the method in FIG. 10 is to add an electrical extraction or simulation component to predict the resistance, capacitance and overall electrical impact of the feature dimension variation that results from lithography,a lithography process flow including etch. One may also use this invention for full interconnect level electrical characterization by combining predicted feature width and topographical variation that occurs subsequent ECD or CMP steps and providing this information to electrical extraction or simulation tools. To evaluate electrical impact in FIG. 11, the feature width variation computed in 600 and the topographical variation computed in subsequent process steps 252 may be imported into electrical simulations to characterize the electrical performance for interconnect level 1 and this may be repeated for each interconnect level. To evaluate electrical impact in FIG. 12, the feature width variation computed in 600 may be examined and transferred to the verification component in 246 and 250 and the topographical variation computed in 252 may be imported into electrical simulations to characterize the electrical performance for interconnect level 1 and this may be repeated for each interconnect level. In the final verification pass for a given IC design a combination of both process models and electrical simulations may be used to gauge the performance of a given IC design and compare the prediction against the desired wafer quality and electrical parameters as well as design rule criteria 800. Illustrative embodiments are described in the following sections: Section a. describes the layout generation process. Section b. describes the extraction of layout parameters related to process variation as a method to transform the large design files into a manageable set of features. Layout extraction is not required but is useful. Section c. describes a desirable use of process and electrical models to characterize the impact of pattern dependencies and process variation on chip-level topography. Section d. describes the mapping of wafer topography and designed (or desired) circuit features to predicted feature dimension variation that results from a lithography process flow. Section e. describes the verification process of comparing predicted and desired feature dimension values across the full-chip and a correction process for modifying design features and generating new GDS design files for mask tape-out and creation. Section f. describes the creation and use of test wafers to characterize pattern dependencies associated with lithography process flows. Section g. describes applications using the procedures described in sections b. through f. Section h. describes the construction and computational framework used to implement the methods and the applications described in Section g., as well as the operation of the system and methods by users. a. Layout Generation Depending on how the techniques is used (for example, as shown in 10B or 10C), the lithography prediction may be used within an EDA design flow, as shown in FIG. 55, or in series with an EDA design flow, as shown in FIG. 56. In both FIG. 11 and FIG. 12, the lithography modeling may come before or after the layout extraction component. Generally, layout design files are sent through an OPC correction step resulting in the creation of a post OPC layout design file. The OPC correction may either be rule based or model based, but in either case the layout design file is modified from its original form in order that the lines actually printed on the wafer surface after passing through the optics of the lithography process most closely represent what was originally intended. In FIG. 29C, verification is performed at the designed feature resolution and no abstraction of the features, using layout extraction, is needed. As such, this is a case where lithography variation is characterized and perhaps corrected at the feature dimension resolution. The layout extraction component must be performed on a pre OPC design file and account for any possible errors that the OPC correction may fail to account for, or, if the layout extraction is performed on the post OPC design file, it must remove the effects of the OPC correction in order that it most closely represents what will actually be printed on the wafer surface. If one is to utilize the lithography model component for OPC and rely on its ability to change the GDS design file such that you get what is designed into the GDS file, then modifications based on topography variations due to CMP may also be moved up above the lithography modeling/OPC block. In other words, if the techniques are integrated within an EDA tool, any modification of feature widths are to be made before OPC, so that the OPC tool could insert and adjust changes to the GDS file (in it normal operating fashion). Alternatively, the topographical variations (.DELTA.h) could just be forwarded into the OPC tool and it could adjust for both the surface variations and the optical proximity. All of these are options, depending on how the techniques are to be used and whether it is used with an EDA tool and OPC component or not. Two such ways of generating process layouts (or electronic design files) are described in FIG. 13A and FIG. 13B. FIG. 13A describes a method of correcting masks for a layout generated in a design flow, typically performed using an EDA tool. Layout generation 280 describes the process that converts a functional circuit design to a layout. An IC design is commonly represented electronically in a layout design file (e.g., in a Graphical Data Stream or GDS format) in a library of files that define structures and their locations at each level of an integrated circuit. The process begins with a layout of where major components (blocks of circuitry) are located on the physical die 282. Place and route 284 is then done to determine precisely where every cell or block is positioned and how all components are connected. Dummy fill addition 286 may be performed to modify the density of materials in a given layer, while minimizing the electrical impact (Additional information concerning dummy fill is set forth in U.S. patent application Ser. Nos. 10/165,214, 10/164,844, 10/164,847, and 10/164,842, all filed Jun. 7, 2002). Dummy fill may also be performed later after topographical variation is characterized as part of the prediction component 300. The next step 288 is physical verification in which the design is checked to make sure that it meets all the design rules and parameters that are specified by manufacturing (e.g., a foundry). A common option, during or after the physical verification step in a design flow, is to pass the design through optical proximity correction (OPC) to adapt the design file used to create masks with regard to feature density. Within the methods described here, the step may be performed in the lithography modeling component 600 so that manufacturing variation may be taken into account along with feature density. Often electrical extraction and simulation are performed 290 to verify that the chip, as verified in the prior step and with dummy fill added, meets electrical performance requirements. Within the context of the methods described here, electrical impact also includes full-chip prediction of sheet resistance, total copper loss, capacitance, drive current and timing closure parameters. The design modifications are generated in a layout design file format and assembled into a library. To achieve a smaller electronic file size, a hierarchical method may be used to compress the size of the design files (Such a hierarchical method is described in U.S. patent application Ser. Nos. 10/165,214, 10/164,844, 10/164,847, and 10/164,842, all filed Jun. 7, 2002.). Once layout generation is completed, the design may be input into the layout extraction component 310. The layout extraction, the actual full-chip design at the feature resolution or some portion of the circuit such as a critical network is fed into the prediction component 300. The layout generation process described in FIG. 13B the generation and verification of a design. The components are the same as described in FIG. 13A and the prior paragraphs in this section. However the order is different so that the physical and electrical impact of feature width variation may be inserted into the design process directly. The process in FIG. 13B is similar to that of FIG. 13A in that it begins with a layout of where major components (blocks of circuitry) are located on the physical die 282. Place and route 284 is then done to determine precisely where every cell or block is positioned and how all components are connected. Dummy fill addition 286 may be performed to modify the density of materials in a given layer, while minimizing the electrical impact (Additional in formation concerning dummy fill is set forth in U.S. patent application Ser. Nos. 10/165,214, 10/164,844, 10/164,847, and 10/164,842, all filed Jun. 7, 2002). Dummy fill may also be performed later after topographical variation is characterized as part of the prediction component 300. The next step 288 is physical verification in which the design is checked to make sure that it meets all the design rules and parameters that are specified by manufacturing (e.g., a foundry). In this mode, the techniques described here work with the physical verification component and may, as shown later in FIG. 54 and FIG. 55, be directly embedded or integrated within a physical verification component within an EDA tool. In some cases where the computational burden is a constraint, a layout extraction may be performed (described in more detail in Section b.) 310. In other cases, the actual design file or some portion of the circuit (e.g. a critical sub-network) may be directly imported into the physical verification 288 and prediction components 300. The prediction component examines and characterizes feature width variation 300 and updates a design file, which reflects the variation in manufactured circuit if the masks use the original layout produced in 280. The electrical impact of this variation on circuit performance may be evaluated by using electrical extractions and simulations that are performed 290 to verify that the chip meets electrical performance requirements. Within the context of the methods described here, electrical impact also includes full-chip prediction of sheet resistance, total copper loss, capacitance, drive current and timing closure parameters. The overall impact of feature width variation on physical and electrical characteristics for the interconnect level are evaluated against desired device specifications. In later figures and descriptions, layout generation will indicated with a `L` and may include any and all of the cases discussed in this section but is not limited to the two cases described in FIG. 13A and FIG. 13B. b. Layout Parameter Extraction As described in section a., a layout is a set of electronic files that store the spatial locations of structures and geometries that comprise each layer of an integrated circuit. It is known that variation during manufacturing, which negatively impacts the chip-level planarity of processed films, is related to the variation in spatial densities and the spatial distribution of features within a given design. This relationship may be characterized using layout extraction, in which characteristics of the feature layout (e.g. width and spaces of lines and pattern density) are extracted spatially across a chip from the geometric descriptions in layout files. The extracted information may then be used to determine areas of the chip that exceed design rule criteria, such as limits on feature dimensions and distances to neighboring structures. The layout parameter most often used to compute dummy fill is the effective pattern density. Although the dummy fill method works with extracted densities, it is useful to include the extracted feature widths and spaces. Since lithography impact must take into consideration all features, whether electrically active or dummy structures, it is recommended to use designs with dummy fill added and the associated layout parameters for purposes of layout extraction. The flowchart in FIGS. 14A, 14B and 14C provides a detailed flow of the layout extraction component 310 of FIG. 10. The layout file is transferred or uploaded to the computer where the extraction algorithm is running 311. The layout is divided into discrete grids, small enough so that aggregate computations of mean, maximum, and minimum features can be used to represent the structures in the grid and still allow accurate feature representation 312. The trade-off is between higher and lower grid resolution is the increased extraction, calibration, and prediction compute times versus a more faithful representation of the layout and more accurate predictions. It is recommended to use a grid size that is less than feature dimensions; however section e. and FIG. 29A presents a method for using larger grid sizes such as 40 .mu.m.times.40 .mu.m for verification and correction. The grids are ordered or queued for processing 313. One desirable approach is to use multiple processors to compute the grids in parallel 314. A grid is selected 315 and within that grid the width of each object 316 is computed 317. This process is repeated for every object within that grid 318. For each set of neighboring objects (e.g. adjacent objects or objects within some defined distance of an object in being processed) the maximum, minimum, and mean space is computed 319. The effective density for the entire grid is then computed 320. This process is repeated for all the remaining grids 321. Once all the grids are processed, the extracted features such as width, space, and density are reassembled from the parallel processors 322. A table is then created and the maximum, minimum, and mean width, space, and density for each grid are placed in it as well as the maximum, minimum, and mean width for the whole chip 323. The minimum and maximum widths for the whole chip are used to compute a range. Bins are useful for computing statistical and probabilistic distributions for layout parameters within the range specified by the bin. The width range (M) for the chip is divided by a number of desired bins (N) 324 to determine the relative size of each of the N bins. For example, the first bin would span from the minimum width or small nonzero value .DELTA. to the width (M/N). Successive bins would be defined similarly up to the N.sup.th bin, which will span the width from min FW.sub.BinN=(N-1)(M/N) to max FW.sub.BinN=(N)(M/N), which is also the maximum feature width. The limits for each of these bins may also be set manually by the user. There are three sets of bins, a set of bins for each of maximum, minimum, and mean width. Each grid is placed in the appropriate bins according to its max, min, and mean width 325. A histogram is also created for each bin showing the distribution of values within that bin 326. This information is stored in the database and fed into process models 327. The maximum, minimum, and mean feature space ranges are computed for the full chip 328. The space range (M) is divided by the number of desired bins (N) 329 to determine the relative size of each of the N bins. For example, the first bin would span from the minimum space or small nonzero value .DELTA. to the space (M/N) and successive bins would be defined similarly up to the N.sup.th bin, which will span the space from min FS.sub.BinN=(N-1)( M/N) to max FS.sub.BinN=(N)(M/N), which is also the maximum space. The limits for these bins may also be set manually by the user. There are three sets of bins, a set of bins for each of maximum, minimum, and mean feature space for the full chip. Each grid is separated into the appropriate bins according to its max, min, and mean space 330. A histogram is also created for each bin showing the distribution of values within that bin 331. This information is stored in the database and fed into process models. The density range is computed for the full chip 333. The density range (M) is divided by the number of desired bins (N) 334 to determine the relative size of each of the N bins. For example the first bin would range from the minimum density or small nonzero value .DELTA. to the density value (M/N) and other bins would be defined similarly up to the Nth bin which will span the density from min FD.sub.BinN=(N-1)(M/N)+.DELTA. to max FD.sub.BinN=(N)(M/N), which is also the maximum density. The limits for these bins may also be set manually by the user. There is one set of bins for density. Each grid is assigned to the appropriate bins according to its density 335. A histogram is also created for each bin showing the distribution of values within that bin 336. This information is stored in the database and fed into process models 337. Finally all the width, space, and density information 338 are stored either in the database or on the file system for later use in process model prediction 400, 600, and 800. FIG. 15 provides an illustration of how an extraction table 362 (for all the grids across the full-chip or die) is generated using the process described in FIGS. 14A, 14B and 14C. The chip or die 360 is segmented into discrete grids 364 and the extraction procedure, described in FIG. 13, is used to compute the width 47 space 48, and density 49 for each grid element 46. For each discrete grid on the die 364 there exists a feature in the extraction table for the grid coordinates 366 with the relevant pattern dependent characteristics, for example density, feature width (FW), and feature space (FS). The figure also shows an example of two grids with (x, y) coordinates (1, 1) 376 and (2, 1) 378 and how they may appear in the extraction table. FIG. 13 indicates how these characteristics, feature width (FW) 368, feature space (FS) 370, and density 372 values, may be placed in an extraction table 362. In many cases, the max, min, and mean of the features within each grid are stored in the table as well. c. Pattern-Dependent Process Models A process model or a series of models (e.g., a model of a flow) can be used to predict the manufactured variation in physical and electrical parameters of an actual IC device from an IC design. By characterizing the process variation relative to IC structures using the model, variations in topography across the chip may be predicted and used to estimate printed feature size variation during lithography or physical feature dimensions that result from use of lithography and etch processing. As described in FIG. 16, pattern-dependent process models and model flows 540 are used to map extracted IC patterns and characteristics 310 to chip-level topographic variation across the chip 580. Each process tool generally has unique characteristics and thus a model typically needs to be calibrated to a particular recipe and tool 500. As such, the pattern-dependent model component 400 includes the calibration step 500 and the feed-forward prediction step 540. Full-chip or partial chip predictions may include copper thickness, dishing, erosion or electrical impact of topographical variation. The following paragraphs describe the calibration step 500. It is common practice to physically process integrated circuits in accordance with a given IC design to determine the impact of processing on physical and electrical parameters and to develop or calibrate process models specific to a particular tool or recipe, as shown in FIG. 17A. In the calibration process 500 shown in FIG. 17A, the actual product wafer 464 is processed using a recipe 465 on a particular tool 466. Pre-process wafer measurements 467 and post-process wafer measurements 468 are used to fit model parameters 469. A semi-empirical model is used to characterize pattern dependencies in the given process. The calibration model parameters or fitting parameters 470 may be extracted using any number of computational methods such as regression, nonlinear optimization or learning algorithms (e.g. neural networks). The result is a model that is calibrated to the particular tool for a given recipe 471. In other words, it is a model that, for the particular tool and recipe, is useful in predicting the characteristics of finished ICs that are processed according to a particular chip design. Certain IC characteristics, such as feature density, width, and spacing are directly related to variation in topography for plating, deposition, and CMP processes. Test wafers that vary these features throughout some range across the die can be used to build a mapping from design parameters (e.g. width, space, density) to manufacturing variation (e.g. film thickness, total copper loss, dishing and erosion) for a given tool and recipe. Test wafers are an attractive alternative for assessing process impact than actual designed wafers because they are generally less expensive to manufacture and one test wafer design can be used to characterize any number of processes or recipes for a wide range of IC designs. As shown in FIG. 17B, a test wafer 390 can be also be used to generate a calibrated process model or multiple process models or a process flow. The calibration model parameters may be computed similarly to the method shown in FIG. 17A. One difference is that the pre-process measurement, 474, may be conducted by the test wafer manufacturer and retrieved in an electronic form, such as via the internet, email, disc or CD, or in paper form. Another difference is that the resulting calibration 478 normally spans a much larger range of feature width, spacing, and density, and thus is more applicable to a broad range of devices that could be fabricated on the tool using the recipe. Since a test wafer is normally designed to span a large design space, the calibration process described in FIG. 17B is recommended. More details regarding the use of test wafers in calibrating a process are provided in FIG. 18. A test wafer die 479 is patterned with a range of line width and line space values 480. The test wafer is processed (e.g., by CMP, ECD, or deposition) on a particular tool using a given recipe 481 and the resulting variation in a parameter is measured across the chip 483 using a metrology tool (e.g. film thickness, 484 ). This mapping 482, dictated by the calibration model parameters, may be considered a model that maps a wide range of line width and line space values to a particular film thickness variation for this tool and recipe. These mappings are useful for predicting process variation for new IC designs, as shown in FIG. 19A. Feature widths and spaces that fall within the range 486 spanned by the test die and wafer are extracted 485 from a new IC layout. The extracted feature widths and spaces for spatial locations across the chip 486 are input into the mapping 487 and an accurate prediction of film thickness variation across the chip 489 and 490 can be acquired for a given tool and a given recipe before processing of the new IC design. As shown in FIG. 19B, the predicted process variation 491 (which may include variation due to lithography) can be fed into electrical models or simulations 492 to assess the impact of processing on the electrical performance of the chip 493. Some of the electrical parameters that may be computed using the models include variation in sheet resistance, line resistance, capacitance, interconnect RC delay, voltage drop, drive current loss, dielectric constant, signal integrity, IR drop or cross-talk noise. These predictions can be used to determine the impact of feature dimension variation on electrical performance for the full-chip or critical networks (also called critical nets). The following paragraphs and figure descriptions provide a detailed flow of the use of process and electrical models to characterize variation, as implemented for lithography. FIG. 20 describes the steps involved in calibrating a process model to a particular tool or recipe. Layout extraction 310 parameters are computed, or in the case of test wafers, uploaded from the wafer provider. The second step 501 pre-measures the wafer using metrology equipment. These measurements may include film thickness and profilometry scans to acquire array and step heights. The test wafer is processed 502 using the particular process or process flow that is to be characterized. Such processes or flows may include plating, deposition, and/or polishing steps. It is particularly useful to calibrate on individual processes and also to calibrate on sections of the flow as a way to capture any coupling of variation between subsequent process steps in a flow. It is also recommended to calibrate the model for different recipe parameters such as time. The processed wafers are measured 503 at the same locations as the pre-measurements; such measurements may include film thickness, profilometry, or electrical characteristics; and the variation for the given process may be characterized 504. Process models or representations are uploaded in 505 and the pre and post measurements as well as computed variation may be used to calibrate or fit the model or representation to a particular tool and/or recipe or recipes. These models may be formulated and uploaded by a user or selected from a library of models on a modeling computer system. The pre- and post-processing measurements and computed process variation are used to fit the model or simulation parameters for the given tool and recipe 506. The result 507 is a process model calibrated to a particular tool and recipe or recipes. The result may also include a series of calibrated process models that can be used to simulate a process flow. The calibration model parameters for specific models (e.g. ECD, etch, and CMP), tools, recipes and flows are loaded into the database and into the models during feed-forward prediction 520. The steps that constitute the feed-forward prediction component 540 are described in FIG. 21A. A damascene process flow for predicting pre-lithography wafer topography is used to illustrate how a prediction may work but any process flow or single process step may be substituted. To simplify the process flow descriptions, pre- and post-processing wafer treatments that do not significantly affect wafer topography are ignored. Also to simplify the example to a generic damascene flow, the term interconnect level is used as a global reference to include both metal and via levels. Any additional oxide deposition or etch steps to form vias are not shown. The damascene flows illustrated can be easily extended to dual-damascene and other damascene process flows. The extraction 310 is loaded into the prediction component 540. The prediction component then retrieves the incoming wafer topography 542. For interc