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United States Patent7069526
Schubert , ; et al.June 27, 2006
Title
Hardware debugging in a hardware description language
Abstract
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
Inventors:Schubert; Nils Endric (Sunnyvale, CA), Beardslee; John Mark  (Menlo Park, CA), Perry; Douglas L.  (San Ramon, CA)
Assignee:Synplicity, Inc. (Sunnyvale, CA)
Appl. No.:11/027,052
Filed:December 29, 2004
Current U.S. Class:716/4 716/5 
Current International Class:G06F 17/50 (20060101)
Field of Search:716/4-8 703/14-16 714/724
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Primary Examiner: Whitmore; Stacy A.
Assistant Examiner: Tat; Binh
Attorney, Agent or Firm:Blakley, Sokoloff, Taylor & Zafman LLP
Parent Case Text


CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. patent application Ser. No. 10/406,732, filed on Apr. 2, 2003, now U.S. Pat. No. 6,904,577 which is a continuation of U.S. patent application Ser. No. 09/724,702 filed on Nov. 28, 2000, now issued as U.S. Pat. No. 6,581,191. This application also claims the benefit of: (i) U.S. Provisional Patent Application No. 60/168,266, filed Nov. 30, 1999, and entitled "INTERACTIVE DEBUGGING OF HDL SOURCE CODE", and which is hereby incorporated by reference herein; and (ii) U.S. Provisional Patent Application No. 60/230,068, filed Aug. 31, 2000, and entitled "HDL-BASED HARDWARE DEBUGGING", and which is hereby incorporated by reference herein.
Claims

What is claimed is:
1. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging a fabricated integrated circuit containing an electronic circuit design, the method comprising: receiving a high level HDL description of the electronic circuit design; determining aspects of the electronic circuit design to be examined or modified during debugging; determining additional circuitry to be incorporated into the electronic circuit design to facilitate debugging; producing a modified high level HDL description of the electronic circuit design by incorporating an HDL description of the additional circuitry into the high level HDL description of the electronic circuit design; storing information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the modified high level HDL description; and debugging the fabricated integrated circuit fabricated in accordance with the modified high level HDL description by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the modified high level HDL description or the high level HDL description.

2. The machine-readable medium as recited in claim 1, wherein at least a portion of the high level HDL description is written in a language selected from the group consisting of VHDL, Verilog HDL, C, C++ and SystemC.

3. The machine-readable medium as recited in claim 1, wherein debugging the fabricated integrated circuit does not require a testbench, wherein while debugging the fabricated integrated circuit, the fabricated integrated circuit is operating in its target environment without interruption and running at its target speed, and wherein the target environment includes real-time characteristics.

4. The machine-readable medium as recited in claim 1, wherein the method further comprises: relating the debug information back to the high level HDL description for the electronic circuit design; enabling a user to determine the aspects of the electronic circuit design to be examined or modified during debugging through interactive selection; customizing the additional circuitry for use with at least a portion of the electronic circuit design; and altering the additional circuitry to trade-off debugging coverage versus area cost.

5. The machine-readable medium as recited in claim 1, wherein the information about the additional circuitry further includes one or more trigger conditions and at least one of design control information, design visibility information and design patch information.

6. The machine-readable medium as recited in claim 1, wherein the fabricated integrated circuit is part of an electronic system that also includes software, wherein the method further comprises debugging the software, wherein the fabricated integrated circuit includes a processor, wherein the software is executed by the processor, and wherein debugging the fabricated integrated circuit is synchronized with debugging the software.

7. The machine-readable medium as recited in claim 6, wherein the hardware debugging system does not require a testbench, wherein while debugging the fabricated integrated circuit, the fabricated integrated circuit is operating in its target environment and running at its target speed, and wherein the target environment includes real-time characteristics.

8. The machine-readable medium as recited in claim 1, wherein the HDL description contains a hierarchical structure of HDL building blocks, wherein the electronic circuit design includes both analog and digital aspects, and wherein the aspects of the electronic circuit design to be examined or modified during debugging are determined in different ones of the HDL building blocks of the hierarchical structure.

9. The machine-readable medium as recited in claim 1, wherein the electronic circuit design includes at least one pre-designed block of circuitry having instrumentation circuitry, wherein the high level HDL description of the electronic circuit design is partitioned into two or more design parts, wherein the additional circuitry is partitioned into two or more partitions, each partition to debug a different part of the electronic circuit design, and wherein each design part contains its own additional circuitry to debug its corresponding design part.

10. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging an electronic system designed according to an electronic circuit design, the electronic circuit design being described by a high level HDL description, the method comprising: receiving the high level HDL description of the electronic circuit design or a description derived therefrom; determining aspects of the electronic circuit design to be examined or modified during debugging; determining additional circuitry to be incorporated into the electronic circuit design to facilitate debugging; incorporating the additional circuitry into the electronic circuit design; storing information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the high level HDL description; and debugging the electronic system by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the high level HDL description.

11. The machine-readable medium as recited in claim 10, wherein at least a portion of the high level HDL description is written in a language selected from the group consisting of VHDL, Verilog HDL, C, C++ and SystemC.

12. The machine-readable medium as recited in claim 10, wherein the method further comprises: identifying functional failures that result from one or more of design errors, tool errors and manufacturing faults; and identifying functional failures that result from specification errors.

13. The machine-readable medium as recited in claim 10, wherein debugging the electronic system does not require a testbench, wherein while debugging the electronic system, the electronic system is operating in its target environment and running at its target speed, and wherein the target environment includes real-time characteristics.

14. The machine-readable medium as recited in claim 10, wherein the high level HDL description contains a hierarchical structure of HDL building blocks, wherein the electronic circuit design includes both analog and digital aspects, and wherein the method further comprises determining, in different ones of the HDL building blocks of the hierarchical structure, aspects of the electronic circuit design to be examined or modified during debugging.

15. The machine-readable medium as recited in claim 10, wherein the method further comprises: customizing the additional circuitry for use with at least a portion of the electronic circuit design; altering the additional circuitry to trade-off debugging coverage versus area cost; and implementing at least one of a design layout tool, a synthesis tool and a simulation tool.

16. The machine-readable medium as recited in claim 10, wherein the electronic system includes hardware and software, wherein the method further comprises debugging the hardware and the software together, wherein the electronic system includes a processor, the processor to execute the software, and wherein debugging the electronic circuit is synchronized with debugging the software.

17. The machine-readable medium as recited in claim 10, wherein the electronic system comprises at least one of an integrated circuit hardware product, a programmable integrated circuit and a printed circuit board with electronic components thereon, each of the integrated circuit hardware product, the programmable integrated circuit and the printed circuit board with electronic components thereon including at least a portion of the electronic circuit design.

18. The machine-readable medium as recited in claim 10, wherein the electronic circuit design includes at least one pre-designed block of circuitry having internal circuitry, wherein the electronic circuit design is partitioned into different sections, each different section of the electronic circuit design containing its own portion of the additional circuitry for debugging its corresponding section of the electronic circuit design, and wherein the additional circuitry is partitioned into different sections, each different section of the additional circuitry to debug a different portion of the electronic circuit design.

19. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging an electronic system having instrumentation circuitry included therein, wherein the electronic system is described with a hardware description language (HDL), the method comprising: activating at least one aspect of the instrumentation circuitry available for debugging the electronic system via the instrumentation circuitry, the aspect selected from the group consisting of design visibility, design patching and design control; determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; configuring the instrumentation circuitry in accordance with the configuration information; receiving debug data from the configured instrumentation circuitry operating within the electronic system; translating the debug data into HDL-related debug information; and relating the HDL-related debug information to the HDL description of the electronic system.

20. The machine-readable medium as recited in claim 19, wherein at least a portion of the HDL description of the electronic system is written in a language selected from the group consisting of VHDL, Verilog HDL, C, C++ and SystemC.

21. The machine-readable medium as recited in claim 19, wherein the HDL description is a high-level HDL description and the HDL-related debug information is described in a high-level HDL, and wherein the method further comprises displaying the HDL description with the HDL-related debug information related thereto.

22. The machine-readable medium as recited in claim 19, wherein the method operates without any requirement for a testbench, wherein translating is performed automatically, and wherein the debug data includes at least status information or sampling data.

23. The machine-readable medium as recited in claim 19, wherein activating operates to enable a user to activate the certain design visibility, design patching or design control aspects, and wherein activating is performed using a graphical user interface.

24. The machine-readable medium as recited in claim 19, wherein the design control aspects include trigger conditions, and wherein activating operates to enable a user to set one or more trigger conditions from the trigger conditions available by the instrumentation circuitry.

25. The machine-readable medium as recited in claim 19, wherein the electronic system includes a hardware portion and a software portion, and wherein the method further comprises: interacting with a software debugger that debugs the software of the electronic system; and interacting with a functional simulator that simulates a portion of the electronic system.

26. The machine-readable medium as recited in claim 19, wherein the electronic system is operated in its target environment without interruption and running at its target speed during the debugging, and wherein the target environment includes real-time characteristics.

27. The machine-readable medium as recited in claim 19, wherein the method further comprises identifying at least one fault of the electronic system, wherein the at least one fault is selected from the group consisting of specification error, design error, tool error, device driver error, timing error, manufacturing fault and environment error.

28. The machine-readable medium as recited in claim 19, wherein the instrumentation circuitry comprises design instrumentation circuitry, wherein the method further comprises interoperating the design instrumentation circuitry with a logic analyzer, and wherein at least a portion of the debug data stems from the logic analyzer.

29. The machine-readable medium as recited in claim 19, wherein the electronic system comprises an integrated circuit product, and wherein the method further comprises: examining the integrated circuit product by the instrumentation circuitry; and modifying the behavior of the integrated circuit product by the instrumentation circuitry.

30. A machine-readable medium containing instructions that when executed on a data processing system causes the system to perform a method for debugging an integrated circuit product having instrumentation circuitry included therein, wherein the integrated circuit product was designed with a high-level HDL description of the integrated circuit product, the method comprising: activating certain aspects available for examining or modifying by the instrumentation circuitry; determining configuration information based on the certain aspects that are activated; configuring the instrumentation circuitry in accordance with the configuration information; receiving debug data from the configured instrumentation circuitry operating within the integrated circuit product; translating the debug data into HDL-related debug information; relating the HDL-related debug information to the high-level HDL description; retrieving circuit status information for the integrated circuit product via the instrumentation circuitry; and displaying state information concerning the integrated circuit product based on the retrieved circuit status information.

31. The machine-readable medium as recited in claim 30, wherein at least a portion of the HDL description of the electronic system being written in a language selected from the group consisting of HDL, Verilog HDL, C, C++ and SystemC.

32. The machine-readable medium as recited in claim 30, wherein the HDL-related debug information is described in a high-level HDL.

33. The machine-readable medium as recited in claim 30, wherein displaying comprises: relating the state information to the high-level HDL description; and displaying the high-level HDL description of the integrated circuit product with the state information related thereto, wherein the state information includes signal values for signals, and wherein relating operates to relate the signal values to HDL identifiers within the high-level HDL description that correspond to the signals.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic systems and, more particularly, to debugging of electronic systems.

2. Description of the Related Art

Electronic systems are designed by designers to operate in specific ways. Electronic systems are systems that contain digital and/or analog electronic components connected together to perform specific operations or functions. Besides the electronic components, electronic systems may also include software. Once designed, the electronic systems may need to be debugged. Debugging electronic systems is a process which involves detection, diagnosis, and correction of functional failures. In the detection step, the designer of the electronic system observes a functional failure. When the designer is able to gather enough information about the incorrect behavior of the electronic system, the designer of the electronic system can draw the necessary conclusions to diagnose the functional failure. For correction of the functional failure, a fix is applied and subsequently tested. When the design is provided in a Hardware Description Language (HDL), such a fix may be a textual change to the HDL description of the electronic system.

In general, debugging has conventionally been performed by various different approaches. In particular, debugging has been performed by computer software debugging, hardware description language functional verification, hardware logic level analysis, or hardware behavioral source level emulation. These different approaches are discussed below.

Computer software debugging is conventionally performed using a computer software debugger. A computer software debugger is a software tool that allows a software developer to control the execution of a running computer software program by setting break-points, sequentially single-stepping through the execution of the computer software program, and looking at the program's state by examining and displaying variables and expressions. One example of such a software debugging tool is the GNU Debugger (GDB), which can be obtained from Red Hat, Inc. in Sunnyvale, Calif.

Software debuggers usually offer interactive debugging of software programs which are sequentially executed on computers. However, some software debuggers also support limited concurrency such as threaded program execution. Some software debuggers support debugging programs written at different levels of abstraction from high-level computer languages such as C++ down to assembler code and/or machine code. To assist with debugging of programs written in high-level computer languages, the software debugging system can add extra debug information (e.g., symbolic names and references to source code) to the compiled code during compilation of the computer software program. In combination with in-circuit emulators, software debuggers may provide a limited capability to analyze the underlying Central Processing Unit (CPU) of the computer executing the computer software program. A major disadvantage of software debuggers is, however, that they cannot be used for efficiently debugging general hardware of electronic systems.

Hardware description language functional verification is used to verify that the parts of an electronic system which are described using HDL match their functional specification. Such functional verification can be achieved through functional simulation or formal verification.

Functional simulation is performed by a functional simulator. A functional simulator is a software program that runs on a host computer and simulates the operation of an electronic system using its HDL description. Examples of functional simulators include VCS and VSS from Synopsys, Inc. in Mountain View, Calif., and ModelSim from Mentor Graphics Corp. in Wilsonville, Oreg. To increase simulation performance some functional simulators additionally make use of special purpose hardware which acts as a co-processor and accelerates the simulation. An example of a hardware-accelerated functional simulator is the Hammer system from Tharas Systems, Inc. in Santa Clara, Calif. Unfortunately, one major disadvantage of functional simulation is the need for simulation models. In order to be able to simulate, there must exist a simulation model with the proper functional behavior for each component of the HDL design for the electronic system. For some components such simulation models may not be readily available and must be generated. Additionally, the HDL design must be stimulated by a testbench. Since the ideal testbench must correctly and exhaustively match the behavior of the target environment, creation of a testbench can be very difficult and time consuming. On the other hand, a testbench that is too simple will not provide the necessary coverage to find all the design errors. Although functional simulation is useful, using functional simulation to debug design errors is too burdensome. Not only are the testbenches difficult to create, but also the more complex the HDL design is, the lower the performance of functional simulation. For state-of-the-art HDL designs simulation is now a million times slower than the fabricated hardware. Hardware-acceleration can typically speedup functional simulation by a factor on the order of one-hundred. Accordingly, its low performance makes it impractical to use functional simulation either to debug real-time applications or to concurrently debug hardware and software of complex electronic systems.

Formal verification is performed by a formal verification tool. Formal verification can help with the problem of incomplete coverage in functional simulation due to testbench limitations. One approach checks the HDL description for properties. Such properties may be explicitly provided by the designer of the electronic system or implicitly extracted from the HDL description by the formal verification tool. An example of such a formal verification tool is Solidify from Averant, Inc. in Sunnyvale, Calif. One disadvantage of formal verification is that it is impractical to use to re-produce functional failures observed in a running electronic system.

Both techniques, functional simulation and formal verification, have the major disadvantage that they do not operate on fabricated hardware. Instead, both techniques operate on a model of the electronic system and a model of the environment in which the electronic system runs, i.e., a testbench. Thus, their use is limited to debugging design errors. As such, neither technique is applicable for debugging manufacturing faults, environment errors, timing errors and/or tool errors. Also, inadequacies in the testbench have the potential to hide or introduce design errors in the HDL design during functional simulation which can later, when the HDL design is fabricated, show up as functional failures of the running electronic system.

Hardware logic level analysis is a technique that works at the logic level of a fabricated electronic system. The logic level of abstraction is also referred to as gate-level. Since electronic systems have been designed at the logic level for many years (for example using schematic entry of logic gates and flip-flops), there exists a wide variety of different techniques for debugging at logic level, including: digital logic is analyzers, in-circuit emulators, Design-For-Test (DFT) techniques, and hardware emulation, each of these different techniques are discussed below.

Digital logic analyzers operate to probe a limited number of digital signals and record their logic values. Probing is accomplished by physically connecting probes of the digital logic analyzer to exposed pins and/or circuitry on the fabricated design. Recording is controlled by trigger conditions, which are conditional expressions built upon the values of the recorded signals provided by the probes. The values for the recorded signals are stored in dedicated memory inside the digital logic analyzer so as to be available for subsequent display. Digital logic analyzers can be external devices or blocks embedded inside the digital circuits of an electronic system. An example of an external digital logic analyzer is the Agilent 16715A from Agilent Technologies, Inc. in Palo Alto, Calif. Examples of embedded logic analyzers are SignalTap from Altera Corporation in San Jose, Calif., or ChipScope from xilinx, Inc. in San Jose, Calif. Another example of an embedded logic analyzer was presented at the 1999 IEEE International Test Conference by Bulent Dervisoglu in "Design for Testability: It is time to deliver it for Time-to-Market". Since embedded logic analyzers are added to the circuitry of the design, they can probe internal signals. Thus, embedded digital logic analyzers overcome the limited access to internal signals problem of external logic analyzers because access to the internal signals is not restricted by the pins of the fabricated circuits.

An in-circuit emulator is a specialized piece of hardware that connects to a CPU for debugging the CPU and the software that runs on the CPU. An example of an in-circuit emulator is visionICE from Windriver in Alameda, Calif. However, since in-circuit emulators only work for the specific target CPU for which they were built, in-circuit emulators are inappropriate for debugging general digital circuits.

DFT techniques, such as boundary scan and built-in self test, provide access to the internal registers of a running fabricated digital circuit. An example of such technique is described in the IEEE 1149.1 JTAG standard available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J. DFT techniques are also described in "Digital Logic Testing and Simulation" by Alexander Miczo, published by Wiley, John and Sons Inc., 1985. DFT techniques were originally developed for and applied to testing of manufacturing faults and have the major disadvantage that they do not relate back to the HDL description.

Hardware emulation systems map a synthesized HDL design onto special emulation hardware. Such emulation hardware comprises many re-programmable FPGA devices and/or special purpose processors. The emulation hardware then executes a model of the HDL design. Thus hardware emulation has the same disadvantage as functional simulation, namely, that it works on a model of the electronic system and not on the fabricated hardware. As a result, hardware emulation systems are limited to design error debugging, and cannot be used for diagnosing manufacturing faults, tool errors, timing errors, etc. An example of such a hardware emulation system is System Realizer from Quicktum Systems, in San Jose, Calif. Specially built prototyping systems comprising FPGAs/PLDs can also be seen as hardware emulation systems. Since hardware emulation is usually much faster than functional simulation, hardware emulation systems may enable use of the software that is supposed to run on the HDL design to be used as a testbench. Even so, hardware emulation typically runs at speeds below one MegaHertz (MHz) while the HDL design is supposed to run at many hundred MegaHertz. In some cases the emulator speed may allow the user to connect the HDL design to the target environment which makes the design of testbenches unnecessary. Even so, with the high speeds of state-of-the-art HDL designs, hardware emulation is not capable of debugging the majority of real-time applications. Another disadvantage is that the special synthesis, mapping, and multi-chip partitioning steps required to bring an HDL design into a hardware emulation system are very complicated and time consuming.

A major drawback of all logic level debugging techniques is that they work at the logic level of abstraction. Since the HDL-based design methodology of electronic systems is much more efficient for todays complex designs, HDL designs have largely replaced logic level designs. Application of logic level debugging techniques to HDL design methodology is highly inefficient. Since logic level debugging does not-relate back to the HDL description, it normally would not provide the designer of the electronic system with sufficient information to correctly diagnose a functional failure.

Hardware behavioral source level emulation provides hardware emulation of source level designs. One technique for debugging HDL designs described at the behavioral level HDL using hardware emulation is described in "Interaktives Debugging algorithmischer Hardware-Verhaltensbeschreibungen mit Emulation" by Gemot H. Koch, Shaker Verlag, Germany, 1998. Some of which is also described in Koch et al., "Breakpoints and Breakpoint Detection in Source Level Emulation," ACM Transactions on Design Automation of Electronic Systems, Vol. 3, No. 2, 1998. The therein described technique is referred to as Source Level Emulation (SLE) and offers an approach for emulating HDL designs, however only if such designs are described in behavioral VHDL. During behavioral synthesis a behavioral HDL design is enhanced for debugging by generating and adding additional circuitry for break-point detection. The behavioral synthesis tool writes out synthesized VHDL which contains a register transfer level description of the enhanced HDL design. The register transfer level description is then synthesized, mapped, and multi-chip partitioned into the emulation hardware. During hardware emulation with a hardware model of the HDL design, the user is able to examine particular variables in the behavioral HDL description.

Control is provided via break-points which are detected using the additional circuitry inside the running hardware model. Break-points in SLE have a very specific meaning. In particular, such break-points are closely tied to behavioral operations in the data-flow of the behavioral HDL description, and are associated with particular states of a controller which is generated by the behavioral synthesis. Additionally, break-points can be made conditioned upon particular values of data-path registers. When a break-point is detected, the execution of the hardware model is stopped. This is done by halting some or all of the system clocks and prevents the registers from changing their current values. Once halted, internal registers can be read. These registers form a scan-chain such that their values can be read by an emulation debugging tool.

Examination of variables in the behavioral HDL description is done in two ways. For variables which are mapped by the behavioral synthesis into registers in the hardware model, their values can be read and related back to HDL identifiers. This is done using map files which keep track of the transformations in behavioral synthesis, register transfer level synthesis, mapping, and multi-chip partitioning. For variables which have not been mapped to registers in the hardware model, their values are computed using a functional model of the behavioral HDL design. This functional model is created during behavioral synthesis and requires the existence of functional models of its components. The values, either read or computed, are then displayed in the behavioral HDL description. Optionally, by overwriting some or all of the registers of the hardware model while the hardware model is halted, the behavior of the HDL design can be modified once the execution of the hardware model is resumed.

Although source level emulation provides a debugging method which works at the level of the HDL description (in this case behavioral VHDL), it has various drawbacks which limits its use in practice. Several of the drawbacks are as follows. First, enhancements for source level emulation must be done inside a behavioral synthesis tool, since it needs special information about the behavioral HDL design which is only available during the behavioral synthesis process. Second, source level emulation does not allow the designer to perform customization. For example, a designer is not able to select trade-offs between hardware overhead and debugging support. Third, source level emulation cannot handle HDL descriptions on levels of abstraction other than the one provided by behavioral VHDL. Explicitly, source level emulation is not applicable for the most commonly used levels of abstraction of RTL HDL and gate-level HDL. Fourth, source level emulation supports neither hierarchy nor re-use of pre-designed blocks. Fifth, there are various limitations and difficulties in relating registers back to behavioral HDL source code. Sixth, in order to examine the state of the hardware model, it is required that some or all of the system clocks be halted and the hardware stopped, which makes source level emulation inapplicable for debugging the majority of today's electronic systems which are not to be stopped.

Thus, there is a need for efficient and effective approaches for debugging HDL-based electronic system designs.

SUMMARY OF THE INVENTION

Broadly speaking, the invention relates to techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

The invention can be implemented in numerous ways including, a method, system, device, and computer readable medium. Several embodiments of the invention are discussed below.

As a hardware debugging system for debugging a fabricated integrated circuit containing an electronic circuit design, one embodiment of the invention includes at least: an instrumentor configured to receive a high level HDL description of the electronic circuit design, to determine aspects of the electronic circuit design to be examined or modified during debugging, to determine additional circuitry to be incorporated into the electronic circuit design to facilitate debugging, and to produce a modified high level HDL description of the electronic circuit design by incorporating an HDL description of the additional circuitry into the high level HDL description of the electronic circuit-design; a design instrumentation database configured to store information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the modified high level HDL description or the high level HDL description; and a HDL-based hardware debugger configured to debug the fabricated integrated circuit fabricated in accordance with the modified high level HDL description by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the modified high level HDL description or the high level HDL description.

As a hardware debugging system for debugging an electronic system containing an electronic circuit design, the electronic circuit design being described by a high level HDL description, one embodiment of the invention includes at least: an instrurentor configured to receive the high level HDL description of the electronic circuit design or a description derived therefrom, to determine aspects of the electronic circuit design to be examined or modified during debugging, to determine additional circuitry to be incorporated into the electronic circuit design to facilitate debugging, and to incorporate the additional circuitry into the electronic circuit design; a design instrumentation database configured to store information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the high level HDL description; and a HDL-based hardware debugger configured to debug the electronic system by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the high level HDL description.

As a hardware debugging system for debugging an electronic system containing an electronic circuit design, the electronic circuit design being described by a high level HDL description, another embodiment of the invention includes at least: instrumentation means for receiving the high level HDL description of the electronic circuit design or a description derived therefrom, determining additional circuitry to be incorporated into the electronic circuit design to facilitate debugging, and incorporating the additional circuitry into the electronic circuit design; a design instrumentation database configured to store information about the additional circuitry including relationships between signals of the electronic circuit design and portions of the high level HDL description; and a HDL-based hardware debugger configured to debug the electronic system by interacting with the electronic circuit design using the additional circuitry and by operating to present debug information with respect to the high level HDL description.

Other aspects and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1A is a block diagram of a hardware debugging system according to one embodiment of the invention;

FIG. 1B is a block diagram of a hardware debugging system according to another embodiment of the invention;

FIG. 2 is a flow diagram of basic instrumentation processing according to one embodiment of the invention;

FIG. 3 is a block diagram of an instrumentation system according to one embodiment of the invention;

FIGS. 4A and 4B are flow diagrams of detailed design instrumentation processing according to one embodiment of the invention;

FIG. 5A is a flow diagram of selection processing according to one embodiment of the invention;

FIG. 5B is a flow diagram of break-point processing according to one embodiment of the invention;

FIG. 5C is a flow diagram of explicit trigger condition selection processing according to one embodiment of the invention;

FIG. 5D is a flow diagram of sampling signal selection processing according to one embodiment of the invention;

FIG. 6 is a diagram of a design instrumentation database according to one embodiment of the invention;

FIG. 7A is a block diagram of an instrumentation system according to one embodiment of the invention;

FIG. 7B is a diagram of a hard block resolution system according to one embodiment of the invention;

FIG. 8 is a block diagram of a representative Design Instrumentation Circuit (DIC) according to one embodiment of the invention;

FIG. 9 describes a representative generic configurable circuitry which can implement design sampling and design patching according to one embodiment of the invention;

FIG. 10 illustrates a representative generic configurable trigger detection circuit according to one embodiment of the invention;

FIG. 11 illustrates a representative state based Finite State Machine design control circuit according to one embodiment of the invention;

FIG. 12 illustrates a representative transition based Finite State Machine design control circuit according to one embodiment of the invention;

FIG. 13 illustrates a representative data-path register design control circuit according to one embodiment of the invention;

FIG. 14 illustrates a representative part of the design control circuit according to one embodiment of the invention;

FIG. 15 is a block diagram of a portion of an instrumentation system which includes a cross-reference analysis module and a cross-reference database according to one embodiment of the invention;

FIG. 16 is a block diagram of a portion of an instrumentation system which includes a DFT analysis module according to one embodiment of the invention;

FIG. 17 is a data flow diagram illustrating DIC creation processing according to one embodiment of the invention;

FIG. 18 is a flow diagram of HDL-based hardware debugging processing according to one embodiment of the invention;

FIG. 19 is a data flow diagram of a debugging process performed by a HDL-based hardware debugger according to one embodiment of the invention;

FIG. 20 is a block diagram of a hardware/software co-debugging system according to one embodiment of the invention; and

FIG. 21 is a block diagram of a hardware/software co-debugging system according to one embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment to the HDL of the hardware designs.

The following discussions will be made clearer by a brief review of the relevant terminology as it is typically (but not exclusively) used. Accordingly, to assist readers in understanding the terminology used herein, the following definitions are provided.

"Software" is defined as but not limited to programming language content written using a programming language. Examples of programming languages include C, C++, Basic, assembly, and Java.

"HDL" is a Hardware Description Language. A hardware description language is defined as any programming language that can describe the hardware portion of an electronic system. Examples of HDLs include VHDL which is described in the IEEE Standard VHDL Language Reference Manual available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J., which is hereby incorporated by reference; Verilog HDL which is described in Hardware Modeling with Verilog HDL by Eliezer Stemnheim, Rajvir Singh, and Yatin Trivedi, published by Automata Publishing Company, Palo Alto, Calif., 1990, which is hereby incorporated by reference; and SystemC which stems from the Open SystemC Initiative (OSCI) originally started by Synopsys, Inc. of Mountain View, Calif. General purpose programming languages such as C++, C, and assembly languages may also be used as a HDL.

A "high level HDL description" is a HDL description in which at least a portion of the description is at register transfer level (RTL) or higher. For VHDL this synthesizable, register transfer level subset is described in the IEEE 1076.6-1999
Standard for VHDL Register Transfer Level (RTL) Synthesis, available from the Institute of Electrical and Electronic Engineers in Piscataway, N. J., which is hereby incorporated by reference. The synthesizable register transfer level subset of the Verilog HDL is described in "Verilog HDL: A Guide to Digital Design and Synthesis" by Samir Palnitkar, SunSoft Press, 1996.

A "RAM" is a Random Access Memory--defined as an electronic component capable of storing data.

"ASIC" is an Application Specific Integrated Circuit. An ASIC device is an electronic component of a system. ASICs are custom devices created for a specific 5 purpose within the electronic system. ASIC devices are easier and faster to create with respect to a full custom semiconductor device. An ASIC may be described using HDL and implemented using synthesis.

An "FPGA" is a Field Programmable Gate Array. FPGAs are electronic components that have a configurable function. These devices are able to change their 10 functionality via an information stream transferred to the device. These electronic components are available from a number of different suppliers in a wide range of sizes and speeds. One example of these devices are the Virtex FPGA devices from Xilinx, Inc. located in San Jose, Calif. An FPGA design may be described using HDL and implemented using synthesis.

A "Central Processing Unit" or "CPU" is circuitry controlling the interpretation and execution of software programmed instructions, performs arithmetic and logical operations on data, and controls input/output functions. For the following descriptions the term CPU will be used to also denote other processing elements such as microprocessors, digital signal processors, microcontrollers, etc.

A "register" is an element in digital circuitry which can store one or more bits. Examples for registers are the various types of flip-flops and latches.

A "PLD" is an Programmable Logic Device. PLDs are electronic components that have a configurable function. These devices are able to change their functionality via an information stream transferred to the device. These electronic components are available from a number of different suppliers in a wide range of sizes and speeds. One example of these devices are the Apex PLD devices from Altera Corporation in San Jose, Calif. A PLD design may be described using HDL and implemented using synthesis.

"Electronic Components" are defined as but not limited to, transistors, logic gates, integrated circuits, semi-custom integrated circuits, full custom integrated circuits, application specific integrated circuits (ASICs), gate arrays, programmable logic devices (PLDs), field prograrrmable gate arrays (FPGAs), CPUs, Random Access Memory (RAM), mixed signal integrated circuits, systems on a chip (SOC), and systems on a printed circuit board.

An "Electronic System" is defined as a system that contains one or more digital and/or analog Electronic Components connected together to perform specific operations or functions. An Electronic System can be implemented entirely of hardware (Electronic Components) or consist of a mix of hardware and software (programming language content).

"Mixed-signal designs" are defined as Electronic System designs which incorporate both digital and analog signals.

The "HDL Design" is referred to as the portion of the electronic system which is described in HDL and implemented in hardware. It is also referred to as the "Design under Test" (DUT).

An "SOC" is a System On Chip. A SOC is defined as a device large enough to contain an entire electronic system implementation. SOC devices can integrate a number of electronic devices into one device.

An "HDL description" is the textual description of an HDL Design. "HDL source code" is referring to the text files which contain the HDL description.

An "HDL identifier" is an object in an HDL description which represents a signal, a set of signals, a storage element, or a set of storage elements and which can take a value from a set of possible values. Each HDL identifier is associated with a particular scope defined by the syntax of the umderlying hardware description language.

A "Technology Mapping Process" is defined as the process of transforming a particular representation of an electronic design into a design consisting entirely of primitive electronic elements from a design library for a target technology. The representation of said electronic design from which the Technology Mapping Process begins is dependent on the particular Technology Mapping Process being employed. However, said representation usually consists of simple boolean elements. For example, said representation may consist entirely of an interconnected set of 2-input/1-output logic elements with each said element performing the NAND function. An example of a tool that performs the Technology Mapping Process is Design Compiler from Synopsys in Mountain View, Calif.

"Synthesis" is defined as the process of creating an electronic implementation from the functional description of a system. An example of a tool that performs this operation is Design Compiler from Synopsys in Mountain View, Calif. which reads electronic system descriptions written in a synthesizable subset of VHDL and Verilog and produces a technology mapped design as an output.

"Behavioral HDL" is an HDL description at an algorithmic level of abstraction in which neither the timing behavior nor the structure of the HDL Design is explicitly described.

"Behavioral synthesis" transforms a behavioral HDL description into a register transfer level (RTL) description where the timing behavior and the structure of the HDL Design is fixed. This RTL description is then processed in synthesis and technology mapping. An example of a tool that performs behavioral synthesis is Behavioral Compiler from Synopsys, Inc. of Mountain View, Calif.

A "System Clock" is defined as a main timekeeping signal in a design. All operations that are relative to the System Clock will proceed when the System Clock becomes active.

"Constraints" are defined as limits placed on parameters for the implementation of an electronic system. Parameters of an electronic system can include but are not limited to register to register propagation delay, system clock frequency, primitive element count, and power consumption. These constraints can be used by synthesis tools to guide the implementation of the electronic design.

"Fabrication" is the process of transforming a synthesized and technology mapped design into one or more devices of the target technology. For example, the fabrication of ASICs involves manufacturing and the fabrication of FPGAs and PLDs involves device configuration.

"DFT" is Design-for-test. DFT is defined as a process in which an electronic system designer will include structures in the electronic system that facilitates manufacturing testing.

"Design Rule Check" (DRC) are checks performed before integrated circuit manufacturing to ensure that in the placed and routed technology mapped design none of the rules of the target technology process is violated. Examples for such DRC are checks for shorts, spacing violations, or other design-rule problems between logic cells. An example for a tool that does DRC is Dracula from Cadence Design Systems, Inc. in San Jose, Calif.

A "Functional Specification" is defined as the documentation that describes the necessary features and operations of a system.

A "functional failure" is a behavior of a design which does not meet the functional specification which was used in the creation of the design. Every step in the design process can potentially cause a functional failure. Functional failures can be classified depending on which step of the design process caused the functional failure.

A "fault" is a specific type of functional failure. This type of failure is due to one or more manufacturing defects causing a functional failure in the fabricated design.

A "design error" is a specific type of functional failure where the HDL description's behavior did not match the functional specification.

A "tool error" is a specific type of functional failure which was introduced by design tools because the HDL description was not properly processed such that the functional specification is not met by the implementation.

An "environment error" is a specific type of functional failure caused by a particular combination of environmental parameters such as temperature, humidity, pressure, etc.

A "Functional Simulator" is a tool that mimics the functional behavior of a model of an electronic system which is described using HDL.

A "Testbench" is defined as an electronic system description that presents stimulus to and/or gathers information from the target electronic system design to be verified. In some cases the testbench ignores the response from the target electronic system design. A testbench is used to mimic the behavior of the target environment in which the electronic system being developed will operate. A testbench may comprise both hardware and software.

A "Target Environment" is the system the electronic system is specified to interact with and/or to run in. A target environment may comprise both hardware and software.

The "Target Speed" of an electronic system is the speed and/or the speed range the electronic system is specified to run at. Examples for measures for the target speed and the speed range are clock frequency, response time, time to propagate, and cycle time.

"Debugging" is the process of comparing the behavior of an implementation of the electronic system to the electronic system functional specification. The purpose of debugging is to find causes and remedies for functional failures.

"Co-Debugging" or "hardware/software co-debugging" is defined as the process of debugging the software and hardware of an electronic system concurrently.

A "FSM" is Finite State Machine--defined as an electronic system control structure. The design and implementation of FSM is described in great detail in Synthesis and Optimization of Digital Circuits, by Giovanni DeMicheli, McGraw Hill, 1994.

A "HDL Building Block" is a functional unit of an HDL Design from which the HDL Design is constructed. A HDL Building Block (BB) performs calculations on the signals to which it is connected and communicates with other BBs in the design. The communication is through connecting internal signals of a BB to communication ports of the BB and/or connecting internal signals of the BB to communication ports of other BBs in the HDL Design. Examples of BBs are Entities in the VHDL language and Modules in the Verilog language.

A "Hard Block" is an electronic system which has a pre-defined functionality and which can be incorporated into another electronic system. Commonly, the form of the Hard Block is such that the functionality of the Hard Block can not be altered. An example of a hard block is an HDL Design which implements a industry standard bus controller.

A "Design State" is defined as the logical values taken by the storage elements of the design at a particular time, combined with the logical values taken by the inputs of the design taken at the same particular time.

The "System State" or "State of the System" is a synonym for "Design State." "Real-time" means a task, process or response occurs substantially immediately. The term is used to describe a number of different computer features. For example, real-time operating systems are systems that respond to input immediately. Real-time is also used for describing tasks in which the computer must react to a steady flow of new information without interruption. Real-time can also refer to events simulated by a computer at the same speed that they would occur in real life.

Embodiments of this aspect of the invention are discussed below with reference to FIGS. 1 21. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments.

FIG. 1A is a block diagram of a hardware debugging system 100 according to one embodiment of the invention. The hardware debugging system 100 operates to debug a hardware product referred to herein as a Device Under Test (DUT) 102. The DUT 102
is typically part of a larger hardware product referred to as an electronic system 104. The DUT 102 can pertain to a single integrated circuit chip, multiple integrated circuit chips, a system on a chip, or a system on a printed circuit board.

According to the invention, the DUT 102 includes Design Instrumentation Circuitry (DIC) 106. The DIC 106 is provided within the DUT 102 in order to facilitate debugging of the DUT 102. The DIC 106 can be provided within the DUT 106 in either a centralized or distributed manner.

The hardware debugging system 100 operates to determine the DIC 106 that is provided within the DUT 102. In this regard, an original HDL description 108 of the electronic system 104 is received at an instrumentor 110. The instrumentor 110
modifies or alters the original HDL description 108 to produce an instrumented HDL description 112. The instrumented HDL description 112 represents not only the electronic system 104 with the DUT 102 provided therein, but also the DIC 106 that is provided within the DUT 102. The instrumentor 110 also stores DIC information to a design instrumentation database 114. By storing the DIC information in the design instrumentation database 114, the hardware-based debugging of the DUT 102 is facilitated.

The hardware debugging system 100 also includes synthesis and place & route systems 116. The synthesis and place & route systems 116 receives the instrumented HDL description 112 and performs conventional synthesis as well as place & route operations in order to produce an instrumented design 118. Although not shown in FIG. 1A, other additional tools can be utilized to produce or enhance the instrumented design 118. Examples of additional tools include a Design-For-Test (DFT) tool or a Design Rule Check (DRC) tool. The instrumented design 118 represents a description (e.g., design files) of the electronic system 104 that would be thereafter fabricated. Hence, once the instrumented design 118 is available, fabrication 120 can be performed. The fabrication 120 produces the electronic system 104 having the DUT 102 with the DIC 106 provided therein. Fabrication is the process of transforming a synthesized and technology mapped design (e.g., the instrumented design 118) into one or more devices of the target technology. For example, if the target technology is Application Specific Integrated Circuits (ASICs) then the fabrication involves manufacturing, and if the target technology is Field Programmable Gate Arrays (FPGAs) or Programmable Logic Devices (PLDs) the fabrication involves device configuration.

At this point, the electronic system 104 is a hardware product that has been produced. This hardware product can then be debugged using a HDL-based hardware debugger 122. More particularly, the HDL-based hardware debugger 122 couples to the DIC
106 so that it is able to communicate with the DIC 106 when debugging the DUT 102. The HDL-based hardware debugger 122 also couples to the design instrumentation database 114 so that access to the DIC information is available. As a result, the HDL-based hardware debugger 122 enables a user to debug the DUT 102 and/or hardware and/or software interacting with the DUT 102 in close relation to the original HDL description 108. Further, in one embodiment, debugging can be performed while the electronic system 104 and the DUT 102 operate in the target environment, at target speed.

FIG. 1B is a block diagram of a hardware debugging system 150 according to another embodiment of the invention. The hardware debugging system 150 is similar to the hardware debugging system 100 and includes many of the same components. Hence, the hardware debugging system 150 enables a user of the HDL-based hardware debugger 122 to debug the DUT 102 of the electronic system 104 and/or hardware and/or software interacting with the DUT 102, as noted above. However, the hardware debugging system 150 includes a synthesis and place & route system 152 that includes an instrumentor 154. Hence, the original HDL description 108 is supplied to the synthesis and place & route system 152. The synthesis and place & route system 152 can then produce the instrumented design 118 while using not only synthesis and place & route tools but also the instrumentor 154. In this embodiment, the instrumentor 154 is able to be embedded within synthesis and place & route system 152. Here, the instrumentor 154 assists with producing the instrumented design 118 which represents the electronic system 104 having the DIC 106 provided within the DUT 102. However, with the hardware debugging system 150, the original HDL description 108 need not be modified to produce an instrumented HDL description.

FIG. 2 is a flow diagram of basic instrumentation processing 200 according to one embodiment of the invention. The basic instrumentation processing 200 is, for example, performed by the instrumentor 110 illustrated in FIG. 1A or the instrumentor
154 illustrated in FIG. 1B.

The basic instrumentation processing 200 initially receives 202 a HDL description for an electronic system. The HDL description is then analyzed 203 to understand the characteristics of the electronic system. Next, parts (or portions) of the electronic system that are to be examined and/or modified are determined 204. Typically, the parts of the electronic system to be examined and/or modified (e.g., instrumented) are within a DUT such as the DUT 102 illustrated in FIGS. 1A and 1B. Hence, the parts of the electronic system to be examined and/or modified represent various signals and/or components within the DUT. After the parts of the electronic system to be examined and/or modified have been determined 204, design instrumentation circuitry (DIC) is generated 206. Preferably, the DIC is determined 204 based on the parts of the electronic system to be examined and/or modified. In this regard, the DIC can be at least partially customized to the application such as the amount or degree of testing or debugging desired. Thereafter, the DIC is incorporated 208 into the electronic system. The DIC can be incorporated 208 into the electronic system (namely, the DUT) in various ways. In one embodiment, the DIC can be incorporated by adding HDL to the original HDL for the electronic system. In another embodiment, the DIC can be incorporated by modifying a netlist description for the electronic system. Following the operation 208, the basic instrumentation processing 200 is complete and ends.

Design instrumentation (DI) is a process by which a HDL description of an electronic system is analyzed, and then a DIC computed. The DIC is thereafter incorporated (e.g., added) into the electronic system to facilitate debugging. The DIC can be added to the electronic system in a variety of ways. In one embodiment, DIC can be added to the electronic system by adding an HDL description of the DIC to the HDL description of the electronic system. In another embodiment, the DIC can be added to the electronic system during synthesis. The DIC provides mechanisms to control the examination and/or modification of a running electronic system. Thus, the DIC allows to analyze, diagnose, and/or debug the DUT by giving detailed and accurate information about its current state of operation, as well as the state history.

FIG. 3 is a block diagram of an instrumentation system 300 according to one embodiment of the invention. The instrumentation system 300 operates to perform design instrumentation operations to produce an appropriate DIC.

The instrumentation system 300 includes an instrumentor 302. The instrumentor 302 operates to determine the appropriate DIC for the electronic system (namely, the DUT) that is to be eventually hardware debugged. The instrumentor 302 receives an original HDL description 304 as well as instrumentation directives 306. The instrumentation directives 306 are instructions to the instrumentor 302 that inform the instrumentor 302 of the portions, parts or areas of the original HDL description 304 that are to be examined and/or modified. The instrumentation directives 306 can be predetermined or interactively provided by a user through a user interface. Additionally, the instrumentor 302 can further receive design constraints 308, Design For Test (DFT) information 310, instrumented pre-designed blocks 312 and DIC template(s) 314.

The design constraints 308 are constraints on the particular design associated with the original HDL description 304. More particularly, design constraints are limits placed on parameters for an implementation of an electronic system. Some examples of the parameters that can be limited by design constraints include register-to-register propagation delay, system clock frequency, primitive element count, and power consumption. The constraints on the parameters are used by synthesis and place & route tools to guide the implementation of the electronic design.

The DFT information 310 is information about features (e.g., structures) of the original HDL description 304 that pertain to testing. The DFT information is used to facilitate manufacturing testing. For example, the DFT information 310 can provide a description of a scan-chain provided within the original HDL description 304. The instrumentor 302 can utilize portions of the DFT information 310 to reduce the circuitry required for the DIC.

The DIC can make use of previously instrumented pre-designed blocks 312. In case the electronic system contains pre-designed blocks which have been instrumented, the DIC can communicate with the previously instrumented pre-designed blocks 312 to facilitate their debugging. The DIC template(s) 314 provide one or more templates for the instrumentor 302 to utilize when producing the DIC.

The instrumentor 302 outputs an instrumented description 316. In one embodiment, the instrumented description 316 can be represented as an instrumented HDL description in which the original HDL description 304 has been enhanced to include a HDL description of the DIC (see FIG. 1A). In another embodiment, the instrumented description 316 can represent an instrumented netlist (see FIG. 1B). The instrumentor 302 also produces an optional DIC HDL description 318. The DIC HDL description 318 can be utilized by a functional simulator or synthesis and place & route tools. The instrumentor 302 can also produce an optional DIC simulation model 322 that permits functional simulation of the instrumented description 316. Still further, the instrumentor 302 can output synthesis and place & route constraints 324 and modified DFT information 326. The synthesis and place & route constraints 324 can be utilized by the synthesis and place & route tools. The modified DFT information 326 can also be used by the synthesis and place & route tools, so that the resulting electronic system is able to be tested as originally designed.

The instrumentation system 300 also includes a design instrumentation database 320 that stores instrumentation information. The instrumentation information includes information on the types of instrumentations that have been done, the DIC and other information as explained in greater detail below. As noted above, an HDL-based hardware debugger (e.g., debugger 122) eventually utilizes the DIC information stored in the design instrumentation database 320 when performing hardware debugging of the electronic system. Additional details on the design instrumentation database 320 are provided in FIG. 6 below.

FIGS. 4A and 4B are flow diagrams of detailed design instrumentation processing 400 according to one embodiment of the invention. The detailed design instrumentation processing 400 is, for example, performed by the instrumentor 110 illustrated in FIG. 1A, the instrumentor 154 illustrated in FIG. 1B, or the instrumentor 302 illustrated in FIG. 3.

The detailed design instrumentation processing 400 initially receives 402 a HDL description of an electronic system. The HDL description is then parsed and analyzed 404. The analysis 404 of the HDL description can identify portions that cannot be instrumented or that can only be instrumented in certain ways. The result of the analysis 404 can be used to determine whether particular instrumentation directives are valid, and thus can be followed by the instrumentor.

Additionally, one or more of design constraints, DFT information, predetermined instrumentation directives, or pre-designed blocks may also optionally be received 406. Then, instrumentation directives are determined 408. Here, instrumentation directives can be predetermined and thus provided or can be determined through user interaction. FIGS. 5A 5D, discussed below, pertain to user interaction to produce instrumentation directives.

After the instrumentation directives are determined 408, a customized DIC is produced 410 based on the HDL description and the instrumentation directives. Hence, the customized DIC is tailored to the particular HDL description and the particular instrumentation directives. By tailoring the DIC to the particular HDL description and the particular instrumentation directives, the customized DIC makes efficient use of its circuitry. Since the DIC consumes area (e.g., die space) on the hardware product (e.g., semiconductor chip), making the customized DIC efficient and compact is advantageous. In producing the customized DIC, the detailed design instrumentation processing 400 is able to reuse pre-designed blocks that have already been instrumented. In other words, the customized DIC can communicate with existing DICs of pre-designed blocks that represent other portions of the electronic system (or even external systems).

Additionally, the DIC can be optimized 412 to reduce hardware overhead and/or maximize coverage. Here, the optimization 412 to the DIC enables the hardware overhead associated with the DIC to be reduced which is advantageous in producing or using integrated circuit products. For example, cost analysis can be performed during the optimization to explore the different structures in the context of a given implementation technology and given design constraints. Variations of the DIC can thus be explored in order to minimize the overhead of the DIC on the hardware in terms of area, delay, power consumption, routability, and/or testability. Variations of the DIC can be described via DIC templates. The optimization 412 can also try to increase the effects of the instrumentation with regards to the hardware overhead. For example, if some certain signals can be examined, some other signals may also be able to be examined without any or minimal hardware overhead.

Next, a decision 414 determines whether design constraints have been provided. Typically, the design constraints are provided in a file which contains specifications for area, delay, power consumption, routability and testability. When the decision 414 determines that design constraints have been provided, then the DIC may be modified 416 in view of the design constraints. Also, modifications to the design constraints may be performed so that the overall design of the electronic system (including the DIC) complies with the intent of the original design constraints. For example, timing constraints may be changed to reflect the insertion of the DIC. In addition, additional design constraints might be generated, which, for example, may be used to guide synthesis and place & route tools in optimizing the DIC.

Following operation 416, as well as following the decision 414 when design constraints are not provided, a decision 418 determines whether DFT information has been provided. When the decision 418 determines that DFT information has been provided, then the DFT information is complied with or reused 420. When complied with, the detailed design instrumentation processing 400 renders the customized DIC compatible or compliant with the DFT information (e.g., existing DFT structures in the design). For example, scan-chains or boundary-scans can be provided or modified to take into account the DIC. Alternatively, when the DFT information is reused, the customized DIC can make use of portions of the circuitry made available through the DFT information and thereby make use of existing circuitry. The modifications to the DFT information can reflect the ability of the DIC to utilize portions of the circuitry within the electronic system associated with the DFT information as well as with the ability to modify the DFT information to preserve the intent of the designer after the DIC is included within the electronic system.

Following the operation 420, as well as following the decision 418 when the DFT information is not provided, a decision 422 determines whether instrumented, pre-designed blocks have been provided. When the decision 422 determines that instrumented, pre-determined blocks have been provided, then the DIC of each instrumented, pre-designed block is connected 424 to the current DIC. This facilitates debugging of the electronic system which contains pre-designed blocks.

Following operation 424, as well as following the decision 422 when instrumented, pre-designed blocks are not provided, DIC information is stored 426 to a design instrumentation database. The DIC information includes a description of the DIC, the instrumentation directives, and DIC connectivity information. The DIC information can also include cross-reference data that relates elements in the design of the electronic system (i.e., hardware implementation) to and from the HDL description. Then, the customized DIC can then be added 428 to the electronic system. The customized DIC can be added 428 to the electronic system in a variety of different ways. For example, with respect to an embodiment such as illustrated in FIG. 1A, the customized DIC can be added 428 to the electronic system by producing the instrumented HDL description which describes the electronic system with the DIC included therein. Alternatively, with respect to an embodiment such as illustrated in FIG. 1B, the customized DIC can be added to the electronic system by modifying a netlist that defines the electronic system.

Following operation 428 the detailed design instrumentation processing 400 operates to produce and output 430 the instrumented description, an optional DIC simulation model and an optional DIC HDL description. The DIC simulation model can be used by a simulator when functionally simulating the operation of the DUT. The DIC HDL description may for example also be used for simulation. Following the operation 430, the detailed design instrumentation processing 400 is complete and ends.

As noted above, the instrumentation directives can be predetermined and thus provided or can be determined through user interaction. When the instrumentation directives are predetermined, they can be obtained from a design instrumentation file. In one embodiment, the instrumentation directives specify design visibility, design patching and design control criteria for particular portions of the design for the electronic system.

Design Visibility (DV) is monitoring the entire or partial state of the DUT at, and relative to, predetermined events. An important aspect of DV is relating the states of operation back to identifiers in the original HDL description for examination during HDL-based hardware debugging. In one embodiment, DV is done by sampling the values of one or more signals of the DUT for a particular time interval determined by one or more predetermined events. The events are determined by Design Control which is described below. Design Visibility serves to monitor the state of operation of the DUT, but does not alter the DUT's behavior in any way. However, in some situations, it is advantageous to have a method to alter the behavior of the DUT after the hardware has been fabricated. Design Patching (DP) is to alter the behavior of the DUT to a predetermined particular desired state at predetermined events. The events are determined by Design Control which is described below. A particular desired state of a DUT is a particular setting of the values of all or a subset of all storage components in the DUT.

Design Control (DC) provides the designer with a method to specify the events that control DV and DP. DC can be accomplished by one or more trigger conditions. A trigger condition is a conditional expression comprising HDL identifiers where the conditional expression denotes a combination comprising a particular state and/or state transition, and/or history of states and/or history of state transitions, the DUT, or a portion of it, can be in. Each time a particular trigger condition is met an associated trigger event is produced. One or more trigger events can be combined to issue a particular predetermined trigger action which may control the DV and DP and may control other functions related to HDL-based hardware debugging. A unique combination comprising one or more units of DV and/or DP all controlled by the same trigger action forms a trigger action group.

A watch-point is a special case of a trigger condition which is explicitly defined using a predetermined conditional expression of HDL identifiers. A watch-point has no direct relationship with the HDL description other than its expression is made up with identifiers of the HDL description.

A break-point is a special case of a trigger condition, where the trigger condition is implicitly specified by selecting a particular source code location in the HDL description. A source code location is a unique combination comprising a file name, a line number and a column position within a textual HDL description.

An error trap is a special case of a watch-point where the trigger condition describes an erroneous or undesired state of the hardware. A property check is a special case of an error trap where the trigger condition is explicitly specified by a particular property of a portion of the hardware. In the event such property is not fulfilled the trigger condition is met. Properties to be checked can either be implicitly derived from the functionality of the hardware or explicitly given by the designer of the electronic system.

FIG. 5A is a flow diagram of selection processing 500 according to one embodiment of the invention. The selection processing 500 pertains to user interaction with the HDL description to produce instrumentation directives. The selection processing 500 is, for example, performed by operation 406 illustrated in FIG. 4A when determining instrumentation directives.

The selection processing 500 initially displays 502 a HDL description. The HDL description pertains to the electronic system. At this point, a user can interact with a graphical user interface to make a specific instrumentation directive with respect to the HDL description being displayed. Optionally, to guide a user in his selections, the results of an analysis of the original HDL description can be displayed as well (e.g., operation 404, FIG. 4A). Examples of the particular types of instrumentation directives include a selection of a trigger condition, a sampling signal or a patching signal. Hence, a decision 504 determines whether a trigger condition selection has been made. When the decision 504 determines that a trigger condition selection has been made, then trigger condition selection processing 506 is performed. Alternatively, when the decision 504 determines that a trigger condition selection has not been made, then a decision 508 determines whether a sampling signal selection has been made. When the decision 508 determines that a sampling signal selection has been made, then sampling signal selection processing 510 is performed. On the other hand, when the decision 508 determines that a sampling signal selection has not been made, then a decision 512 determines whether a patching signal selection has been made. When the decision 512 determines that a patching signal selection has been made, then patching signal selection processing 514 is performed. Following any of operations 506, 510 and 514, as well as following the decision 512 when a patching signal selection has not been made, instrumentation optimization can be performed 516. The instrumentation optimization operates to consolidate the various selections so that the DIC required to implement the various trigger conditions, sampling signals and patching signals can be efficiently implemented. Following the operation 516, a decision 518 determines whether more selections are to be made by the user. When the decision 518 determines that more selections are to be made, then the selection processing 500 returns to repeat the decision 504 and subsequent operations. Alternatively, once the decision 518 determines that no more selections are to be made, the selection processing 500 is complete and ends.

The trigger condition selection processing 506 illustrated in FIG. 5A can be utilized to select or establish implicit trigger conditions or explicit trigger conditions. An example of an implicit trigger condition is a break-point, and an example of an explicit trigger condition is a watch-point, or an error trap, or a property check.

FIG. 5B is a flow diagram of break-point processing 520 according to one embodiment of the invention. The break-point processing 520 represents an embodiment of the trigger condition selection processing 506 in the case in which an implicit trigger condition (namely, a break-point) is involved.

The break-point processing 520 initially identifies 522 feasible break-point conditions and types. Typically, such information is obtained analyzing the original HDL description (e.g., operation 404, FIG. 4A). Next, the feasible break-point conditions and types are displayed 524. Here, the feasible break-point conditions and types can be displayed to a user by a user interface. At this point, a user is able to select a location within the HDL description of the electronic system where a break-point is to be set. In one embodiment, a user interface assists the user in making such a location selection with respect to the HDL description (i.e., HDL location). A decision 526 determines whether a HDL location has been selected. When the decision 526 determines that a HDL location selection has not yet been made, then the decision 526 causes the break-point processing 520 to await such a selection. Once the decision 526 determines that a HDL location has been selected, then a decision
528 determines whether the selected HDL location is permitted. In other words, the decision 528 determines whether it is valid to instrument the location within the HDL description of the electronic system with a break-point. When the decision 528
determines that the selected HDL location is not permitted, then an error message is displayed 530. On the other hand, when the decision 528 determines that the selected HDL location is permitted, then the status type of the selected break-point is updated 532. Next, break-point information is entered 534 into the trigger condition database for later processing. The break-point information comprises the IDL location of the selected break-point, and the current status type. According to one embodiment, the status type for a selected break-point is "selected".

FIG. 5C is a flow diagram of explicit trigger condition selection processing 540 according to one embodiment of the invention. As noted previously, one example of an explicit trigger condition is a watch-point. The explicit trigger condition selection processing 540 begins with a decision 542 that determines whether a trigger condition expression has been received. In one embodiment, a user interface assists the user in providing such information. The trigger condition expression defines the explicit trigger condition being set. When the trigger condition expression has not yet been received, the decision 542 causes the explicit trigger condition processing 540 to await receipt of such information (selections). When the decision 542
determines that a trigger condition expression has been received, the status type of the selected trigger condition is updated 544. For example, the status type for the selected (explicit) trigger condition is "selected". Then trigger condition information is entered 546 into the trigger condition database. The trigger condition information includes the trigger condition expression, the HDL identifiers involved in building the trigger condition expression, and a status type.

Although the break-point processing 520 and the explicit trigger condition processing 540 illustrated in FIGS. 5B and 5C pertain to selection and/or entry of trigger conditions, it should be noted that selections can also be made to de-select previously selected trigger conditions. Such processing is generally similar to the selection processing, with the major exception being that the status type of the selected trigger condition is updated to "non_selected", meaning that no instrumentation shall be performed regarding to that portion of the HDL description.

FIG. 5D is a flow diagram of sampling signal selection processing 560 according to one embodiment of the invention. The sampling signal selection processing 560 is, for example, one representative implementation of the sampling signal selection processing 510 illustrated in FIG. 5A.

The sampling signal selection processing 560 begins with a decision 562 that determines whether a signal selection has been received. Here, a user is able to select signals by selection of an HDL identifier within the HDL description of the electronic system. In one embodiment, a user interface assists the user in making such a selection with respect to the HDL description. Hence, the decision 562 determines whether such a signal selection has occurred. When the decision 562 determines that a signal selection has not yet occurred, the sampling signal selection processing 560 awaits such a selection. Once the decision 562 determines that a signal selection has been received, then a decision 564 determines whether the selected signal is to be associated with an existing trigger action group of a prior signal selection or whether it becomes a member of a new trigger action group. When decision 564 determines that the signal selection is to be associated with an existing trigger action group, a decision 566 determines whether the user has selected an existing trigger action group. In one embodiment, a user interface assists the user in making such a selection. When the decision 566 determines that a trigger action group selection has not yet been received, the sampling signal selection processing 560 awaits such a selection. Once the decision 566 determines that a trigger action group has been selected, the selected signal is associated 568 with the selected trigger action group. On the other hand, when the decision 564 determines that the selected signal shall become a member of a new trigger action group, a new trigger action group is created 570 and the selected signal is associated 568 with that new trigger action group. Following operation 568, the status type of