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United States Patent6941536
MuranakaSeptember 6, 2005
Title
Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip
Abstract
In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.
Inventors:Muranaka; Masaya (Akishima, JP)
Assignee:Hitachi, Ltd. (Tokyo, JP)
Hitachi ULSI Systems Co., Ltd. (Tokyo, JP)
Appl. No.:433161
Filed:October 15, 2003
PCT 102e Date:October 15, 2003
PCT 371 Date:October 15, 2003
PCT File Date:September 6, 2001
PCT No:PCT/JP01/07727
PCT Pub Date:June 6, 2002
PCT Pub No:WO02/45139
Foreign Application Priority Data
Dec 01, 2000 [JP] PCT/JP00/08500
Current U.S. Class:716/14 257/E21.521 257/E23.179 
Field of Search:716/4 700/97 702/108 710/23 257/E23.179
U.S. Patent Documents
5617364April 1997Hatakeyama
5983331November 1999Akamatsu et al.
6161052December 2000Charlton et al.
6161213December 2000Lofstrom
6289292September 2001Charlton et al.
6415339July 2002Farmwald et al.
Foreign Patent Documents
1-100943Apr., 1989JP
1-269299Oct., 1989JP
10-55939Feb., 1998JP
11-214274Aug., 1999JP
4-369750Dec., 1992JP
5-67683Mar., 1993JP
56-50526May., 1981JP
6-196435Jul., 1994JP
6-291170Oct., 1994JP
64-37847Feb., 1989JP
7-335509Dec., 1995JP
7-50233Feb., 1995JP
8-213464Aug., 1996JP
8-29493Feb., 1996JP
Primary Examiner: Lebentritt; Michael
Assistant Examiner: Stevenson; Andre
Attorney, Agent or Firm:Miles & Stockbridge P.C.
Claims

What is claimed is:
1. A semiconductor integrated circuit device having a plurality of identification elements formed to have the same form through the same manufacturing process as one another, and configured to have unique identification information determined by said plurality of identification elements, wherein said unique identification information takes a state corresponding to a relation of respective magnitudes of a parameter of said plurality of identification elements to one another, caused by variations in characteristics of said plurality of identification elements, and wherein said unique identification information includes a plurality of comparison information representing results of comparing the parameter of each identification element with the parameter of the other identification elements.

2. A semiconductor integrated circuit device according to claim 1, wherein each of said plurality of comparison information includes a plurality of bits representing the results of comparing the parameter of respective particular identification elements.

3. A semiconductor integrated circuit device according to claim 2, wherein each of said plurality of comparison information includes information, having a compressed number of bits, generated by data-converting information generated from a direct comparison of the parameter of said respective particular identification elements.

4. A semiconductor integrated circuit device according to claim 3, wherein said unique identification information includes ordering information, indicative of an order of the respective magnitudes of the parameter of said plurality of identification elements, having a smaller number of bits than a number of comparisons of a particular identification element with other identification elements.

5. A semiconductor integrated circuit device according to claim 1, wherein said unique identification information includes a plurality of ordering information corresponding to said plurality of identification elements, respectively.

6. A semiconductor integrated circuit device according to claim 1, wherein said unique identification information includes ordering information which reflects an order of the respective magnitudes of the parameter of said plurality of identification elements.

7. A semiconductor integrated circuit device according to claim 6, wherein said ordering information includes a number of bits less than a number of comparisons of a particular identification element with other identification elements.

8. A semiconductor integrated circuit device according to claim 1, wherein each of said identification elements includes a logic circuit, and said relation of magnitude in the parameter indicates a relation of magnitude in an electrical parameter of the logic circuits.

9. A semiconductor integrated circuit device according to claim 8, wherein said logic circuits include inverter circuits.

10. A semiconductor integrated circuit device according to claim 8, wherein each of said logic circuits provides an output voltage equal to a threshold value voltage at its respective output, wherein said threshold value voltage is said electrical parameter, and wherein said logic circuits have their respective inputs electrically connected to their respective outputs.

11. A semiconductor integrated circuit device according to claim 10, wherein said logic circuits include inverter circuits.

12. A semiconductor integrated circuit device according to claim 10, wherein each identification element includes a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET, each of which is applied with an input voltage at an input to form an output voltage at an output terminal thereof.

13. A semiconductor integrated circuit device according to claim 12, wherein said CMOS inverter circuit input terminal is connected to said CMOS inverter circuit output terminal to form said output voltage.

14. A semiconductor integrated circuit device according to claim 13, further comprising: a voltage comparator circuit having a first input terminal and a second input terminal; a first switch and a second switch provided for each of said CMOS inverter circuits, said first switch transferring an output voltage of a CMOS inverter circuit corresponding thereto to the first input terminal of said voltage comparator circuit, said second switch transferring the output voltage to the second input terminal of said voltage comparator circuit; and a control circuit for controlling said first switches and said second switches such that said voltage comparator circuit compares the respective output voltage of each CMOS inverter circuit with the output voltages of the other CMOS inverter circuits.

15. A semiconductor integrated circuit device according to claim 14, wherein said first and second switches are MOSFET switches.

16. A semiconductor integrated circuit device according to claim 13, further comprising: a first switch, a second switch and a third switch provided for each of said CMOS inverter circuits; and a control circuit for controlling said first, second and third switches, wherein said first switch is disposed between an input terminal and an output terminal of a CMOS inverter circuit associated therewith; said second switch is disposed between a common first circuit node and the input terminal of the CMOS inverter circuit associated therewith; said third switch is disposed between the output terminal of the CMOS inverter circuit associated therewith and a common second circuit node; and said control circuit controls said first, second and third switches such that two each of said CMOS inverter circuits are grouped into a set, and an input terminal and an output terminal of one of the CMOS inverter circuits are connected to output an output voltage from the one CMOS inverter, the output voltage of the one CMOS inverter circuit is supplied to an input terminal of the other CMOS inverter circuit through said first circuit node, and an output signal, which is the result of determining a potential of the output voltage of said one CMOS inverter circuit, is applied from the other CMOS inverter circuit to said second circuit node, with a logical threshold value voltage of the other CMOS inverter circuit being used as a reference voltage.

17. A semiconductor integrated circuit device according to claim 16, wherein said first, second and third switches are MOSFET switches.

18. A semiconductor integrated circuit device according to claim 16, wherein said CMOS inverter circuits and said first, second and third switches comprise elements which make up a CMOS gate array.

19. A semiconductor integrated circuit device according to claim 18, wherein said first, second and third switches are MOSFET switches.

20. A semiconductor integrated circuit device according to claim 16, wherein said CMOS inverter circuits are applied with a limited operating voltage when no operation is performed for determining the relation of magnitudes of the electrical parameter.

21. A semiconductor integrated circuit device according to claim 20, wherein said first, second and third switches are MOSFET switches.
Description
TECHNICAL FIELD

The present invention relates to a method for identifying a semiconductor integrated circuit device, a method for manufacturing a semiconductor integrated circuit device, a semiconductor integrated circuit device and a semiconductor chip, and mainly relates to the technology for assigning identification information unique to semiconductor integrated circuit devices or semiconductor chips to identify individual semiconductor integrated circuit devices or semiconductor chips.

BACKGROUND ART

A semiconductor integrated circuit device can be utilized in a variety of desired manners based on identification information unique thereto, if such identification information is assigned. If unique identification information can be set to semiconductor integrated circuit devices on a one-by-one basis, a novel manufacturing method and product management technique, demonstrated by the inventors, can be provided under the utilization of the unique identification information, as described later.

When a fault occurs at a stage such as an actual use stage of a semiconductor integrated circuit device, factors causing the fault is readily pursued if unique identification information can be retrieved from the semiconductor integrated circuit device. For example, a semiconductor maker can acquire information such as the manufacturing term, manufacturing line, manufacturing lot, testing history, design information and the like based on the unique identification information of the semiconductor integrated circuit device. This facilitates the pursuit of factors which cause the fault and countermeasures to be taken therefor.

The marking based on an ink printing method or a laser impressing method given to a package, which forms part of a semiconductor integrated circuit device, can be regarded as one type of identification information. While this type of marking mainly comprises a product model name of the semiconductor integrated circuit device, the product model name may be accompanied by a code representation of the manufacturing term such as year, week and the like. However, with this type of marking representation, it is difficult to set unique identification information to semiconductor integrated circuit devices on a one-by-one basis, which can be manufactured in large quantity or manufactured over a long term as industrial products, due to the shortage of the amount of information which can be represented thereby.

It can be assumed to set a programmable element such as a fuse element to a semiconductor chip which forms part of a semiconductor integrated circuit device and to give unique identification information inherent to the programmable element. However, if the original semiconductor integrated circuit device does not need a program element, this type of assumable technique would disadvantageously cause a complicated manufacturing process and an increased cost of the semiconductor integrated circuit device due to the requirement for an additional manufacturing step for the programmable element. The manufacturing process will be free from additional complication if the semiconductor integrated circuit device originally has a programmable element. Even in this case, an additional or modified manufacturing step is needed for writing unique recognition information into the programmable element.

In a know technique referred to as "silicon signature," a product model name or unique information is written into a semiconductor integrated circuit device in such a manner that they can be electrically read out. However, this type of technique requires an additional or modified manufacturing step for writing the information, as is the case with the foregoing.

The inventors were informed, through an investigation after the present invention had been made, that inventions described in JP-A-6-196435, JP-A-10-055939, JP-A-11-214274, JP-A-7-335509, and JP-A-7-050233 existed as related to the present invention, later described. Either of the inventions described in the official documents is recognized to require an extra manufacturing step for writing unique identification information into each chip. However, these official documents are not recognized to include any description related to a method for identifying a semiconductor integrated circuit device which does not particularly require an additional or a modified manufacturing step as the present invention, later described.

It is therefore an object of the present invention to provide a semiconductor integrated circuit device or a semiconductor chip which can be individually identified in a simple configuration, and a method for identifying a semiconductor integrated circuit device or a semiconductor chip. It is another object of the present invention to provide a semiconductor integrated circuit device which is capable of identifying individual semiconductor integrated circuit devices or semiconductor chips with a high reliability. It is a further object of the present invention to provide a rational method for manufacturing a semiconductor integrated circuit device. The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

DISCLOSURE OF THE INVENTION

Representatives of the inventions disclosed in this application are briefly described in summary as follows. Specifically, in course of a manufacturing process of semiconductor integrated circuit devices, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as the basis for identification information unique to the semiconductor integrated circuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a basic circuit diagram illustrating one embodiment of an identification number generator circuit according to the present invention;

FIG. 2 is a basic circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 3 is a basic circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 4 is a diagram for describing the operation of the identification number generator circuit of FIG. 3;

FIG. 5 is a basic circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 6 is an equivalent circuit diagram for describing the circuit in the embodiment of FIG. 5;

FIG. 7 is a circuit diagram illustrating a specific embodiment corresponding to the embodiment of FIG. 5;

FIG. 8 is a timing chart for describing the operation of the circuit in the embodiment of FIG. 7;

FIG. 9 is a diagram for describing the operation of the circuit in the embodiment of FIG. 7;

FIG. 10 is an exemplary modification illustrating one embodiment of a unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention;

FIG. 11 is an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention;

FIG. 12 is an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention;

FIG. 13 is an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention;

FIG. 14 is an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention;

FIG. 15 is an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention;

FIG. 16 is a circuit diagram illustrating one embodiment of a CMOS inverter circuit used in the identification number generator circuit according to the present invention;

FIG. 17 is a circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 18 is a waveform chart for describing the operation of the circuit in the embodiment illustrated in FIG. 17;

FIG. 19 is a block diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 20 is a block diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 21 is a general block diagram illustrating one embodiment of a semiconductor integrated circuit device according to the present invention;

FIG. 22 is an element layout diagram illustrating one embodiment of the semiconductor integrated circuit device according to the present invention;

FIG. 23 is an equivalent circuit diagram corresponding to the foregoing FIG. 22;

FIG. 24 is a block diagram illustrating one embodiment in which the present invention is applied to dynamic RAM;

FIG. 25 is a general schematic diagram illustrating one embodiment of a semiconductor integrated circuit device which employs the identification number generator circuit according to the present invention;

FIG. 26 is an explanatory diagram for explaining an algorithm for identifying an identification number according to the present invention;

FIG. 27 is an explanatory diagram for explaining an algorithm for identifying an identification number according to the present invention;

FIG. 28 is a schematic diagram illustrating one embodiment of a method of registering a matching algorithm in a system for identifying a semiconductor integrated circuit device according to the present invention;

FIG. 29 is a schematic diagram illustrating one embodiment of the method of registering a matching algorithm in the system for identifying a semiconductor integrated circuit device according to the present invention;

FIG. 30 is an explanatory diagram showing an exemplary comparison method in the foregoing FIG. 29;

FIG. 31 is an explanatory diagram showing a comparison method when using the order of logical threshold values in a CMOS inverter circuit;

FIG. 32 is an explanatory diagram showing a comparison method when using the order of logical threshold values in the CMOS inverter circuit;

FIG. 33 is a schematic diagram illustrating one embodiment of a semiconductor integrated circuit device to which the present invention is applied;

FIG. 34 is a block diagram illustrating one embodiment of a multi-chip module to which the present invention is applied;

FIG. 35 is a block diagram illustrating one embodiment of a dedicated program chip in the foregoing FIG. 34;

FIG. 36 is a schematic diagram for describing a manufacturing step of one embodiment of a semiconductor integrated circuit device which is mounted with the identification number generator circuit according to this application;

FIG. 37 is a schematic diagram for describing a manufacturing step of one embodiment when a semiconductor integrated circuit device mounted with the identification number generator circuit according to this application is assembled into a circuit mounting board;

FIG. 38 is a schematic diagram for describing a manufacturing step of another embodiment of the semiconductor integrated circuit device which mounted with the identification number generator circuit according to this application;

FIG. 39 is a block diagram illustrating an exemplary application specific LSI which is provided with the identification number generator circuit according to the present invention;

FIG. 40 is a circuit diagram illustrating an embodiment in which variations in logical threshold value of the CMOS inverter according to the present invention is applied to a random number generator;

FIG. 41 is a schematic diagram for describing an exemplary use of a chip identification number generator circuit for purposes of reducing fraudulent actions and a variety of troubles in an inter-enterprise electronic part procurement market;

FIG. 42 is a basic circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 43 is a basic circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 44 is a basic circuit diagram illustrating another embodiment of the identification number generator circuit according to the present invention;

FIG. 45 is a specific circuit diagram illustrating one embodiment of the identification number generator circuit according to the present invention;

FIG. 46 is a specific circuit diagram illustrating a further embodiment of the identification number generator circuit according to the present invention;

FIG. 47 is a timing diagram for describing the operation of the circuit in the embodiment of FIG. 46;

FIG. 48 is a circuit diagram illustrating another embodiment of the unit circuit used in the embodiment of the foregoing FIG. 46;

FIG. 49 is a circuit diagram illustrating a further embodiment of the identification number generator circuit according to the present invention;

FIG. 50 is a circuit diagram illustrating a further embodiment of the identification number generator circuit according to the present invention;

FIG. 51 is a circuit layout diagram illustrating one embodiment of a semiconductor integrated circuit device or a semiconductor chip to which the present invention is applied;

FIG. 52 is a block diagram illustrating a standard embodiment of the I/O cell;

FIG. 53 is a circuit layout diagram illustrating one embodiment of an I/O cell provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention;

FIG. 54 is a circuit diagram illustrating one embodiment of an output buffer circuit which is provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention;

FIG. 55 is a circuit diagram illustrating another embodiment of an output buffer circuit which is provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention;

FIG. 56 is a general schematic diagram illustrating one embodiment of a semiconductor integrated circuit device according to the present invention;

FIG. 57 is a block diagram illustrating one embodiment of a basic JTAG cell for the semiconductor integrated circuit device according to the present invention;

FIG. 58 is a schematic diagram for describing one embodiment of an operation of serially outputting an identification number, making use of a shifting operation of a boundary scan register of the semiconductor integrated circuit device according to the present invention;

FIG. 59 is a schematic diagram for describing another embodiment of the operation of serially outputting an identification number, making use of the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention;

FIG. 60 is a schematic diagram for describing another embodiment of the operation of serially outputting an identification number, making use of a shifting operation of a boundary scan register of the semiconductor integrated circuit device according to the present invention;

FIG. 61 is a schematic diagram for describing another embodiment of the operation of serially outputting an identification number, making use of the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention;

FIG. 62 is a circuit diagram illustrating a further embodiment of the identification number generator circuit according to the present invention;

FIG. 63 is an explanatory diagram of an identification number according to the present invention;

FIG. 64 is an explanatory diagram of the identification number according to the present invention;

FIG. 65 is a flow chart for describing one embodiment of a fast identification number matching (searching) algorithm for an identification number generated by the identification number generator circuit according to the present invention;

FIG. 66 is a schematic diagram corresponding to the embodiment of FIG. 65;

FIG. 67 is a flow chart illustrating one embodiment of a method for designing circuits for a semiconductor chip which incorporates the identification number generator circuit according to the present invention;

FIG. 68 is a flow chart illustrating one embodiment of a method for designing an LSI which has the built-in identification number generator circuit according to the present invention;

FIG. 69 illustrates a flow chart of one embodiment of a method for manufacturing a semiconductor integrated circuit device which uses a semiconductor chip with a built-in identification number generator circuit according to the present invention;

FIG. 70 is a flow chart illustrating one embodiment of a process of assembling a semiconductor integrated circuit device which uses a semiconductor chip mounted with the identification number generator circuit according to the present invention;

FIG. 71 is a schematic diagram illustrating one embodiment of a method of reducing the number of bits of the identification number generator circuit according to the present invention;

FIG. 72 is a schematic diagram illustrating one embodiment of a method of reducing the number of bits of the identification number generator circuit according to the present invention;

FIG. 73 is a schematic diagram for describing a testing method which utilizes the identification number generator circuit mounted in the semiconductor integrated circuit device according to the present invention;

FIG. 74 is a schematic diagram for describing the testing method which utilizes the identification number generator circuit mounted in the semiconductor integrated circuit device according to the present invention;

FIG. 75 is a schematic diagram for describing a method for managing correlation of characteristic data for each semiconductor chip in each test step, making use of the identification number generator circuit mounted in the semiconductor integrated circuit device according to the present invention;

FIG. 76 is a schematic diagram for describing a method for automatically managing wafers in a preprocess, making use of the identification number generator circuit mounted in the semiconductor integrated circuit device according to the present invention;

FIG. 77 is a schematic diagram for describing a method of storing and searching an identification number of the identification number generator circuit mounted in the semiconductor integrated circuit device according to the present invention;

FIG. 78 is a schematic diagram for describing another example of the method of storing and searching an identification number of the identification number generator circuit mounted in the semiconductor integrated circuit device according to the present invention;

FIG. 79 is a schematic diagram illustrating one embodiment of a method for recovering a semiconductor integrated circuit device, making use of the identification number generator circuit according to the present invention;

FIG. 80 is a layout diagram illustrating one embodiment of a semiconductor integrated circuit device which is mounted with the identification number generator circuit according to the present invention;

FIG. 81 is a partially enlarged layout diagram of the layout diagram in FIG. 80;

FIG. 82 is a layout diagram illustrating another embodiment of the semiconductor integrated circuit device which is mounted with the identification number generator circuit according to the present invention;

FIG. 83 is a circuit diagram corresponding to the layout in FIG. 81;

FIG. 84 is a schematic diagram illustrating a further embodiment of the semiconductor integrated circuit device which comprises the identification number generator circuit according to the present invention;

FIG. 85 is a partially plan pattern diagram of a semiconductor integrated circuit device which forms part of the embodiment in FIG. 84;

FIG. 86 is another partially plan pattern diagram of the semiconductor integrated circuit device which forms part of the embodiment in FIG. 84; and

FIG. 87 is a circuit diagram illustrating one embodiment of the semiconductor integrated circuit device which comprises the identification number generator circuit according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

For discussing the present invention in greater detail, the invention will be described with reference to the accompanying drawings.

FIG. 1 illustrates a basic circuit diagram of one embodiment of an identification number generator circuit according to the present invention. CMOS inverter circuits INV1 to INV4 are configured to have the same characteristics as one another within an actually controllable range on the design and manufacturing of a semiconductor integrated circuit device. A specific configuration suitable for the present invention in order to provide a plurality of inverters with the same characteristics as one another will be better understood with reference to later FIG. 22 and description thereon. Therefore, a technique for providing the same characteristics as one another will be generally described below.

In a CMOS inverter circuit, it is understood that its characteristics are generally determined by the relative conductance of a P-channel MOSFET and an N-channel MOSFET which comprise the CMOS inverter circuit. In this respect, it can be understood that CMOS inverters having the same characteristics can be implemented by MOSFETs which have the same ratio W/L of a channel width W to a channel length L but have different sizes. However, the influence on the electric characteristics due to variations in semiconductor integrated circuit devices during the manufacturing is different for elements of different sizes.

In the embodiment, preferably, the plurality of CMOS inverters INV1 to INV4 are each implemented by elements, forming parts of the respective CMOS inverter, which have the same structure and the same size as one another. It goes without saying that these elements are manufactured in accordance with the characteristics of semiconductor integrated circuit devices which are manufactured in batches under the same process. In this way, the plurality of CMOS inverters INV1 to INV4 uniformly suffer from the influence due to manufacturing variations such as variations in machining dimensions during the manufacturing of semiconductor integrated circuit devices, variations in thicknesses of various layers, variations in impurity concentrations, and the like.

In the CMOS inverter circuit which has short-circuited input and output as illustrated in FIG. 1, an output voltage reaches a logical threshold value voltage. When all the CMOS inverter circuits have completely the same electric characteristics, the four inverter circuits INV1 to INV4 have an equal potential at a short-circuited node. However, this is an ideal condition, and in an actual semiconductor device, slight differences in the characteristics result in a difference in the potential at the input/output short-circuited nodes of the respective inverter circuits INV1 to INV4, i.e., the logical threshold value voltage.

It may be understood that the variations in the logical threshold value in the CMOS inverter circuits are dominated by variations in the MOS transistor characteristics. Also, the cause for the variations in the MOS transistor characteristics can be the gate width of the MOS transistor, the film thickness of a gate insulating film, a conduction determinant impurity concentration, its distribution, and the like. These variations can be classified into a macroscopic aspect and a microscopic aspect. The macroscopic aspect includes variations in the gate width among a plurality of wafers in the same lot.

The invention of this application mainly utilizes the variations in the microscopic aspect, and uses variations among elements which are disposed in relatively close proximity to one another. This is because such microscopic variations are observed as randomly generated in elements arranged in relatively close proximity to one another.

Specifically, variations in the logical threshold value in the inverter circuits INV1 to INV4 in FIG. 1 can also be thought to be random. The variations in the logical threshold value constitute the basis of a solution which involves "extracting variations in a characteristic feature possessed by a semiconductor element as unique identification information," which is a problem to be solved by this application. When CMOS inverter circuits are used, variations occurring in the logical threshold value can be regarded as the sum of variations possessed by an N-channel MOS transistor and variations possessed by a P-channel MOS transistor, wherein a wide variation range permits an identification number or identification information to be generated in an effective manner.

In the embodiment illustrated in FIG. 1, the order of magnitude is determined for the logical threshold values of the four inverter circuits INV1 to INV4. Specifically, voltages at the short-circuited input/output nodes in the respective CMOS inverter circuits INV1 to INV4 (corresponding to the logical threshold value) are selected by a switch and sequentially inputted to an analog/digital converter ADC. A quantized measurement (digital signal) is stored in a register for comparing the magnitude by a digital comparator or the like, not shown.

In other words, the digitized logical threshold values of the four CMOS inverter circuits INV1 to INV4, stored in the register, are compared by a comparator or the like with respect to the magnitude, and are arranged in a descending order or an ascending order. When a semiconductor integrated circuit device formed with the identification number generator circuit is mounted with a processor such as CPU, this may be used for the comparison of magnitude in software.

For example, digital values are stored corresponding to numbers 1 to 4 assigned to the CMOS inverter circuits INV1 to INV4, and the order is determined through the comparison of magnitude, for example, such as 1-3-2-4. Identification information is then generated based on the order of 1-3-2-4.

FIG. 2 illustrates a basic circuit diagram of another embodiment of the identification number generator circuit according to the present invention. In this embodiment, an analog comparator COMP is employed. In this embodiment, a voltage corresponding to the logical threshold value of each of the CMOS inverter circuits INV1 to INV4 is sequentially supplied by the switch for comparison with a reference potential of the comparator COMP. This reference voltage is changed in steps, and a detected level is stored in a register when a comparison result of the comparator changes from a low level to a high level, followed by comparing the magnitudes of the logical threshold values of the CMOS inverter circuits INV1 to INV4. Specifically, the logical threshold value is regarded as being smallest when the output signal of the comparator changes from the low level to the high level with the lowest reference voltage.

The identification number geneator circuits illustrated in FIGS. 1 and 2 require circuits such as the high resolution analog/digital converter ACD, comparator COMP, step voltage generator, and the like, i.e., those circuits which do not appear in digital circuits or logical circuits.

FIG. 3 illustrates a basic circuit diagram of another embodiment of the identification number generator circuit according to the present invention. This embodiment takes into account to readily implement a form which may utilize a type of cell that substantially comprises a digital circuit or a logical circuit. In this embodiment, logical threshold values of the four CMOS inverter circuits INV1 to INV4 are combined two by two for comparison by the comparator COMP. The logical threshold values of these CMOS inverter circuits INV1 to INV4 are compared in round robin (league tournament).

FIG. 4 is a diagram for describing the operation of the identification number generator circuit in FIG. 3, showing an exemplary result of the round robin comparison. FIGS. 4(A) and (B) are, so to speak, match tables indicating to make on-state every one of switches Y1 to Y2 and switches X1 to X4, wherein a symbol "+" is written into the figure when a positive (high level) result is presented by subtracting the potential at a short-circuited node of a CMOS inverter circuit selected by a switch (X) connected to a non-inverting input terminal (-) of the comparator COMP from the potential at a short-circuited node of the CMOS inverter circuit (i.e., the logical threshold value voltage) selected by a switch (Y) connected to a non-inverting input terminal (+) of the comparator COMP, while a symbol "-" is written when a negative (low level) result is presented. "*" indicates a self match (no match) and therefore is invalid.

Referring to FIG. 4(A), Y1 has three "+" i.e., a clean score. Then, Y2 has two "+"; Y3 has one; and Y4 has zero (complete defeat). Specifically, since the logical threshold values (VLT) of the CMOS inverter circuits can be determined in magnitude with the number of "+," they are in the order of VLT1 (logical threshold value of INV1)-VLT2-VLT3-VLT4.

FIG. 4(B) shows another example. It is assumed herein that apparent differences exist among the logical threshold values of the respective CMOS inverter circuits. Specifically, actual games and the like involve draw matches and competitors having the same number of wins. A draw match is represented by (=). When there is such a draw match (=), Y1 and Y2 are at the same rank, while Y3 and Y4 are also at the same rank, failing to establish the order as mentioned above. Also, while the comparison (game) is made 16 times in this embodiment, the minimum number of games with n teams in round robin is n(n-1)/2 with suffice, so that six times may be actually sufficient.

The embodiment of FIG. 3 is composed of one comparator and two selector circuits in a relatively simple configuration as compared with the embodiments of FIGS. 1 and 2. However, since the identification number generator circuit employs the comparator COMP which is an analog circuit, it may encounter difficulties in the formation in a semiconductor integrated circuit device such as a gate array and logic ASIC.

FIG. 5 illustrates a basic circuit diagram of another embodiment of the identification number generator circuit according to the present invention. This embodiment does not employ any analog circuit as in the embodiments of FIGS. 1 to 3, but represents a basic circuit composed only of a CMOS logic circuit and a MOSFET switch.

All the CMOS inverter circuits INV1 to INV4 in FIG. 5 have the same size. Each of the CMOS inverter circuits INV1 to INV3 is provided with four switches. Switches A (A1 to A4) and B (B1 to B4) are simultaneously opened and closed in association with each other. Likewise, switches C (C1 to C4) and D (D1 to D4) are also opened and closed in association with each other.

FIG. 6 illustrates an equivalent circuit corresponding to open/close states of the switches for describing the circuit in the embodiment of FIG. 5. In FIG. 5, switches A1, B1, C2, D2 are closed (on-state). The switch B1 short-circuits the input/output of the CMOS inverter circuit INV1, and the voltage at the short-circuited node is supplied to a common node P through the switch A1. A potential at the common node P is applied to the input of the CMOS inverter circuit INV2 through the switch C2, and the output of the CMOS inverter circuit INV2 is supplied to a common node PP through the switch D2. Amplifier circuits AMP1 and AMP2 are configured of CMOS inverter circuits which are congruent in shape with INV1 to INV4.

In the equivalent circuit of FIG. 6, the input and output of the CMOS inverter circuit INV1 are short-circuited by the switch B1 which is turned on, and the potential at the common node P is equal to the logical threshold value of the CMOS inverter circuit INV1 by the action of the switch A1 which is turned on. The input to the CMOS inverter circuit INV2 is connected to the common node P through the switch C2 which is turned on. If the CMOS inverter circuits INV1 and INV2 have completely the same electrical characteristics, the potential at the common node PP connected to the output of the CMOS inverter circuit INV2 is qual to that at the common node P. Similarly, the amplifier circuits AMP1 and AMP2 also have the same potential at output nodes. In other words, the input/outputs of the four inverters are all equal to the logical threshold value voltage of the CMOS inverter circuit INV1. However, this is an ideal condition, and in an actual semiconductor device, slight differences in the characteristics result in different potentials at the respective nodes.

For example, when the logical threshold value VLT1 of the CMOS inverter circuit INV1 and the logical threshold value VLT2 of the CMOS inverter circuit INV2 are in a relationship represented by VLT1<VLT2, the potential at the common node PP is higher than the potential at the common node P. Conversely, when VLT1>VLT2, the potential at the common node PP is lower than the potential at the common node P.

The CMOS inverter circuit, which is a high gain inverting amplifier, has a gain which varies depending on the operation point. A maximum gain is provided when an input potential is near the logical threshold value of the CMOS inverter circuit. Generally, the CMOS inverter circuit has an inverting gain in a range of several tens to one hundred times near the logical threshold value thereof.

Therefore, the difference between the logical threshold values of the CMOS inverter circuits INV1 and INV2 in FIG. 6 is amplified by the CMOS inverter circuit INV2 at the later stage. Specifically, the logical threshold value voltage generated by the former CMOS inverter circuit is compared in magnitude with the logical threshold value voltage of the later CMOS inverter circuit itself, as a reference voltage, and amplified.

The amplification is also made by the amplifier circuits AMP2, AMP3, so that the difference between the logical threshold values of the CMOS inverter circuits INV1 and INV2 is amplified by a factor of several tens of thousands of times by the CMOS inverter INV2 and amplifier circuits AMP1, AMP2. Finally, a CMOS supply voltage amplitude signal can be generated at a node Q. Specifically, the result of a comparison of magnitude between the logical threshold values of the two CMOS inverter circuits INV1 and INV2 (a positive or negative sign) can be detected by the CMOS amplitude signal.

By changing a combination of opened and closed switches as in FIG. 6, all the CMOS inverter circuits INV1 to INV4 can be readily compared to provide the result as shown in FIG. 4(A). In this way, the circuit in this embodiment is suitable for a comparison of logical threshold values of CMOS inverter circuits.

Specifically, with a combination of CMOS inverter circuits and switches, a single CMOS inverter circuit can be used as a source of the logical threshold value voltage, or can be used as a determination circuit for determining a logical threshold value voltage generated by another CMOS inverter circuit, so that an extra comparator is not required, making it possible to significantly simplify the circuit configuration. Moreover, since the entirety, including the CMOS inverter circuits, is built by MOSFETs which perform switching operations, no particular difficulties will be experienced when mounted in a semiconductor integrated circuit device such as a gate array and a logic ASIC.

FIG. 7 illustrates a circuit diagram of a specific embodiment corresponding to the embodiment of FIG. 5. The CMOS inverter circuits INV1 to INV4 and amplifier circuits AMP1, AMP2 are CMOS inverter circuits in congruent shape. In this embodiment, N-channel MOSFETs are used as the aforementioned switches. Then, a binary counter and a decoder are provided for forming control signals Y1 to Y4 and X1 to X4 for these switches.

The CMOS inverter circuit INV1 is taken as an example in the following description. The control signal X1 is supplied to the gate of a switch MOSFET which short-circuits the input and output of the CMOS inverter circuit INV1, and a switch MOSFET which connects the common node P to the input. The control signal Y1 is supplied to the gate of a switch MOSFET which connects the input of the CMOS inverter circuit INV1 to the common node P and a switch MOSFET which connects the output to the common node PP. Likewise, in the respective CMOS inverter circuits INV2 to INV4, the control signals X2 to X4 and control signals Y2 to Y4 are connected to the gates of the corresponding switch MOSFETs, respectively.

The binary counter is a binary counter having a total of four bits, which is reset by a reset signal RES and counts the number of pulses in a clock signal CLK supplied thereto. The decoder forms the control signals Y1 to Y4 corresponds to the lower two bits of a count output, and forms the control signals X1 to X4 corresponding to the higher two bits of the count output.

FIG. 8 shows a timing chart for describing the operation of the circuit in the embodiment of FIG. 7. The reset signal RES is for initializing the binary counter. Here, the output of the binary counter is all "1" during a reset (RES="H") and immediately after the reset. Therefore, X4 and Y4 are active in the output of the decoder. The binary counter advances (+1) at the time the clock CLK first rises after the reset is released, so that the output changes to all "0." Therefore, the control signals X1 and Y1 are active in the output of the decoder.

Subsequently, the output of the binary counter repeatedly advances (+1) at the timing at which the clock signal CLK rises, causing the decoder to advance as shown in FIG. 8. Of course, it goes without saying that the output of the binary counter again returns to all "0" when the clock signal CLK rises 17 times. However, since necessary information can be retrieved up to 16 operations in this embodiment, the clock operations are not needed at the 17th time onward.

After the reset is released, the binary counter advances its counting operation each time the clock signal CLK rises, and information b1 to b16 delivered at an output node OUT each time is as shown in FIG. 9. As described above, the difference between the logical threshold values of the CMOS inverter circuits is amplified by the amplifier circuits AMP1, AMP2, and "H" (high level) is outputted at the output terminal when VLTQy-VLTQx>0, and "L" (low level) is outputted at the output terminal OUT when VLTQy-VLTQx<0.

Thus, the results of matches in round robin among the four CMOS inverter circuits INV1 to INV4 can be utilized as they are as the identification signals b1 to b16. Among the results b1 to b16 in the round robin of the four CMOS inverter circuits INV1 to INV4, those of self matches may be previously set to a particular level, high level or low level, as later described. Numbers 1 to 4 assigned to the four CMOS inverter circuits are replaced with 2-bit information pieces which can be arranged in the descending order, for example, as 1-2-3-4, so that resulting identification information can be compressed to one half, as 2.times.4=8 bits.

FIG. 10 illustrates an exemplary modification of one embodiment of a unit circuit which comprises a CMOS inverter circuit and switch MOSFETs that are the core of the identification number generator circuit according to the present invention. In the circuit of FIG. 10, each of the four switch MOSFETs (A to D) in FIG. 5 is composed of a CMOS pair. Specifically, an N-channel MOSFET and a P-channel MOSFET are connected in parallel, and complimentary signals X and X/ are supplied to their gates, respectively.

When the CMOS switches are used in this manner, a voltage signal transmitted through the switch MOSFETs is not limited by the threshold value voltages, so that this is effective for a circuit which operates at a low voltage, wherein a voltage difference between a supply voltage or a ground potential of the circuit and the logical threshold value voltage, or a differential voltage between the supply voltage or the ground potential of the circuit and a voltage to be outputted to the common node PP is smaller than the threshold value voltage of the switch MOSFET.

FIG. 11 illustrates an exemplary modification of another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention. The circuit in FIG. 11 changes the position of the N-channel switch MOSFET which supplies the common node P with the input/output short-circuit potential of the CMOS inverter circuit. In other words, the output side of the CMOS inverter circuit, which is short-circuited between the input and output, is connected to the common node P.

FIG. 12 illustrates an exemplary modification of another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention. The circuit of FIG. 12 comprises two P-channel MOSFETs which are connected in series between the input of the CMOS inverter circuit and a supply voltage terminal. These P-channel MOSFETs are supplied with selection signals X, Y at the gates, respectively. In this embodiment, when the CMOS inverter circuit is not selected, i.e., when neither the selection signal X nor Y is activated, the P-channel MOSFET is turned on to clamp the input of the CMOS inverter circuit at a high level such as a supply voltage to prevent a through current in the CMOS inverter circuit. Specifically, when the input of the CMOS inverter circuit is floating, a resulting intermediate potential can cause a large through current to flow between the N-channel MOSFET and P-channel MOSFET of the CMOS inverter circuit. Thus, the P-channel MOSFETs are provided to prevent the through current.

FIG. 13 illustrates exemplary modification of another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention. In the circuit of FIG. 13, the switch MOSFETs are changed from the N-channel MOSFETs as in the foregoing embodiment to P-channel MOSFETs, and the input of the CMOS inverter circuit is clamped to a low level by an N-channel MOSFET when it is placed in an inactive state. In this event, selection signals applied to the gates of the N-channel MOSFETs are inverted signals X/ and Y/.

FIG. 14 illustrates an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention. The circuit of FIG. 14 comprises two N-channel MOSFETs connected in series between the input of the CMOS inverter circuit and the ground potential of the circuit for preventing the common node PP from being indefinite at the aforementioned self match (no match), i.e., the output from being instable whether it becomes "H" or "L," and the input of the CMOS inverter circuit is clamped to a low level.

These N-channel MOSFETs are supplied with selection signals X and Y at the gates, respectively. In this way, the selection signals X, Y are at high level during a self match, and the input is supplied with the ground potential of the circuit. A short-circuit switch provided between the input and output of the CMOS inverter circuit is comprised of a series circuit of an N-channel MOSFET which receives the selection signal X and a P-channel MOSFET which receives the selection signal Y. In this way, the input and output are not short-circuited during a self match, and a high level can be outputted corresponding to the clamped low level supplied to the input. Also, the input is clamped to a high level such as a supply voltage, as is the case with the embodiment of FIG. 12, upon non-selection.

FIG. 15 illustrates an exemplary modification illustrating another embodiment of the unit circuit which comprises a CMOS inverter circuit and switch MOSFETs which are the core of the identification number generator circuit according to the present invention. In the circuit of FIG. 15, the input of the CMOS inverter circuit is clamped to a high level for preventing the common node PP from being indefinite at the aforementioned self match (no match), i.e., the output from being instable whether it becomes "H" or "L," and the input of the CMOS inverter circuit is clamped to a low level. In a manner similar to the foregoing, for preventing short-circuit between the input and output during the self match, the short-circuit switch is comprised of a series circuit of an N-channel MOSFET and a P-channel MOSFET, as is the case with the embodiment of FIG. 14.

The object and effect of avoiding an indefinite level at the common node PP will be described later in detail. The respective exemplary modifications illustrated in FIGS. 10 to 15 may be implemented in combination. For example, the N-channel switch MOSFETs in FIG. 14 may be replaced with a CMOS pair.

In the embodiments of FIGS. 14 and 15, the self match (*) fields in FIG. 9 can be utilized to embed fixed information. Inherently, the self match field is indefinite, strictly speaking, this is the result of a comparison between the logical threshold values of each CMOS inverter circuit and amplifier circuit AMP, so that the identification ability will not be degraded even if information in this field is ignored or used for a different purpose. When the added N-channel MOSFETs in series connection are clamped to the ground potential or supply voltage as in FIGS. 14 and 15, the inputs of the CMOS inverter circuits INV1-INV4 can be biased to a low level or a high level side to arbitrarily set the output for the self match field.

In recent years, the semiconductor integrated circuit device technology is under progress for mounting bare chips on a substrate referred to as a build-up substrate, wherein either a product or a shipment date cannot be identified from the appearance, so that there is an increasingly high need for inserting a unique number for identifying the product or shipment date. Specifically, in System On Chip (SOC) as later described, individual product management becomes increasingly important, as to what is mounted on a base chip, which types of individual chips are combined, which chips should be combined, and the like. Therefore, the assignment of the unique number is advantageous.

FIG. 16 illustrates a circuit diagram illustrating one embodiment of a CMOS inverter circuit used in the identification number generator circuit according to the present invention. Generally, a CMOS inverter circuit comprises a P-channel MOSFET and an N-channel MOSFET arranged in series between a supply voltage and a ground potential of the circuit, their gates are connected in common for use as an input, and their drains are connected in common for use as an output. The CMOS inverter circuits INV1 to INV4 and amplifier circuits AMP1, AMP2 in the aforementioned embodiments can be each comprised of two MOSFETs as described above.

In contrast, in this embodiment, a CMOS inverter circuit is comprised of two P-channel MOSFETs and two N-channel MOSFETs. The two N-channel MOSFETs are connected in parallel between an output terminal and a ground potential point of the circuit, while the two P-channel MOSFETs are connected in series between the supply voltage and output terminal.

In this configuration, the N-channel MOSFETs have large conductance, whereas P-channel MOSFETs have small conductance. Specifically, a current flowing into the N-channel MOSFETs is set by the small conductance (large on-resistance) of the P-channel MOSFETs. Apparently, since a constant voltage can flow into the N-channel MOSFETs, the threshold value voltages of the two N-channel MOSFETs predominantly act on the logical threshold voltage of the CMOS inverter. In this way, the logical threshold value of the CMOS inverter circuit is less prone to the influence of fluctuations in the supply voltage.

With the P-channel MOSFETs operated as simple high resistance elements and the N-channel MOSFETS having the threshold value voltages predominantly acting on the logical threshold value, the resulting configuration is advantageously less prone to the influence of deteriorated element characteristics (NBTI), later described.

As will be later described, when an identification number generator circuit is comprised of a gate array, N-channel MOSFETs and P-channel MOSFETs have fixed element sizes, so that a plurality of MOSFETs may be combined as mentioned above to equivalently provide a different ratio of the element size of an N-channel MOSFET to the element size of a P-channel MOSFET to set a logical threshold value corresponding thereto.

FIG. 17 illustrates a circuit diagram of another embodiment of the identification number generator circuit according to the present invention. This embodiment illustrates a circuit for fixing a portion of an identification number to an arbitrary number in addition to the function so far described for generating a random identification number. In the embodiment illustrated in FIG. 7, 24 different identification numbers can be generated. The number of information bits are 16 bits including the self match result. Briefly describing the circuit in this embodiment, the output node (common node) P of the CMOS inverter circuit shown at the first stage in the aforementioned FIG. 6 is forcedly fixed to an arbitrary value. In this event, the first stage and second stage cannot be changed in the order.

In the circuit of this embodiment, from the circuit in the embodiment of FIG. 7, an output node corresponding to the CMOS inverter circuit INV1 is clamped to "H" (=VDD) by MOSFET Q11, and an output node corresponding to the CMOS inverter circuit INV2 is clamped to "L" (=VSS) by MOSFET Q21. Since the MOSFETs Q11 and Q12 for forming the thus clamped levels "H" and "L" are not inputs to the common node P, decode signals Y1 and Y2 are not needed. For this reason, the binary counter circuit is provided in a three-bit configuration, and the decoder circuit forms output signals as Y3, Y4.

FIG. 18 illustrates a waveform chart for describing the operation of the circuit in the embodiment illustrated in FIG. 17. There are four options at the first stage and two options at the second stage, so that a total of eight different outputs can be provided. In other words, the number of information bits are eight bits. In this embodiment, output signals b1 to b4 present "0," "0," "1," "1" at all times. The remaining b5 to 58 represent the result due to variations in logical threshold values of CMOS inverter circuits Q3 and Q4. This embodiment can generate only two different fixed numbers and two different random identification numbers at maximum.

In actual use, the fixed section and random section can be a combination of arbitrary sizes. A possible application may be such that the fixed section indicates a product code, and the random section indicates a sample number. A fixed identification number may be inserted into an information bit sequence in several other methods. For example, there are the method of replacing the self match field, the method of replacing one of repeated matches (comparison of changed first and second stages), as described in connection with FIGS. 14, 15. For actually implementing these circuits, a problem arises in that which part of a registration and matching system is burdened with the function, not only the circuit for generating identification numbers. However, in the overall system, the registration and matching functions are likely to be mainly implemented by computer software, so that advanced functions can be relatively readily implemented.

FIG. 19 illustrates a block diagram illustrating another embodiment of the identification number generator circuit according to the present invention. A logical threshold value determination unit, substantially represented by blocks in FIG. 19, is operated by a voltage V2, which is relatively low and stabilized, outputted from a power supply circuit shown in FIG. 19 and next described.

Specifically, a P-channel MOSFET applied with a ground potential of the circuit at its gate at all time operates as a loading means to supply an operating current to four N-channel MOSFETs serially connected in diode configuration which act as voltage regulator elements. In this way, a constant voltage V1 is formed corresponding to a constant voltage (threshold value voltage) between the gate and source of the N-channel MOSFETs in series connection, and is supplied as an operating current V2
for the logical threshold value determination unit through the gate and source of the N-channel MOSFET. The voltage supplied to such a logical threshold value voltage determination unit is made constant. As a result, the logical threshold values of the CMOS inverter circuits INV1 to INV4 and the like are less affected by fluctuations in the supply voltage VDD. In this way, a more stable operation can be expected for determining the logical threshold value.

In the invention of this application, it is not essential to provide a constant operating voltage to the logical threshold value determination unit as described above. Specifically, the invention of this application does not employ the absolute values of the logical threshold value voltages of a plurality of CMOS inverter circuits, but sets an identification number corresponding to a difference between the logical threshold value voltages of the individual CMOS circuits. Since the fluctuations in the supply voltage similarly affects the logical threshold value voltages of the respective CMOS inverter circuits, the relation of magnitude will not be significantly changed.

FIG. 19(B) illustrates a specific circuit for preventing aging changes of MOSFET. The threshold value voltage of a MOS transistor may undesirably fluctuate due to an electric field stress which depends on an electric field strength and temperature. Particularly, a phenomenon referred to as NBTI (Negative Bias Temperature Instability) remarkably appears in P-channel MOSFET. Often used as countermeasures to this is a method of applying a high voltage to the gate of the PMOS out of an intended time. In this embodiment, the ground potential VSS of the circuit of the logical threshold value determination unit is supplied from the N-channel MOSFET, and the N-channel MOSFET is turned on by a power supply control signal PON at high level in a logical threshold value determining operation to supply the ground potential VSS of the circuit. Then, except for the logical threshold value determining operation, the power supply control signal PON is brought to low level to turn off the N-channel MOSFET and to turn on the P-channel MOSFET to supply the supply voltage VDD to the ground potential side of the circuit as well. Then, the P-channel MOSFET is applied with a fixed gate voltage at the gate to supply the supply voltage VDD. In this way, the P-channel MOSFET is equi-potential, equal to the supply voltage VDD, at all of the gate, drain, source and substrate (channel), thereby minimizing fluctuations in the logical threshold value due to aging changes of the MOSFETs.

FIG. 20 illustrates a circuit diagram of another embodiment of the identification number generator circuit according to the present invention. In the circuit of this embodiment, a series circuit of P-channel MOSFET is provided at the input of each CMOS inverter circuit INV1 to INV4 to minimize fluctuations in the logical threshold value due to aging changes of the MOSFETs. At a reset, at which a signal RES/ is set to low level, the inputs of the CMOS inverter circuits INV1 to INV4 are clamped to the supply voltage.

Specifically, with the signal RES/ at low level (logical zero), output signals of AND gate circuits, which receive count outputs B0 to B3 of a binary counter circuit, are all set to high level (logical one). As a result, all of output signals Y1
to Y4 and X1 to X4 of NOR gate circuits, which form parts of a decoder circuit, transition to low level (logical zero), causing the P-channel MOSFETs in series connection arranged between the inputs of the respective CMOS inverter circuits INV1 to INV4
and the supply voltage VDD to turn on, thereby clamping them to the supply voltage. In this way, the supply voltage VDD is supplied to the gates of the P-channel MOSFETs which form parts of the respective CMOS inverter circuits INV1 to INV4.

Further, in this embodiment, the P-channel MOSFET, which is turned on by the signal RES/ at low level, clamps the inputs of the amplifier circuits AMP1 and AMP2 to the supply voltage VDD, to supply the voltage voltage to the gates of P-channel MOSFETs which form parts of the amplifier circuits.

Alternatively, the selection signals Y1 to Y4 may be all turned on to clamp the common input node P to the supply voltage. In any case, an action may be taken to control the gate voltages of the P-channel MOSFETs which form parts of the CMOS inverter circuits INV1 to INV4 and amplifier circuits AMP1, AMP2 in this manner, or to fully shut off the power supply to the identification number generator circuit. However, in the method of fully shutting off the power supply, it is necessary to take into consideration the electric separation of the element regions, in which the MOSFETs that form parts of the identification number generator circuit are formed, from other circuits. Specifically, this is because, even if the power supply is shut off, a constant voltage always applied to the substrate gate (channel) of MOSFET is not desirable from view point of the degradation in the element characteristics.

On the other hand, when attention is paid to such NBTI, a problem arises in a normal reliability guarantee. Specifically, the provision of a means for circumventing a stress as mentioned above disables screening of process defects which is performed in a so-called burn-in step. While there is no concern if the scale of the circuit is extremely smaller than the entire LSI, it should be advisable to bear in mind those applications which need the screening. In this event, a mode is provided for arbitrarily releasing a reset or a power-off in the burn-in step or the like.

Of course, it is well contemplated that the stress causes an identification number to fluctuate. However, a final identification number can be retrieved after the burn-in step for re-registration in a database, and even large fluctuations in the identification number exert small influence because lots treated in the burn-in step are limited in size in a range of several hundreds to several thousands.

FIG. 21 illustrates a general block diagram of one embodiment of a semiconductor integrated circuit device according to the present invention. This embodiment is directed to a power control for a system LSI which is mounted with the identification number generator circuit of this application. This system LSI employs two different types of power supplies VDD1 and VDD2 by way of example.

The identification number generator circuit receives the power supply from VDD1 in operation. Here, "in operation" refers to a time period for which an identification number is sent out in response to an identification number read request from the LSI circuit main unit 1. In other states, the power supply is shut off. A signal for controlling the power supply is a power supply control signal which is applied to a power supply control circuit. The power supply control circuit is composed of an N-channel MOSFET and a P-channel MOSFET which receive the power supply control signal at the gate. When the power supply control signal is at high level, the power supply of the identification number generator circuit is clamped to VSS, and an identification number output signal is clamped at low level. When the power supply control signal is at low level, the identification number generator circuit is supplied with VDD1. Circuits included in the illustrated identification number generator circuit are, for example, the logical threshold value determination circuit for CMOS inverter circuits, binary counter, and decoder, which are shown in FIG. 20, wherein the binary counter and decoder may be included in the LSI circuit main unit 1.

FIG. 22 illustrates an element layout diagram of elements in one embodiment which is suitable for the semiconductor integrated circuit device according to the present invention. Though the illustrated configuration is not particularly limited, the layout may be understood to be an example suitable for a so-called master-slice semiconductor integrated circuit device. For the ease of understanding, FIG. 22 only illustrates a plane pattern of active regions which comprise MOS transistors, and a wiring layer pattern such as metal wiring layers are omitted from the illustration. The essence of the technique will be well understood from the fact that even such a plane pattern predominantly affects the circuit characteristics which should be provided in the MOS transistors, but less affects the circuit characteristics which should be provided in wires such as metal wires.

The basic device structure itself of the semiconductor integrated circuit device is not directly related to the present invention, so that detailed description thereon is not made. However, this may be generally described as follows.

Specifically, a semiconductor device used herein is made of N-type single crystal silicon, and an N-type well region and a P-type well region are formed on the surface of the semiconductor substrate by a localized impurity introduction technique. An opening is formed for defining an active region in a so-called field insulating film which may be made of a silicon oxide film, disposed on the surface of the semiconductor substrate, and a gate insulating film is formed on the surface of the N-type well region and P-type well region, which are exposed through the opening, by a silicon thermal oxidization method or the like. A gate electrode layer, which may be made of a polycrystalline silicon layer, is selected on the gate insulating film and field insulating film. A P-type impurity is introduced using the gate electrode layer and field insulating film as substantial impurity introducing masks to form P-type semiconductor regions on the surface of the N-type well region for providing a source region and a drain region of a P-channel MOS transistor. Similarly, an N-type impurity is introduced using the gate electrode layer and field insulating film as substantial impurity introducing masks in a similar manner to form N-type semiconductor regions on the surface of the P-type well region for providing a source region and a drain region of an N-channel MOS transistor. This basic device structure is formed with desired wiring layers by known wiring layer forming technique and insulating layer forming technique.

In FIG. 22, a relatively small substantially square pattern defines an active region. One unit region is made up of the relatively small substantially square pattern and two elongated patterns in parallel with each other which are drawn to overlap the square pattern to mean gate electrode layers, respectively. For example, a unit region is made up of a relatively small square pattern positioned at an upper right end of the drawing and labeled with symbols PP, B, P, and two elongated patterns which are drawn to overlap the square pattern and labeled with symbols Y0/, X0/, respectively.

Thus, one active region is formed with two MOS transistors by two parallel gate electrode layers, and semiconductor regions for the source and drain formed on the surface of the active region in self alignment to the two gate electrodes.

In FIG. 22, a plurality of unit regions for N-channel MOS transistors, and a plurality of unit regions for P-channel MOS transistors are arranged in columns as illustrated. In the column comprised of four unit regions for P-channel MOS transistors, located at the highest position (hereinafter referred to as the "first region column"), the respective unit regions are configured to have the same plane dimensions and the same extension direction as one another. Likewise, the respective unit regions in the column comprised of four unit regions for N-channel MOS transistors located immediately below the first column are configured to have the same plane dimensions and the same extension direction as one another. The first region column and second region column are provided to create an inverter and a switch MOS transistor connected thereto as in FIG. 20.

Similarly, a third region column and a fourth region column are provided to create an X-decoder unit, while a fifth region column and a sixth region column are provided to create a Y-decoder unit.

The entirety of the first region column to sixth region column in FIG. 22, each of which is comprised of four unit regions, is designated as a basic repetition unit. Specifically, a plurality of basic repetition units in FIG. 22 are arranged side by side in the lateral direction in FIG. 22 in accordance with a circuit scale to be achieved. According to this configuration, the first region columns in different basic repetition units also constitute a single column (also referred to as the "global region column") in the entire layout. Similarly, the second columns and onward constitute global region columns, respectively.

The layout in FIG. 22 and the repeated layout as mentioned above provide an example suitable for forming identification information of the present invention.

Instead of the layout in FIG. 22, if a plurality of unit regions which should make up the same region column are disposed across element regions or the like which make up other circuits and therefore are spaced by a relatively large distance from one another, the following difficulties may arise. Specifically, a plurality of unit regions significantly suffer from the influence exerted by macroscopic fluctuations in pattern dimensions as based on fluctuations in manufacturing conditions of the semiconductor integrated circuit device, or macroscopic fluctuations such as distorted patterns, resulting in a relatively large difference in pattern shape.

Since a mechanical stress applied to a semiconductor chip by mounting the semiconductor chip can differ from one site to another of the semiconductor chip, a plurality of unit regions can be applied with mechanical stresses which relatively largely differ from one unit region to another. A rise in operating temperature caused by a power supply current flowing through the circuit is not uniform in the plurality of unit regions. The thickness of the gate insulating film and a subtle change in the concentration of introduced impurities can be relatively increased due to the plurality of unit regions which are relatively distanced from one another.

In the layout of FIG. 22, a plurality of unit regions belonging to the same region column are disposed in relatively close proximity, and have the same size and the same direction as one another, so that they are less susceptible to the influence exerted by relative pattern dimensions, distorted patterns, mechanical stress, operating temperature, film thickness, and impurity concentrations, as mentioned above.

A so-called phase shift mask technique is understood to be an effective technique for miniaturizing circuit components, wires and the like, which make up a semiconductor integrated circuit device, to a so-called sub-micron level. In such a phase shift mask technique, a pattern can suffer from asymmetry or distortions such as a difference in shape in the left and right halves of a pattern to be formed, due to even a slight change in phase difference of light for exposing a photosensitive material layer which is later used as a mask. The layout as in FIG. 22 can sufficiently reduce deviated electric characteristics of a plurality of unit regions even if such a type of distorted pattern is present.

The influence exerted by the crystal orientation dependance of the carrier mobility in the semiconductor, together with the difference in configuration in the foregoing point of view, cannot be treated lightly for the present invention which utilizes the microscopic characteristics as mentioned above. In the layout of FIG. 22, the MOS transistors belonging to the first region column and the MOS transistors belonging to the second region column are free from the difference in the characteristics due to the crystal orientation dependency because all of a plurality of gate electrode layers forming part of the first region column are made in the same orientation and in the same pattern as one another, and all of a plurality of gate electrode layers forming part of the second region column are also made in the same orientation and in the same pattern as one another.

It will be understood from the foregoing that the layout of FIG. 22 is made in consideration of a significant reduction in the macroscopic variations or deviations in characteristics as mentioned above from the viewpoint of designing and manufacturing of the semiconductor integrated circuit device and in consideration of appropriate utilization of the microscopic variations as mentioned above.

When a need exists for more fully eliminating the deviations in electric characteristics of the MOS transistors created in the layout of FIG. 22, a dummy region can be set for solving an end effect of the overall array comprised of a plurality of the basic repetition units of FIG. 22. The dummy region is provided to make the ends of the overall array comparable to the interior of the overall array on the layout, and is comprised of at least a plurality of unit regions at the ends in the basic repetition units.

When this type of dummy region is not set, a machined shape of such ends can be affected depending on the configuration outside the ends in the overall array, and such ends and the remaining portions can be applied in different manners with a force which can affect the element characteristics, such as a stress produced between the semiconductor substrate and the insulating film on the surface thereof. They can be factors of causing the deviations in the electric characteristics. When the dummy region as mentioned above is set, the factors of causing the deviations in the electric characteristics are fully eliminated.

The dummy region can be provided as a region which is not utilized as a circuit or as a region for making other circuit which does not require attention to the deviations in the electric characteristics.

FIG. 23 illustrates an equivalent circuit diagram corresponding to the foregoing FIG. 22. In FIGS. 22 and 23, the terminal names and element numbers are corresponding. However, details of the decoder unit are not illustrated because there are no particular restrictions except that it is disposed below (or above) the CMOS logical threshold value detector circuit. When the basic repetition units as in FIG. 22 are disposed in parallel, CMOS inverter circuits formed of elements can match the shape and surrounding environment with the same circuits adjacent thereto. In an layout scheme other than a gate array scheme, the basic repetition units may be laid out such that the CMOS inverter circuits are congruent. When the circuit is built using such gate arrays, the embodiment in FIG. 16 may be applied, in which case variations in the threshold value voltage of the N-channel MOSFET can be predominantly reflected to the logical threshold value, while reducing the influence of variations in the supply voltage.

FIG. 24 illustrates a block diagram of one embodiment when the present invention is applied to a dynamic RAM (random access memory, hereinafter simply referred to as the "DRAM"). In this embodiment, the binary counter and decoder are removed from the identification number generator circuit illustrated in FIG. 20 or the like. Instead of these counter and decoder, a row address signal and a column address signal of a DRAM, which is mounted with the same, are supplied with the signals X and Y, formed by the decoder, for direct use as a selection signal for the logical threshold value determination circuit of the CMOS inverter circuit. An identification number read mode is set for the DRAM, a start signal is generated by a circuit DFT, and address signals X and Y are supplied from the outside for the read, to output an identification number generated by the identification number generator circuit through an input/output circuit and a DQ pin, instead of a selection operation of the memory array. In this event, since the address signals X and Y can be input in an arbitrary order, fixed information in the self match fields alone can be specified for reading. Alternatively, the order in which the address signals X and Y are inputted may be entered as a code, such that a particular one can output a fixed signal corresponding to the self match or the identification number.

This configuration can be applied as well to semiconductor integrated circuit devices other than DRAM, such as other semiconductor memory devices such as another static RAM, flash EPROM and the like or a CPU (microprocessor) having address terminals, and the like.

FIG. 25 illustrates general schematic diagram of one embodiment of a semiconductor integrated circuit device which employs the identification number generator circuit according to the present invention. The essential purpose of assigning an identification number to a semiconductor integrated circuit device is to give a unique number to each LSI. While a numbering method may use a laser fuse, a flash (FLASH) memory or the like, a special process or program step and the like are required.

In this embodiment, an identification number generated by the identification number generator circuit of this application in a wafer state is read by a tester for registration in relation to a variety of data and the like in a workstation. After each LSI is finished into a product and mounted in an electronic device such as a personal computer PC and the like, the identification number is read from the LSI. The identification number read a this time is not ensured to completely match because even the same LSI differs in an operating environment and condition from the registration time. However, it can be estimated to be the same or not from the degree of discrepancy in identification number.

Description will be made on a determination algorithm for the identification system in this application. The identification number in this embodiment indicates the order of magnitude of the logical threshold values of a plurality of CMOS inverter circuits. A circuit having four CMOS inverter circuits as in the foregoing embodiment is counted as one unit. For example, there are 24 possible orders (the number of permutations) .sub.4 P.sub.4 =4!=4.times.3.times.2.times.1=24 for the logical threshold values of the four CMOS inverter circuits. Assuming now that there are two units, if the logical threshold values completely randomly vary, the two units of CMOS inverter circuits has the same order with a probability of approximately
4.2% (=1-23/24).

Otherwise, when one unit is comprised of eight CMOS inverter circuits, there are 8!=40,320 possible orders. When there are 50 such units, one set or more of those having the same order exist with a probability of approximately 3% (=1-(40320.times.40319.times. . . . .times.40271)/40320.sup.50).

In a unit comprised of 16 CMOS inverter circuits, possible combinations amount to 16!=2.09E13. As such, the permutations of 16 is an extraordinary number, meaning that when the logical threshold values of the CMOS inverter circuits randomly vary, there hardly exist those which are in the same arrangement. Actually, when there are 1,000,000 units, it is estimated that one set or more of units in the same order exist with a probability of at least 5% or less (at a rough estimate because a strict calculation is difficult due to a large number of digits). In other words, there is one set per 20,000,000 units when roughly speaking. It is contemplated from such calculations that approximately 16 CMOS inverter circuits are required in one unit for completing a practical identification number. Therefore, the following description will be made on a unit comprised of 16 CMOS inverters, given as an example.

When 16 CMOS inverter circuits in one unit are implemented as in FIG. 7, round-robin comparison results amount to 256 including self-matches. In the following, one comparison result output is referred to as "one bit."

FIG. 26 is the most simple example in which the logical threshold values of 16 CMOS inverter circuits are arranged in sequence as VLTQ1>VLTQ2> . . . >VLTQ16.

FIG. 27 is an example in which the logical threshold values of CMOS inverter circuits are at random. "1" indicates that the second CMOS inverter circuit has a logical threshold value higher than that of the first one, "0" indicates that the second CMOS inverter circuit has a logical threshold value lower than that of the first one, and "*" indicates a self-match or indefinite. As can be seen in the two examples, bit patterns at OUT of the circuits corresponding to FIGS. 26 and 27 change to inherent patterns depending on how the logical threshold values of the CMOS inverter circuits are ordered. Thus, a direct use of the bit pattern at the output OUT as the identification number can be deemed to be the most simple manner. The number of bits of the identification number information in this method, i.e., data amount is 256 bits.

The bit pattern is nothing but a so-called match result table itself. On the other hand, the concept which underlies this application is the order of magnitude of logical threshold values of a plurality of CMOS inverter circuits. It is contemplated that the data amount of information to be handled can be reduced if information on the order of magnitude alone can be retrieved from the match result table.

FIGS. 26 and 27 show on the lower side and right side total numbers of "1" or "0" in the vertical direction and horizontal direction except for the self-match fields. For example, looking at totals of "1" on the lower sides of FIGS. 26 and 27, the order of the magnitude of number corresponds to the order of the magnitude of the logical threshold value. Compared to a league match of sports such as foot ball or baseball, this is the same as a stronger team having a larger number of wins. Speaking with the CMOS inverter circuits, as a higher logical threshold value has a larger number of "1."

Since the number of wins or the total number of "1" is equivalent to the rank, the total number of "1" can be used to represent the order of magnitude of the logical threshold values of the CMOS inverter circuits. Of course, no change is basically caused even if the total number of "0" is used or a total number of "1" or "0" in the horizontal direction is used. With the use of this method, the data amount of information bit can be reduced. Since each CMOS inverter circuit can have an order which can be represented by a number from 0 to 15, four bits of information amount are required in binary notation. Since there are 16 CMOS inverters, a total of 64 bits (=4.times.16) are required. As compared with the foregoing comparison result (match result) table, the data amount can be reduced by a factor of four from 256 bits to 64 bits.

While one unit is herein comprised of 16 CMOS inverter circuits, this effect is increased as the number of CMOS inverter circuits is larger. For example, with one unit comprised of 32 CMOS inverter circuits, the comparison result table requires
1024 bits, whereas when the order is used, the number of bits is reduced to 160 bits (5.times.32) by a factor of 6.5. Stated another way, although the comparison results are increased by a factor of four (=1024/256), this can be reduced to an increase by a factor of 2.5 (=160/64) with the order-based information. This is advantageous in that the identification system manages a less amount of data, and a processing time spent for matching can be reduced.

FIGS. 28 and 29 each illustrate a schematic diagram of one embodiment of a matching algorithm in the identification system for the semiconductor integrated circuit device according to the present invention. While description is herein made on a method using comparison result information of the logical threshold values of CMOS inverter circuits, a method using the order of magnitude of logical threshold values is identical in general flow.

FIG. 28 illustrates a registration method.

(1) 256-bit comparison result information for the logical threshold values of the CMOS inverter circuits is read from the identification number generator circuit.

(2) The comparison result information is registered in an identification number management ledger and assigned a management number for relating to a database which stores information such as measurement data and the like.

(3) The number of registrations is incremented by one. While it is herein assumed that a newly registered identification number is not the same as those previously registered at all times, it is effective to add a procedure for confirming a duplication of registered one and generating some alarm upon new registration.

FIG. 29 illustrates a matching method. This system is characterized by allowing fluctuations in identification number due to a difference in environment and conditions between a registration instance and a matching instance.

(1) 256-bit comparison result information for the logical threshold values of the CMOS inverter circuits is read from the identification number generator circuit.

(2) Registered identification numbers are sequentially retrieved from the management ledger.

(3) The registered identification numbers are compared with an identified number. A comparison method will be later described.

(4) The one having the smallest difference between a registered identification number and the identified number is selected as a matching candidate. By repeating (2) to (4), the one finally having the smallest difference of all the registered identification numbers is selected as the most probable identical candidate.

FIG. 30 illustrates an explanatory diagram for an exemplary comparison method in FIG. 29. The identified number is shown by extracting 24 bits or a portion of the 256-bit comparison result output of the logical threshold values of the CMOS inverter circuits. Identification numbers 1 to 5 are registered identification numbers. Shaded portions in them are portions different from the bits of the identified number. A total number of unmatch bits is shown at the right end.

As described in connection with FIG. 8, since the "0" and "1" output patterns of the identification number generator circuit are unique to respective units, it can be determined whether or not an identification number is outputted from the same unit from the proportion of the number of matching bits which make up the pattern. While the identification number here is a mere example for description, the identification number 5 has the number of unmatch bits equal to one, and the remainders have the number of unmatch bits in a range of 5 to 17, making it apparent that the identification number 5 has a markedly high matching ratio. Therefore, the identification number 5 can be selected as the most probable candidate.

FIGS. 31 and 32 show explanatory diagrams of an exemplary identification number comparison method using the order of logical threshold values of CMOS inverter circuits. FIG. 31 is shown in a tabular form, while FIG. 32 is shown in a graphic representation. It is assumed herein, for simplifying the description, that the order of elements of identified numbers, i.e., the arrangement of the logical threshold values of the CMOS inverter circuits is the same order as element numbers. The identification number 1 is such that the element numbers 8 and 9 change place with each other, and the remainders are matching. In comparison with the identified numbers, a total of absolute values of distances of both orders is two. The identification number 2 has a random order, a total distance of order equal to 66, and its average equal to 4.13. Since an expected value of a total of the distances of this order is 85 in theory and 5.3 on average, the identification number 1 having the total of the distances of the order equal to 2 and an average equal to 0.125 can be said to be highly likely to be the same. In other words, for allowing fluctuations in identification numbers due to a difference in environment and conditions between the registration instance and matching instance, this system selects the one having the smallest total of discrepancies of identified numbers to registered identification numbers as a matching candidate.

In the identification number 3 in FIGS. 31 and 32, the order of the element number 1 deviates by five steps. The element numbers 2 to 6 deviate by one step, and the others deviate by zero step. A total and average of the distances of order are
10 and 0.625, respectively. As long as these values are concerned, they are sufficiently lower than expected values, so that it is highly likely to be a matching candidate. However, a deviation of the order by five steps in the element number 1 is deemed to be a rarely encountered phenomenon. If there were one which indicates an order distance equivalent to or slightly larger than the identification number 3, it is effective to add a maximum disparity of the order distance of each element to determination criteria in order to confirm more accurate identity. A specific example of the criteria is to add "the order distance of each element is two or less" to a reference which states "a total of order distances is 16 or less." Actual criteria differ depending on the characteristics of the identification number generator circuit and a system to which the present invention is applied.

FIGS. 31 and 32 illustrate when the number of elements for the identification number, i.e., the number of CMOS inverter circuits is 16. There can be some cases where the number of elements for the identification number is increased for such a reason as satisfying a higher capabilities of identification. For this purpose, a method of expanding the configuration as illustrated in FIG. 20, for example, is one of the most simple methods. An increase in the number of elements in the configuration of FIG. 20 can be achieved by setting CMOS inverters and switch MOSFETs corresponding to the number, setting the number of counter bits corresponding to the number, and setting the decoder. Another alternative method for increasing the number of elements may involve disposing a plurality of identification number generator circuits mainly comprised, for example, of 16 CMOS inverters in the same semiconductor integrated circuit device.

After delivered from the pre-process, semiconductor integrated circuit devices LSIs are subjected to a probe test in a wafer state, a screening test in a packaged state, and the like to detect faults. For memories, logic LSIs which mixedly include relatively large scaled memories, and the like, a so-called redundancy remedial technique has been introduced for substituting spare memory cells for defective memory cells which are detected in the probe test. With the miniaturization, higher speed and higher performance in the recent semiconductor processing technologies, a number of defective products are detected in a final screening step. Moreover, since semiconductor integrated circuit devices LSIs are more and more increased in scale, such defective devices detected after the manufacturing process are problematic because they causes a higher cost.

Thus, there is an increasing need for again recovering defects detected in products after assembly. For example, giving a memory as an example, chips damaged by the burn-in step and the like are collected, and deteriorated bits included in defective chips are again recovered with remaining spare memory cells.

Specifically considering the second recovery technique, the next two representative methods are contemplated for the recovery technique. A first method involves giving an independent number to each LSI to manage all recovery information in a probe test step for each memory chip. For the second recovery, the chip number is extracted from a memory chip, recovery information collected in the probe test step is retrieved from a management computer, and unused memory cells are identified based on them for the second recovery. A second scheme involves extracting the first recovery information from memory chips each time the second recovery is carried out. This employs a technique referred to as a so-called address roll call.

The following techniques are required for applying these second recovery techniques. In the first scheme, an independent number must be given to each memory chip. This can be implemented by programming an identification number upon a recovery performed after a probe test. In addition, in both the first and second schemes, it is necessary to contain an electrically programmable element upon second recovery. While the electrically programmable element may be provided at present by fusing polysilicon with a current, breaking an insulating film with a high electric field, using a FLASH memory, and the like, all of them can produce side effects such as an increased number of steps, the reliability of the programming element, an increased peripheral circuits, and the like.

Both the foregoing schemes involve mounting any programming element in an LSI body. The inventors of this application investigated a third scheme for dividing both parties into separate chips from another angle. This third scheme features that a dedicated process suitable for programming can be applied to a dedicated programming chip. Even this third scheme still has the following problems.

One problem is how LSI bodies are corresponded to the dedicated programming chips. Consider a method of solving this problem, taking a multi-chip module as an example. In the multi-chip module, both chips are finally assembled into a single semiconductor integrated circuit device on a module substrate. However, the combination must be strictly managed until each chip is assembled into the module. It is not easy to build an LSI manufacturing line which realizes this. It is therefore contemplated to assign an identification number to an LSI body, read the identification number of the LSI body which is mounted on the module substrate, and program information corresponding to the LSI body into a dedicated programming chip.

When a technique of cutting with a laser irradiating device, for example, is used as a programming method, such a laser irradiation cutting device can cut a fuse of a chip in a wafer state, but experiences difficulties in cutting a chip on a package or a module. This is because an alignment of fuse coordinates of a chip on a package or a module to a laser beam is technically difficult, and even if it is achieved, the alignment is required for each chip, resulting in an extremely low throughput. Essentially, a problem exists in how to read the identification information of the LSI body before irradiation of laser. For this reason, the dedicated programming chip is limited to an electrical programming scheme which can continuously execute a read-out of the identification number of the LSI body and a program on the same device.

Thus, a realistic form of the third method is "to mount an LSI body accompanied by an identification number and a dedicated program chip having an electrical programming element on a multi-chip module and program." However, the third scheme is also established on several constraints, and is not always the best option in the LSI production activities, for example, in view of the cost and reliability.

One of the constraints is the use of a multi-chip module as a premise. However, it is further unrealistic to employ a method of combining two chips directly on a substrate, for example, without using a multi-chip module.

A second constraint is the requirement of using processes which enable an electric program for a programming element used in the dedicated programming chip, for example, a polysilicon fuse, a FLASH memory, FRAM and the like. Each of these elements requires special processes, has a peripheral circuit in large scale, and is seemingly problematic in the reliability. As a relatively inexpensive scheme which suffers less from these problems, there is a programming scheme which uses a laser cut metal fuse, however, it cannot be said to be compatible with the third scheme, as mentioned above.

A third problem is the programming (marking) of an identification number into an LSI body. This programming also requires a laser fuse and an electrical program element. However, if a similar process is added to the LSI body even though the dedicated program chip is separately provided, the advantage of a reduced cost of the LSI body is mitigated. Thus, to solve these problems, the identification number generator circuit which uses variations in logical threshold values of CMOS inverter circuits is extremely useful.

FIG. 33 illustrates a schematic diagram of one embodiment of a semiconductor integrated circuit device to which the present invention is applied. First, a probe test is conducted for the LSI body. In this event, if faults are detected, for example, in a memory mounted in the LSI, recovery information is created for replacing the defective memory with a spare memory cell. For normal general-purpose memories and the like, a laser recovery is performed subsequently, whereas in the semiconductor integrated circuit device of this embodiment, the LSI body is diced as it is and assembled. Further, fault information subsequently detected in such steps as aging, screening and the like is added to the recovery information at the probe test. The final recovery information is written into the dedicated programming chip. The LSI body and dedicated program chip are used in combination as a multi-chip module.

FIG. 34 illustrates a block diagram of one embodiment of the multi-chip module to which the present invention is applied. Data is serially communicated between the LSI body and dedicated program chip through a data exchange control circuit in synchronism with a clock. In other words, an identification number generated in the identification number generator circuit of the LSI body is transferred to the dedicated program chip through the data exchange control circuit.

The dedicated program chip holds a plurality of registration numbers (identification numbers) corresponding to one unit and their defect recovery information in one-to-one correspondence as programming data. The dedicated program chip registers identification numbers transferred thereto from the LSI body through the data exchange control circuit into an identified number register through a counter.

A matching circuit compares such an identified number with registered identification numbers in the programming data for matching. This matching operation makes the determination while allowing fluctuations in identification numbers due to a difference in environment and condition between the registration instance and matching instance in accordance with the algorithm illustrated in FIGS. 30 and 31. As a matching candidate number is detected, register data in the programming data is read to a data read circuit. Then, reverse to the identification number, the recovery information is transferred from the dedicated program chip to the LSI body through the data exchange control circuit. This recovery information is serial-to-parallel converted and held in the data register for use in the defect recovery.

Since the dedicated program chip has defect recovery information for a plurality of chips corresponding to one unit, one type of dedicated program chip is formed for a plurality of LSI bodies for one unit, and is commonly combined for use. For this reason, it is not necessary to manufacture, manage and assemble the LSI bodies and dedicated program chips in a one-to-one correspondence.

FIG. 35 illustrates a block diagram of one embodiment of the dedicated program chip. Though not particularly limited, the dedicated program chip is composed of an identification number decoder circuit, a matching circuit, a circuit for reading programming data and data, and the like. The registered identification number and resister data are registered by selectively cutting fuses with irradiation of laser.

In the matching circuit, corresponding to the determination algorithm in FIGS. 30 and 31, an absolute value of a subtraction result using a subtractor is compared with an upper limit value in a comparator 1 for detecting an alienation. A comparator 2 compares a cumulative distance outputted from the accumulator with reference to a minimum cumulative distance which is sequentially replaced, and one matching candidate number is outputted from 1 to N by a determination circuit together with the alienation detection signal. Register data is selected by this matching candidate number and transferred to the data read circuit. The data read circuit is designed to have an ECC function (error correcting function). This improves the reliability of data.

FIG. 36 illustrates a schematic diagram of manufacturing steps (1) to (13) in one embodiment, referred to as a so-called post-process, of a semiconductor integrated circuit device which is mounted with the identification number generator circuit according to this application. In this embodiment, it is assumed that the LSI body is a large scaled system LSI which comprises a mixture of DRAM and SRAM, and the dedicated program chip is implemented by laser cut metal fuses. In the following, the flow of manufacturing steps will be described with reference to FIG. 36.

(1) The LSI body is tested by a probe tester. An identification number in the LSI is transferred to a host computer together with defective memory cell recovery information, an internal power supply circuit trimming setting, a delay circuit setting and the like in the DRAM and SRAM. The host computer stores the information sent thereto in a database in conjunction with other manufacturing management information.

(2) An LSI body wafer is diced.

(3) The LSI body alone is preliminarily mounted on a multi-chip module substrate. While there is one LSI body in FIG. 36, there can be a plurality of LSI bodies.

(4) The identification number is read from the LSI body by a screening tester and sent to the host computer. The host computer recognizes the LSI body from the identification number, and returns information necessary to the individual LSI body to the tester. The necessary information refers to the defective memory cell recovery information, LS1 body identification information and the like which are managed by the host computer in the database. This is referred to as the "LSI body register information." The screening tester stores the LSI body register information in a recovery address register of a recovery circuit in the LSI body if it is, for example, defective memory cell recovery information, and stores the LSI body register information in a trimming value setting register in an internal circuit if it is an internal power supply circuit trimming setting.

The screening tester conducts a fast operation test and the like which cannot be covered by the probe test, after setting the LSI body register information. The screening tester also transfers fault information on those which are additionally detected as faulty to the host computer. The host computer analyzes the fault information sent thereto together with collected information to determine whether either a second recovery or an adjustment can be made, and again stores the information in the database.

(5) The register information necessary to the LSI body is programmed into the dedicated program chip. Further, manufacturing management information, customer information, cipher, function information and the like are programmed, if necessary. The dedicated program chip can store therein information on a plurality of LSI bodies. For example, assuming that the dedicated program chip has a capacity of storing information on 100 LSI bodies, a laser cutter receives identification numbers and register information of 100 LSI bodies from the host computer, and programs the same register information of the 100 LSI bodies into all of 100 dedicated program chips based on the received information.

Here, an estimation is made for a fuse cutting time for the dedicated program chip. Assuming for example that the number of bits for programming per LSI body is 1,000 bits, and one dedicated program chip can store (register) information for 100
LSI bodies, one dedicated program chip has 100,000 (1000.times.100) fuses. Since the recent laser cutter has the ability of 5,000 pulses or more per second, 100,000 fuses can be cut in about 20 seconds, i.e., for one dedicated program chip. 2,000
seconds (33 minutes.) are taken for 100 chips. Also, the dedicated program chip has the area of 1.5 square millimeters for the fuses, assuming that one fuse has a size of 15 square microns, and approximately three square millimeters, including peripheral circuits and pads.

(6) A probe test is conducted for removing laser cut defective chips. In some cases, a step may be added before the main process for depositing a protective film for protecting a chip. A test data pattern is received from the host computer. Here, since laser cut defective chips can be produced, more than 100 chips should be programmed in the foregoing step (5). This number is adjusted by results of yield rate. Here, if the dedicated program chips are less than the LSI bodies, surplus LSI bodies are recovered and mixed into another group. Conversely, surplus dedicated program chips, if any, are discarded. Though a damage is caused in any case, this is more economical than discarding expensive LSI bodies.

(7) The dedicated program chips are diced. From diced chips, 100 chips and a margin, which have been programmed with the same information in the step (6), are picked up and collected into a group (lot) which corresponds to the LSI bodies.

(8) A dedicated program chip is mounted in a multi-chip module package. In this event, the groups corresponded in the steps (4) and (6) must be combined. However, since the individual LSI bodies need not be corresponded one-to-one to the dedicated program chips, no significant change in steps is needed as compared with the conventional assembling steps. While in this embodiment, complete encapsulation or capping is not performed in consideration of a subsequent separation step (10) in this assembling steps, the present invention is not necessarily limited to this method.

(9) Completed multi-chip modules are finally tested for screening. The dedicated program chip contains (registers) recovery information for 100 chips. When the LSI body on a board is activated, data is exchanged between the LSI body and dedicated program chip. Specifically, the identification number is sent from the LSI body to the dedicated program chip, and the dedicated program chip compares the sent identification number with identification numbers stored therein to identify the LSI body mounted in the module, and sends necessary register information such as recovery information to the LSI body. The LSI body performs internal initial settings based on the register information sent thereto. Subsequently, a final test is conduced. Those which pass the final test are conveyed to the next encapsulation step, while those which fail the final test are conveyed to a separation step, and simultaneously, fault information is sent to the host computer to analyze whether or not the defective ones can be recycled.

(10) Modules which have passed the