REGISTER  |  SIGN IN
United States Patent6904110
Trans , ; et al.June 7, 2005
Title
Channel equalization system and method
Abstract
A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention increases channel capacity by using a parallel or multi-channel structure in such wireless and wireline at the edge or the core of. This new architecture of the present invention uses parallel bitstreams in a flexible way and distributed switching/routing technique, is not only to avoid the potential bottlenet of centralized switches, but also to increase speed with intelligence that is seamlessly integrating into the Fiber Optic Backbone such as WDM and SONET of the MAN/WAN network with a Real-time guarantees, different types of traffic (such as Stringent synchronous, isochronous, and asynchronous data messages) with different demands, and privacy & security of multi access and integrated services environment.
Inventors:Trans; Francois (Los Altos, CA), Le-Ngoc; Tho  (Anjou, Quebec CA)
Appl. No.:847097
Filed:May 1, 2001
Current U.S. Class:375/350 375/229 
Field of Search:375/229-234,285,346,350 708/300.301,322,323,319,300,301 333/18,28R
U.S. Patent Documents
4412341October 1983Gersho et al.
4630217December 1986Smith et al.
4648060March 1987Allen et al.
4905282February 1990McGlynn et al.
5111208May 1992Lopez
5162723November 1992Marzalek et al.
5181228January 1993Takatori
5293402March 1994Crespo et al.
5541955July 1996Jacobsmeyer
5550810August 1996Monogiousdis et al.
5625651April 1997Cioffi
5675612October 1997Solve et al.
5680451October 1997Betts et al.
5754352May 1998Behrens et al.
5787363July 1998Scott et al.
5812594September 1998Rakib
5841667November 1998Martin
5864545January 1999Gonikberg et al.
5930267July 1999Daneshrad et al.
6144697November 2000Gelfand et al.
6236645May 2001Agazzi
6377640April 2002Trans
6538986March 2003Isaksson et al.
6553085April 2003Trans
Other References
Per Lindgren; A Multi-Channel Network Architecture Based on Fast circuit Switching; May 1996; Kungel Teknisha Hogskolan Royal Institute of Technology; pp. I-180..~
Primary Examiner: Bocure; Tesfaldet
Attorney, Agent or Firm:Fenwick & West LLP
Parent Case Text


RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 09/550,395, filed on Apr. 14, 2000, now abandoned, which is a continuation-in-part of U.S. provisional application Ser. No. 60/170,455, filed on Dec. 13, 1999.

This application is also a continuation-in-part of U.S. patent application Ser. No. 09/444,007, filed on Nov. 19, 1999, now abandoned; which is a continuation-in-part of U.S. patent application Ser. No. 09/417,528, filed on Oct. 13, 1999, now issued as U.S. Pat. No. 6,553,085 on Apr. 22, 2003; which is a continuation-in-part of U.S. provisional application Ser. No. 60/104,316, filed on Oct. 13, 1998, and which is a continuation-in-part of U.S. provisional application No. 60/109,340, filed on Nov. 20, 1998.

This application is also a continuation-in-part of U.S. patent provisional No. 60/129,314, filed on Apr. 14, 1999. This application is also a continuation-in-part of PCT application number PCT/US00/06842, filed Mar. 15, 2000.

This application is also a continuation-in-part of U.S. patent application Ser. No. 09/127,383, filed on Jul. 31, 1998, now U.S. Pat. No. 6,377,640, which is a continuation-in-part of U.S. provisional application No. 60/089,526, filed on Jun. 15, 1998; and which is also a continuation-in-part of U.S. provisional application No. 60/085,605, filed on May 15, 1998; and which is also a continuation-in-part of U.S. provisional application No. 60/054,415, filed on Jul. 31, 1997; and which is also a continuation-in-part of U.S. provisional application No. 60/054,406, filed on Jul. 31, 1997.

This application is related to all of the above applications and herein incorporates by reference all of these applications in their entirety.
Claims

What is claimed is:
1. A system for reducing interference in a communication system, the interference occurring on a data sample signal having a precursor inter-symbol interference (ISI) portion and a post-cursor ISI portion, the system comprising: a first precursor equalizer, for receiving the data sample signal and for performing an equalization operation on said data sample signal to reduce the precursor ISI and to generate an ISI equalized sample signal; a summer, coupled to said first precursor equalizer, for combining said ISI equalized sample signal and a post-cursor cancellation signal to generate an equalized estimated sample signal; a slicer, coupled to said summer to receive said equalized estimated sample signal, for generating a detected symbol signal representing a preliminary symbol value of said equalized estimated sample signal; a precursor canceller, for receiving said equalized estimated sample signal and said detected symbol signal, for further reducing the precursor interference, said precursor canceller having: a finite impulse response filter, for receiving said detected symbol signal and for determining the precursor ISI on said detected symbol signal to generate a precursor cancellation signal, a first delay component to receive said equalized estimated sample signal, for delaying said equalized estimated sample signal by a first amount and to output a delayed equalized estimated sample signal, said first amount corresponding to a delay caused by said slicer and finite impulse response filter, a DPIC summer to combine said precursor cancellation signal and said delayed equalized estimated sample signal to generate a second output signal representing said data sample signal having a reduced precursor interference portion; and a first post-cursor canceller, for receiving said detected symbol signal, and for reducing the post-cursor interference on said detected symbol signal to generate said post-cursor cancellation signal.

2. The system of claim 1, wherein said post-cursor canceller includes a plurality of taps having input coefficients.

3. The system of claim 2, wherein said coefficients automatically adjust in response to the post-cursor interference on the data sample signal.

4. The system of claim 1, wherein said first precursor equalizer includes a plurality of taps having input coefficients to reduce the pre-cursor interference.

5. The system of claim 1, wherein said finite response filter includes a plurality of taps having input coefficients to reduce the pre-cursor interference.

6. The system of claim 1, wherein said first delay component aligns said equalized estimated sample signal and said slicer output signal.

7. The system of claim 1, further comprising: a second delay component, coupled to receive said data sample signal, for delaying said data sample signal by a second amount and for outputting a delayed data sample signal; and a second precursor equalizer, for receiving said delayed data sample signal and for performing an equalization operation on said delayed data sample signal to reduce precursor interference and to generate a delayed equalized signal; wherein said DPIC summer receives said delayed precursor equalized output wherein said delayed equalized estimated sample signal represents said data sample signal having a reduced precursor interference portion.

8. The system of claim 7, wherein said second amount corresponds to a delay caused by said first precursor equalizer, said summer, and said first delay component reduced by the delay caused by said second precursor equalizer.

9. The system of claim 7, wherein said second precursor equalizer includes a plurality of taps having input coefficients to reduce the pre-cursor interference.

10. The system of claim 7, further comprising: a DPIC slicer, coupled to said DPIC summer to receive said second output signal, for generating a DPIC slicer output signal representing a preliminary value of said second output signal; and a second post-cursor canceller, for receiving said DPIC slicer output signal, and for reducing the post-cursor interference of said DPIC slicer output signal to generate a DPIC post-cursor cancellation signal; wherein said DPIC summer combines said DPIC post-cursor cancellation signal with said precursor cancellation signal, said delayed equalized estimated sample signal and said delayed equalized signal to generate said second output.

11. The system of claim 10, wherein said second post-cursor canceller includes a plurality of taps having input coefficients.

12. The system of claim 11, wherein said coefficients automatically adjust in response to the post-cursor interference on the data sample signal.
Description
BACKGROUND OF THE INVENTION

Throughout history, people to people communication delivery system is a most challenging subject and countless new technologies were invented and strive to resolve. The people to people communication, perceptions and all five of the senses need to be extended into the global distance. Video, Voice, Data delivery systems are the current mechanism of extending the human perceptions or Tele-senses. Each of the communication means have made many independently advances in the past decade. Still, the voids are still there and hence there is a need to invent new technology for striving and enabling the human Tele-senses in a global scale. New application types drive new demands on the communication infrastructure as to integrate all of the existing technologies to a seamless manner for delivering the human Tele-senses.

The industries that in any of particular technology sector such as Television, Radio systems, Voice Phone systems, Data Enterprise Networking, Wireless, . . . etc are all currently and independently handle the problems. Each of the technology sector have devised a new way of delivering the information and communication in the global scale. In the Data Networking sector, new Local and Wide Area Networking such as IEEE 802.3x, IEEE-802.5 and ATM standards are formulated to deliver a means of interoperable data communication delivery system. In the television technology sector, the TV data and signals are currently deployed by Wireless Satellite receivers and transmitters such as DSS and DirectTV data delivery system. In the Voice technology sector, the integrated analog data modem and voice technology are currently deployed by Phone Carrier such as AT&T to carry either data or voice.

With all of the above technologies, the interoperable and integration of these technologies is difficulty since there is no "Unified" or common architecture that the mentioned communication means can seamlessly be integrated with. The communications industry has continuously pushed the bandwidth and capacity envelope, to the edge of the network, by developing and beginning the deployment of a number of higher bandwidth technologies.

These include 10/100/1000 Mb/s Ethernet within the enterprise, T1/E1, HDSL2, ADSL Modem applications for small business and homes, and high speed satellite modems for personal and business data communication use. These technologies promise to provide end users with the higher level of bandwidth required for today's applications.

The capacity of the backbone and edge network links has been the main bottleneck in a data and telecommunication system. As an example, the evolution of high speed data transfer at the telecommunication edge changes this situation; with the large amount of data capacity offered by ATM/SONET backbone networks, the bottleneck is moving towards the processing and buffering in switch-points and end-points. The same also applies to the wireless as well as for data communication with 10/100/1000
Mb/s Ethernet edge communication devices. Each of these communication methods have their own unique services, protocols and centralized processing architecture.

The impact of these technical changes imposed on end-to-end network architecture with the new integrated services demand new network requirements of different network architectures, such as unified telecommunication wireline & wireless and data communication high speed networking to support these different service requirements.

The current circuit-switched networks for existing wireline Telecommunication backbone and edge have many attractive properties in terms of providing real-time services from end-equipment to end-equipment. Traditionally, circuit-switched networks which are only available for the telecommunication infrastructure, have been too inflexible to provide a data service that is suitable for a wireline data communication and wireless data communication integrated services network. A "Unified" new generation of information delivery system, UniNet, illustrated in FIG. 01, that has the infrastructure support for integrated services in wireline and wireless telecommunication and data communication architecture that is needed.

The Com2000 Technologies described below supports a new data communication architecture. The new architecture is the Unified Communication System--Fast Circuit Switch (packet/circuit) communication processors which enables a new Internet Exchange Networking Processor Architecture. The Com2000.TM. Technologies set out to increase speeds over any communication channels, synchronizing, enabling, improving, controlling and securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data corn backbone, is illustrated in FIG. 02.

SUMMARY OF THE INVENTION

The Com2000.TM. Technologies increase speeds over any communication channel, synchronizing, enabling, improving, controlling and securing all of the data transmission of Web OS enabled applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data corn backbone. The Com2000.TM. Technology addresses all of the challenges for the new unified architecture of packet/circuit processors of internet networking processor, which includes the increased speed and delivery of a highly integrated services and solutions of the convergence nature of Security and Intelligence limitations over existing wireline and wireless data communication and telecommunication infrastructures. The breakthrough Com2000.TM. Speed, Security and Intelligent solutions enabling increase speed and robust transport schemes, over existing copper wire line and wireless infrastructures, illustrated in FIG. 03.

Com2000.TM. technologies represents a collection of state-of-the-art schemes in multi-channel signal modulation/coding, advance adaptive equalization, precision synchronization, reconfigurable DSP structures to increase speed and to deliver real-time, robust and deterministic multiple-access, and intelligence transport protocols which can be used for mapping of legacy protocols. It reflects the concept of reconfigurable and remote computing internet networking processor applied to future communications so-called software radio/wireless/wireline or web transceiver/internet processor.

Speed

Com2000.TM. Speed technology addresses the current wireless and wireline capacity limitation and challenges with a highly integrated solution that will enhance any data and telecommunications where noise is a problem. This technology, as an example, can be applied and deployed in numerous major market segments such as Standard Compliance High Speed Networking 1000BaseT Copper Gigabit (802.3ab) Single & Quad, or Broadband Access (HDSL2 focus) and other high-speed wireless and wireline networking. This technology can be applied and deployed in numerous new major market segments such as Next Generation High Speed Networking 2000BaseT (2 G/s) Copper Gigabit (802.3ab+) Single & Quad, 10 Gigabit Networking over Copper, Next Generation Fiber Channel SAN over copper, Next Generation Broadband Access (HDSL3 w/3 Mb/s), Next Generation 100 Mb/s Home Networking over POTs and other next generation high-speed wireless and wireline networking applications.

The Com2000.TM. Speed technology represents the collection of state-of-the-art FIR filtering schemes in multi-channel signal coding (advance adaptive equalization) that enhance the channel Inter-symbol Interference (ISI) and Cross Talk noise suppression for wireline and Multipath Noise and Fading Suppression for wireless applications, as illustrated in FIG. 04.

To demonstrate the Com2000.TM. Speed technology, techniques and analysis in this application, the initial wireline applications for the technology are Copper Gigabit Ethernet and HDSL2.

Through detailed analysis, the present invention has shown dramatic improvements in signal to noise ratio (SNR) in both Copper Gigabit and HDSL2. Analysis shows an improvement of the SNR by 8 dB over Copper Gigabit with respect to the 802.3ab IEEE Standard suggested 10 dB receiver designs. It further shows a >5 dB SNR improvement over the current HDSL2 suggested front-end designs of T1/E1 on the downstream and >3 dB upstream for crosstalk models represent the 1% worst-case coupling scenario for all the packings of N disturbers into a 50-pair binder group.

With this higher SNR margins, the present invention can be used to increase the higher performance and data rate capacity of the channel or to reduce the cost of the channel. For example, increasing the SNR results in simpler Forward Error Correction (FEC) and filtering schemes that reduce the design complexity which leads to power savings and die size reduction. This can be used in higher performance applications such as higher speeds or longer distance. In the higher data rate applications, the enhanced SNR coupled with the multi-channel signal coding can be used to deliver the increased bandwidth. As an example in longer distance or higher speeds for 1000BaseT application, with Com2000.TM. Speed technology, the new transceiver can deliver 1000 Mb/s over 200 meters vs. 100 meter 802.3ab standard for longer distance applications or 2000 Mb/s vs. 1000 Mb/s standard for higher speed applications respectively. As an example for HDSL2 application, the new transceiver can deliver 1.5 Mb/s over 18 Kft vs. 12 Kft HDSL2 T1/E1 standard for longer distance applications or 3 Mb/s vs. 1.5 Mb/s standard for higher speed applications.

Intellegence (Physical Layer)

Com2000.TM. Intelligence--Modem technology, in general, utilizes a combination of the frequency division, phase division and time division duplex techniques in signal coding and latency controls to provide new and integrated solutions for next generation universal synchronous networking communications. It supports legacy modulations and also as an integrated platform for 2-dimensional CDMA (Phase), TDMA (Time) and FDM (Frequency) multi-access scheme's. Each of these legacy schemes in each of the transmitting domain will be further exploited for higher data rate transfers with the help of 3-dimensional multi-access scheme and controls. However, in contrast to conventional systems, when all of the domain are exercised for the most optimal data transfer mechanism, along with all 3-dimensional multi-access scheme's precision controls, data transfers will be further increased as the results of orthogonal signal parameters are characterized, as illustrated in FIG. 05.

A new Com2000.TM. data delivery architecture for wireline and wireless is the shared or non-shared medium access with multi-channel networks with the support of synchronous and controlled environment. To support the precision controls in bits, symbol, subsymbol, frame, sampling, carrier and phase timing of synchronous transceivers, the Com2000.TM. Intelligent (Modem)--Precision Clock Transfer technology is used to enable the synchronous data communication networks. The precision clock transfer and control technology relates to stringent applications such as ITU global and local synchronization level service of SONET and telecom synchronization, as illustrated in FIG. 02.

In any type of communication channel, there is distortion that can cause errors in data signaling thereby reducing effective throughput. When data is transmitted over a communication channel at a particular signal parameter and characteristics, the signal's characteristics often changes as the signal propagates along the channel. The imperfections in the communication channel tend to reduce the resolution of the data bandwidth of the signal being transmitted across the channel. Furthermore, the data may not be interpreted correctly at the receiving end of the channel if the transmitted signal's characteristics are outside of a defined signal's parameter range. Com2000.TM. Intelligence (Modem)--Channel Measurement and Calibration Control Technology measures and calibrates the communication channel to determine the highest possible data capacity for a particular medium, as illustrated in FIG. 05.

Advanced Channel Measurement & Control techniques also enable any topology media channel calibration for optimal signal controls and intelligence flow. Today's cable and wireless communication infrastructures are less than ideal. The communications channel must be first characterized so that errors and imperfections, such as frequency, phase, time and other distortions, can be identified. Com2000.TM.'s calibration system then uses these measurements to improve communication channel resolution by controlling the errors and imperfections of the channel. The Residual measurements of the Com2000.TM. Intelligence (Modem)--Channel Measurement and Calibration Control (343) system are very powerful tools for troubleshooting and calibrating communications across any wireline and wireless channels. Once the reference signal has been subtracted, it is easier to see small errors that may have been swamped or obscured by the signal distortion and modulation itself.

In the Com2000.TM. digital communication system, non-uniform noise distribution or discrete signal peaks indicate the presence of externally coupled interference. A goal of the Com2000.TM. Measurement and Calibration system is to ensure that the sending and receiving of selected parameters are measured and calibrated. Seven parameters measured by the Com2000.TM. Measurement system include power, frequency, phase, timing and other code modulation accuracy related parameters. The frequency and phase counter capabilities provide another method of measurement for the Com2000.TM. Measurement (343) system for determining the channel transmission medium frequency and phase distortions. Com2000.TM. Measurement Technology is used to measure many parameters that contribute to the propagation delays of communication channel infrastructure. The Com2000.TM. Measurement circuitry is also used to measure phase interval, frequency, period, pulse width, phase, rise and fall time and also does event counting

The Com2000.TM. Technologies set out to adapt over any communication channels and topologies. The Com2000.TM. Intelligent (Modem)--Advanced Medium Adaptation & Equalization Technology seamlessly filter adaptation techniques over any channel's topologies in any wireless & wireline infrastructure such as bus, point-to-point, point-to-multipoint, mesh, etc., so that higher speed and more reliable data transmission may be achieved, as illustrated in FIG. 05.

As an example with higher data rate applications in the new optimal phase domain alone, the Com2000.TM. Intelligent (Modem)--Multi-Channel Signal Coding technology allow to deliver higher data rates in a unique way from a single continuous or burst streams carrier frequency. The technology delivers multi-channel (phase division) network architecture that uses parallel bitstream in a novel way. It uses the non-complex or complex base band symmetry signal with phase division multiplex coding scheme or PDM to deliver the multi-channel requirements which also meets the selected media FCC constraints, as illustrated in FIG. 05.

As an example of the equivalent multi-channel optical networks based on wavelength division multiplexing (WDM), the phase domain's multi-channel wireline and wireless network utilize the optimal phase division multiplexing (PDM) for multi-channel wireline and wireless network. The Com2000.TM. Intelligent (Modem)--Precision Sampling technology enables to the precision sample the signal's parameters any or combination of the Time (Multi-Timne Slot sampling), Phase (Multi-Channel Phase sampling) and Frequency (Multi-Carrier sampling) signal spaces, as illustrated in FIG. 05.

As in most of M-PAM or M-QAM (M symbol Pulse Amplitude Modulation or M symbol Quadrature Amplitude Modulation) base-band modulation scheme, the signal coding and decoding is orchestrated in a "Relative" Phase Synchronization manner. The receivers recover the clock and phase from the received signal and use it for the sample timing to recover the data. Our enhanced technique is not only to deliver the "Relative" Synchronization scheme, but it also delivers the "Absolute" Synchronization technique to enable multitude of novel ways to increase bandwidth and intelligence controls. With the absolute and relative synchronization capabilities, the ordinary and single carrier frequency channel can be interpreted in a vector of channels, which can be characterized through precision phase channel measurement and calibration. Every other channel in a multi-channel media will be a non-interference channel with respect to the other channel and the selected M-PAM or M-QAM signal coding can be used to transmit over channels as in the current scheme.

Intellegence (Mac & Higher Layers)

Today a network carrier can be analogized with an airline business. You buy jumbo jets and attempt to ensure that all the seats in that jet are full. The goal is to make sure the network is full all the time. All traffic today is delivered via cargo class, but emerging needs such as voice and video traffic will require higher priority and must be upgraded to first class. With this capability, the present invention also allows to monitor which traffic moves in which class, and charge higher rates for better service. The carriers want to find ways to extract more revenue, and we are going to provide that capability of offering different tiers of network service. The carrier would also be able to have more intelligence about what their customers are doing with the network, so they could have separate billing for voice traffic or for Internet traffic, as illustrated in FIG. 01.

Com2000.TM. Intelligence (Transport)--QoS Transfers technology, as illustrated in FIG. 05, utilizes a synchronous and controlled enviromnent via a precision clock transfer and controls resident at the edge and the core of the network, to deliver universal and next generation synchronous, isochronous and asynchronous integrated data services or a novel Synchronous and Distributed Switching and Routing method. This precision controlled synchronous clock transfer technology not only enables the physical layer to communicate in increased speeds with a high capacity multi-channel and shared medium access, but also provides a basis for true quality of service, or Hard QoS. This can fundamentally be interpreted as a universal transport mechanism for integrated services that seamlessly map into and out of any new or current and legacy data corn and telecom protocols. These protocols include ATM, SONET, Frame Relay, and T1/E1, etc,. from the telecom services and IP networking protocols such as TCP/UDP from data communications. In short, this universal transport mapping or Fast Protocol Synchronous Circuit Switching, which is anything over anything transport mechanism such as IP over ATM, IP over SONET, ATM over IP, ATM over SONET, PPP over SONET, . . . etc. is applicable to all protocols from a very stringent synchronous services such as SONET, loosely isochronous services such as ATM and Frame Relay, etc, to a very loosely and best effort asynchronous data services such as Internet IP protocols. Due to precision network synchronization and fixed cell based processing at the physical layer of the transceivers, the data processing intelligence (distributed QoS/switching/routing) and networking system intelligence (Advanced Bandwidth Improvement via TCP/UDP/IP Latency Suppression, Timed Policy Based System Management, Web Remote Computing, and many other applications) are enabled with a new dimension and capabilities.

The ultra high speed bandwidth and network element and data processing intelligence enable a new architecture such as the Fast Data Synchronous Circuit Switching architecture which the fabric intelligence performs most of its tasks at the edge such as: fragmentation/defragmentation of the received packet based into Cell based for QoS controls and other network element intelligence such as the Switching/Router Functional intelligence in a distributed intelligence manner. These networking intelligence tasks, such as addressing, switching or forwarding, routing, policing and shaping, sequencing and flow controls for each switching node, for example, can be migrated to the edge node systems or Com2000.TM. UniNet PHY in this case. The high speed network connection between the end node(s) and the core node(s) is (are) just the extension of the "QoS" switching fabric, as illustrated in FIG. 06.

The ultra optimized method of time division multiplexing (TDM) data of the UniNet PHY, the network system intelligence are enabled with a new architecture Fast Transport Synchronous Circuit Switching architecture which the network intelligence performs most of its tasks at the edge such as: (a) Multiprocessor TDM Networking Operating System & Scheduling which can be used in different remote OS applications such as fragmentation/defragmentation of the received TCP/IP packet based into TDM cell TCP/IP based for further bandwidth improvements; (b) Time Policy based Management; (c) Follow the SUN Management (Universal UTC-Time based Management); (d) Web Remote Computing; and many more other applications.

Advanced TCP/UDP/IP Latency Reduction and TDM Scheduling Software Techniques, as an example, which are derived from Fast Transport Synchronous Circuit Switching, to further improve the bandwidth or capacity at the upper layer, e.g., when the layers deal with the information that are transferring over the data line for a convergence data/video/voice related applications and host. Each application such as in Video (Video Conference--TCP/IP) or Data (Email--UDP/IP ) or Voice (Tele-Conference TCP/IP) has the dedicated network connection such as IP addresses for different host nodes or/and at different TCP ports addresses for the same host node that is hosting all of the related applications. DOCCIS 1.1 for cable modem of most home with digital cable MSC intemet access will be installed with this single IP address scenario. For Telephone carrier xDSL for Telephone Digital Services allow more than one IP address for each of the access node, as illustrated in FIG. 01.

Security

The precision controlled environment at the physical layer and other layers offers a new method for the next generation security systems and services. Com2000.TM. Security--E-DNA Technology of packet/circuit processors for internet networking processor technology set out securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data-com backbone. SSI Com2000.TM. Security is to deliver, in a novel way, the lowest encryption and decryption layer possible without significantly impacting the speed by generating unique electronic signal signatures that proliferate through the entire data communication network, as illustrated in FIG. 02.

Summary

In summary, the Com2000.TM. Technology addresses Speed, Security and Intelligence limitations of the new information communication challenges, not only at the physical level for universal shared and non-shared medium interface, such as POTs, CAT5, wireless etc.; but also at the universal transport layer with stringent telecom delays & jitter requirements for Circuit Switching time sensitive related applications at media access layer or above. Com2000.TM. Technology addresses and meets all of the above challenges for the new unified architecture of packet/circuit processors for internet networking processor requirement and solutions, as illustrated in FIG. 02.

This new unified network can be used, in ISO application layer, directly for application-to-application communication or may be used in physical, data and transport layers as a carrier network for other protocols, such as ATM, ISDN or IP. The universal law of the unified network apply and traverse across the ISO layers for which it supports the legacy and new protocols for each of the ISO layer with the most optimal delivery mechanism. Com2000.TM. Technology for next generation universal synchronous networking communications will not only coexist with all legacy communication system but also as a new information communication platform that can be used to enable new technology advancement for future data commnunication challenges.

The Analogy

The Com2000.TM. technologies can be further explained in terms and analogy of the Internet Data Super Highway Management with emphasis of copper wireline applications.

As the population growth increases within a local or regional metropolitan area, the freeway traffic and its associated traffic congestion also increases. Due to increasing demand for commuting car, trucks, semi (data type loads) in the metropolitan (Internet) area, the freeway (Internet data freeway) needs to be widened so that new lanes can be built and trafficregulations are needed in place for accommodating new traffic type and demands. The freeway overpasses are added and needed to be re-architectured for easy access, freeway changeover, freeway entry, exits and timely regulated freeway admission during the particular time of the day. The commute lanes are also created during certain time of the day for removing traffic congestion. Notice that we can see all of our traffic demands and loads are correlated to our working hours. The demands are different and different time zone for example of pacific and eastern time zone or world standard time (UTC) as far as the global scale traffic demand is concerned.

The Com2000.TM. Speed Technology addresses the capacity (widen the road) of the network over the existing infrastructure copper links which has been the main bottleneck in a broadband access and high speed networking data communication system at the edge and the core of the network. The demands for high-capacity communications keep increasing at an exponential rate in recent years and have opened doors for opportunities to offer broadband communications solutions for multimedia services.

The Infrastructure to support such demands is in question and represents a major cost segment. Let us take a look into the current Broadband Access market and goals. One question is if we can use the existing infrastructure such as copper POTs media so that there is minimum additional/new costs for broadband communications and access? This question is "translated" into a general technical question: what are the limits of these media on capacity? or how fast we can send data over them? and can we do it? The last question has pushed the transmission technologies and techniques combined with VLSI technologies to achieve the theoretical capacity limits. Wireless communications, on the other hand, offers its advantages over wireline counterpart in fast system configuration and re-configuration.

Moreover, it provides a cost-effective solution in terms of infrastructure. However, bandwidth limitation is always a challenge for development of wireless broadband communications. The revolutionary Com2000.TM. Speed Technology of the wireline copper changes this situation; with the large amount of data capacity offered by copper at the edge networks. However, with the current and legacy architecture, the bottleneck is still moving towards the processing and buffering in central switch-points of the enterprise and telecom networks. In combination of Com2000.TM. Intelligence and Speed Technology, the data bottleneck problem at the core and the edge of the network are addressed and resolved. For example, the Com2000.TM. Speed and Intelligence transceiver technology can deliver up to 2.4 Gb/s over existing 4 pairs CAT5 infrastructure for enterprise high speed networking backbone with the intelligence of distributed switch-points processing.

SSI's Com2000.TM. Speed technology offers a unique approach for suppressing ISI and cross talk noise to previously unprecedented low levels, to guarantee and even increase the bandwidth (Signal to Noise Ratio) available over the existing copper cable infrastructure. As mentioned previously, An aspect of Com2000.TM. Speed technology is a collection of state of the art filtering schemes which filter noise intelligently in both the pre-ISI and post-ISI processing, interference and signal distortion and hence substantially boosting the signal-to-noise ratio. SSI Com2000.TM. Speed or Noise Suppression via Advanced Equalization Techniques are invented to increase capacity of any channel such as to deliver a .about.3.times. Signal to Noise Ratio Increase over existing copper infrastructure so that higher speed and more reliable data transmission can be achieved.

Com2000.TM. Intelligent Technology addresses and resolves the bottleneck problems at the edge and core of the network (overpasses and traffic regulations). The new generation fast circuit-switched network architecture is addressed to enhance the current legacy circuit-switched techniques to a high capacity multimedia network with an integrated services enviromnent. This new architecture is interoperable with a robust protocol suite in which is only available at the telecommunication fiber backbone such as SONET, and WDM transports.

The legacy and current Circuit-switched for the existing telecommunication architecture and packet-switched networks of data communications have very different characteristics. They can both support an integrated service environment, but have different merits in terms of providing various service aspects. A new fast or next generation integrated network architecture that is an effort to enhance existing circuit-switched techniques of telecommunication and with seamless integration to existing packet switching system of the wireless and wireline data communication domain are required for the next generation data transfer and delivery infrastructure. This new Intelligent architecture should seamlessly extend a high capacity to the edge of the network with an integrated service environment and seamlessly integrate with the existing wireline and wireless backbone networking without having to resolve the heavy bottleneck processing and buffering in switching points and end-points.

The Com2000.TM. Intelligent technologies for modem offer automatic selection of operating spectrum and bandwidth for a given medium transmission rate and modulation adaptively to given environment to select the optimum capacity versatility and universal in topology: bus (mesh), star (point-to-multi-point), linear (point-to-point), robustness and deterministic in transmission, worldwide or global synchronization and capacity allocation to support Synchronous data delivery such as SONET (SDH), Isochronous data delivery such as real-time data delivery, Asynchronous data delivery such as IP and other different QoS requirements for multimedia services. This is done based on the unified multi-access controllers of the frequency/phase/time multiple access schemes with fixed bursting switching frame size. Time, Phase and Frequency Division multi-access scheme for reconfigurable system are supported with flexible frame structure and slot definition and global signal synchronization for supporting current and future wireless and wireline information conmmunication.

In the Com2000.TM. Intelligent Technology wireline applications, we examine the capability of multi-channel and multi-data stream networks that run over the same copper pair. Our Com2000.TM. Intelligent Technology delivers a revolutionary way of delivering a combination of multiple distinct Burst data Switching channels via the Time Division Multiplexing scheme and multi-data stream via the multi-channel Phase Controlled Signal Coding scheme simultaneously over the copper media. This is possible via the Com2000.TM. Intelligent Signal Coding and Precision Sampling Technology. We believe that the parallel channel and parallel data stream structure in such networks are a more flexible solution in terms of bandwidth on demand services, than increasing the bitrate of a single bitstream. This revolutionary Com2000.TM. Intelligent Technology proposes and evaluates a network architecture that uses parallel channels and bit streams in a flexible way, and uses distributed switching to avoid the potential bottleneck of centralized switches.

In the Com2000.TM. Intelligence for wireline modem applications, we unify the networks based on Time, Phase division multiplexing (TDM, PDM) using multi-channel signal coding with distinct phases and time in multi-channel with each have parallel bits stream. All of them are transmitted over a single carrier communication scheme. The capacity of the channel will increase when multi-carrier communication scheme is deployed. These multi-channel (TDM) and multi-data stream (FDM, PDM) networks provide a circuit-switched type service with a programmable coarse or fine-grain channel granularity. Often the highest channel granularity is a single bitstream, e.g., a signal with appropriate phase delay. Before starting to send data, a synchronization between sender and receiver is needed so that they are attached and connected to the same bitstream.

SSI Com2000.TM. Intelligence delivers the capability of creating and removing new and dedicated data signal lanes in which can simultaneously transmit from any node to any node in point-to-point, point-to-multipoint, multidrop bus topologies. With this capability over existing copper infrastructure, higher speed lanes (commuted lanes) can be intelligently created and managed during the traffic jam time period of the day. This will also allow the Unified Packet/Circuit Switch data type and transmission for convergence of data communication and telecommunication can be seamlessly integrated. Com2000.TM. Intelligence delivers the capability of differentiating services between different traffic class or type (such as car/truck/semi) for each of the new data lane traffic.

SSI Com2000.TM. Intelligence delivers the capability of differentiating between one's network receiving and sending nodes with respect to the other's receiving and sending nodes on shared switched medium data lane traffic (Overpasses with Distributed Switching Nodes). The technology delivers a capability of simultaneously transmitting and receiving on the shared medium of any circuit node to any circuit node, in point-to-point, point-to-multipoint, multidrop bus topologies of local and other networking switching node of existing copper infrastructure. The Com2000.TM. Intelligence delivers an intelligent routing and switching, selection of the data freeway overpasses, exiting and admitting back into the freeway for real time delivery of the assembled and reassembled data for all of the data types, channels, circuits. The overpass is also intelligently created and managed during the traffic jam time period of the day between local region and world wide Internet Freeway UTC traffics.

SSI Com2000.TM. Intelligence delivers Synchronous, Isochronous and Asynchronous data messages and services. It is used to seamlessly integrate to the existing SONET telecommunication systems, enhance the capacity of the channels, and synchronize all of the data types channels and circuits.

Com2000.TM. Security set out securing all of the data transmission of web applications over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data-com backbone. Com2000.TM. Security is a collection of the state of the art algorithms that applies across the ISO layers for delivery of the encryption and decryption data message over a defined channel.

At the upper layers such as Application, Transport and Network ISO layers of the TCP/UDP/IP data messages, the data is encrypted and transported with a higher level E-DNA (Electronic--Deterrence Network Address Access) protocols. The average absolute and relative predictable time and the measured time for a message to travel over a predefined and calibrated channel is generally known to within a precise time window. UTC absolute and relative Time Division Password Algorithm, Connection Awareness Algorithms of the present invention deliver the encryption and decryption to a standard delivery channel with an unsecured key source of the channel communications without the possibility of impacting the speed at the application level and at the highest data security level. In general, the message is encrypted and decrypted with a scrambled & unscrambled key of certain symbol at certain time. The secured transport protocols and connection will be monitored and queried at certain period of time for Deterring Network Address (IP or TCP port ) Access (DNA).

The Electronic elements of the Com2000.TM. Security (E-DNA) system are designed from the start to enable data and network security at the physical signal layer. The technique greatly reduces the overhead associated with today's encryption and decryption schemes and is implemented to generate unique electronic signal signatures that proliferate through the entire data communication network.

At the physical layer security, the absolute and precision control of a universal time event via the Com2000.TM. Clock Transfer technology is marching along between the communicating nodes. This precision and bias forward in time marking is used as the basis for a security seed. This seed will be used to generate a true and unbreakable random number generator during one's lifetime. There will be three markings for the 3 dimensional cubical seeds such as Time, Phase and Frequency matrix cell. This is the Carrier Signal Offset Algorithm.

The signal's signature is composed of both the waveform signal itself and the content of the waveforms. The security system transmits the signature of the waveform by pre-positioning the signal at a specific frequency and phase matrix cell. The signal signature of the waveform's content is provided via the pseudo-random noise (PN) signature for each node of the network. The PN auto correlation will be exercised for multi user ID access. This PN signature provides network security by prohibiting any unauthorized intrusion by validating the signature, or E-DNA, of the sending node.

In the combination of The Com2000.TM. Security (E-DNA) technology at the physical layer such as the Carrier Signal Offset Algorithm for the signaling security systems, and in conjunction with standard MAC layer encryption and decryption algorithms, such as the UTC absolute and relative Time Division Password Algorithm, Connection Awareness Algorithm, The Com2000.TM. Security technology make transmissions over the Com2000.TM. system virtually impregnable from unwanted snooping and unauthorized access.

In Summary, Com2000.TM. Technology, as illustrated in FIG. 01, aims to develop the next generation Fast (Data & Transport) Circuit Switch for Information Communication System or Internet Networking Processor. It resides either at the edge and/or the core of the unified convergence network with a focus of integrated services such as multi-media data transmission over existing wireline and wireless infrastructure. This new architecture will seamlessly integrate to the legacy telecom & datacom backbone. This is done via an innovative and breakthrough software and hardware solutions and intellectual property based on SSI's Com2000.TM. technology, as disclosed herein. The technology addresses the universal nature of Speed, Security and Intelligence limitations over existing data communication and telecommunication infrastructures. As described above, Com2000.TM. Technology is applied on higher level of application layers which reside in the Web OS host. It is described for a high-speed Web OS host interface between a non centralized workstation and a network node with remote computing via Web enabled processing and IT distribution capability. The CyberIT Web host interface has been designed to provide a virtual Web IT Management and Controls of applications with the flexibility and intelligence of buffer management using conditional interrupts, allowing cacheable shared memories and support of fast connection establishment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 01 is an illustration of the Universal Intelligence Network "UniNet".

FIG. 02 is an illustration of the deployment example of the Private UniNet Network.

FIG. 03 is an illustration of the interconnect of the Private UniNet Network.

FIG. 04 is an illustration of a NEXT & FEXT Noise example of the UniNet Network.

FIG. 05 is an illustration of the node access in Time Domain of UniNet Share Medium Network.

FIG. 06 is an illustration of a QoS example of the UniNet Network.

FIG. 07 is an illustration of a Network Layers example of the UniNet Network.

FIG. 08 is an illustration of a Parallel Cross Talks Noise example of the UniNet.

FIG. 09 is an illustration of a UniNet Hierarchical Structure.

FIG. 10 is an illustration of the Copper Gigabit Ethernet over 4 Pairs of UTP Cables.

FIG. 11a is an illustration of the Copper Gigabit 802.3ab Suggested design Overall margins.

FIG. 11b is an illustration of the Copper Gigabit 802.3ab Suggested design FEXT noise margins.

FIG. 12a is an illustration of the Copper Gigabit 802.3ab Insertion Loss of 100 m CAT5 Cable.

FIG. 12b is an illustration of the Copper Gigabit 802.3ab Impulse Response of 100 m CAT5.

FIG. 13a is an illustration of the Copper Gigabit 802.3ab Return Loss ECHO of 100 m CAT5.

FIG. 13b is an illustration of the Copper Gigabit 802.3ab Worst Case ECHO Loss wrt Signal.

FIG. 14 is an illustration of the Copper Gigabit 802.3ab Worst Case NEXT Loss wrt Signal.

FIG. 15 is an illustration of the Copper Gigabit 802.3ab Worst Case FEXT Loss wrt Signal.

FIG. 16 is an illustration of the Copper Gigabit 802.3ab System Modeling for Analysis.

FIG. 17 is an illustration of the Copper Gigabit 802.3ab Received Desired Impulse Response.

FIG. 18 is an illustration of the Copper Gigabit 802.3ab Received ECHO Impulse Response.

FIG. 19a is an illustration of the Copper Gigabit 802.3ab Received NEXT Impulse Response.

FIG. 19b is an illustration of the Copper Gigabit 802.3ab Received FEXT Impulse Response.

FIG. 20a is an illustration of the Copper Gigabit 802.3ab Receiver Cancellers prior to FFE.

FIG. 20b is an illustration of the Copper Gigabit 802.3ab Receiver Cancellers after to FFE.

FIG. 20c is an illustration of the new Gigabit 802.3ab cascaded FSLE/DFE receiver Structure.

FIG. 21 is an illustration of the different Gigabit 802.3ab cascaded FFE/DFE SNR comparisons.

FIG. 22 is an illustration of different Gigabit 802.3ab cascaded FSFE/DFE SNR comparisons.

FIG. 23 is an illustration of the new cascaded FSFE/DFE and old FFEIDFE SNR comparisons.

FIG. 24 is an illustration of the Current proposed Gigabit 802.3ab SNR receiver architecture.

FIG. 25 is an illustration of the Margin offered by DPIC architecture scheme relative 802.3ab.

FIG. 26 is an illustration of the Improved performance DPIC architecture scheme relative 802.3ab.

FIG. 27 is an illustration of the Improved Performance DPIC architecture without NEXT.

FIG. 28 is an illustration of the Margin offered by various architecture schemes relative 802.3ab.

FIG. 29 is an illustration of the current HDSL2 architecture schemes.

FIG. 30 is an illustration of the Improved Performance DPIC architecture scheme relative HDSL2.

FIG. 31 is an illustration of the Improved Performance DPIC architecture scheme Measurement Pt.

FIG. 32 is an illustration of the Improved Performance DPIC architecture scheme relative HDSL2.

FIG. 33a is an illustration of the Society of Automobile Engineering Delong Network architecture.

FIG. 33b is an illustration of the SAE Delong Network's Impulse Response.

FIG. 34 is an illustration of the Delong Network for NG 1553 System Modeling for Analysis.

FIG. 35 is an illustration of the Current 1553 Transceiver Architecture & Data Coding Scheme.

FIG. 36 is an illustration of the DPIC-FSFE application on 1553 ISI cable for Precursor.

FIG. 37 is an illustration of the DPIC-FSFE application on 1553 ISI cable for Pre & Postcursor.

FIG. 38 is an illustration of the DPIC-FSFE application on 1553 ISI cable for Postcursor.

FIG. 39a is an illustration of the Newly Proposed High Level Next Generation 1553 Structure.

FIG. 39b is an illustration of the Newly Proposed Med Level Next Generation 1553 Structure.

FIG. 39c is an illustration of the Newly Proposed Detail Level Next Generation 1553 Structure.

FIG. 40 is an illustration of the Newly Designed UniNet Time, Frequency Multiplexing Scheme.

FIG. 41 is an illustration of the Newly Developed Synchronous PAM Signal Coding Scheme.

FIG. 42 is an illustration of the Newly UniNet Internet Communication Processor.

FIG. 43 is an illustration of the Newly Clock Transfer and Measurement Scheme.

FIG. 43a is an illustration of the Clock Transfer Subsection--Discipline Signal Generator.

FIG. 43b is an illustration of the Clock Transfer Subsection--Osc Reference Clock Generator.

FIG. 43c is an illustration of the Clock Transfer Subsection--Precision Ref Clock Generator.

FIG. 43d is an illustration of the Clock Transfer Subsection--Measurement Source Selector.

FIG. 43e is an illustration of the Clock Transfer Subsection--Correct Output Generator.

FIG. 43f is an illustration of the Clock Transfer Subsection--Communication Ref Clock Gen.

FIG. 44 is an illustration of the Newly UnNet Internet Clock Transfer Control Logics.

FIG. 45 is an illustration of the Typical Least Mean Square Adaptive Equalizer Control Logics.

FIG. 46 is an illustration of the Newly UniNet Internet Clock Transfer Transition Diagram.

FIG. 47a is an illustration of the High Level UniNet Internet System Block Diagram.

FIG. 47b is an illustration of the High Level UniNet Internet System Architecture Diagram.

FIG. 48 is an illustration of the High Level UniNet Internet Clock Tuning Logics.

FIG. 49 is an illustration of the High Level Intersymbol Interference Definitions.

FIG. 50 is an illustration of the Conventional FFE and DFE Equalizer.

FIG. 51a is an illustration of a phase dependent coverage of a FFE/DFE filter.

FIG. 51b is an illustration of the Subsymbol Sampling Phase and SNR Correlation.

FIG. 52a is an illustration of the Eye Opening Diagram of Biphase Manchester, MLT3, PAM5.

FIG. 52b is an illustration of the Signal Spectrum and Eye Opening Diagram of SPAM-5.

FIG. 53 is an illustration of the A/D Samples and Canceller Taps Errors for ECHO & NEXT.

FIG. 54 is an illustration of the Precision Angle Phase Control for Precision Signal Coding.

FIG. 55 is an illustration of the Time, Frequency and Phase Multiple Access Coding Scheme.

FIG. 56 is an illustration of the 2000 Mb/s Com2000.TM. Gigabit System Block Diagram.

FIG. 57 is an illustration of the Coherent Carrier Recovery PLL for Com2000.TM. Receiver.

FIG. 58 is an illustration of the General UniNet Frame Structure.

FIG. 59 is an illustration of the UniNet Downstream and Upstream Frame Structure.

FIG. 60 is an illustration of the UniNet Simplified Burst and Cell Structure.

FIG. 61 is an illustration of the UniNet Time Relationship between various Frame Markers.

FIG. 62 is an illustration of the UniNet Transmit Frame Gating Signal.

FIG. 63 is an illustration of the UniNet Receive Frame Formatter.

FIG. 64 is an illustration of the IP Packet Network Processing Functions.

FIG. 65 is an illustration of the Distributed Packet Switching Architecture.

FIG. 66 is an illustration of the UniNet Application over existing Ethernet IP Networks.

FIG. 67a/b is an illustration of the UniNet Variable TCP Window and Size Controls.

FIG. 67c is an illustration of the UniNet Variable IP Address Multiplexing and Controls.

FIG. 67d is an illustration of the UniNet Variable TCP & IP Window Controls.

FIG. 67e is an illustration of the UniNet Variable TCP & IP Access Window Controls.

FIG. 67f is an illustration of the UniNet Variable Password Access Window Controls.

FIG. 67g is an illustration of the UniNet CSOA Control algorithms.

FIG. 67h/i is an illustration of the UniNet E-DNA DES Algorithms.

FIG. 67j/k is an illustration of the UniNet E-DNA Key Encryption Control algorithms.

FIG. 67L is an illustration of the RIPEMD-160 Hash Control algorithms.

FIG. 68 is an illustration of the UniNet Communication Processor System Block Diagram.

FIG. 69a is an illustration of the UniNet Baseband Converter and Sampler Block Diagram.

FIG. 69b is an illustration of the UniNet Proposed Baseband Processor Block Diagram.

FIG. 70 is an illustration of the Prototype System for Applications using POTS as the Communications Media.

FIG. 71 is an illustration of the Block Diagram of the Prototype.

FIG. 72 is an illustration of the Ethernet Interface and Buffer Management Function.

FIG. 73 is an illustration of the DCA Block & Interface Diagram.

FIG. 74 is an illustration of the DCA Assignment Process.

FIG. 75 is an illustration of the Packetizer Block Diagram.

FIG. 76 is an illustration of the Multi-Frame Format of the Communication Protocol.

FIG. 77 is an illustration of the Standard Frame Format of the Communication Protocol.

FIG. 78 is an illustration of the Burst Format of the Communication Protocol.

FIG. 79 is an illustration of the TDMA Controller Interface Block Diagram.

FIG. 80 is an illustration of the TDMA Rx Framer Block Diagram.

FIG. 81 is an illustration of the Receive Framer Block Diagram.

FIG. 82 is an illustration of the Receive Frame Synchronizer Flow Chart.

FIG. 83 is an illustration of the Transmit Framer Block Diagram.

FIG. 84 is an illustration of the Tx Framer Control Flow Chart.

FIG. 85 is an illustration of the Burst-Mode Modem Block Diagram.

FIG. 86 is an illustration of the Block Diagram of Burst-Mode Modulator.

FIG. 87 is an illustration of the Block Diagram of the Equalizer.

FIG. 88 is an illustration of the Block Diagram of Burst-Mode Demodulator.

FIG. 89 is an illustration of the Synchronizer Block & Interface Diagram.

FIG. 90 is an illustration of the Analog Front End Block Diagram of the System.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

One aspect of the present invention is taking advantage of non-optimal way of current data communication, telecommunication, application communication and processing. The Com2000.TM. Internet Communication Processor can be thought as a most ideal platform for application processing, data communication & telecom communication and processing (Information Communication System or InfoCom).

The improvement can start at the media or channel(s) and then moving into higher level such as of ISO data communication and processing layers (Physical, Data, Network, Transport, Session, Presentation, Application). The Com2000.TM. Technologies set out to increase speeds over any communication channel, synchronizing, enabling, improving, controlling and securing all of the data transmission with Web OS related application's processing over existing wireline and wireless infrastructure while providing seamless integration to the legacy telecom & data corn backbone, as illustrated in FIG. 07.

At the Physical Layer (Channel & Equalization), Com2000.TM. technologies, represents the collection of state-of-the-art characterization and optimization schemes which is not only improving the current data communication over any channel, but also enables a new information communication architecture which enable multitudes of new technologies. We now describe each of ISO layers and the medium optimization schemes, as illustrated in FIG. 07.

The non-characterized signal parameters of a relatively slow in time invariant Gaussian communication channel (from one node to another communication node) of any wireline communication, allows a new optimum way of recovering the signal parameters as to consider the combination of the trellis encoder (FEC--Forward Error Correction) and the channel as on large finite-state machine. The combination of advance and adaptive precoder equalization, Trellis Coding Modulation and Channel Shaping schemes allows us to take advantage of non-characterized channel samples during Symbol Detection, Error Correction and filtering processing of the front-end receiver. This new scheme results in increased Signal to Noise Ratio or SNR and is called "DCA" or Decision Channel Adaptation (Channel Adaptive Equalization). This is described below. A difference between a wireline channel and a wireless channel "DCA" is that in the wireless channel, the channel is estimated for every sending frame or burst while the channel impulse response measurement for wireline channel is refreshed periodically.

To characterize the communication channel and signal parameters distortion over a channel allows new way of controlling and recovering the sending signal symbols as to consider the combination of Precision Network Synchronization, Channel Measurements and Calibration Schemes. These new scheme allow us to take advantage of non characterized and non synchronized channel(s) distortion results in further increased SNR and are called "XFER" and "CMEAS" or "Clock Transfers" and "Channel Measurement & Calibration". They are described in section 2.1.1 and 2.1.2 respectively.

The non-synchronized and un-optimized signal processing of a receiving distorted signal and noise also allows the present invention to take advantage of non-optimized noisy A/D samples and Symbol samples detection, filtering processing of the front-end receiver. This scheme results in further increased Signal to Noise Ratio or SNR and is called "DPIC" or Decision Precursor Intersymbol Interference Canceller, as illustrated in FIG. 08.

The synchronized transmitted signals over multiple media or communication channels exhibits a cyclostationary noise and cross-talk characterization that allows new advance and adaptive equalization scheme to further enhanced the SNR. This new advance and adaptive equalization which take advantage of pseudo-synchronized receiving signals (vector) over multiple media or channels simultaneously, is called "FS-DPIC" or Fractional Space Linear Equalization with DPIC. It is described in section
1.0. The section also described the vector equalization processing for removing multi-path of the wireless channel.

The non-synchronized phase plane controls the baseband signal processing of a receiving distorted signal and noise also allows new advance multi-channel signal coding scheme to take advantage of non-optimized and non-synchronized phase offset controls Symbol samples detection processing of the front-end receiver. This scheme results in further increased data bits per hertz or Bps/Hz. This new advance signal coding scheme which takes advantage of synchronized controls of Phase Signal Space of receiving signals (vector) over multiple media or channels simultaneously and is called "MSC" or Multi-Channel Signal Coding and is described below. Com2000.TM. Intelligent (Modem)--Multi-Channel Signal Coding technology allows higher data rates to be delivered in a unique way from a single continuous or burst streams carrier frequency. The technology delivers multi-channel (phase division) network architecture that uses parallel bitstream in a novel way. It uses the non-complex or complex base band synmmetry signal with phase division multiplex coding scheme or PDM to deliver the multi-channel requirements, as illustrated in FIG. 03.

As an example of the equivalent multi-channel optical networks based on wavelength division multiplexing (WDM), the phase domain's multi-channel wireline and wireless network utilize the optimal phase division multiplexing (PDM) for multi-channel wireline and wireless network. The Com2000.TM. Intelligent (Modem)--Precision Sampling technology enables to the precision sampling of the signal's parameters or combination of the Time (Multi-Time Slot sampling), Phase (Multi-Channel Phase sampling) and Frequency (Multi-Carrer sampling) signal spaces. The non-synchronized in time, frequency and phase signal plane controls of the baseband signal processing for the receiving distorted signal and noise also allows new advance multi-channel signal sampling scheme which takes advantage of non-optimized and non-synchronized time, frequency, phase offset controls Symbol samples detection and vector processing over multiple media or channels and is called "PSAM" or

Precision Sampling, which is described below, as illustrated in FIG. 03.

The Com2000.TM. Multi-Channel DPIC capitalize on the synchronous nature of the vector wireless or wireline receiver. Conceptually, each stream of data for each channel in turn is considered to be the desired signal, and the remainder are considered as interferers. The Com2000.TM. Multi-Channel DPIC take advantage of the non-linear alternative approach which is to exploit the signal parameters synchronization inherent in the new synchronous transmit and receiver Com2000.TM. systems. The synchronous signal parameters are carrier, carrier phase, symbol timing, sampling phase synchronous vectors, as illustrated in FIG. 03 and FIG. 08.

As an example of wireless application, using only the symbol timing synchronization, the symbol cancellation as well as linear nulling to perform the detection. Using symbol cancellation, interference from already-detected components of the symbol vector, is subtracted out from the received signal vector, resulting in a modified received vector in which, effectively, fewer interferers are present. This is similar to DFE or Decision Feed back Equalization of DPIC. This technique can be applied any other or to all of the synchronization signal parameters such as Carrier Synchronization, Carrier Phase Synchronization, Sampling Phase Synchronization and others for the simultaneous transmitting signal space in Frequency (FDM,CDMA)), Phase(CDMA), Time(TDMA) and receiving vector signal processing. When one component cancellation or all of the combination of component cancellation are used, the order in which the component for each of the signal state data vector becomes important to the overall performance of the system.

At the Data Layer (Frainer & Media Access), Com2000.TM. technologies, as illustrated in FIG. 07, represents a collection of state-of-the-art characterization and optimization schemes which not only improves the current data communication over any protocols, but also to enables a new information communication structure that enables a multitude of new QoS and controls technologies. The reconfigurable DSP structures of the design to increase speeds and to deliver real-time, robust and deterministic multiple-access, and intelligence transport protocols, which can be used of mapping of legacy protocols. It reflects the concept of reconfigurable and remote-computing internet networking processor applied to future communications so-called software radio/wireless/wireline or web transceiver/intemet processor.

The non-synchronized application & data distribution and processing of the current packet and circuit switching data processing also allows new advance multi-channel and multi-purpose QoS or Quality Service distribution scheme which take advantage of non-optimized and non-synchronized quality service controls, detection and processing over multiple media or channels and is called "QoS-XFER" or QoS Transfers, as illustrated in the FIG. 09.

Circuit-switched for existing telecommunication architecture and packet-switched networks for data communications have very different characteristics. They can both support an integrated service environment, but have different merits in terms of providing various service aspects. With Com2000.TM. Speed, Security and Intelligence Technology, we are architecting, developing and marketing the new "Information Communication System--Internet Networking Processor", as illustrated in FIGS. 02 and 03, at the networking edge environment such as Home Networking, SOHO office, Private Enterprise. This new "Columbus" architecture, stems from Com2000.TM. technology, is a highly integrated networks, which are set out to address and resolve the following networking issues:

1. Com2000.TM. Intelligence technology addresses and resolves the real-time guarantees issues, e.g., bounded end-to-end delay and bounded delay variations (jitter);

2. Com2000.TM. Intelligence technology addresses and resolves the Multicast issues, i.e., sending data from one sender to many receivers;

3. Com2000.TM. Speed technology addresses and resolves the High capacity over any media and any topology;

4. Com2000.TM. Speed & Intelligence technology addresses and resolves the Bandwidth on demand service, i.e., providing a multi-rate service;

5. Com2000.TM. Intelligence technology addresses and resolves the Transaction support, for example support for bursts of messages with short access delay;

6. Com2000.TM. Intelligence technology addresses and resolves different types of traffic with different demands. Traffic in our future network will be both isochronous/asynchronous and distributive/commutative and the services associated with each will be different;

7. Com2000.TM. Intelligence technology addresses and resolves the capability of a network interface which should depend on the level of service assigned to a service access point, not the capacity of the total network;.

8. Com2000.TM. Intelligence technology addresses and resolves the Distributed Intelligence and data switching/routing processing that seamless integrated into the Fiber Optic Backbone;

9. Com2000.TM. Security technology addresses and resolves the Privacy & Security issues of data communication;

10. Com2000.TM. Intelligence technology addresses and resolve the Wireless access support, i.e. mobility;

This detailed section of the paper is divided into 6 subsections. The subsection 1 describes the Universal Speed Technology for the Higher Speed in wireline and wireless. The subsection 2 describes the Universal Wireline Intelligence Technology for any type of services, any type of media and any channel topology adaptations. The subsection 3 describes the Universal Security Technology for any data type of services, any type of media and any channel topology adaptations. The subsection 4
describes the Universal Wireless Intelligence Technology for any type of services, any type of media and any channel topology adaptations. The subsection 5 describes the Universal Network Processor and Communication System from the System Architecture point of view. The subsection 6 describes the Universal Operating System or Environment for Network Processor and Communication System's application from the System Architecture point of view. And the last subsection 7 describes the summary of the current and next generation Com2000.TM. technology.

1. Universal High Speed: Channel Equalization Technology

This subsection of the paper presents a revolutionary Noise Suppression Com2000.TM. Technology that allows much higher data speed over wireline and wireless than is currently available. Com2000.TM. Noise Suppression Technology is applicable to all wireline such as xDSL, Copper Gigabit and Cable Modem Standards, as illustrated in FIG. 01.

A. Increased Wireline Channel Capacity Data-General

In any type of wireline communication channel, there is distortion that can cause errors in data signaling thereby reducing effective throughput. When data is transmitted over a communication channel at a particular signal parameter and characteristics, the signal's characteristics often changes as the signal propagates along the channel. The imperfections in the communication channel tend to reduce the resolution of the data bandwidth of the signal being transmitted across the channel. Furthermore, the data may not be interpreted correctly at the receiving end of the channel if the transmitted signal's characteristics are outside of a defined signal's parameter range.

To illustrate the technical solution of the current problem, we select Copper Gigabit IEEE 802.3ab problem statement as an example.

Performance Analysis of Interference-Suppression Based FSLE/DFE Receiver over Cat5 Cables Technique:

I. Introduction

Interference (echo and crosstalk) is one of the major performance-liniting impairments on UTP cables. In this note, we consider various receiver structures suitable to the transmission of Gigabit Ethernet over 4 UTP cables. In particular, we examine the performance of a receiver structure using a cascade of FSLE and DFE for interference suppression. Our investigation is also based on the assumption that the interference can be cyclostationary, i.e., interference statistics are periodic with period equal to a symbol interval. This property can result if all transmitter symbol timing clocks are synchronized in frequency.

Suppression of cyclostationary interference by linear equalizers has been considered in [1]. The more general case of multiple channel outputs has been investigated in [2-5]. It was pointed out that linear processing of cyclostationary interfering signals can exploit spectral correlation properties peculiar to these signals.

In Section II, we describe the channel characteristics and modeling. In Section III, we present the different receiver structures suitable to the transmission of Gigabit Ethernet over 4 cat-5 UTP cables. In Section IV, we present the analytical model for the cascaded FSLE/DFE receiver structure using interference suppression approach and its performance analysis. Numerical results on the SNR and numbers of taps required for the FSLE and DFE are discussed in Section V.

II. Channel Characteristics and Modeling

The two major causes of performance degradation for transceivers operating over UTP wiring are propagation loss and crosstalk generated between pairs, as shown in FIG. 10 [6]. As shown in FIG. 10, each UTP support a 250 Mb/s full-duplex channel using a 5-level 125 Mbaud transmission scheme. Consider the transmission on pair#1. With respect to the Receiver #1L on the left, its wanted signal is sent by the Transmitter #1R on the right. The transmitter #1L on the left sends a signal to the Receiver #1R on the right, but also generates spurious signal (called echo) to its own Receiver#1L on the left. The interference signals generated by Transmitters 2L-4L on the left appear at the input of the Receiver #1L are called near-end crosstalk (NEXT) interferers, NEXT_21 to NEXT_41. The interference signals generated by Transmitters 2R-4R on the right appear at the input of the Receiver #1L are called far-end crosstalk (FEXT) interferers, FEXT_21 to FEXT_41.

A. Propagation Loss:

The models for the propagation loss of a loop that are presented in this section are valid for frequencies that are larger than about 500 kHz. The signals considered in this paper have a very small amount of energy below this frequency. Thus, for simplicity, we will assume that the propagation loss models discussed here are valid at all frequencies.

The transfer function H(d,f) of a perfectly terminated loop with length d can be written as follows

where .gamma. (f) is the propagation constant, .alpha.(f) is the attenuation constant, and, .beta.(f) is the phase constant. The quantity that is usually specified in practice is the propagation loss for a given cable length (e.g., d=100
meters). The propagation loss (or insertion loss) limit L.sub.p (f) for category 5 (cat-5) 100 m cable is a positive quantity expressed in dB ##EQU1##

The plot of the suggested 3 dB and 10 dB designs relative to the residual Echo, NEXT and FEXT noise are shown in FIGS. 11a and 11b. The Plot of the propagation loss limit for cat-5, 100 m cable and the cable impulse response are shown in FIGS.
12a and b, respectively.

B. ECHO Loss:

The Echo loss is indicated by the return loss. FIG. 13 shows the plot of the measured return loss and the return loss limit which is 15 dB for frequency from 1 to 20 MHz and 15-10 log (f/20) for frequency from 20 to 100 MHz.

C. NEXT Loss:

The wavy curves in FIG. 4 give the measured pair-to-pair NEXT loss characteristics for three different combinations of twisted pairs in 100 m cat-5 cables. The existence of the minima (small loss) and maxima (large loss) in these curves is due to the fact that the frequencies considered here correspond to wavelengths that are in the same length range as the distance between points of unbalance in the NEXT coupling path. Notice that the minima and maxima usually occur at different frequencies for the three pair combinations. Notice also that the NEXT loss corresponding to the minima decreases with increasing frequency and tends to follow the smooth dotted curve on the bottom in the figure, which is defmed as the worst-case pair-to-pair NEXT loss (or NEXT loss limit) as a function of frequency. The worst-case TIA/EIA-568-A NEXT loss model shown in FIG. 14 is 27.1-16.8log(f/100) in dB.

D. FEXT Loss:

FIG. 16 shows the channel model including the effects of partial response, DAC and hybrid filtering in the transmitter, the main and coupling channel characteristics, and the filtering in the receiver front-end. The DAC and hybrid filtering is represented by the cascade of two identical first-order Butterworth sections with a comer frequency of 180 MHz. This introduces a 4 ns rise/fall time. The receiver front-end is modelled as a fifth-order Butterworth filter with a corner frequency of 80
MHz. The main channel, echo coupling and NEXT coupling channels are represented by C(.omega.), E(.omega.), N.sub.2 (.omega.), N.sub.3 (.omega.), and N.sub.4 (.omega.), respectively. The models for the FEXT's are similar to those of the NEXTs except the coupling channels will be F.sub.2 (.omega.), F.sub.3 (.omega.), and F.sub.4 (.omega.), instead of N.sub.2 (.omega.), N.sub.3 (.omega.), and N.sub.4 (.omega.). The pulse responses of the main, echo, NEXT's and FEXT's at the input of the RECEIVER shown in FIG. 16 are shown in FIGS. 17, 18, and 19, respectively.

1) Summary of Wireline Advanced Signal Equalization Techniques

The non-synchronized and un-optimized signal processing of a received distorted signal and noise also allows a new advance and adaptive equalization scheme to take advantage of non-optimized noisy A/D samples and Symbol samples detection, filtering processing of the front-end receiver. This scheme results in further increased Signal to Noise Ratio or SNR and is called "DPIC" or Decision Precursor Intersymbol Interference Canceller. The frequency synchronized transmitted signals over multiple media or communication channels exhibits a cyclostationary noise and cross-talk characterization which allows new advance and adaptive equalization scheme to further enhance the SNR. This new advance and adaptive equalization which takes advantage of frequency, phase pseudo-synchronized receiving signals (vector) over multiple media or channels simultaneously, is called "FS-DPIC" or Fractional Space Linear Equalization with DPIC. The section also descnbes the vector equalization processing for removing multi-path of the wireless channel. Achieving the increased throughput requires the line signal channel to be as noise free as possible. This is accomplished through two methods:

(a) Single DPIC Channel Optimization ("DPIC" )--The method delivers the optimally suppression the noise propagation in the FFE/DFE equalizers by which suppress the residual of white noise errors between the A/D Samples and Symbol Recovery Samples. The method minimize the Precursor ISI errors in a close loop fashion, so that the error between the white correlated noise induced by the Feed Forward filter's coefficient taps from its digital sampling A/D clocking and the white noise induced by the Decision Feed Back filter's coefficient taps from its digital sampling A/D clocking are suppressed;

(b) Symbol or Channel Vector DPIC Processing ("FS-DPIC")--The specific and salient point of our introduced scheme here is to effectively combine the fractionally spaced feed forward equalizer (FSFFE) and decision feedback equalizer (DFE) to suppress the cyclostationary interference and post-cursor ISI with the newly introduced decision precursor ISI canceller (DPIC) to remove the pre-cursor ISI. The method delivers the optimally suppression the residual of cyclostationary interference and ISI errors between the multi-channel A/D Samples and multi-channel Symbol Recovery Samples. The method, which utilizes the receiving channel's carrier phase and delay synchronization feature to control the correlation of the crosstalks and noise in a multi-channel or vector environment. The correlated cross talks and noises between multi-channel behaved as in a cyclic pattern or in a cyclo-stationary fashion. This pattern is further utilized to in minimize the Vector Precursor ISI errors in a close loop fashion. It is done so that the error between the multi-channel residuals of pre ISI correlation noise, which are induced by the Feed Forward filter's coefficient taps from its digital sampling A/D clocking and the multi-channel post ISI correlation noise induced by the Decision Feed Back filter's coefficient taps from its digital sampling A/D clocking are suppressed.

The multi-channel precision synchronization is done from utilizing the channel's characterization and error calibration of channels. The suppression of induced communication channel distortion and signal distortion to more thoroughly characterize the communication channel signal response. The reason, that inter-stream jitter degrades the performance of the ECHO, NEXT Canceller and FFE/DFE filters of the selected channel equalization, because it creates a transient mismatch between the true signal SAMPLES of the ECHO or NEXT Canceller, FFE, DFE impulse responses and the taps of the cancellers for each associated channel. The method such as the Phase Residual Detector Error Vector Measurement or EVM, are used to determine the external ISI coupling and non-linearity of the signal zero-crossings for each of the channel. This is done so that the multi-channel DPIC can be optimized of the ECHO/NEXT/FFE/DFE filters quantization jitter or noise for each perspective channel.

Com2000.TM. Single or Multiple Channel DPIC Equalization Technology is comprised of a set of multiple conventional FFE/DFE filters and delays with a unique combination of multi-stage filtering and Slicer. Every component of the DPIC filter is the conventional. However, the combination of filter taps and delays for each of the multi-stage FFE/DFE, slicer, along with the A/D Samples input and logic paths are defined the algorithm for DPIC.

The Com2000.TM. Single or Multiple Channel DPIC Equalization Technology provides a revolutionary approach involving adaptive filters and algorithms that model the estimated signal and channel responses to optimize signal recovery for improving the signal to noise ratio (SNR) of the Com2000.TM. system. This increased SNR margins allow many applications such as cost reduction of the current standard design or delivery a ultra high-speed data modulation methods that increase the channel capacity and data for every Hz bandwidth of signal frequency.

In this section, we introduce a new Decision Precursor ISI Cancellation Technique for wireline advanced equalization. As an example of the application, we picked 802.ab and HDSL2 to illustrate the performance increase. The new DPIC receiver that can significant improve the performance of the currently proposed receiver structure for the Copper Gigabit Transmission over CAT-5 Cable and HDSL2 transmission over POTs.

We will provide a brief review of the performance of the currently proposed receiver structure for the Gigabit Transmission over CAT-5 Cable, and then introduced the new scheme and its improved performance. We will also discuss the implication and applications of the newly introduced scheme. The results of POT cable application for HDSL2 also illustrated.

2) Detailed Method Steps of Interference Suppression ("FSFFE")

Reliable duplex operation at 250 Mb/s over two pairs of a CAT-5 UTP cable requires the usage of some kind of technique to combat interference including echo, NEXT and FEXT. Since the FEXT has a small contribution in interference level, we can neglect FEXT's and focus on the echo and NEXT's. Since the transmission on all four pairs uses the same Tx clock, the crosstalk can be shown to be cyclostationary, i.e., crosstalk statistics are periodic with period equal to a symbol interval. The two techniques that are presently being used are NEXT cancellation and NEXT equalization (or suppression). FIGS. 20a-c show three general receiver structures.

Structures shown in FIGS. 20a and b are based on interference cancellation. A NEXT canceller synthesizes, in an adaptive fashion, a replica of the NEXT interferer. The interferer is then cancelled out by subtracting the output of the canceller from the signal appearing at the receiver. A NEXT canceller has the same principle of operation as an echo canceller, and all the familiar structures used for echo cancellers can also be used for NEXT cancellers. The cancellers needs to have access to the local transmitters from which they get their input signals. Typically, this input signal is the stream of symbols generated by the transmitter's encoder. In FIG. 10a the output signal of the canceller is subtracted from the received signal immediately after the A/D. With such an approach, the canceller has to generate outputs at the same rate as the sampling rate of the A/D. An alternative is to make the subtraction at the input of the slicer as shown in FIG. b. In this case, the outputs of the canceller need only be generated at the symbol rate.

The FFE (feed-forward equalizer) in FIGS. 20a and b can be a symbol-spaced (SS) or fractionally spaced (FS) FFE or an analog equalizer. It is used to equalize the precursor ISI. The DFE is used to remove the post cursor ISI. Note that the performance of the DFE is also dependent on the reliability of the symbols detected by the slicer and influenced by the error propagation. For this, one may replace the simple slicer by a sequence detector (such as Viterbi decoder) for a better performance. In that case, the long processing delay of the decoder can be an issue.

With NEXT equalization shown in FIG. 20c , no attempt is made to cancel out the NEXT interferer and there is no need to have access to the transmitter generating the interferer. Rather, what is done is to equalize the interfering NEXT signals at the receiver in such a way that it passes through zero at all the sampling instants of the slicer. In FIG. 10b , the FSFFE or DFE used by the receiver equalizes the desired signal received from the other end of the cable and the echo and NEXT interferers, but in a different fashion. Let f(t) be the impulse response of the in-phase component of the desired signal and r(t) be the impulse response of the in-phase component of the interferer. The conditions for perfectly equalizing the desired signal and interferer in the desired fashion can then be written as f(kT)=.delta.(k) and r(kT)=0 where k is an integer, T is the symbol period, and .delta.(.) is the Dirac delta function, i.e., .delta.(0)=1 and .delta.(k)=0 for k.noteq.0. These conditions also guarantee that the impulse responses of the quadrature component of the far signal and NEXT interferer satisfy f(kT)=r'(kT)=0 for all k. Interference equalization is only feasible if the transceiver uses a large excess bandwidth. Specifically, it can be shown that, with one cyclostationary interferer, these conditions can only be satisfied if the transmitter uses an excess bandwidth of at least 100%. Heuristically, the need for such a large excess bandwidth can be explained as follows. With 0% excess bandwidth, an adaptive equalizer has just enough degrees of freedom to perfectly equalize one signal, but cannot do anything else. In order to equalize two signals, the number of degrees of freedom available to the equalizer has to be doubled with respect to what is required for one signal. This is achieved by doubling the bandwidth of the transmitted signal, which results in an excess bandwidth of 100%. Theoretically, it is possible to perfectly equalize the two interferers, but this requires the usage of an excess bandwidth of 200%, and, in general, perfect equalization of n interferers requires an excess bandwidth of n times 100%. For most applications of bandwidth-efficient digital transmission schemes, the usage of excess bandwidth would be considered as a waste of bandwidth.

IV. Analysis of the Receiver Using Cascaded FSLE/DFE:

FIG. 16 shows the overall system that is used to study the performance of the receiver structure using a FSLE cascaded with a DFE (shown in FIG. 20c) in the presence of interference (echo and NEXTs), ISI, and additive white noise (AWN). The AWN has power spectral density of N.sub.0 /2. The waveform received by the receiver is: ##EQU2##

where

the first term of r(t) is the desired signal (i.e., sequence to be detected), while the second term represent N interferers, and n(t) is the AWN at the input of the FFE.

0.ltoreq..OMEGA..sub.1.ltoreq.T is the Ith interferer's delay. .PHI..sub.0 (t) is the overall end-to-end pulse response (e.g., FIG. 17), and .PHI..sub.1 (t) is the pair-to-pair pulse response of the Ith interferer (e.g., FIGS. 18-19).

a.sub.k is the transmitted symbol, b.sub.k1 is the interfering symbol. It is assumed that:

1) all a.sub.k and b.sub.k1 are uncorrelated;

2) E(a.sub.k)=0; E(a.sub.k.sup.2)=1;

3) E(b.sub.k1)=0; E(b.sub.k1.sup.2)=1; and

4) there are no decision errors (i.e., practically negligible).

The input to the slicer (in FIG. 20c) is ##EQU3##

where .theta. is the sampling phase representing time shift in a symbol period, D=T/M is the delay element used in the FFE (M=1 for symbol-spaced FFE and M>1 for fractionally spaced FFE). W.sub.m 's and f.sub.m 's are the tap settings of the FFE and DFE, respectively, and p is the delay in the receiver's decision relative to the receiver's input. The FFE and DFE coefficients are optimized to minimize the mean squared error (MSE), where the error is:

and includes interference, ISI, and AWN.

Equation (2) for the output of the slicer can be expressed as: ##EQU4##

where T is the transpose operator: ##EQU5##

The MSE we need to minimize is:

where A=E [X.sub.n X.sub.n.sup.T ], and V=E [X.sub.n a.sub.n-p ].

Setting the derivative of the MSE to zero, we find the optimum weight of the forward and feedback coefficients, which is:

and the corresponding minimum MSE is

where V and A are obtained by taking expectations, using (4): ##EQU6## ##EQU7##

This matrix A could be written as ##EQU8##

where A.sub.1 =E(R.sub.n R.sub.n.sup.T), A2=E(R.sub.n a.sup.T.sub.n-1-p), and I is the identity matrix.

Under our assumptions, we find that A.sub.2 =[x.sub.i,j ], where

and A.sub.1 =[q(i,j)], where ##EQU9##

R(t) is the autocorrelation function of the power spectral density of AWN at the output of the receiver filter.

Note that for stationary interference with power spectrum equal to that of the cyclostationary interference, the results are the same except the q(i, j) term becomes: ##EQU10##

V. Numerical Results and Discussions

The above model and analysis are used with pulse shapes shown in FIGS. 17-19 to compute the SNR at the slicer input for different values of taps and D.

We assume a small contribution of AWGN, i.e. in the absence of NEXT, the receiver signal-to-noise ratio is about 60 dB The choice of a low AWN level ensures that crosstalk is the dominant additive impairment.

The performance measure used in the evaluations of this and the next section is output SNR, defined as SNR=10*log.sub.10 (1/MSE) where the mean squared error (MSE) expression is shown by Equation (7) above. Thus, the transmitted data symbol levels are normalized so as to have unit variance. Note that we do not address the problem of error propagation in the DFE.

With the above channel models, SNR, maximized with respect to receiver sampling phase, has been evaluated for two interferers for various numbers of DFE feedforward and feedback tap coefficients. Preliminary results on the SNR performance as a function of receiver sampling phase are summarized in FIGS. 21 and 22. In these figures,

NT is the span of the FFE in terms of the number of symbol intervals, and D is the delay element used in the FFE. Hence, the number of taps of the FFE is given by the product of (NT)(T/D); and

NF is the number of DFE taps.

As shown in FIG. 21, for the case of symbol-spaced FFE (i.e., D=T), the SNR is quite sensitive to the sampling phase with a variation of 6 dB. With a proper choice of sampling phase we can achieve an SNR of 27.36 dB. It also indicates that with a symbol-spaced FFE (i.e., D=T), the increase in NT from 16 to 32 does not make any noticeable improvement in SNR. In other words, NT=16 is sufficient.

For the case of fractionally spaced FFE (i.e., D=T/M with M>1), we can make the following observations:

The SNR is very much less sensitive to the sampling phase.

For NT>5, increasing NT from 6 to 32 introduces an increase in SNR of around 2.5 dB. As NT increases, the SNR increase get smaller and smaller. An SNR of 30 dB is achievable.

With NF=20, changing D=T/2 to D/4 will not provide a noticeable increase in SNR.

For NT=16 or larger, increasing NF from 20 to 80 does not provide a noticeable increase in SNR.

The results indicates that combinations of NF=20, NT=16 and D=T or T/2 is the good choices:

The combination of NF=20, NT=16 and D=T with a proper sampling provides an SNR of 27.36 dB with symnbol-spaced 16-tap FFE and

The combination of NF=20, NT=16 and D=T/2 can achieve an SNR of 29.63 dB with a fractionally space 32-tap FFE, i.e. an increase of 2.27 dB in SNR at the expense of doubling the sampling rate and number of FFE taps.

Numerical Results Used in FIGS. 21-22

NT = 2, NT = 4, NT = 6, NT = 8, NT = 10, NT = 12, NT = 14, NT = 16, sampl'g NF = 20, NF = 20, NF = 20, NF = 20, NF = 20, NF = 20, NF = 20, NF = 20, time D = T/2 D = T/2 D = T/2 D = T/2 D = T/2 D = T/2 D = T/2 D = T/2 0 1.85 24.80 27.58
27.97 28.56 29.23 29.28 29.63 2 1.79 25.19 27.55 27.94 28.54 29.24 29.27 29.62 4 1.78 25.70 27.53 27.92 28.51 29.17 29.28 29.54 6 1.83 26.19 27.54 28.00 28.49 29.06 29.25 29.44 8 1.93 26.44 27.57 28.13 28.55 29.00 29.15 29.36 10 2.77 26.50
27.57 28.19 28.64 28.94 29.03 29.28 12 5.96 26.53 27.58 28.24 28.72 28.91 28.99 29.23 14 10.02 26.58 27.62 28.30 28.82 28.97 29.08 29.29 NT = 16, NT = 16, NT = 16, NT = 16, NT = 16, NT = 32, NT = 32, sampl'g NF = 40, NF = 60, NF = 80, NF = 20, NF = 20, NF = 20, NF = 20, time D = T/2 D = T/2 D = T/2 D = T D = T/4 D = T D = T/2 0 29.75 29.87 29.91 26.38 29.70 26.60 30.61 2 29.73 29.84 29.88 24.43 29.66 24.64 30.57 4 29.64 29.75 29.79 22.65 29.76 22.86 30.47 6 29.54 29.66 29.71 21.29 29.76
21.49 30.34 8 29.47 29.61 29.66 21.32 29.76 21.50 30.22 10 29.40 29.55 29.62 23.74 29.75 23.91 30.10 12 29.36 29.54 29.61 26.43 29.93 26.59 30.07 14 29.42 29.60 29.67 27.36 29.91 27.54 30.17

The above results assume cyclostationary or synchronized interferers. We also investigated the performance in case of stationary interferers when the delays of various interferers are uniformly distributed. As shown in FIG. 23, by using FSLE, the obtained SNR is worse than that in the case of cyclostationary interferers by more than 3 dB for 2 interferers. For 4 interferers, it is expected to have 6 dB worse in SNR.

From the obtained results, we can conclude that the proposed receiver structure using a fractionally spaced FFE combined with a DFE can be used to suppress the NEXT's. It has a simpler structure than the receiver using NEXT cancellers. Compared to the proposed receiver structure shown in FIG. 20c , FIG. 20a or b requires 4 additional cancellers. It is also noted that the proposed receiver in FIG. 20c can suppress the FEXT's.

The following references are incorporated by reference herein in their entirety:

1. E. Biglieri, M. Elia, and L. LoPresti, "The optimal linear receiving filter for digital transmission over nonlinear channels," IEEE Trans. Inform. Theory, vol. 35, no. 3, pp. 620-625, May 1989;

2. W. VanEtten, "An optimal linear receiver for multiple channel digital transmission systems," IEEE Trans. Commun., pp. 828-834, August 1975;

3. J. Salz, "Digital transmission over cross-coupled linear channels," AT&T Tech. J., vol. 64, no. 6, pp. 1147-1159, August 1985;

4. P. Crespo, M. L. Honig, and K. Steiglitz, "Suppression of near- and far-end crosstalk by linear pre- and post-filtering," IEEE JSAC, pp. 614-629, April 1992; and

5. M. Abdulrahman, D. D. Falconer, "Cyclostationary Crosstalk Suppression by Decision Feedback Equalization on Digital Subscriber Loops", IEEE JSAC, pp. 640-649, April 1992.

3) Detailed Method Steps of Decision Precursor ISI ("DPIC") Cancellation

In this Section of the paper, we introduce a new Decision Precursor ISI Cancellation Technique that can significant improve the performance of the currently proposed receiver structure for the Gigabit Transmission over CAT-5 Cable.

We will provide a brief review of the performance of the currently proposed receiver structure for the Gigabit Transmission over CAT-5 Cable, and then introduced the new scheme and its improved performance. We will also discuss the implication and applications of the newly introduced scheme.

2. Background:

Currently, the proposed structure of the receiver prior to the 4D-TCM Viterbi decoder consists of 4 paths and each path includes:

one M-tap Symbol-Spaced (SS) Feedforward Equalizer (FFE) to remove the precursor ISI,

one N-tap Decision Feedback Equalizer (DFE) to remove the post-cursor ISI,

one E-tap Echo Canceller to eliminate the echo interference, and

three X-tap NEXT Cancellers to eliminate the NEXT interferers as shown in FIG. 24.

Including the coding gain of 6 dB from the 4D-TCM Viterbi Decoder, calculations have been made to achieve 3 dB and 10 dB margins and a target output SNR of 16.2 dB for a BER=1E-10. For convenience, we will call the corresponding 3 dB-margin and
10 dB-margin designs Scheme PL (Proposed structure with Low complexity) and Scheme PH (Proposed structure with High complexity), respectively. Their structures and numbers of taps are:

SCHEME PL: ONE 50-TAP ECHO CANCELLER, THREE 12-TAP NEXT CANCELLERS, SYMBOL-SPACED 12-TAP FFE, AND 10-TAP DFE (and ADC with effective 48 levels).

SCHEME PH: ONE 121-TAP ECHO CANCELLER, THREE 72-TAP NEXT CANCELLERS, SYMBOL-SPACED 16-TAP FFE, AND 12-TAP DFE (and ADC with effective 96 levels).

Note that study was done with the assumption that the FEXT's are neglected. The margin was expected to be adequate for FEXT's. Therefore, in the presence of 3 FEXT's, the margins provided by Schemes PL and PH are reduced. It is noted that Scheme PL has a much lower complexity than Scheme PH (a total saving of 71 echo canceller taps, 180 NEXT taps, 4 FFE taps and 2 DFE taps per path). FIG. 25 shows the plots of the margin including 6 dB coding gain when FEXT's are present. It indicates that Scheme PL is not acceptable due to the insufficient margin (i.e., shown as negative margin) while the margin of Scheme PH varies between 1.5 dB to 4.5 dB dependent on the sampling phase. This can be marginal in practice.

3. Decision Precursor ISI Cancellation Technique:

An investigation of the contribution of interferers shows the following distribution of equivalent RMS voltages of the interference at the receiver input: 104 mV for ISI, 35.5 mV for Echo, 4.5 mV for total NEXT and 3.1 mV for total FEXT. It indicates a large value of ISI. The Symbol-Spaced Feedforward Equalizer is supposed to remove the precursor ISI. However, it works with samples (not detected symbols) and samples contain noise (predominantly quantization noise). Therefore, the Symbol-Spaced Feedforward Equalizer is not so effective in removing the precursor ISI. In other words, there is a substantial level of residual precursor ISI at the input to the Slicer and it reduces the output SNR.

To improve further the output SNR we propose the new decision precursor ISI cancellation technique.

FIG. 26 shows the position of the newly introduced Decision Precursor ISI Canceller (DPIC). The DPIC makes use of the D detected symbols from the output of the Slicer to estimate the precursor ISI which still exists at the input sample of the Slicer. The estimation of the residual ISI value is done by a D-tap Finite Impulse Filter (FIR). This D-tap FIR has the same structure as the DFE or the Echo or NEXT canceller except the values of the coefficients. Since it calculates, A D-symbol delay element is used to keep the DT-delayed sample, from which the corresponding residual precursor ISI computed by the D-tap FIR is removed.

The DPIC has a simple structure with D-symbol delay (or a memory of D locations) and a D-tap FIR. The value of D is small. We consider a DPIC with D=10 or 12 in the following schemes:

SCHEME IL: ONE 50-TAP ECHO CANCELLER, THREE 12-TAP NEXT CANCELLERS, SYMBOL-SPACED 12-TAP PFE, 10-TAP DFE(and ADC with effective 48 levels) and ONE 10-TAP DECISION PRECURSOR ISI CANCELLER. (i.e., SCHEME PL with DPIC)

SCHEME IH: ONE 121-TAP ECHO CANCELLER, THREE 72-TAP NEXT CANCELLERS, SYMBOL-SPACED 16-TAP FFE, 12-TAP DFE (and ADC with effective 96 levels), and ONE 12-TAP DECISION PRECURSOR ISI CANCELLER. (i.e., SCHEME PH with DPIC)

It can be seen that Schemes IL and IH are actually the improved versions of Schemes PL one 10-tap DPIC and PH with one 12-tap DPIC, respectively.

FIG. 25 shows the performance of Schemes IL and IH as compared to Schemes PL and PH. We observe from FIG. 25 the following:

The performance of both new Schemes IL and IH is robust, insensitive to the sampling phase.

Both new Schemes IL and IH provide positive margins.

The new Scheme IL provides a margin of 4 dB while the currently proposed Scheme PH has a worse performance than new Scheme IL except for the timing phases of 10T/16 to 15T/16 where Scheme PH is better by at most 0.5 dB. Note that the complexity of currently proposed Scheme PH is much higher than that new Scheme IL as shown in Table 1 (3 times).

The new Scheme IH provides a large margin of 8 dB (including 6 dB from the 4D-TCM Viterbi Decoder) or a performance improvement of 4 dB over the currently proposed design. This implies that without 4D-TCM and complex Viterbi Decoder, the new Scheme IH still provide 2 dB margin. In other words,

the 4D-TCM and complex Viterbi Decoder can be dropped for cost and simplicity, or

the new DPIC technique can be used in conjunction with 4D-TCM and complex Viterbi Decoder for high performance and longer distance, or higher capacity.

TABLE 1 Complexity of PL, PH, IL, and IH currently currently new, new, proposed proposed improved improved Scheme PL Scheme PH Scheme IL Scheme IH Echo Canceller 50 taps 121 taps 50 taps 121 taps (using symbols): NEXT 3 .times. 12 taps 3
.times. 72 taps 3 .times. 12 taps 3 .times. 72 taps Cancellers (using symbols): FFE (using 12 taps 16 taps 12 taps 16 taps samples): DFE 10 taps 12 taps 10 taps 12 taps (using symbols): DPIC 10 taps 12 taps (using symbols): Delay element 10
locations 12 locations Total no. of 96 taps 349 taps 106 taps 361 taps taps using symbols: Total no. of 12 taps 16 taps 12 taps 16 taps taps using samples: TOTAL NO. 106 taps 361 taps 116 taps 371 taps OF TAPS:

4) Detailed Method Steps of the Combination ("DPIC-FSFFE")

DPIC can be used with FFE (Fractionally Spaced or Symbol Spaced) plus DFE plus Echo Canceller to obtain an excellent performance without NEXT Cancellers as shown in FIG. 27 below.

We consider 3 more schemes, ILE(T), IHE(T) and IHE(T/2) using the structure shown in FIG. 27. ILE(T) and IHE(T) use a Symbol-Spaced FFE while IHE(T/2) use a Fractionally Spaced T/2-FFE. The numbers of taps and complexity of these schemes for the Gigabit receiver are summarized in Table 2 below

TABLE 2 Complexity of various schemes CURRENTLY OUR SCHEMES WITH OUR SCHEMES WITHOUT PROPOSED NEXT CANCELLERS NEXT CANCELLERS PL PH IL IH ILE(T) IHE(T) IHE(T/2) Echo Canceller (using 50 taps 121 taps 50 taps 121 taps 50 taps 121 taps
121 taps symbols): NEXT Cancellers (using 3 .times. 12 taps 3 .times. 72 taps 3 .times. 12 taps 3 .times. 72 taps symbols): FEE (using samples): 12 taps 16 taps 12 taps 16 taps 12 taps 16 taps 32 taps DFE (using symbols): 10 taps 12 taps 10 taps
12 taps 10 taps 12 taps 12 taps DPIC (using symbols): 10 taps 12 taps 10 taps 12 taps 12 taps Delay element: 10 12 10 12 12 locations locations locations locations locations Total no. of taps using 96 taps 349 taps 106 taps 361 taps 70 taps 145
taps 145 taps symbols: Total no. of taps using 12 taps 16 taps 12 taps 16 taps 12 taps 16 taps 32 taps samples:

The performance in terms of margin (including the 6 dB from the Viterbi decoder is shown below:

MARGIN [dB] PL IL PH IH ILE(T) IHE(T) IHE(T/2) 6 0.59 3.94 4.00 7.83 3.47 6.56 7.84 2 -0.03 3.89 3.35 7.80 3.37 6.49 7.88 4 -0.93 3.84 2.40 7.78 3.31 6.45 7.91 6 -1.55 3.83 1.49 7.80 3.30 6.48 7.93 8 -0.53 3.87 2.66 7.87 3.35 6.55 7.95 10
0.45 3.93 3.99 7.94 3.45 6.67 7.96 12 0.86 3.97 4.40 7.99 3.54 6.78 7.97 14 0.89 3.97 4.38 7.99 3.55 6.81 7.98

FIG. 28 indicates the best performance with a margin (including Viterbi decoder) of 8 dB offered by our introduced schemes IH and IHE(T/2). From Table 2, Scheme IHE(T/2) only needs 145 "symbol" taps and 32 "sample" taps. The number of "symbol" taps is about 1.4 times larger than that of Scheme IL and still less than 0.5 that of the currently proposed scheme PH. Scheme IHET/2) needs a 32-tap T/2-spaced FFE operating at twice the symbol rate. Compared to IHE(T/2), the performance of IHE(T) is about 1 dB worse. However, Scheme IHE(T) uses a 16-tap Symbol-Spaced FFE operating at the symbol rate as the currently proposed PH. Scheme IHE(T) provides a significant improvement in both performance and complexity as compared to the currently proposed scheme PH (called "10 dB margin design): 2.4 dB better in performance and 42% of the complexity.

5) Detailed Method Steps of the "DPIC-FSFFE" on HDSL2

This application disclosed some of the potential applications of the DPIC to xDSL (Digital Subscribed Loop) to enhance the transmission performance without affecting the proposed coding standards. For illustrative purposes, the HDSL and SHDSL (or HDSL2) are used in the following discussions.

HDSL is an extension of DSL based on the same 2B1Q baseband line coding to provide 2-pair repeaterless T1/E1 symmetric service. The transmission throughput improvement of HDSL over DSL is due to shorter CSA (Carrier Serving Area) operation range instead of that defined by all non-loaded loops.

The critical issues were that the required performance would include a BER of 1E-7 and that the margin used in theoretical and simulation studies would be 12 dB, while the margin on a measured piece of equipment need only be 6 dB. The crosstalk model has a NEXT loss of about 57 dB at 80 kHz and decreases at about 15 dB per decade for frequencies above about 20 kHz.

Early study results indicated that single-pair HDSLs using modified basic access technology would have a range of about a mile, or 5.3 kft at 1.544 Mb/s. At 800 kb/s, it performs satisfactorily on most CSA loops, but would have only 6 dB (theoretical) margin on the lossiest loop in a population of CSA loops. IT was found that performance is not enhanced by increasing the length of the symbol-spaced feedforward equalizer (in a configuration using DFE) more than 9.

Measured results indicated a margin of 3.7 dB on a 12 kft, 24-AWG loop for a full-duplex 772 kb/s system using 2B1Q. Margins of greater than 6 dB on some CSA loops for a half DS1 rate 2-pair simplex system with simulated crosstalk noise were achieved.

Study for single-pair HDSL (SHDSL) was proposed by Metalink at the June 95 T1E1.4 meeting based on the claim that a 6 dB margin could be achieved with coded 16PAM on 5 CSA test loops for 10.6 kft/24-AWG and 7.7 kft/26-AWG. Coded 64-CAP can also provide a slightly shorter distance.

On CSA 12 kft 24-AWG loop, coded 16PAM and coded 64QAM offer a margin of 3.1 dB and 2.9 dB, respectively. On CSA 9 kft 26-AWG, both coding schemes provide only 1.9 dB of margin.

At the December 1997 T1E1.4 meetings, the basics of an HDSL2 standard were agreed and include the following recommendations

Performance margin of 5 dB on all CSA loops (measured by increasing the crosstalk noise until a BER of 1E-7 is reached).

Use of asymmetrical Tx power spectrum OP'NS (Overlapped PAM Transmission with Interlocking Spectra)

Use of a progranmnable encoder for rate-3/4, 512-state trellis codes for 5.1 dB of coding gain.

FIG. 29 shows the currently proposed transceiver structure for SHDSL. The symbol timing recovery is not shown in this figure. The receiver includes a 20-tap fractionally spaced (T/2) equalizer, an 128-tap DFE and an 165-tap symbol-spaced echo canceller.

As discussed above, the performance margin is very tight and a rate 3/4 512-state Trellis Code is used in order to provide 5.1 dB of coding gain required for a proper operation. It is therefore desired to enhance the transceiver performance so that a larger margin can be provided. Additional margin can be used to increase the range (distance) or Tx rate. FIG. 30 shows the proposed transceiver structure using DPIC.

Preliminary analysis shows an improvement of 3 dB in performance margin can be achieved. Further improvement is possible and under study. Schemes IHE(T) or IHE(T/2) are applicable to xDSL to improve the performance of the current xDSL. Especially, the Scheme IHE(T/2) use a Fractionally Spaced FFE to suppress the NEXT's and FEXT's as NEXT and FEXT cancellation is not possible in the environment of xDSL. The specific and salient point of our introduced scheme here is to effectively combine the fractionally spaced feed forward equalizer (FSFFE) and decision feedback equalizer (DFE) to suppress the cyclostationary interference and post-cursor ISI with the newly introduced decision precursor ISI canceller (DPIC) to remove the pre-cursor ISI.

HDSL2 Simulation Results

These results present an SNR evaluation of a uncoded HDSL2 using some enhanced equalization technique.

Data and parameters: We used the data and parameters provided by a member of T1E1 Standard Committee. -140 dBm/Hz background, 26AWG cable @9000 ft.

Assumptions: For a quick analysis, we considered the uncoded HDSL2, i.e., using PAM8 at 1.544 Mbps, in our study of three following cases:

Ideal--Case 1: Rx with infinite-length DFE f