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United States Patent
6369855
Chauvel , ; et al.
April 9, 2002
Title
Audio and video decoder circuit and system
Abstract
An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
Inventors:
Chauvel; Gerard
(Antibes,
FR
)
, Lasserre; Serge
(Frejus,
FR
)
, Giani; Mario
(Cagnes sur Mer,
FR
)
, Spits; Tiemen
(North Richland Hills,
TX
)
, Benbassat; Gerard
(St-Paul-de-Vence,
FR
)
, Laczko, Sr.; Frank L.
(Allen,
TX
)
, Chiang; Y. Paul
(Richardson,
TX
)
, Walker; Karen L.
(Topeka,
KS
)
, Paley; Mark E.
(Dallas,
TX
)
, Chae; Brian O.
(Plano,
TX
)
Assignee:
Texas Instruments Incorporated
(Dallas,
TX
)
Appl. No.:
962514
Filed:
October 31, 1997
Current U.S. Class:
348/423.1
348/558
370/474
Field of Search:
370/474 348/558,553,423,461,569,564,423.1
U.S. Patent Documents
4962427
October 1990
Lunn et al.
5668601
September 1997
Okada et al.
5686965
November 1997
Auld
5689509
November 1997
Gaytan et al.
5712853
January 1998
Mathur et al.
5745488
April 1998
Thompson et al.
5781549
July 1998
Dai
5784277
July 1998
Meyer
5796743
August 1998
Bunting et al.
Primary Examiner:
Kostak; Victor R.
Attorney, Agent or Firm:
Laws; Gerald E. Brady, III; W. James Telecky, Jr.; Frederick J.
Parent Case Text
CROSS-REFERENCE TO INCORPORATED PROVISIONAL APPLICATIONS
Provisional Application Ser. Nos. 60,030,107, 60/030,106, 60/030,105, 60/030,104, 60/030,108 and 60/029,923, all filed Nov. 1, 1996; and application Ser. No. 08/691,731, filed Aug. 2, 1996; are incorporated herein by reference. All of the foregoing applications have a common Assignee.
This application claims priority under 35 USC .sctn.119(e)(1) of Provisional Application Numbers: Ser. Nos. 60,030,107, 60/030,106, 60/030,105, 60/030,104, 60/030,108 and 60/029,923, all filed Nov. 1, 1996.
Claims
What is claimed is:
1. A video and audio decoder system, comprising:
a packet parser for receiving a digital data stream;
a first memory for storing program instructions;
a second memory for storing data;
an address bus coupled to said first and second memory;
a data bus coupled to said first and second memory;
an audio decoder for decoding selected audio portions of said digital data stream and providing an audio output;
a video decoder for decoding selected video portions of said digital data stream;
an NTSC/PAL encoder coupled to said video decoder for providing a video output;
a coprocessor coupled to said video decoder and NTSC/PAL encoder for processing selected OSD portions of said digital data stream;
a controller coupled to said coprocessor, video decoder, audio decoder, address bus, data bus, and packet parser for moving selected portions of said data stream therebetween; and
a central processing unit coupled to said address and data bus for processing selected portions of said data stream.
2. An integrated circuit, comprising:
a transport packet parsing circuit for receiving a transport data packet stream,
a central processing unit for initializing said integrated circuit and for processing portions of said data packet stream,
a ROM circuit for storing data,
a RAM circuit for storing data,
an audio decoder circuit for decoding audio portions of said data packet stream,
a video decoder circuit for decoding video portions of said data packet stream,
an NTSC/PAL encoding circuit for encoding video portions of said data packet stream,
an OSD coprocessor circuit for processing OSD portions of said data packets,
a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit,
an extension bus interface circuit,
a P1394 interface circuit,
a communication coprocessors circuit,
an address bus connected to said circuits, and
a data bus connected to said circuits.
3. A digital television signal receiver capable of receiving multiple signals, with each signal consisting of a set of digital data packets, comprising:
decoding means for decoding the incoming digital signals, adapted to identify said data packets so they can be selected to form trains of packets of the same type and a means for processing said packets adapted so as to generate, from packets of the same type, corresponding analog signals and deliver these analog signals to a device for displaying the video signals and transmitting the audio signals, wherein that the decoding means comprises:
circuitry for extracting a portion of data from each header signal, which is representative of the nature of the corresponding useful signal;
memory for storing reference data, at addresses each corresponding to one packet type; and
comparison circuitry for comparing the piece of data extracted from each header signal with said reference data stored in memory and delivering data representative of an address to a data processing unit indicating the type of packet, wherein said memory and said comparison circuitry consist of an associative memory adapted to ensure the simultaneous comparison of the piece of data extracted from each header signal with the reference data stored in memory.
4. The device of claim 3, wherein the associative memory comprises a network of rows and columns of memory cells each comprising a set of charge transistors for the storage of reference data, and control transistors controlled by an addressing row for the selective connection of said charge transistors to columns for the transmission of said data extracted from the header signal; each memory cell also comprising a set of transistors assembled as a comparator ensuring the comparison between the data present in the columns for the data transmission and the reference data stored in the charge transistors so as to deliver, when a reference byte stored in a memory cell row is identical to a byte present in the data transmission columns, a pairing signal to an address coding system connected to the data processing unit.
5. The device of claim 4, wherein the memory cells are MOS transistor memory cells.
6. The device of claim 3, wherein the associative memory is an associative memory with a storage capacity of 32 bytes of 14 bits.
7. The device of claim 3, further comprising a random-access memory controlled by the data processing unit for successive storage in said random-access memory of data packets of the same type, in a zone corresponding to a preselected packet type.
8. The device of claim 3, further comprising a means for extracting, from each header signal, bits used for the numbering of the packets of the same type, and for supplying these bits to the data processing unit for the selection of the packets.
9. The device of claim 8, wherein the means for extracting said data from each header signal and said bits used for the numbering of the packets consists of circuitry for decoding the header signal of each packet.
10. The device of claim 3, wherein at least one of the sets of digital data packets is a set of digital television signal packets which have been transmitted in series at a speed of approximately 60 Mbps.
11. The device of claim 3, wherein are at least one of the sets of digital data packets is a set of digital television signal packets which have been transmitted in parallel at a speed of approximately 7.5 Mbps.
12. A digital television signal receiver capable of receiving multiple signals, with each signal consisting of a set of digital data packets comprising:
decoding circuitry for decoding the incoming digital signals, adapted to identify said data packets so they can be selected to form trains of packets of the same type and a means for processing said packets adapted so as to generate, from packets of the same type, corresponding analog signals and deliver these analog signals to a device for displaying the video signals and transmitting the audio signals, wherein that the decoding circuitry comprises:
circuitry for extracting a portion of data from each header signal, which is representative of the nature of the corresponding useful signal;
memory for storing reference data, at addresses each corresponding to one packet type; and
comparison circuitry for comparing the piece of data extracted from each header signal with said reference data stored in memory and delivering data representative of an address to a data processing unit indicating the type of packet, wherein said memory and said comparison circuitry comprise an associative memory adapted to ensure the simultaneous comparison of the piece of data extracted from each header signal with the reference data stored in memory.
Description
NOTICE
(C) Copyright 1996 Texas Instruments Incorporated. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
FIELD OF THE INVENTION
This invention generally relates to audio-visual systems and integrated circuits used therein, and more particularly, to improved audio-visual systems and improved integrated circuits used therein.
BACKGROUND OF THE INVENTION
Currently, digital television DSS/DVB signals are transmitted in an MPEG format. In the MPEG format, the signals are transmitted in the form of data packets, with each packet including a useful signal or data and a header signal or data containing information about the contents of the useful signal or data.
Such a digital signal generally consists of packets of various types, such as audio data packets, video data packets and packets containing information pertaining to the program transmitted.
In general, the decoding of such digital signals takes place in a decoder in a reception station, which identifies and selects, in the incoming signals, desired audio and video data packets and then decodes these packets to form data trains, of the audio and video types, respectively. The audio data trains are decoded by means of an audio decoder for forming an analog acoustic signal. Similarly, the video data trains are used to form an image as well as chrominance and luminance signals.
There are known devices for the identification of packets. These devices extract a piece of data from each header signal, which is representative of the type of the corresponding useful signal. They include a means for storing reference data in a memory, at addresses each corresponding to one packet type, and a means for comparing the piece of data extracted from each header signal with said reference data (stored in the memory) then delivering to a data processing unit for further processing, an address signal indicating the nature of the corresponding packet. The processing unit then selects the identified packets for decoding and for forming corresponding data trains.
For this type of identification device, the comparison between the piece of data extracted from the header signal and the reference data stored in memory is conducted successively; that is, at a transition of a synchronization clock, an extracted piece of data is compared to a reference piece of data.
However, since the transmission rate of the packets is very high, the packet being identified must be stored, for example, in a memory of the FIFO type, associated with a piloting circuit and then further processed by the data processing unit.
Consequently, this type of identification device is relatively slow, requires a large number of components, and requires a large amount of memory and/or local storage buffers.
International standardization committees have been working on the specification of the coding methods and transmission formats for several compression algorithms to facilitate world wide interchange of digitally encoded audiovisual data. The Joint Photographic experts Group (JPEG) of the International Standards Organization (ISO) specified an algorithm for compression of still images. The ITU (formerly CCITT) proposed the H.261 standard for video telephony and video conference. The Motion Pictures Experts Group (MPEG) of ISO specified a first standard, MPEG-1, which is used for interactive video and provides a picture quality comparable to VCR quality. MPEG has also specified a second standard, MPEG-2, which provides audiovisual quality of both broadcast TV and HDTV. Because of the wide field of applications MPEG-2 is a family of standards with different profiles and levels.
The JPEG coding scheme could be in principal also used for coding of images sequences, sometimes described as motion JPEG. However, this intraframe coding is not very efficient because the redundancy between successive frames is not exploited. The redundancy between succeeding frames can be reduced by predictive coding. The simplest predictive coding is differential interframe coding where the difference between a current pixel of the present frame and the corresponding pixel of the previous frame is quantized, coded and transmitted. To perform such interframe prediction a frame memory for storing one or more frames is required to allow for this pixel by pixel comparison. Higher efficiency than the simple differential interframe coding can be achieved by a combination of discrete cosine transform (DCT) and interframe prediction. For so-called hybrid coding the interframe difference, which is similar to JPEG, is obtained, DCT coded and then transmitted. In order to have the same prediction at both the receiver and transmitter the decoder is incorporated into the coder. This results in a special feedback structure at the transmitter which avoids coder-decoder divergence.
Variable word length coding results in a variable bit rate which depends on image content, sequence change, etc. Transmission of the coded information over a constant rate channel requires a FIFO buffer at the output to smooth the data rate. The average video rate has to be adjusted to the constant channel rate. This is performed by controlling the quantizer according to the buffer content. If the buffer is nearly full, the quantization is made more sever and thus the coded bitrate is reduced. Conversely, if the buffer is nearly empty, the quantization is relaxed.
In general, the MPEG coding use a special predictive coding strategy. The coding starts with a frame which is not differentially coded; it is called an Intraframe (I). Then prediction is performed for coding one frame out of every M frames. This allows computation of a series of predicted frames (P), while "skipping" M-1 frames between coded frames. Finally, the "skipped" frames are coded in either a forward prediction mode, backward prediction mode, or bi-directional prediction mode. These frames are called bi-directionally interpolated (B) frames. The most efficient prediction mode, in terms of bitrate, is determined by the encoder and its selected mode is associated with the coded data. Thus the decoder can perform the necessary operations in order to reconstruct the image sequence. A main difference between MPEG-1 and MPEG-2 is that MPEG-1 has been optimized for non-interlaced (progressive) format while MPEG-2 is a generic standard for both interlaced and progressive formats. Thus, MPEG-2 includes more sophisticated prediction schemes.
In more detail, motion pictures are provided at thirty frames per second to create the illusion of continuous motion. Since each picture is made up of thousands of pixels, the amount of storage necessary for storing even a short motion sequence is enormous. As higher and higher definitions are desired, the number of pixels in each picture grows also. This means that the frame memory used to store each picture for interframe prediction also grows; current MPEG systems use about 16 megabits (MB) of reference memory for this function. Fortunately, lossy compression techniques have been developed to achieve very high data compression without loss of perceived picture quality by taking advantage of special properties of the human visual system. (A lossy compression technique involves discarding information not essential to achieve the target picture quality to the human visual system). An MPEG decoder is then required to reconstruct in real time or nearly real time every pixel of the stored motion sequence; current MPEG decoders use at least about 16 MB of frame memory for reconstruction of frames using the encoded interframe prediction data.
The MPEG standard specifies both the coded digital representation of video signal for the storage media, and the method for decoding to achieve compatibility between compression and decompression equipment. The standard supports normal speed playback, as well as other play modes of color motion pictures, and reproduction of still pictures. The standard covers the common 525- and 625-line television, personal computer and workstation display formats. The MPEG-1 standard is intended for equipment supporting continuous transfer rate of up to 1.5 Mbits per second, such as compact disks, digital audio tapes, or magnetic hard disks. The MPEG-2 standard supports bit rates from 4 Mbits/sec (Mbits) to 15 Mbits and is targeted for equipment that complies with the International Radio Consultative Committee (CCIR) recommendation 601 (CCIR-601). The MPEG standard is intended to support picture frames at a rate between 24 Hz and 30 Hz. ISO-11171 entitled Coding for Moving Pictures and Associated Audio for digital storage medium at 1.5 Mbit/s, provides the details of the MPEG-1 standard. ISO-13838 entitled Generic Coding of Moving Pictures and Associated Audio provides the details of the MPEG-2 standard.
Under the MPEG standard, the picture frame is divided into a series of "Macroblock slices" (MBS), each MBS containing a number of picture areas (called "macroblocks") each covering an area of 16.times.16 pixels. Each of these picture areas is represented by one or more 8.times.8 matrices which elements are the spatial luminance and chrominance values. In one representation (4:2:2) of the macroblock, a luminance value (Y type) is provided for every pixel in the 16.times.16 pixels picture area (in four 8.times.8 "Y" matrices), and chrominance values of the U and V (i.e., blue and red chrominance) types, each covering the same 16.times.16 picture area, are respectively provided in two 8.times.8 "U" and two 8.times.8 "V" matrices. That is, each
8.times.8 U or V matrix covers an area of 8.times.16 pixels. In another representation (4:2:0), a luminance value is provided for every pixel in the 16.times.16 pixels picture area, and one 8.times.8 matrix for each of the U and V types is provided to represent the chrominance values of the 16.times.16 pixels picture area. A group of four continuous pixels in a 2.times.2 configuration is called a "quad pixel"; hence, the macroblock can also be thought of as comprising 64 quad pixels in an 8.times.8
configuration.
The MPEG standard adopts a model of compression and decompression. Initially, interframe redundancy is first removed from the color motion picture frames. To achieve interframe redundancy removal, each frame is designated either "intra" "predicted" or "interpolated" for coding purpose. Intraframes are least frequently provided, the predicted frames are provided more frequently than the intraframes, and all the remaining frames are interpolated frames. The values of every pixel in an intraframe ("I-picture") is independently provided. In a prediction frame ("P-picture"), only the incremental changes in pixel values from the last I-picture or P-picture are coded. In an interpolation frame ("B-picture"), the pixel values are coded with respect to both an earlier frame and a later frame. Again, large (16 MB) frame or reference memories are required to store frames of video to allow for this type of coding.
The MPEG standard does not require frames to be stored in strict time sequence, so that the intraframe from which a predicted frame is coded can be provided in the picture sequence either earlier or later in time from the predicted frame. By coding frames incrementally, using predicted and interpolated frames, much interframe redundancy can be eliminated which results in tremendous savings in storage requirements. Further, motion of an entire macroblock can be coded by a motion vector, rather than at the pixel level, thereby providing further data compression.
The next steps in compression under the MPEG standard remove intraframe redundancy. In the first step, a 2-dimensional discrete cosine transform (DCT) is performed on each of the 8.times.8 values matrices to map the spatial luminance or chrominance values into the frequency domain.
Next, a process called "quantization" weights each element of the 8.times.8 matrix in accordance with its chrominance or luminance type and its frequency. In an I-picture, the quantization weights are intended to reduce to one many high frequency components to which the human eye is not sensitive. In P- and B- pictures, which contain mostly higher frequency components, the weights are not related to visual perception. Having created many zero elements in the 8.times.8 matrix, each matrix can now be represented without information loss as an ordered list of a "DC" value, and alternating pairs of a non-zero "AC" value and a length of zero elements following the non-zero value. The list is ordered such that the elements of the matrix are presented as if the matrix is read in a zigzag manner (i.e., the elements of a matrix A are read in the order A00, A01, A10, A20, A11, A02, etc.). The representation is space efficient because zero elements are not represented individually.
Finally, an entropy encoding scheme is used to further compress the representations of the DC block coefficients and the AC value-run length pairs using variable length codes. Under the entropy encoding scheme, the more frequently occurring symbols are represented by shorter codes. Further efficiency in storage is thereby achieved.
In decompression, under MPEG, the processes of entropy encoding, quantization and DCT are reversed. The final step, called "absolute pixel generation", provides the actual pixels for reproduction, in accordance to the play mode (forward, reverse, slow motion e.g.), and the physical dimensions and attributes of the display used. Again, large (16 MB) frame or reference memories are required to store frames of video to allow for this type of reproduction.
Since the steps involved in compression (coding) and decompression (decoding), such as illustrated for the MPEG standard discussed above, are very computationally intensive and require large amounts of memory, for such a compression scheme to be practical and widely accepted, the decompression processor must be designed to provide decompression in real time, and allow economical implementation using today's computer or integrated circuit technology.
The purpose of the present invention is to overcome these short-comings and drawbacks. Improvements in circuits, integrated circuit devices, computer systems of all types, and methods to address all the just-mentioned challenges, among others, are desirable, as described herein.
SUMMARY OF THE PRESENT INVENTION
Generally, and in one form of the present invention, an improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
The present invention provides a fully functional decoder using a single 16 Mbit external SDRAM.
The present invention provides a decoder that accepts transport bitstreams up to 40 Mbits per second.
The present invention provides an on-chip DES module for descrambling.
The present invention provides a video decoder that decodes MPEG-1 and MPEG-2 Main Profile and Main Level bitstreams.
The present invention provides an audio decoder that decodes MPEG-1 Layer I and II and MPEG-2 Multichannel bitstreams.
The present invention provides an audio output in both PCM and SPDIF formats.
The present invention provides an OSD processor that enables mixture of OSD and video data with transparent BitBLT hardware that accelerates memory block move.
The present invention provides a 32/16 bit ARM/Thumb processor that removes the need of another CPU in the set-top box.
The present invention provides a firmware that controls device operation and provides application access to hardware resources.
The present invention provides an on-chip NTSC/PAL encoder that incorporates Closed Caption and Video Aspect Ratio Identification Signal encoding and the MacroVision logic for anti-taping protection.
The present invention provides an analog Y, C, and Composite video outputs with 9-bit precision.
The present invention provides an internally or externally generated sync signals.
The present invention provides a digital video component output that also contains Aspect Ratio ID.
The present invention provides an on-chip SDRAM controller for 16, 20, 24, or 32 Mbit SDRAM.
The present invention provides a general purpose 16-bit extension bus.
The present invention provides a 1394 interface that allows connection to external 1394 devices.
The present invention provides two 2-wire UART data ports.
The present invention provides a Smart Card interface.
The present invention provides an I.sup.2 C master/slave interface.
The present invention provides one IR, one SIRCSI, and one RF input data port.
The present invention provides two general purpose I/O pins.
The present invention provides a JTAG interface.
The present invention provides a 3.3 volt device with some 5 volt tolerant pins for interfacing to the 5 volt devices.
It is an object of the present invention to provide a fully functional decoder using a single 16 Mbit external SDRAM.
It is an object of the present invention to provide a decoder that accepts transport bitstreams up to 40 Mbits per second.
It is an object of the present invention to provide an on-chip DES module for descrambling.
It is an object of the present invention to provide a video decoder that decodes MPEG-1 and MPEG-2 Main Profile and Main Level bitstreams.
It is an object of the present invention to provide an audio decoder that decodes MPEG-1 Layer I and II and MPEG-2 Multichannel bitstreams.
It is an object of the present invention to provide an audio output in both PCM and SPDIF formats.
It is an object of the present invention to provide an OSD processor that enables mixture of OSD and video data with transparent BitBLT hardware that accelerates memory block move.
It is an object of the present invention to provide a 32/16 bit ARM/Thumb processor that removes the need of another CPU in the set-top box.
It is an object of the present invention to provide a firmware that controls device operation and provides application access to hardware resources.
It is an object of the present invention to provide an on-chip NTSC/PAL encoder that incorporates Closed Caption and Video Aspect Ratio Identification Signal encoding and the MacroVision logic for anti-taping protection.
It is an object of the present invention to provide an analog Y, C, and Composite video outputs with 9-bit precision.
It is an object of the present invention to provide an internally or externally generated sync signals.
It is an object of the present invention to provide a digital video component output that also contains Aspect Ratio ID.
It is an object of the present invention to provide an on-chip SDRAM controller for 16, 20, 24, or 32 Mbit SDRAM.
It is an object of the present invention to provide a general purpose 16-bit extension bus.
It is an object of the present invention to provide a 1394 interface that allows connection to external 1394 devices.
It is an object of the present invention to provide two 2-wire UART data ports.
It is an object of the present invention to provide a Smart Card interface.
It is an object of the present invention to provide an I.sup.2 C master/slave interface.
It is an object of the present invention to provide one IR, one SIRCSI, and one RF input data port.
It is an object of the present invention to provide two general purpose I/O pins.
It is an object of the present invention to provide a JTAG interface.
It is an object of the present invention to provide a 3.3 volt device with some 5 volt tolerant pins for interfacing to the 5 volt devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention may be understood by referring to the detailed description which follows, read in conjunction with the accompanying drawings in which:
FIG. 1A depicts a communication system of the present invention;
FIG. 1B depicts a high level functional block diagram of a circuit that forms a portion of the communications system of the present invention;
FIG. 2 depicts a portion of FIG. 1B and data flow between these portions;
FIG. 3 shows the input timing for the circuit of FIG. 1B;
FIG. 4 shows the timing of the VARIS output for the circuit of FIG. 1B;
FIG. 5 shows the timing of 4:2:2 and 4:4:4 digital video output for the circuit of FIG. 1B;
FIG. 6 depicts the data output of PCMOUT alternates between the two channels, as designated by LRCLK for the circuit of FIG. 1B;
FIG. 7 shows an example circuit where maximum clock jitter will not exceed 200 ps RMS for the circuit of FIG. 1B;
FIG. 8 (read) and FIG. 9 (write) show extension bus read and write timing, both with two programmable wait states for the circuit of FIG. 1B;
FIG. 10 shows the timing diagram of a read with EXTWAIT signal on for the circuit of FIG. 1B;
FIG. 11 depicts the connection between circuitry of the present invention, an external packetizer, Link layer, and Physical layer devices;
FIG. 12 shows a functional block diagram of the data flow between the TPP, DES, and 1394 interface;
FIGS. 13 and 14 depict the read and write timing relationships on the 1394 interface for the circuit of FIG. 1B;
FIG. 15 shows the data path of ARM processor core for the circuit of FIG. 1B;
FIG. 16A depicts the data flow managed by the traffic controller for the circuit of FIG. 1B;
FIGS. 16B through 16Q depict details of the traffic controller of FIG. 1B;
FIGS. 16R and 16Q illustrate details of the arbiter block 313-12 of FIG. 16N;
FIG. 16S illustrates timings;
FIG. 17A is an example circuit for the external VCXO for the circuit of FIG. 1B;
FIG. 17B depicts details of a transport packet containing 188 bytes;
FIG. 17C depicts a system where the video and audio decoders are in a separate device;
FIG. 17D depicts how header information is processed by the circuit of FIG. 1B;
FIG. 17E depicts the contents of a packet analyzer control register;
FIG. 17F depicts a block diagram for processing packet header information;
FIG. 17G is the flow diagram used to analyze a packet header;
FIG. 17H describes the structure of the PES packet;
FIGS. 17I-17P depicts the details of a presently preferred embodiment of the TPP of FIG. 1B;
FIGS. 18A to 18Y depict details of the OSD module;
FIGS. 18Z to 18AR depict details of OSD portions of the presently preferred OSD block of FIG. 1B;
FIGS. 18AS to 18BA depict details of BitBLT portions of the presently preferred OSD block of FIG. 1B;
FIG. 19 shows example displays of two OSD output channels for the circuit of FIG. 1B;
FIG. 20 show an example of the IR input bitstream for the circuit of FIG. 1B;
FIG. 21 shows a model of the hardware interface for the circuit of FIG. 1B; and
FIGS. 22A-22S depict details associated with software utilized on or with the circuit of FIG. 1B.
Corresponding numerals and symbols in the different Figures refer to corresponding parts unless otherwise indicated.
DETAILED DESCRIPTION
The present invention provides an improved communications system 100. FIG. 1A depicts an improved communications system 100 of the present invention. More particularly, there may be seen a satellite reception dish 5 that receives signals from a satellite and provides them to a low noise amplifier 10. The low noise amplifier provides its signals to a tuner 20. The tuner 20 is employed to select the signals a user wishes to watch. The tuner 20 is connected to a quadrature phase-shift keying (QPSK) circuit 30 that recovers the digital data in the selected signal. This data is then error corrected by a forward error correction (FEC) circuit 40 using Viterbi, Reed-Solomon, or other techniques to compensate for data errors. The corrected received data is then passed to the circuit 200 of the present invention. The circuit 200 parses the packets of data and converts the data to video, audio and OSD, which may be appropriately displayed on an audio/visual display 130 or after RF modulation 110, on an NTSC/PAL TV 150. Alternatively, the digital video output may be converted, via a converter 90 and displayed on other types of TV's 110, for example, a French TV.
The audio output is converted to an analogue signal by DAC 120. The circuit 200 is also shown connected to a memory 70, an infrared (IR) receiver 50, a modem 60 and a voltage controlled oscillator (VCXO) 80 that provides circuit 200 with a precise but adjustable clock. The clock is adjusted to be synchronized with the clock signals found in the received digital data.
Referring now to FIG. 1B, there may be seen a high level functional block diagram of a circuit 200 that forms a portion of a communications system 100 of the present invention and its interfaces with off-chip devices and/or circuitry. More particularly, there may be seen the high level architecture of a circuit, including on-chip interconnections, that is preferably implemented on a single chip as depicted by the dashed line portion of FIG. 1B.
As depicted inside the dashed line portion of FIG. 1B, this circuit consists of a transport packet parser (TPP) block or module 210 that includes a bitstream decoder or descrambler 212 and clock recovery circuitry 214, an ARM CPU block 220, a data ROM block 230, a data RAM block 240, an audio/video (A/V) core block 250 that includes an MPEG-2 audio decoder 254 and an MPEG-2 video decoder 252, an NTSC/ PAL video encoder block 260, an on screen display (OSD) controller block 270 to mix graphics and video that includes a bitblt hardware (H/W) accelerator 272, a communication coprocressors (CCP) block 280 that includes connections for two UART serial data interfaces 280-4, 280-5, infrared (IR) and radio frequency (RF) inputs 280-2, SIRCS input and output 280-7, an I2C port 280-3 and a Smart Card interface 280-1, a P1394 interface (I/F) block 290 for connection to an external 1394 device, an extension bus interface (I/F) block 300 to connect peripherals such as additional RS232 ports 300-6, display and control panels 300-4, 300-5, external ROM, DRAM 300-1, or EEPROM memory 300-2, a modem 300-3 and an extra peripheral 300-7, and a traffic controller (TC) block 310 that includes an SRAM/ARM (on-chip memory (CPU)) interface (I/F) 311 and a (memory) DRAM I/F 313.
There may also be seen an internal 32 bit address bus 320 that interconnects the blocks and an internal 32 bit data bus 330 that interconnects the blocks. The TPP receives a high speed bit stream of transport data that requires it to analyze the bit stream and direct the data to the right destination. The TPP discards packets not selected by an application and routes as many packets as possible without real-time help from either the ARM CPU 220 or software running on the ARM CPU. External program and data memory expansion 310-2, 300-1, 300-2, allows the circuit to support a wide range of audio/video systems, especially, for example, but not limited to, set-top boxes, from low end to high end.
The consolidation of all these functions onto a single chip with a large number of inputs and outputs allows for removal of excess circuitry and/or logic needed for control and/or communications when these functions are distributed among several chips and allows for simplification of the circuitry remaining after consolidation onto a single chip. More particularly, this consolidation results in the elimination of the need for an external CPU to control, or coordinate control, of all these functions. This results in a simpler and cost-reduced single chip implementation of the functionality currently available only by combining many different chips and/or by using special chipsets. However, this circuit, by its very function, requires a large number of inputs and outputs, entailing a high number of pins for the chip.
In addition, a JTAG block 280-6 is depicted that allows for testing of this circuit using a standard JTAG interface that is interconnected with this JTAG block.
In addition, FIG. 1B depicts that the circuit is interconnected to a plurality of other external blocks. More particularly, FIG. 1B depicts a set of external memory blocks. Preferably, the external memory is SDRAM 312, although clearly, other types of RAM may be so employed. The external memory 312 is described more fully later herein. The incorporation of any or all of these external blocks and/or all or portions of the external memories onto the chip is contemplated by and within the scope of the present invention.
Referring now to FIG. 2, there may be seen a portion of the components of FIG. 1B. The components depicted in FIG. 2, serve as the basis for an initial discussion of data flows between the components to help understand the functionality provided by each block or module and the overall circuit 200. Continuing to refer to FIG. 2, it may be seen how the circuit 200 accepts a transport bitstream from the output of a forward error correction (FEC) device (not depicted) with a maximum throughput of
40 Mbits/s or 7.5 Mbytes/s. The Transport Packet Parser (TPP) 210 in the circuit 200 processes the header of each packet and determines whether the packet should be discarded, further processed by ARM CPU 220, or if the packet contains relevant data and may be stored without any intervention from the ARM 220. The TPP 210 sends all packets requiring further processing or containing relevant data to the internal RAM 240 via the traffic controller (TC) 310. The TPP 210 also activates or deactivates the decryption engine (DES) 212 based on the content of an individual packet. Conditional access keys for decryption (or encryption) are stored in RAM 240 or off-chip memory locations, such as, for example, a smart-card, and managed by special firmware running on the ARM CPU 220. The data transfer from TPP 210 to SDRAM 312 is done via DMA set up by the traffic controller (TC) 310.
Further processing on the packet is done by the ARM firmware, which is activated by an interrupt from the TPP 210 after the completion of the packet data transfer. Two types of transport packets are stored in the RAM 240 which is managed as a first-in first-out buffer (FIFO). One type is for pure data which will be routed to SDRAM 312 without intervention from the ARM 220, and the other type is for packets that need further processing by the ARM 220. Within the interrupt service routine, the ARM 220 checks the FIFO for packets that need further processing, performs necessary parsing, removes the header portion, and establishes DMA for transferring payload data from RAM 240 to SDRAM 312. The traffic controller 310 repacks the data and gets rid of the voids created by any header removal.
Together with the ARM 220, the TPP 210 also handles System Clock Reference (SCR) recovery with an external VCXO 80. The TPP 210 will latch and transfer to the ARM 220 its internal system clock upon the arrival of any packet which may contain system clock information. After further processing on the packet and identifying the system clock, the ARM 220 calculates the difference between the system clock from a bitstream and the actual system clock at the time the packet arrives. Then, the ARM
220 filters the difference and sends it through a Sigma-Delta DAC 216 in the TPP 210 to control the external voltage controlled oscillator (VCXO) 80. During start-up when there is no incoming SCR, the ARM will drive the VCXO 80 to its center frequency.
The TPP 210 will also detect packets lost from the transport stream. With error concealment by the audio/video decoder and the redundant header from DSS bitstream, the circuit 200 minimizes the effect of lost data.
After removing packet headers and other system related information, both audio and video data is stored in external SDRAM 312. The video 252 and audio 254 decoders then read the bitstream from SDRAM 312 and process it according to the ISO standards. The circuit 200 decodes MPEG-1 and MPEG-2 main profile at main level for video and Layer I and II MPEG-1 and MPEG-2 for audio. Both video 252 and audio 254 decoders synchronize their presentation using the transmitted Presentation Time Stamps (PTS). In a Digital Satellite System (DSS), the PTS is transmitted as picture user data in the video bitstream and an MPEG-1 system packet bitstream for audio. Dedicated hardware decodes the PTS if it is in the MPEG-1 system packet and forwards it to the audio decoder 254. The video decoder 252 decodes PTS from picture user data. Both video 252 and audio 254 decoders compare PTS to the local system clock in order to synchronize presentation of the reconstructed data. The local system clock is continuously updated by the ARM 220. That is, every time the System Clock Reference (SCR) of a selected SCID is received and processed, the ARM 220 will update the decoder system clock.
The video decoder 252 is capable of producing decimated pictures using 1/2 or 1/4 decimation per dimension, which results in reduced areas of 1/4 or 1/16. The decimated picture can be viewed in real time. Decimation is achieved by using field data out of a frame, skipping lines, and performing vertical filtering to smooth out the decimated image.
When decoding a picture from a digital recorder, the decoder can handle trick modes (decode and display I frame only), with the limitation that the data has to be a whole picture instead of several intra slices. Random bits are allowed in between trick mode pictures. However, if the random bits emulate any start code, it will cause unpredictable decoding and display errors.
Closed Caption (CC) and Extended Data Services (EDS) are transmitted as picture layer user data. The video decoder 252 extracts the CC and EDS information from the video bitstream and sends it to the NTSC/PAL encoder module 260.
The video decoder 252 also extracts the aspect ratio from the bitstream and sends it to the ARM 220 which prepares data according to the Video Aspect Ratio Identification Signal (VARIS) standard, EIAJ CPX-1204. The ARM 220 then sends it to the NTSC/PAL encoder 260 and OSD module 270.
The OSD data may come from the user data in the bitstream or may be generated by an application executed on the ARM 220. Regardless of the source, the OSD data will be stored in the SDRAM 312 and managed by the ARM 220. However, there may be limited space in the SDRAM 312 for OSD. Applications that require large quantities of OSD data preferably store them in an external memory attached to the extension bus 300. Based on a request from a user application, the ARM 220 will turn the OSD function on and specify how and where the OSD will be mixed and displayed along with the normal video sequence. The OSD data can be represented in one of the following forms: bitmap, graphics 4:4:4 component, CCIR 601 4:2:2 component, or just background color. A special, dedicated bitBLT hardware 272 expedites memory block moves between different windows.
DES 212 processing is signaled by the arrival of a control word packet. That is, a conditional access is triggered by the arrival of a control word packet (CWP). The ARM firmware recognizes a CWP has been received and hands it to the Verifier, which is NewsDataCom (NDC) application software running on the ARM 220. The Verifier reads the CWP and communicates with an external Smart Card through a Smart Card I/O interface in communication coprocessor 280. After verification, it passes the pointer to an 8 byte key back to the firmware, which then loads the key for the DES 212 to decrypt succeeding packets.
The ARM 220 is a 32-bit processor running at 40.5 MHz and with its associated firmware provide the following: initialization and management of all hardware modules; service for selected interrupts generated by hardware modules and I/O ports; and application program interface (API) for users to develop their own applications.
The ARM firmware is stored in the on-chip ROM 230, except for OSD graphics and some generic run time support code. The ROM 230 is preferably 12K bytes, but other sizes may be so employed. The on-chip RAM 240 provides the space necessary for the circuit 200 to properly decode transport bitstreams without losing any packets. The RAM 240 is preferably 4.5K bytes, but other sizes may be so employed. The run-time support library (RTSL) and all user application software is presently preferred to be located in memory outside the circuit 200. Details of the firmware and RTSL are provided later herein.
There are two physical DMA channels managed by the traffic controller 310 to facilitate large block transfers between memories and buffers. That is, as long as there is no collision in the source and destination, it is possible to have two concurrent DMA transfers. A more detailed description of these DMA functions is provided later herein in subsequent discussions of the details of the traffic controller 310.
The circuit 200 accepts DSS transport packet data from a front end such as a forward error correction (FEC) unit. The data is input 8 bits at a time, using a byte clock, DCLK. PACCLK high signals valid packet data. DERROR is used to indicate a packet that has data errors. The timing diagram in FIG. 3 shows the input timings for such data.
As part of the communication coprocessor 280, the circuit 200 includes an interface to the Smart Card access control system. The interface consists of a high speed UART and logic to comply with the News Datacom specification (Document #HU-T052, Release E dated November 1994, and Release F dated January 1996) Directv Project: Decoder-Smart Card Interface Requirements. Applicable software drivers that control the interface are also included, and are described later herein.
It should be noted that the circuit 200 is preferably a 3.3 volt device, while the Smart Card requires a 5 volt interface. The circuit 200 will output control signals to turn the card's VCC and VPP on and off as required, but external switching will be required. It is also possible that external level shifters may be needed on some of the logic signals.
A NTSC/PAL pin selects between an NTSC or a PAL output from encoder 260. Changing between NTSC and PAL mode requires a hardware reset of the device 200.
The circuit 200 produces an analog S-video signal on two separate channels, the luminance (Y) and the chrominance (C). It also outputs the analog composite (Comp) signal. All three outputs conform to the RS170A standard.
The circuit 200 also supports Closed Caption and Extended Data Services. The analog output transmits CC data as ASCII code during the twenty-first video line. The NTSC/PAL encoder module inserts VARIS codes into the 20th video line for NTSC and
23rd line for PAL.
The digital output provides video in either 4:4:4 or 4:2:2 component format, plus the aspect ratio VARIS code at the beginning of each video frame. The video output format is programmable by the user but defaults to 4:2:2. The content of the video could be either pure video or the blended combination of video and OSD.
The pin assignments for the digital video output signals are:
YCOUT(8) 8-bit Cb/Y/Cr/Y and VARIS multiplexed data output
YCCLK(1) 27 MHz or 40.5 MHz clock output
YCCTRL(2) 2-bit control signals to distinguish between Y/Cb/Cr components and VARIS code
The interpretation of YCCTRL is defined in the following table.
TABLE 1 Digital Output Control SIGNALS YCCTRL[1] YCCTRL[0] Component Y 0 0 Component Cb 0 1 Component Cr 1 0 VARIS code 1 1
The aspect ratio VARIS code includes 14 bits of data plus a 6-bit CRC, to make a total of 20 bits. In NTSC the 14-bit data is specified as shown in Table 2.
TABLE 2 VARIS Code Specification Bit Number Contents Word0 A 1 Communication aspect ratio: 1 = full mode (16:9), 0 = 4:3 2 Picture display system: 1 = letter box, 0 = normal 3 Not used Word0 B 4 Identifying information for the picture and 5 other signals (sound signals) that are related 6 to the picture transmitted simultaneously Wordl 4-bit range Identification code associated to Word0 Word2 4-bit range Identification code associated to Word0 and other information
The 6-bit CRC is calculated, with the preset value to be all 1, based on the equation G(X)=X.sup.6 +X+1.
The 20-bit code is further packaged into 3 bytes according to the following format illustrated in Table 3.
TABLE 3 Three Byte VARIS Code b7 b6 b5 b4 b3 b2 b1 b0 lst Byte -- -- Word0 B Word0 A 2nd Byte Word2 Word1 3rd Byte VID_EN -- CRC
The three byte VARIS code is constructed by the ARM 220 as part of the initialization process. The ARM 220 calculates two VARIS codes corresponding to the two possible aspect ratios. The proper code is selected based on the aspect ratio from the bitstream extracted by the video decoder 252. The user can set VID_EN to signal the NTSC/PAL encoder to enable (1) or disable (0) the VARIS code. The transmission order is the 1st byte first and it is transmitted during the non-active video line and before the transmission of video data.
The timing of the VARIS output is shown in the following FIG. 4. The timing of 4:2:2 and 4:4:4 digital video output is shown in FIG. 5.
The PCM audio output from the audio decoder 254 is a serial PCM data line, with associated bit and left/right clocks.
PCM data is output serially on PCMOUT using the serial clock ASCLK. ASCLK is derived from the PCM clock, PCMCLK, according to the PCM Select bits in the control register. PCM clock must be the proper multiple of the sampling frequency of the bitstream. The PCMCLK may be input to the device or internally derived from an 18.432 MHz clock, depending on the state of the PCM_SRC pin. The data output of PCMOUT alternates between the two channels, as designated by LRCLK as depicted in FIG. 6. The data is output most significant bit first. In the case of 18-bit output, the PCM word size is 24 bits. The first six bits are zero, followed by the 18-bit PCM value.
The SPDIF output conforms to a subset of the AES3 standard for serial transmission of digital audio data. The SPDIF format is a subset of the minimum implementation of AES3.
When the PCM_SRC pin is low, the circuit 200 generates the necessary output clocks for the audio data, phase locked to the input bitstream. However, the clock generator requires an additional 18.432 MHz external VCXO 254-1 and outputs a control voltage that can be applied to the external loop filter and VCXO to produce the required input. The clock generator derives the correct output clocks, based on the contents of the audio control register bits PCMSEL1-0, as shown in the following table.
TABLE 4 Audio Clock Frequencies PCMSEL1-0 Description LRCLK (KHz) ASCLK (MHz) PCMCLK (MHz) 00 16 bit PCM, no oversampling 48 1.5360 1.5360 01 16 bit PCM, 256 x oversampling 48 1.5360 12.288 10 18 bit PCM, no oversampling 48 2.304 2.304
11 18 bit PCM, 384 x oversampling 48 2.304 18.432
Maximum clock jitter will not exceed 200 ps RMS. A representative VCXO circuit is shown in FIG. 7.
When PCM_SRC is high, the circuit 200 expects the correct PCM oversampling clock frequency to be input on PCMCLK.
The SDRAM 312 is preferably 16-bit wide SDRAM. The DRAM I/F 313 of the TC 310 is presently preferably configured for this type of bit width; clearly other widths may be selected and so employed. The circuit 200 provides control signals for up to two SDRAMs. Any combination of 4, 8, or 16 Mbit SDRAMs may be used, provided they total at least 16 Mbits. The SDRAM must operate at an 81 MHz clock frequency and have the timing parameters described later herein.
The extension bus interface 300 is a 16-bit bi-directional data bus with a 25-bit address for byte access. It also provides 3 external interrupts, each with it's own acknowledge signal, and a wait line. All the external memories or I/O devices are mapped to the 32-bit address space of the ARM. There are seven internally generated Chip Selects (CSx) for EEPROM memory 300-2, DRAM 300-1, modem 300-3, front panel 300-4, front end control 300-5, parallel output port 300-6, and extra peripheral
300-7. Each CS has its own defined memory space and a programmable wait state register which has a default value 1. The number of wait states depends on the content of the register, with a minimum of one wait state. The EXTWAIT signal can also be used to lengthen the access time if a slower device exists in that memory space.
The extension bus 300 supports the connection of 7 devices using the pre-defined chip selects. Additional devices may be used by externally decoding the address bus. The following table shows the name of the device, its chip select, address range, and programmable wait state. Every device is required to have tri-stated data outputs within 1 clock cycle following the removal of its chip-select (CS).
TABLE 5 Extension Bus Chip Select Chip Wait Select Byte Address Range State Device CS1 0200 0000 - 03FF FFFF 1 - 5 EEPROM (up to 32 MBytes) CS2 0400 0000 - 05FF FFFF N/A DRAM (up to 32 MBytes) CS3 0600 0000 - 07FF FFFF 1 - 7 Modem CS4
0800 0000 - 09FF FFFF 1 - 7 Front Panel C55 0A00 0000 - 0BFF FFFF 1 - 7 Front End Device CS6 0C00 0000 - 0DFF FFFF 1 - 7 1394 Link Device CS7 0E00 0000 - 0FFF FFFF 1 - 4 Parallel Data Port
CS1 is intended for ARM 220 application code, but writes will not be prevented.
CS2 is read/write accessible by the ARM 220. It is also accessed by the TC 310 for TPP 210 and bitBLT 272 DMA transfers.
CS3, CS4, CS5, and CS6 all have the same characteristics. The ARM 220 performs reads and writes to these devices through the extension bus.
CS7 is read and write accessible by the ARM 220. It is also accessed by the TC 310 for TPP 210 DMAs, and it is write only. The parallel port is one byte wide and it is accessed via the least significant byte.
The extension bus 300 supports connection to external EEPROM, SRAM, or ROM 300-2 memory and DRAM 300-1 with its 16-bit data and 25-bit address. The extension bus 300 supports access to 70 ns DRAM with 2 wait states. The DRAM must have a column address that is 8-bits, 9-bits, or 10-bits wide. The DRAM preferably has a data width of 8 or 16 bits. Byte access is allowed even when the DRAM has a 16 bit data width. The system default DRAM configuration is 9-bit column address and 16-bit data width. The firmware will verify the configuration of DRAM during start up. The extension bus 300 also supports DMA transfers to/from the extension bus. DMA transfers within the extension bus are not supported. However, they may be accomplished by DMA to the SRAM, followed by DMA to the extension bus. Extension bus read and write timing are shown in FIG. 8 (read) and FIG. 9 (write), both with two programmable wait states. The number of wait states may be calculated by the following formula:
For example, the CS_delay on the chip is 20 nsec. A device with 80 nsec read timing will need 4 wait states.
There are three interrupt lines and three interrupt acknowledges in the circuit 200. These interrupts and interrupts from other modules are handled by a centralized interrupt handler. The interrupt mask and priority are managed by the firmware. The three extension bus interrupts are connected to three different IRQs. When the interrupt handler on the ARM 220 begins servicing one of these IRQs, it should first issue the corresponding EXTACK signal. At the completion of the IRQ, the ARM 220
should reset the EXTACK signal.
The EXTWAIT signal is an alternative way for the ARM 220 to communicate with slower devices. It can be used together with the programmable wait state, but it has to become active before the programmable wait cycle expires. The total amount of wait states should not exceed the maximum allowed from Table 5. If the combined total wait states exceeds its maximum, the decoder is not guaranteed to function properly. When a device needs to use the EXTWAIT signal, it should set the programmable wait state to at least 2. Since the EXTWAIT signal has the potential to stall the whole decoding process, the ARM 220 will cap its waiting to 490 nanoseconds. Afterwards, the ARM 220 assumes the device that generated the EXTWAIT has failed and will ignore EXTWAIT from then on. Only a software or hardware reset can activate the EXTWAIT signal again. The timing diagram of a read with EXTWAIT signal on is shown in the FIG. 10.
The circuit 200 includes an Inter Integrated Circuit (I.sup.2 C) serial bus interface that can act as either a master (default) or slave. Only the `standard mode` (100 kbit/s) I.sup.2 C-bus system is implemented; `fast mode` is not supported. The interface uses 7-bit addressing. When in slave mode, the address of the circuit 200 is programmed by the API.
Timing for this interface matches the standard timing definition of the 1.sup.2 C bus.
The circuit 200 includes two general purpose 2-wire UARTs that are memory mapped and fully accessible by application programs. The UARTs operate in asynchronous mode only and support baud rates of 1200, 2400, 4800, 9600, 14400, 19200 and 28800
kbps. The outputs of the UARTs are digital and require external level shifters for RS232 compliance.
The IR, RF, and SIRCSI ports require a square wave input with no false transitions; therefore, the signal must be thresholded prior to being applied to the pins. The interface will accept an IR, RF, or SIRCSI data stream up to a frequency of 1.3
KHz. Although more than one may be active at any given time, only one IR, RF, or SIRCSI input will be decoded. Decoding of the IR, RF, and SIRCSI signals will be done by a combination of hardware and software. A more detailed description of these IR, RF functions is provided later herein in subsequent discussions of the details of the module 280.
SIRCSO outputs the SIRCSI or IR input or application-generated SIRCSO codes.
The circuit 200 provides a dedicated data interface for 1394 290. To complete the implementation, the circuit 200 requires an external packetizer 290-1, Link layer 290-2, and Physical layer 290-3 devices. FIG. 11 depicts the inter-connection of these components.
The control/command to the packetizer or the Link layer interface device is transmitted via the extension bus 300. The 1394 data is transferred via the 1394 interface which has the following 14 signals:
TABLE 6 1394 Interface Signals Signal Name I/O Description PDATA (8) I/O 8 bit data PWRITE (1) O if PWRITE is high (active) the circuit writes to the Link device PPACEN (1) I/O asserted at the beginning of a packet and remains asserted during the time of packet transfer PREADREQ (1) I asserted (active high) if the Link device is ready to output to the circuit and the stamped time comes PREAD (1) O if PREAD is high (active) the circuit reads from the Link device CLK40 (1) O 40.5
MHz clock. Wait states can be used to slow data transfer. PERROR (1) I/O indicates a packet error
In recording mode, the circuit 200 will send either encrypted or clean packets to the 1394 interface 290. The packet is transferred as it comes in. When recording encrypted data, the TPP 210 will send each byte directly to the 1394 290 interface and bypass the DES module 212. In the case of recording decrypted data, the TPP 210 will send the packet payload to the DES module 290, then forward a block of packets to the 1394 interface 290. The interface 290 sends the block of packets out byte by byte. No processing will be done to the packet during recording, except setting the encrypt bit to the proper state. In particular, the TPP 210 will not remove CWP from the Auxiliary packet. During playback mode, the packet coming from the interface will go directly into the TPP 210 module. FIG. 12 shows the functional block diagram of the data flow between the TPP 210, DES 212, and 1394 interface 290, via muxes 218 and 219. The packet coming out from TPP 210 can go either to the 1394 interface
290 or to the RAM 240 through traffic controller TC, or to both places at the same time. This allows the circuit 200 to decode one program while recording from 1 to all 32 possible services from a transponder.
FIGS. 13 and 14 depict the read and write timing relationships on the 1394 interface 290. In FIG. 13, CLK40 is 40.5 MHz. When PPACEN is high, circuit 200 toggles PWRITE as needed to output data. There should preferably be at least one cycle between the time that PDATA is valid to the time PWRITE goes high. The duration of PWRITE is one cycle, 25 ns. In FIG. 14, PREADREQ can go high at any time before or coincident with the next packet and it should remain high at least one cycle. PPACEN goes high when PDATA ready and both are synchronized to CLK40. PREAD toggles for one cycle when PDATA will change.
During recording, if the DERROR signal from the front end interface goes high in the middle of a packet, it is forwarded to the PERROR pin. If DERROR becomes active in between packets, then a PERROR signal will be generated during the transfer of the next packet for at least one PDATA cycle.
During playback mode, the external 1394 device can only raise the PERROR signal when the PPACEN is active to indicate either error(s) in the current packet or that there are missing packet(s) prior to the current one. PERROR is ignored unless the PPACEN is active. The PERROR signal should stay high for at least two PCLK cycles. There should be at most one PERROR signal per packet.
The circuit 200 requires a hardware reset on power up. Reset of the device is initiated by pulling the RESET pin low, while the clock is running, for at least 100 ns. The following actions will then occur: input data on all ports will be ignored; external memory is sized; data pointers are reset; all modules are initialized and set to a default state: the TPP tables are initialized; the audio decoder is set for 16 bit output with 256.times. oversampling; the OSD background color is set to blue and video data is selected for both the analog and digital outputs; MacroVision is disabled; and the I.sup.2 C port is set to master mode.
When the reset sequence is finished, the device will begin to accept data. All data input prior to the end of the reset sequence will be ignored.
JTAG boundary scan is included in the circuit 200. Five pins (including a test reset) are used to implement the IEEE 1149.1 (JTAG) specification. The port includes an 8-bit instruction register used to select the instruction. This register is loaded serially via the TDI input. Four instructions (Bypass; Extest; Intest and Sample) are supported, all others are ignored. Timing for this interface conforms to the IEEE 1149.1 specification.
The ARM/CPU module runs at 40.5 MHz and supports byte (8-bit), half-word (16-bit), and word (32-bit) data types. It reads instructions from on-chip ROM or from the extension bus. It can switch between ARM (32-bit) or Thumb (16-bit) instruction mode and has a 32-bit data and 32-bit address lines. It has 7 processing modes and two interrupts, FIQ and IRQ.
Preferably, the CPU 220 in the circuit 200 is a 32 bit RISC processor, the ARM7TDMI/Thumb, which has the capability to execute instructions in 16 or 32 bit format at a clock frequency of 40.5 MHz. Other RISC processors may be employed. The regular ARM instructions are exactly one word (32-bit) long, and the data operations are only performed on word quantities. However, LOAD and STORE instructions can transfer either byte or word quantities.
The Thumb uses the same 32 bit architecture with an 16-bit instruction set. That is, it retains the 32-bit performance but reduces the code size with 16-bit instructions. With 16-bit instructions, the Thumb still gives 70-80% of the performance of the ARM when running ARM instructions from 32-bit memory. ARM and Thumb are used interchangeably herein.
ARM uses a LOAD and STORE architecture, i.e. all operations are on the registers 221. ARM has 7 different processing modes, with 16 32-bit registers visible in user mode. In the Thumb state, there are only 8 registers available in user mode. However, the high registers may be accessed through special instructions. The instruction pipeline is three stage, fetch.fwdarw.decode.fwdarw.execute, and most instructions only take one cycle to execute. FIG. 15 shows the basic data path of ARM processor core.
The ARM CPU 220 is responsible for managing all the hardware and software resources in the circuit 200. At power up the ARM will verify the size of external memory. Following that, it will initialize all the hardware modules by setting up control registers, tables, and reset data pointers. It then executes the default firmware from internal ROM. A set of run-time library routines provides the access to the firmware and hardware for user application programs. The application programs are stored in external memory attached to the extension bus 300.
During normal operation the ARM constantly responds, based on a programmable priority, to interrupt requests from any of the hardware modules and devices on the extension bus. The kind of interrupt services include transport packet parsing, program clock recovery, traffic controller and OSD service requests, service or data transfer requests from the extension bus and Communication Co-Processor, and service requests from the audio/video decoders.
The traffic controller module 310 manages interrupt requests and authorizes and manages DMA transfers. It provides SDRAM interface and manages the extension bus 300. It provides memory access protection and manages the data flow between processors and memories such as: TPP/DES to/from internal Data RAM; Data RAM to/from extension bus; SDRAM to OSD; OSD to/from Data RAM; audio/video decoder to/from SDRAM; and SDRAM to/from Data RAM. It also generates chip selects (CS) for all the internal modules and devices on the extension bus 300 and generates programmable wait states for devices on the extension bus. It also provides 3 breakpoint registers and 64 32-bit patch RAM.
FIG. 16A depicts the various data flows managed by the traffic controller 310.
The SDRAM interface 313 supports 12 nanoseconds 16-bit data width SDRAM 312. It has two chip selects that allow connections to a maximum of two SDRAM chips. The minimum SDRAM size required for a fully functional video decoder is 16 Mbit. Other supported sizes and configurations are:
The access to the SDRAM can be by byte, half word, single word, continuous block, video line block, or 2D macroblock. The interface also supports decrement mode for bitBLT block transfer.
The two chip selects correspond to the following address ranges:
During decoding, the circuit 200 allocates the 16 Mbit SDRAM for NTSC mode according to Table 7.
TABLE 7 Memory Allocation of 16 Mbit SDRAM (NTSC) Starting Byte Address Ending Byte Address Usage 0x000000 0x0003FF Pointers 0x000400 0x000FFF Tables and FIFOs 0x001000 0x009FFF Video Microcode (36,864 bytes) 0x00A000 0x0628FF Video Buffer (2,902,008 bits) 0x062900 0x0648FF Audio Buffer (65,536 bits) 0x064900 0x0E31FF First Reference Frame (518,400 bytes) 0x0E3200 0x161CFF Second Reference Frame (518,400 bytes) 0x161D00 0x1C9DFF B Frame (426,240 bytes, 0.82 frames)
0x1C9E00 0x1FFFFF OSD or other use (222,210 bytes)
However, it is also within the scope of the present invention to put the VBV buffer in optional memory on the extension bus 300 and thereby free up the SDRAM memory by the amount of the VBV buffer. This means that the SDRAM is allocated in a different manner than that of Table 7; that is the OSD memory size may be expanded or any of the other blocks expanded.
Interrupt requests are generated from internal modules like the TPP, OSD, A/V decoder and Communication Processor, and devices on the extension bus. Some of the requests are for data transfers to internal RAM, while others are true interrupts to the ARM CPU. The traffic controller handles data transfers, and the ARM provides services for true interrupts. The interrupts are grouped into FIQ and IRQ. The system software uses FIQ, while the application software uses IRQ. The priorities for FIQs and IRQs are managed by the firmware.
As noted in Table 7, the SDRAM 312 is used to store system level tables, video and audio bitstreams, reconstructed video images, OSD data, and video decoding codes, tables, and FIFOs. The internal Data RAM 240 stores temporary buffers, OSD window attributes, keys for conditional access, and other tables and buffers for firmware. The TC 310 manages two physical DMA channels, but only one of them, the General Purpose DMA, is visible to the user. The user has no knowledge of the DMAs initiated by the TPP, the video and audio decoders, and the OSD module. The General Purpose DMA includes ARM-generated and bitBLT-generated DMAs. The TC 310 can accept up to 4 general DMAs at any given time. Table 8 describes the allowable General Purpose DMA transfers.
TABLE 8 DMA Sources and Destinations DMA Transfer SDRAM Data RAM Extension Bus SDRAM NO YES NO Data RAM YES NO YES Extension Bus NO YES NO
Note that there is no direct DMA transfer to/from the extension bus memories from/to the SDRAM. However, the user can use the bitBLT hardware which uses Data RAM 240 as intermediate step for this purpose. The only constraint is the block being transferred has to start at a 32-bit word boundary.
FIG. 16B depicts the two interior blocks of the SRAM/ARM I/F block 311 of TC 310. More particularly, FIG. 16B depicts the SRAM hardware control block 311-1 and the ARM I/F block 311-2. FIG. 16C provides the details of block 311-2. Similarly, FIG. 16D provides the details of block 311-1.
As may be seen from FIG. 16C, the ARM I/F 311-2 includes a privilege decoder block 311-20 connected to a protection block 311-22. The protection block implements three levels of protection for the memory space of the ARM CPU 220. That is, firmware is allowed access to any memory, while the OS is allowed access to most memory; the application software (user mode) is only allowed access to restricted portions of the DRAM 312 and SRAM 240, but is allowed access to all other external memory. The chip select decoder block 311-24 determines from the ARM bus address the module, register, device or memory that is being addressed and generates a chip select (CS) for that address. In a similar manner, an interrupt control block handle interrupts from the modules or blocks in circuit 200.
A patch logic block 311-28 provides a way to load preselected values onto the bus when a certain address is selected. That is, this circuitry provides a patch from a portion of memory to a different locations, e.g. a patch RAM.
An SDRAM finite state machine 311-30 controls accesses to the SRAM 240. If the ARM tries to access the SRAM while it is busy, the ARM wait state generator 311-32 generates a signal to the ARM that essentially turns off its internal clock signal until the SRAM is available.
The remaining block 311-34 handles byte control for the SRAM. That is, it evaluates an ARM request to determine if the ARM is reading or writing a word, a half word (upper or lower) or a byte of data. It does this by evaluating the ARM control signals and selected ARM address positions.
FIG. 16D depicts the SRAM control block 311-1 and it includes a state machine 311-40 that interfaces with an extension bus interface (I/F) 311-42, a TCDRAM I/F 311-44, a TPP I/F 311-46 and a BitBLT I/F 311-48. It has available to it a TPP DMA table stored in a register 311-50 and a GEN DMA table stored in register 311-52.
The various states for the state machine 311-40 are depicted in FIGS. 16E-16M.
FIG. 16N depicts the interior blocks of the DRAM I/F 313 of the TC 310. More particularly, it may be seen that the DRAM I/F 313 includes an audio/visual I/F 313-10, an arbitration block 313-12, a data path control block 313-14, a data path block
313-10 and a DRAM I/F 313-16. FIG. 16O depicts the details of the A/V block 313-10. It depicts the video buffer and audio buffer management blocks, 313-30 and 313-32, respectively. The audio buffer is managed by the TC 310 hardware, while the video buffer is managed by the TC 310 hardware and video decoder 252 software. The video register file 313-34 allows the circuit 200 access to the video decoder busses and vice-versa. There is also depicted a video bus control state machine 313-36, that allows for single reads and writes and allows the video decoder 252 to cycle steal on the video decoder bus.
FIG. 16P depicts the various state machines in the DRAM I/F 313-16 of FIG. 16N that implement the various commands,line increment (lininc), line decrement (lindec) motion compensation (mc), video scan (vidscan) and refresh (refresh). These state machines generate the appropriate address and control signals to control the SDRAM 312.
FIG. 16Q depicts the data path block 313-18 of FIG. 16N. It provides the details of how data is passed to and from the SDRAM.
The details of the DP control block 313-14 are provided in Appendix A hereto and incorporated by reference herein. The details of the arbitration block 313-12 are provided in Appendix B hereto and incorporated by reference herein.
FIG. 16R depicts a block diagram illustrating additional details about arbiter block 313-12 of FIG. 16N. FIG. 16S depicts the state machine states for the state mahcine of this block. FIG. 16T illustrates timings for data path control (313-18) read and writes.
The TPP Module 210 parses transport bitstreams and accepts bitstreams either from the front end device or from the 1394 interface. It performs System Clock Reference (SCR) recovery and supports transport streams up to 40 Mbits-per-second. It accepts 8-bit parallel input data and supports storage of 32 PID/SCIDs. It provides lost-packet detection and provides decrypted or encrypted packets directly to the 1394 interface. It also provides an internal descrambler 212 for DSS with the Data Encryption Standard (DES) implemented in hardware.
The TPP 210 accepts packets on a byte by byte basis. Each packet contains a unique ID, PID/SCID, and the TPP extracts those packets containing the designated ID numbers. It processes the headers of transport packets and transfers the payload or auxiliary packets to the internal RAM 240 via the DES 212 hardware, if required. Special firmware running on the ARM 220 handles DES key extraction and activates DES operation. The ARM/CPU 220 performs further parsing on auxiliary packets stored in the internal RAM 240. The ARM 220 and TPP 210 together also perform SCR clock recovery. FIG. 17A is an example circuit for the external VCXO 80. The output from the circuit 200 is a digital pulse with 256 levels.
The conditional access and DES block 212 is part of the packet header parsing function. A CF bit in the header indicates whether the packet is clean or has been encrypted. The clean packet can be forwarded to the internal RAM 240 directly, while the encrypted one needs to go through the DES block 212 for decryption. The authorization and decryption key information are transmitted via control word packet (CWP). An external Smart Card 280-1 guards this information and provides the proper key for the DES 212 to work.
The 1394 interface 290 is directly connected to the TPP/DES module 210. At the command of the a program, the TPP/DES can send either clean or encrypted packets to the 1394 interface 290. The user can select up to 32 services to record. If the material is encrypted, the user also needs to specify whether to record clean or encrypted video. In a recording mode, the TPP 210 will appropriately modify the packet header if decrypted mode is selected; in encrypted mode, the packet headers will not be modified. During the playback mode, the 1394 interface 290 forwards each byte as it comes in to the TPP 210. The TPP 210 parses the bitstream the same way it does data from the front end.
The MPEG2 transport stream parser (TPP) receives the MPEG transport stream and selects video, audio or services information packets. After decoding, the packets are stored to memory buffers to form a data stream. The audio decoder 254 processes the MPEG audio stream and produces an analog audio signal. The video decoder 252 decompresses the MPEG video and generates a video sequence.
As depicted in FIG. 17B, a transport packet (A) contains 188 bytes. The packet is divided in two parts, a 32-bit header and 184 bytes of payload. The transport header contains different fields (PID, payload unit start indicator, adaptation field flags, continuity counter index) that will allow the transport packet parser to do a coarse filter. After the transport header, the packet can contain an adaptation field of variable length for a payload. Some of these payloads will themselves start with a header (PES header) B which has also a variable length. The PES header in MPEG2 standard can be bigger than a packet (overflow on the next packet).
The current state of the art for MPEG2 transport stream system analyzer consists of chip set solution including a complete transport stream hardware analyzer and an associated micro-processor and memory. The video and audio decoder are separate devices, as shown in the FIG. 17C. The transport stream parser is in charge of the transport stream full analysis with the current approach leaving to the CPU the tasks of directing the data towards the right destination and controlling the different modules. Another solution would be to implement all the transport analysis in software; however, this solution would require much higher CPU processing power.
The approach for the transport stream parser of the present invention splits the load of the transport stream and MPEG2 analysis between hardware and software to make the analysis more effective. Hardware filtering allows an early decision to be taken based on PIDs recognition; it reduces the data stream very efficiently allowing the firmware to execute much more complex filtering algorithms on the reduced data stream. This approach optimizes the resources. The hardware stays simple while the firmware needs less CPU power because the bit rate it receives has been pre-processed by the hardware.
The parsing and routing of the packets are done with a PID recognition mechanism coupled with a set of attributes stored in a local memory for each PID. These attributes complete the information received from the different headers.
The transport parser module immediately discards all packets which are not selected by the application, and routes as many packets as possible without "real time" help from the firmware.
Once a packet with a valid PID has been detected, the parser checks the condition set which determines if the packet needs further processing by the CPU 220 (see description of EOP interrupt generation later herein). If one of these conditions is met, the packet is sent to a temporary buffer with an attached flag (indicating that further processing is required) and an interrupt EOP is sent to the CPU to indicate that a new packet has been received. Data stored in this temporary buffer is then processed by the firmware before it can be routed or discarded as shown in path (2) of FIG. 17D. Once the data have been processed, the CPU 220 transfers the data itself or initiates DMA transfers to the system buffer in memory 240. The software is also going to modify in some cases some of the PID attributes (ex: stream-id filter) to modify the routing of the following packet (e.g. one with the same PID). If none of the conditions are met, the attached flag indicates that no additional processing is required. The packet can then be automatically forwarded (via path (1) in FIG. 17D) to its final destination via automatic DMA transfers (e.g.: packets containing compressed video information can be sent directly to the system video buffer, . . . ). In this case, no EOP interrupt is sent to the CPU 220 and the packet transfer to the final destination does not require any CPU resource.
FIG. 17D shows the two different data flows; one with CPU intervention, path (2), and one with no intervention, path (1).
FIG. 17D is the key for the trade-off between hardware and software. The transport stream parser can very easily route the packets and let the CPU do more complex analysis on some parts of the bit stream.
Again, this selection is done by analyzing the header (PID, AF flag, PES/PSI start flag [payload unit start indicator], transport error flag, counter continuity index), and the PID attributes because the choice can not always be done by extracting information from the packet itself as depicted in FIG. 17E. Sometimes, the nature of the previous packet (same PID) will determine if the packet needs additional processing (PES header split between two packets). Sometimes, it is linked to the PID number. If a PID contains table information for instance that always require CPU processing then the attribute Spei is set (means that packets with this PID will always be sent to the CPU). The list of information used to generate the EOP interrupt is summarized in FIG. 17E and described below.
FIG. 17E shows where the information comes from. The conditions to generate the EOP are described later herein.
The following is a description of the bits in Packet Analyzer Control Register.
Valid PID
This bit is the result of the PID recognition function. The PID number is the packet identification number received in the transport stream header of each packet. It determines if a packet must be transmitted to the system or not. If the PID number has been selected, the Valid_PID bit goes active `1` when a packet with this PID number is received. It is the first level of packet filtering and the necessary condition for the other analysis steps.
Te (Transport Error Indicator)
This is retrieved from the Transport Stream packet header. The transport error indicator bit is active when the packet received contains some errors.
Pes/Psi Start Flag (Transport Stream Payload Start-unit-indicator)
This is retrieved from the Transport Stream packet header.
When the payload of the Transport stream contains a PES packet data. A `1` indicates that the payload of this Transport stream packet will commence with the first byte of the PES packet (PES header) and a `0` indicates that no PES packet starts in this Transport Stream Packet.
When the payload of the Transport Stream packet contains PSI data. A `1` means that the payload carries at least one beginning of a PSI section and a `0` if no start of a PSI section is carried is this Transport Stream packet.
AF Flag (Transport Stream Adaptation Field)
This two bit field of the Transport Stream header indicates whether the Transport Stream header is followed by an adaptation field or not.
TABLE 9 AF Value Description 00 reserved for future use by ISO/IEC 01 no adaptation field, payload only 10 adaptation field only, no payload 11 adaptation field followed by payload
CC-error
This bit is the result of the hardware discontinuity counter detection function on the continuity counter (CC). The detection is done with a comparison between the CC (4-bits contained in the Transport Stream header) called the Current_CC and the CC from the previous packet of the same PID (called Previous_CC). The Previous_CC is an attribute modified by the hardware. Once the comparison is done, the hardware overwrites the Previous_CC with the Current_CC for the reception of the next packet and so on. If the comparison does not match Current_CC=Previous_CC or Current_CC=Previous_CC+1, the CC_error bit goes active.
Duplicate-packet Flag
If the comparison indicates that Current_CC=Previous_CC the Duplicate-packet goes active.
Hpei (Hardware End of Packet Enable Interrupt)
This is an attribute bit set by Hardware. At reception of a new packet (when packet unit start indicator is active and when it is not a packet with program service information PSI) the Hpei goes active and is reset on the following packet of the same PID. It forces the packet following a packet with a PES header to be temporarily stored in a buffer for further analysis in case the PES header would be split between two packets. This bit is necessary when the bit rate of the incoming bit stream is two high to fit within the EOP service routine latency.
Spei (Software End of Packet Enable Interrupt)
This attribute bit is set by software and covers two different purposes. First, the bit is set at initialization for PID which always requires CPU processing (PID with table information for instance). It is simply used in that case to force all the packets of this PID to be analyzed by the CPU.
The second usage is for audio and video packets whose PES header would be split between two packets. This is only valid for some given system, once the software has determined that its latency response is compatible with the bit stream rate. In that case the software sets the Spei as soon as it receives the EOP interrupt of a packet containing a PES header. It determines afterwards if the PES header overflows on the next packet. If it does not, it resets the Spei attribute bit. In this case the Spei can replace the Hpei which is disabled to gain in efficiency (see En_Hpei).
PSI (Program Service Information Packet Flag)
In MPEG2 transport stream, one flag in the transport stream header (payload unit start indicator) indicates the start of a new PES packet or the start of a section of a program service information. In order to differentiate these two types of data another attribute is needed (PSI). This attribute is set by the firmware at initialization for PIDs containing program service information(PSI).
It is used to generate Hpei and for the detection of the boundary between encrypted/clean bytes. Without this information tightly coupled with the PIDs, the controller could not timely find the encryption flags nor the boundary between encrypted/clean byte without some significant input buffers on the bit stream interface.
Stream-id-filter
This software attribute bit is set by software when it receives a packet containing a PES header with a non selected stream-id. Once this attribute is set, the hardware discards all the packets of this PID containing only payload (AF="1x") until it reaches a new PES header. The packet is sent to the CPU which analyzes the PES header and determines if the new stream-id is valid. If it is, it resets the stream-id-filter for the following packets.
En Hpei
This is a global control bit. The Hpei mechanism can be switched off/on depending on the constraint of the system. If the software determines that it has enough time to react and modify the Spei attribute bit before the reception of the next packet, it can disable the Hpei attribute. The bit stream parsing is more efficient in that case because the packet following a packet with a PES header is only sent to the CPU for further analysis when the PES header is not fully contained in one packet.
En Erroneous P
This global control bit enables transmission of erroneous packets to the temporary buffer. This is mainly to add some flexibility in case some new error concealment is found in the future.
En Duplicate P
This global control bit enables transmission of duplicate packet containing only payload. It is only used for test purposes.
FIG. 17F shows the hardware implementation based on PID recognition. The PID from the Transport packet header 210-5 is compared in parallel with a set of PIDs (32) located in an associative memory 210-10. If the PID in the header corresponds to a PID stored in the associative memory, the CAM encoder outputs a "match" signal (Valid-PID) 210-12 and a CAM address (cam-ad) 210-14 in a single system clock period. The valid-PID is used to initiate the transport stream packet analysis and it enables the process to load the others bits coming from the transport stream headers: AF-load (transport-error, payload-unit-start-indicator, adaptation field flag, continuity counter index and other like encryption flags reserved for the control of the decryption module).
As soon as a valid PID is detected, the cam-ad 210-14 is used to look for the associated attributes. The sequencer 210-16 generates Read-SRAM-attributes to start the state machine controlling the SRAM address generator. The state machine creates the SRAM 240 address from the cam-ad, it reads the SRAM two times, once to retrieve the hardware attributes and a second time to read the software attributes (splitting hardware modified attributes and software modified attributes avoids the use of a complex protection mechanisms).
From both attributes and bit-stream information (bits from headers), the conditions required to generate a EOP interrupt are evaluated. The hardware attributes are then updated for the reception of the next packet (same PID). The software attributes can be updated as part of the EOP interrupt service routine but only for some very precise function (like stream-id-filter). If the attributes need to be modified before the start of the next packet, then the bit rate, the gap between packets and the interrupt routine service latency must respect some constraints to allow this to occur.
Depending on the Packet analyzer control bits (FIG. 17E), the packet is going to be discarded, automatically transmitted to its final destination or processed by the firmware. When one of these conditions to generate an EOP interrupt is met, the bit controlling the interrupt goes active and is reset on the first byte of the following packet. EOP interrupt enable controls the position of the interrupt relative to the end of the packet. The different conditions generating the EOP interrupt
210-20 (FIG. 17E: logic block) are described below.
1 - Erroneous packet If(Te = 1) Normally packets including error are discarded if(En_erroneous_p = 1) but in some cases it might be less disrupting for EOP it the system to enable a small error than to delete else a complete packet. In that case the packet is "discard packet" transmitted to the buffer and the firmware end if makes the final decision depending on the packet type (video, audio, etc. . . . ). 2 - Discontinuity detection elsif(Current_CC = Previous_CC) The EOP packet interrupt will be generated "duplicate packet" after a discontinuity counter detection. In if((AF = "01") and MPEG2 a CC discontinuity is possible when the (En_duplicate_p = 0) discontinuity flas in the adaptation field is set. "discard packet" As shown later, all packets with adaptation field else generate an EOP interrupt. Normally duplicate EOP it packets which contain only payload (AF = "01") end if are discarded. They can be transmitted to let elsif(Current_CC /= Previous_CC + 1) the firmware make the final decision if the EOP it global control bit "En_duplicate_p" is set. 3 - List of other conditions elsif(AF = "1x") An EOP interrupt is generated for: EOP it - all packets containing an adaptation field, elsif(Payload_unit_start_indicator = 1) - all packets whose payload-unit-start-indicator EOP it is set, elsif( Hpei = 1) and (En_Hpei = 1) - all packets following the packets with a EOP it payload-unit-start-indicator set. This is important because the PES header can take more than one packet. This feature can be enabled or disabled if Spei can be set early enough (see FIG. 17G below). elsif( Spei = 1) - all packets which the embedded software EOP it wants to further analyze. elsif(AF = "01" and (((Hpei = 0) and (En_Hpei = 1 )) or (Spei = 0)) and (stream-id = 1)) "discard packet" - all packets containing payload are only else discarded if stream-id is active unless "packet automatically transmitted" attributes to force packets to be analyzed end if by the embedded software are set (previous cases)
Note that all these conditions evaluated sequentially by the foregoing are in fact computed in parallel by the hardware.
Once the EOP interrupt conditions are met the CPU 220 takes on the analysis task. The microprocessor 220 can perform a more complex analysis than the Transport Packet Parser hardware module and will complete the hardware pre-processing. In addition, the processing can differ according on the type of data that corresponds to the packet; in fact, it is very easy to define a software table, based on the PID values, that associates the packet with the particular processing to be used.
The software processing of the transport packet is driven by interrupts; once an EOP interrupt is issued, the process that analyzes the packet is started. Two different methods of processing can be selected, according to the CPU latency response and the bit stream rate.
In first case the software sets the Spei flag in the TPP hardware module as soon as it receives the EOP interrupt of a packet containing a PES header. After processing the packet, the software can detect whether the PES header continues in the following transport packet or not; if the PES header ends in the current packet, the CPU resets the Spei bit in the Packet Analyzer Control Register, since it does not need to analyze the following packet. Otherwise the Spei bit is left unchanged. This method can be used only if the CPU latency, compared with the input bit rate, allows the Spei to be set before the arrival of the following packet.
The second method can be used in any case: If the En_Hpei bit is set in the Packet Analyzer Control Register, the CPU does not have to set the Spei bit after each PES header, because the TPP hardware already provides for sending to the ARM processor the packet including the PES header continuation.
Afterwards the reason of the interrupt is found by reading the flags in the registers of the TPP hardware module; if the adaptation field is present, it is processed.
After the adaptation field analysis the packet can be discarded if there is no payload or the payload is duplicated from the previous packet.
At this point the execution of the software process branches into separate routines, according on the packet type (audio, video, private data, service information, . . . ). Then the data are transferred via a DMA channel to a specific buffer.
FIG. 17G depicts a flowchart that can be used to analyze the packet. The first point in the following list (check of the Pes/Psi start flag and setting of the Spei flag) is optional.
In fact, as mentioned before, if the software latency is short enough to allow the Spei bit to be set before the TPP hardware module analyzes the following transport packet, this operation will minimize the CPU intervention; an EOP interrupt will be sent to the microprocessor only if the packet following a PES header start has to be processed indeed.
Otherwise, if the bit rate of the incoming stream and the CPU latency are too high, the Hpei mechanism can be enabled (En_Hpei=1); the next packet with the same PID following a PES header starting point will be always transmitted to the CPU.
Check if a PES header starts 17-1 in the current transport packet by reading the Pes/Psi start flag in the Packet Analyzer Control Register (Packet Status Word).
If a PES header starts in the current transport packet, the Spei bit 17-2 in the Packet Analyzer Control Register has to be set by the CPU in order to intercept the next packet with the same PID; further, the PES header could continue in the following transport packet.
Check the presence of the adaptation field 17-3 by reading the AF flag in the Packet Analyzer Control Register: Packet Status Word.
If the adaptation field is transmitted into the packet, the associated data have to be processed. In particular, the PCR has to be extracted and filtered in order to control the reconstruction of the reference clock. Another important part consists of the analysis of the discontinuity status 17-4; if the discontinuity status bit in the adaptation field is set, a discontinuity in the continuity counter value does not correspond to a missing packet. If the discontinuity status is set, the local clock has to be re-initialized 17-5 to the PCR value, if present.
Check if the packet is duplicated by reading the duplicate packet flag 17-6 in the Packet Analyzer Control Register.
If the packet is duplicated, it is discarded 17-7; since no other processing is required. If the Spei bit has been modified at the beginning of the packet 17-8 because there is a PES header and the Hpei method is not used, the Spei bit has to be cleared 17-9 before the end of the process.
Check if the packet contains a transport payload by reading the AF flag 17-10 in the Packet Analyzer Control Register.
If there is no payload (adaptation field only) the packet is discarded, since no other processing is required.
This "check the packet" part of the flow diagram is based on a table that associates each selected PID to a particular type of processing to be performed; in this way, the packet is processed by the related routine. The table contains 32
entries, one for each possible selected PID: each entry allows identification of the packet type (i.e. audio packet, video packet, PES private date, PSI, etc.) and the memory address where the data is to be stored. In particular, if the packet type corresponds to a video stream or to an audio stream (in general to an automatic DMA transfer) and the Hpei mechanism is not used, after the packet processing the Spei bit has to be cleared 17-13 if the PES header 17-12 is finished. The data after processing are finally transmitted, via DMA 17-20, to the specific memory buffer.
For the complete flow chart shown in FIG. 17G; the black modules correspond to the logical blocks of the flow chart that are executed only if the Hpei mechanism is disabled.
For example, if the transport stream for a video decoder does not analyze the PES syntax.
In this case only the video elementary stream is sent to the video decoder; the PTS value is extracted and written into a register of the video decoder. All the other fields that could be included in the PES header are not considered, as it is allowed by the DVB recommendations. FIG. 17H describes the structure of the PES packet.
The following steps are used to process the PES packet. The first part of the PES header is stored in a temporary buffer in order to process the interesting fields: if the header is split among different packets, the process continues after the second packet is received and the first bytes of the header have to be written into the temporary buffer.
This example explains only the part related to the PES analysis. For the other part of the CPU processing, the process described earlier herein applies.
Before enabling the PID selection of the TPP hardware module the flags of the TPP control register are initialized as follow:
En_erroneous_p = 0 the packets that contain an error are discarded. En_duplicate_p = 0 the duplicated packets that don't carry an adaptation field are discarded: in this case the payload is identical to the payload of the previous packet. Spei = 0 automatic transfer without the CPU intervention: the packet is intercepted by the CPU only when the conditions described in the previous sections occur. stream-id filter flag = 0 no filter on the stream-id field is required. PSI flag = 0
the video stream is not transmitted by PSI sections, but by using the PES syntax. En_Hpei = 1 the Hpei mechanism is enabled.
The process can also be explained by the following pseudo-code.
PesStatus indicates the status of the PES header processing of the previous status (0=the PES header is finished; 1=the PES header continues from the previous packet and it has not been analyzed yet; 2=the PES header continues from the previous packet and all the useful fields have already been analyzed).
PreviousSize indicates the length of the PES header that has been analyzed in the previous packet and, after the update, the size of the PES packet that has been analyzed in the previous packet plus the size of the PES packet included in the current transport packet.
if(CC-error flag = 1) and There is a continuity counter error but the (discontinuity status = TRUE) discontinuity is not allowed: some of the "start error concealment" previous packets are missed. In this case an appropriate method of error concealment has to be started. if(PES/PSI start flag = 0) and There is no PES header in this packet: all (PesStatus = 0) the payload has to be transferred. "arrange starting point of the data to be transferred" elsif (PesStatus = 2) There is a PES header continuation but all the useful fields have been analyzed in the previous packet. PayloadLength = 184 - Aflength Calculate the payload length in bytes: the payload size is the transport packet size (184 Bytes) minus the adaptation field length. PreviousSize = PreviousSize Update the size. + PayloadLength if(PreviousSize <PES packet length) The PES header does not end in this packet: "no operation" since the PES payload has not started yet, no data have to be transferred. else PesStatus = 0 The PES header ends in this packet: the PES "arrange starting point of the data to be payload has to be transferred. transferred" else PesStatus is not equal to 2: the PES header has not been analyzed yet. PayloadLength = 184 - AFlength Calculate the payload length in bytes: the payload size is the transport packet size (184 Bytes) minus the adaptation field length. "append N bytes to temporary buffer" (N = 14 - PreviousSize) PreviousSize = PreviousSize Update the size. + PayloadLength if(PreviousSize <9) The fixed part of the PES header is not fully included in this packet. PesStatus = 1; else PreviousSize greater or equal to 9: all the flags of the fixed part of the PES header are in this packet. if(pts_flag = 0) No PTS is carried by the PES header. if(PreviousSize < PES header length) No more useful fields but the PES header does PesStatus = 2; not end in this packet. else PesStatus = 0; "arrange starting point of the data to be transferred" The PES header ends in this packet: the PES payload has to be transferred. else The PES header contains a PTS. if (PreviousSize < 14) The PTS is in the following packet PesStatus = 1; else The PTS is in this packet. "write PTS to video decoder" if (PreviousSize <PES header length) The header does not end in this packet. PesStatus = 2; else The header is finished. PesStatus = 0; "arrange starting point of the data to be transferred" The PES header ends in this packet: the PES payload has to be transferred.
In this case the packet is sent to the CPU only when the PES header is present: the occurrence can be easily found by checking the value of the PUS indicator in the transport packet header.
Suppose that the video stream is coded in frames with a bit rate of 15 Mbps, if the CPU has to process each packet, it will be interrupted about every 100 .mu.sec.
On the contrary, by using the preliminary filter and routing performed by the TPP hardware, the CPU is interrupted only for each PES packet; if the PES packet length is equivalent at least to the frame size, the interrupts are generated, in the worst case, each 40 ms.
For example, the transport stream for an audio decoder analyzes the PES syntax and a filter on the stream-id field is performed. In this example, the audio decoder can analyze the PES packet but the CPU has to filter all the PES packet with a stream-id different from a specific value, if the stream-id is identical.
The general flow shown in FIG. 17G and described previously herein is used; the following part describes only the specific part of the processing related to the audio PES packet. In particular, the Hpei mechanism is disabled, so the CPU sets the Spei flag every time a transport packet containing the starting point of a PES header is received.
Before enabling the PID selection of the TPP hardware module the flags of the TPP control register are initialized as follow:
En_erroneous_p = 0 the packets that contain an error are discarded. En_duplicate_p = 0 the duplicated packets that don't carry an adaptation field are discarded: in this case the payload is identical to the payload of the previous packet. Spei = 0 automatic transfer without the CPU intervention: the packet is intercepted by the CPU only when the conditions described in the previous sections occur. stream-id filter flag = 1 a filter on the stream-id field is required. PSI flag = 0 the audio stream is not transmitted by PSI sections, but by using the PES syntax. En_Hpei = 0 the Hpei mechanism is disabled, the CPU has to set and reset the Spei bit.
After the initialization, the TPP hardware module discards all the packets until the first PES header is received. At this point an EOP interrupt is issued and the CPU analyze the packet.
If the stream-id value matches a specific pattern, all the PES packet has to be sent to the audio decoder; as a consequence the CPU 220 clears the stream-id filter flag in the Packet Analyzer Control Register and all the transport packets are automatically transmitted to the audio decoder 254. When another PES header is found by the TPP hardware (the packet unit start indicator in the transport header is set), an interrupt is generated and the CPU can perform another filter operation on the stream-id value of the new PES packet.
If the stream-id value does not match the specified pattern, the CPU sets the stream-id flag in the TPP module and all the following transport packets with the same PID are automatically discarded by the hardware until the next PES header.
The process can also be explained by the following pseudo-code. The CPU does not analyze all the PES header, but only the stream-id field.
PesStatus indicates the status of the PES header processing of the previous status (0=the PES header is finished or the PES header continues from the previous packet but the stream-id value has been already filtered; 1=the PES header continues from the previous packet and the stream-id value has not been filtered yet).
PreviousSize indicates the length of the PES header that has been read in the previous packet.
if(stream-id filter flag = 0) and The current packet does not match the (PES/PSI start flag = 0) stream-id filter pattern and there is no "discard the packet" PES header: the packet has to be discarded. else if(CC-error flag = 1) and There is a continuity counter error but the (discontinuity status = TRUE) discontinuity is not allowed: some of the previous "start error concealment" packets are missed. In this case an appropriate method of error concealment has to be started. if(PES/PSI start flag = 0) and There is no PES header in this packet: all the (PesStatus = 0) payload has to be transferred. "arrange starting point of the data to be transferred" else There is a PES header or a PES header continuation. PayloadLength=184-AFlength Calculate the payload length in bytes: the payload size is the transport packet size (184 Bytes) minus the adaptation field length. PreviousSize = PreviousSize Update the size. + PayloadLength if(PreviousSize <4) The stream-id is not included in this packet. The next transport has to be analyzed PesStatus = 1; else PreviousSize greater or equal to 4: the stream-id field is included in this packet. PesStatus = 0; The CPU does not have to analyze the next packet if(stream-id = "pattern") Filter the stream-id field: if the value is equal to a specific pattern, the PES packet is selected "clear stream-id filter flag" Disable the automatic discarding of the packets by the TPP hardware "arrange starting point of the The PES header ends in this packet: the data to be transferred" PES payload has to be transferred. else The stream-id field is different from the specified pattern: the PES packet has to be discarded. "set stream-id filter flag" Enable the automatic discarding of the packets by the TPP hardware "discard the packet"
At this point the Spei bit is cleared only if PesStatus is equal to zero, since the considered part of the PES header has been already processed.
In this case an interrupt is sent to the CPU only when the PES header is present in order to filter the stream-id value. If the stream-id matches the selected value, the following packets are automatically transmitted to the destination buffer; on the contrary, if the stream-id does not match the selected value all the following packets are discarded by the TPP hardware module until the next PES header.
Without this mechanism, the CPU would be forced to receive an interrupt to discard all the transport packets that are included in a PES packet with an unwanted value of stream-id.
FIG. 17I depicts a high-level block diagram of the presently preferred details of the TPP 210 of FIG. 1B. More particularly, it may be seen that the TPP 210 includes the TPP functional block 210-15, a DES functional block 210-25, a DVCR/1934
block 210-30, a DAC 210-40 and a CPU interface 210-50. The TPP block 210-15 performs the functions noted earlier herein. The DES block 210-25 performs any needed decryption. The DVCR/1394 block 210-30 provides data streams to the 1294 connections and/or a digital VCR. The DAC 210-40 is for controlling the VCXO.
FIG. 17J depicts various DSS bitstream packets and their contents.
FIG. 17K depicts preferred circuit for implementing portions of the blocks depicted in FIG. 17I. More particularly, it may be seen how input multiplexors may be employed to switch the input between a DVB or DSS signal. It further illustrates how the header information/data may be temporarily stored in registers and shifted out to perform the header analysis described earlier herein. In addition, it may be seen how incoming data may be buffered in small registers before being sent out as valid data in "bursts" during and following the header analysis; this assumes the header analysis indicates the data is to be stored for subsequent processing.
FIGS. 17L and 17M depict state machines that control the operations of the TPP block. More particularly, FIG. 17L depicts two basic operations; it depicts a "clean" packet to the TC in the upper right portion and an encrypted packet to the IT in the lower left portion. State S20 is the "idle" state of the state machine. In FIG. 17L, "muxheaderdata" controls the multiplexor between the TPP header and the first data word. FIG. 17M depicts an attribute request and writeback series of states that are in the upper left and start with S10. The remainder of FIG. 17M details other transfers.
FIG. 17N depicts the details of the DAC block 210-40 of FIG. 17I.
FIG. 170 depicts the various signals associated with the TPP and its interface with the CPU 220.
FIG. 17P depicts more details of the block 210-30 of FIG. 17I. More particularly, it illustrates the presence of a record and play state machine and registers that a VCR may write to.
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