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United States Patent
6347063
Dosaka , ; et al.
February 12, 2002
Title
Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof
Abstract
A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.
Inventors:
Dosaka; Katsumi
(Hyogo,
JP
)
, Omoto; Toshiyuki
(Hyogo,
JP
)
, Kumanoya; Masaki
(Hyogo,
JP
)
Assignee:
Ubishi Denki Kabushiki Kaisha
(Tokyo,
JP
)
Appl. No.:
618568
Filed:
July 17, 2000
Foreign Application Priority Data
Nov 06, 1992 [JP] 4-322656
Jun 04, 1993 [JP] 5-160265
Current U.S. Class:
365/233
365/196
365/230.03
Field of Search:
365/233,230.03,196
U.S. Patent Documents
4608666
August 1986
Uchida
4894770
January 1990
Ward et al.
4926385
May 1990
Fujishima et al.
5060196
October 1991
Pae et al.
5175707
December 1992
Murotani
5204837
April 1993
Suwa et al.
5208779
May 1993
Walther et al.
5226009
July 1993
Arimoto
5321843
June 1994
Shoji et al.
5353427
October 1994
Fujishima et al.
5523981
June 1996
Yamaguchi et al.
5535174
July 1996
Harston
5636176
June 1997
Hashimoto et al.
Foreign Patent Documents
1-146187
Jun., 1989
JP
2 235 314
Jul., 1990
GB
40 41 408
Aug., 1992
DE
62-38590
Feb., 1987
JP
Other References
"Writing to a Port", Intel Corp.: Embedded Controller Handbook 1988, pp. 6-4, 6-5. .
"Open-Collector-Bus", by Farber: Bussysteme, 2nd Edition, Munchen: R. Oldenbourg Verlag, 1987, pp. 36-37. .
"Integrated Cached DRAM Lets Data Flow at 100 MHz", by Bursky, Electronic Design, Feb. 20, 1992, pp. 142, 144 and 146. .
"A Circuit Design of Intelligent Cache DRAM with Automatic Write-Back Capability", by Arimoto et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 560-565. .
"A 60-ns 3.3-V-Only 16 Mbit DRAM with Multipurpose Register", by Arimoto et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1184-1190..~
Primary Examiner:
Hoang; Huan
Attorney, Agent or Firm:
McDermott, Will & Emery
Parent Case Text
This application is a Continuation of application Ser. No. 09/007,229 filed Jan. 14, 1998, now U.S. Pat. No. 6,151,269 which is a Divisional of application Ser. No. 08/149,680 filed Nov. 8, 1993, now U.S. Pat. No. 5,777,942.
Claims
What is claimed is:
1. A semiconductor memory device taking an externally applied control signal in synchronization with a clock signal applied externally in a pulse sequence for generating an internal control signal, comprising:
a first array including a plurality of first type memory cells arranged in a matrix of rows and columns;
first control means responsive to said clock signal for taking a first external control signal for generating a control signal to drive said first array;
a second array including a plurality of second type memory cells arranged in a matrix of rows and columns;
input/output circuit means for inputting and outputting data to and from an outside of the memory device;
data transfer means for transferring data with said input/output circuit means and for transferring data between a selected memory cell of said first array and a selected memory cell in said second array;
second control means for taking an externally applied second control signal in response to said clock signal for generating a control signal to drive at least one of said second array and said data transfer means;
first clock gate means responsive to a first clock mask signal for inhibiting transfer of said clock signal to said first control means; and
second clock gate means responsive to a second clock mask signal for inhibiting transfer of said clock signal to said second control means.
2. A semiconductor memory device for taking an external signal in synchronization with a clock signal applied in the form of a pulse, comprising:
a first array including a plurality of first type memory cells arranged in a matrix of rows and columns;
first control means responsive to said clock signal for taking a first external control signal for generating a control signal to drive said first array;
a second array including a plurality of second type memory cells arranged in a matrix of rows and columns;
data transfer means for transferring data at least between a selected memory cell of said first array and a selected memory cell of said second array;
command register means for storing command data for setting a special operation mode of said semiconductor memory device and arrangement of data input and output pins of said semiconductor memory device; and
writing means responsive to said clock signal for storing a prescribed number of bits of an address for selecting a column of said first array in said command register means as the command data.
3. A semiconductor memory device for taking an external signal in synchronization with a clock signal applied in the form of a pulse, comprising:
a first array including a plurality of first type memory cells arranged in a matrix of rows and columns;
a second array including a plurality of second type memory cells arranged in a matrix of rows and columns;
data transfer means for carrying out at least data transfer between a selected memory cell in said first array and a selected memory cell in said second array;
command register means for storing command data for designating at least a special operation mode of said semiconductor memory device; and
means responsive to a combination of external control signal states applied in synchronization with said clock signal, taking in signals currently applied to address input nodes receiving an address for selecting a row and a column of said first array as command data, and taking a part of the currently applied signals as data for designating a type of data transfer mode to said first array of said data transfer means and as data for designating a test mode of said semiconductor memory device, for storing the data in said command register means.
4. The semiconductor memory device according to claim 3, further comprising, means when said test mode is designated, for carrying out auto refresh of said first array.
5. The semiconductor memory device according to claim 3, further comprising means responsive to a combination of said external control signal states for carrying out only setting of said command data at said command register means.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a main memory with a large storage capacity and a high speed cache memory with a small storage capacity integrated on the same chip. More specifically, the present invention relates to a semiconductor memory device containing a cache having a Dynamic Random Access Memory (DRAM) and a Static Random Access Memory (SRAM) integrated on the same chip.
2. Description of the Background Art
(i) Usage of Standard DRAM as a Main Memory
Operation speed of recent microprocessing unit (MPU) has been so much increased as to have operation clock frequency as high as 25 MHz or higher. In a data processing system, a standard DRAM (Dynamic Random Access Memory) is often used as a main memory having large storage capacity, since cost per bit is low. Although access time in the standard DRAM has been reduced, the speed of operation of the MPU has been increased much faster than that of the standard DRAM. Consequently, in a data processing system using the standard DRAM as a main memory, increase of wait state is inevitable. The gap in speed of operation between MPU and the standard DRAM is inevitable because the standard DRAM has the following characteristics.
(1) A row address and a column address are time divisionally multiplexed and applied to the same address pin terminals. The row address is taken in the device at a falling edge of a row address strobe signal/RAS. The column address is taken in the device at a falling edge of a column address strobe signal/CAS. The row address strobe signal/RAS defines start of a memory cycle and activates row selecting circuitry. The column address strobe signal/CAS activates column selecting circuitry. Since a prescribed time period called "RAS-CAS delay time (tRCD)" is necessary from the time the signal/RAS is set to an active state to the time the signal/CAS is set to the active state, there is a limit in reducing the access time, namely, there is a limit derived from address multiplexing.
(2) When the row address strobe signal/RAS is once raised to set the DRAM to a standby state, the row address strobe signal/RAS cannot fall to "L" again until a time period called a RAS precharge time (tRP) has lapsed. The RAS precharge time is necessary for surely precharging various signal lines in the DRAM to predetermined potentials. Due to the RAS precharge time tRP, the cycle time of DRAM cannot be reduced. In addition, when the cycle time of the DRAM is reduced, the number of charging/discharging of signal lines in the DRAM is increased, which increases current consumption.
(3) The higher speed of operation of the DRAM can be realized by circuit technique such as improvement of layout, increase of degree of integration of circuits, development in process technique and by applicational improvement such as improvement in the method of driving. However, the speed of operation of the MPU is increased at much faster rate than DRAM. The speed of operation of semiconductor memories is hierarchical. For example, there are high speed bipolar RAMs using bipolar transistors such as ECLRAMs (Emitter Coupled RAM) and Static RAM, and relatively low speed DRAMs using MOS transistors (insulated gate type field effect transistors). It is very difficult to expect the operation speed (cycle time) as fast as several tens ns (nano seconds) in a standard DRAM formed of MOS transistors.
There have been various applicational improvements to stop the gap between speed of operations of the MPU and the standard DRAM. Such improvements mainly comprise the following two approaches.
(1) Use of high speed mode of the DRAM and interleave method
(2) External provision of a high speed cache memory (SRAM).
The first approach (1) includes a method of using a high speed mode such as a static column mode or a page mode, and a method of combining the high speed mode and the interleave method. In the static column mode, one word line (one row) is selected, and thereafter only the column address is changed successively, to successively access memory cells of this row. In the page mode, one word line is selected, and then column addresses are successively taken by toggling the signal/CAS to successively access memory cells connected to the selected one word line. In either of these modes, memory cells can be accessed without toggling the signal/RAS, enabling higher speed accessing than the normal access using the signals/RAS and/CAS.
In the interleave method, a plurality of memories are provided in parallel to a data bus, and by alternately or successively accessing the plurality of memories, the access time is reduced in effect. The use of high speed mode of the DRAM and combination of the high speed mode and the interleave method have been known as a method of using the standard DRAM as a high speed DRAM in a simple and relatively effective manner.
The second approach (2) has been widely used in a main frame art. A high speed cache memory is expensive. However, in the field of personal computers in which high performance as well as low cost are desired, this approach is employed in some parts of the field with a sacrifice of cost. There are three possible ways to provide the high speed cache memory. Namely,
(a) the high speed cache memory is contained in the MPU itself;
(b) the high speed cache memory is provided outside the MPU; and
(c) the high speed cache memory is not separately provided but the high speed mode supported in the standard DRAM is used as a cache (the high speed mode is used as a pseudo cache memory). When a cache hit occurs, the standard DRAM is accessed in the high speed mode, and at the time of a cache miss, the standard DRAM is accessed in the normal mode.
The above mentioned three ways (a) to (c) have been employed in the data processing systems in some way or other. In most MPU systems, the memories are organized in a bank structure and interleaving is carried out on bank by bank basis in order to conceal the RAS precharge time (tRP) which is inevitable in the DRAM, in view of cost. By this method, the cycle time of the DRAM can be substantially one half that of the specification value.
The method of interleave is effective only when memories are sequentially accessed. When the same memory bank is to be continuously accessed, it is ineffective. Further, substantial improvement of the access time of the DRAM itself cannot be realized. The minimum unit of the memory must be at least 2 banks.
When the high speed mode such as the page mode or the static column mode is used, the access time can be reduced effectively only when the MPU successively accesses a certain page (data of a designated one row). This method is effective to some extent when the number of banks is comparatively large, for example 2 to 4, since different rows can be accessed in different banks. When the data of the memory requested by the MPU does not exist in the given page, it is called a "miss hit" (cache miss). Normally, a group of data are stored in adjacent addresses or sequential addresses. In the high speed mode, a row address, which is one half of the addresses, has been already designated, and therefore possibility of "miss hit" is high.
When the number of banks becomes as large as 30 to 40, data of different pages can be stored in different banks, and therefore the "miss hit" rate is remarkably reduced. However, it is not practical to provide 30 to 40 banks in a data processing system. In addition, if a "miss hit" occurs, the signal/RAS is raised and the DRAM must be returned to the precharge cycle in order to re-select the row address, which sacrifices the characteristic of the bank structure.
In the above described second method (2), a high speed cache memory is provided between the MPU and the standard DRAM. In this case, the standard DRAM may have relatively low speed of operation. Standard DRAMs having storage capacities as large as 4M bits or 16M bits have come to be used. In a small system such as a personal computer, the main memory thereof can be formed by one or several chips of standard DRAMs. External provision of the high speed cache memory is not so effective in such a small system in which the main memory can be formed of one standard DRAM. If the standard DRAM is used as the main memory, the data transfer speed between the high speed cache memory and the main memory is limited by the number of data input/output terminals of the standard DRAM, which constitutes a bottleneck in increasing the speed of the system.
When the high speed mode is used as a pseudo cache memory, the speed of operation thereof is slower than the high speed cache memory, and it is difficult to realize he desired system performance.
Provision of the high speed cache memory (SRAM) in he DRAM is proposed as a method of forming a relatively inexpensive and small system, which can solve the problem of sacrifice of system performance when the interleave method or the high speed operation mode is used. More specifically, a single chip memory having a hierarchical structure of a DRAM serving as a main memory and a SRAM serving as a cache memory has been conceived. The one-chip memory having such a hierarchical structure is called a cache DRAM (CDRAM).
Normally in a CDRAM, a DRAM and an SRAM are integrated on the same chip. At the time of a cache hit SRAM is accessed, while at the time of a cache miss, the DRAM is accessed. Namely, the SRAM operating at high speed is used as a cache memory and the DRAM having a large storage capacity is used as a main memory.
The so called block size of the cache is considered to be the number of bits the contents of which are rewritten in one data transfer in SRAM. Generally, when the block size becomes larger, the hit rate is increased. However, if the cache memory has the same size, the number of sets is reduced in inverse proportion to the block size, and therefore the hit rate is decreased. For example, when the cache size is 4K bits and the block size is 1024, the number of sets is 4. However, if the block size is 32, the number of sets is 128. Therefore, in the conventional CDRAM structure, the block size is made too large, and the cache hit rate cannot be very much improved. A structure enabling reduction in block size is disclosed in, for example, Japanese Patent Laying-Open No. 1-146187.
FIG. 217 shows the whole structure of the conventional CDRAM disclosed in the aforementioned laid-open application. Referring to FIG. 217, the conventional CDRAM includes a memory array 1 including a plurality of dynamic memory cells arranged in a matrix of rows and columns. Memory array 1 is divided into a plurality of memory blocks B#1 to B#4 each including a plurality of columns. Memory blocks B#1 to B#4 share word lines.
The conventional CDRAM further includes a row address buffer 2 taking externally applied address signals A0 to An as a row address signal RA in response to an external row address strobe signal /RAS and generating an internal row address signal; a column address buffer 4 taking address signals A0 to An as a column address signal CA in response to an external column address strobe signals /CAS for generating an internal column address signal; a row decoder 6 responsive to the internal row address signal from row address buffer 2 for generating a signal to select a corresponding row in memory cell array 1; a word driver 8 responsive to a row selecting signal from row decoder 6 for transmitting a driving signal to the selected row of memory cell array 1 to set a word line corresponding to the designated row to a selected state; a sense amplifier group 10 for sensing, amplifying and latching data of the memory cells connected to the selected row in memory cell array 1; a data register circuit 14
including a plurality of data registers provided corresponding to each column of the memory cell array 1; a transfer gate circuit 12 for transferring data between each column of memory cell array 1 and data register circuit 14; an IO gate 16 for decoding the internal column address signal from column address buffer 4 to select a corresponding column of memory cell array 1 or a corresponding data register in data register circuit 14; a block decoder 18 responsive to an externally applied cache hit/miss designating signal CH for selecting a corresponding block in memory cell array 1; an input buffer 24 and an output buffer 26 for inputting/outputting data from and to the outside of the device; a column decoder 20 for decoding the internal column address signal from column address buffer 4 for generating a signal for selecting and connecting the corresponding column of memory cell array 1 or the corresponding data register of data register circuit 14 through IO gate circuit 16 to input buffer 24 and output buffer 26; and a read/write control circuit 28 for controlling enabling/disabling of input buffer 24 and output buffer 26 in response to an externally applied write enable signals /WE and to the column strobe signal /CAS.
Transfer gate circuit 12 and data register circuit 14 are divided into blocks, respectively, corresponding to the blocks B#1 to B#4 of the memory cell array.
The CDRAM further includes a gate circuit 22 responsive to an externally applied cache hit/miss signal CH for transmitting a column address signal, which is, for example, lower 2 bits from column address buffer 4, as a block selecting signal to block decoder 18. Block decoder 18 is activated when cache hit/miss signal CH indicates a cache miss of "L", decodes the applied block address signal to select a corresponding memory cell block in the memory cell array 1, and drives block by block the transfer gate circuit 12 for transferring data between the selected memory cell array blocks and the data register corresponding to the selected memory cell array block.
FIG. 218 shows a structure of a main portion of the semiconductor memory device shown in FIG. 217. FIG. 218 shows a structure at the boundary region between two memory blocks B#1 and B#2.
Referring to FIG. 218, sense amplifier group 10 includes sense amplifiers SA#1 each provided corresponding to each bit line pair BL, /BL of memory block B#1 and sense amplifiers SA#2 each provided corresponding to each bit line pair BL, /BL of memory block B#2. Sense amplifiers SA#1 and SA#2 differentially amplify and latch the signals on the corresponding bit line pair BL, /BL when they are activated.
Transfer gate circuit 12 includes transfer gates DT#1 each provided for each bit line pair BL, /BL of memory block B#1 and transfer gates DT#2 each provided corresponding to each bit line pair BL /BL of memory block B#2. Transfer gates DT#1
provided for memory block B#1 are driven independent from transfer gates DT#2 provided for memory block B#2. More specifically, transfer gates DT#1 provided corresponding to memory block B#1 are driven by a block decoder circuit BD#1 provided for memory block B#1, while transfer gates DT#2 provided for memory block B#2 are driven by a block decoder circuit BD#2 provided for memory block B#2. Block decoder circuits BD#1 and BD#2 decode a block address transmitted at a time of cache miss from gate circuit 22 shown in FIG. 217, and drive a related transfer gate DT (#1 or #2) when the block address indicates a corresponding memory block.
A data register circuit 14 includes a register DR#1 provided corresponding to each bit line pair BL, /BL of memory block B#1 for latching data applied through transfer gate DT#1, and a register DR#2 receiving and storing data on the bit line pair BL, /BL of memory block B#2 through transfer gate DT#2. Data registers DR (#1 and #2) have a structure of an inverter latch circuit.
IO gate circuit 16 includes an IO gate TG provided for each of the bit line pairs BL, /BL of the memory blocks B#1 and B#2, responsive to a column selecting signal from column decoder 20 for connecting the corresponding bit line pair BL, /BL to an internal data transmitting line pair IO. IO gate TG connects the bit line pair BL, /BL of memory blocks B#1 and B#2 to internal data transmitting line pair IO through transfer gate circuit 12 and data register circuit 14. Therefore, when transfer gate circuit 12 is off (cut off state), IO gate TG connects the data register included in data register circuit 14 to internal data transmitting line pair IO. The operation of the semiconductor memory device shown in FIGS. 217 and 218 will be described with reference to the diagram of waveforms of FIG. 219.
The semiconductor memory device shown in FIG. 217 is used in a system including a CPU as an external processing device and a controller for controlling access to the semiconductor memory device in accordance with a request from the CPU. The controller includes a tag memory for storing tag addresses of data stored in data register circuit 14, a comparing circuit for determining coincidence/noncoincidence between a tag address stored in the tag memory and a portion of the address from the CPU (CPU address) corresponding to the tag address for generating a signal CH indicative of a cache hit/cache miss in accordance with the result of determination, and a control circuit (a state machine and an address multiplexer) for controlling address supply and access to the semiconductor memory device in accordance with the result of determination of the comparing circuit.
An address is supplied from the CPU in synchronization with the system clock. When the CPU address designates data stored in data register circuit 14, the externally provided controller sets the cache hit signal CH to "H" which corresponds to the active state. At this time, if the row address strobe signal /RAS is at active "L", the external controller toggles the column address strobe signal /CAS and extracts a column address CA from the CPU address and applies the same to the semiconductor memory device.
In the semiconductor memory device, the applied column address signal CA is taken by a column address buffer 4 which generates an internal column address signal and applies the same to column decoder 20. Since the cache hit signal CH is at "H", the output from gate circuit 22 is at "L", the block decoder 18 is at disabled state (or transmission of block address is inhibited), and block selecting operation is not carried out. In this case, column selecting operation is effected by column decoder 20, the corresponding data register is connected to the internal data line pair IO, and writing of data to or reading of data from the selected data register is carried out. Whether data is to be written or read depends on the write enable signal /WE.
While the data requested by the CPU is stored in data register circuit 14, the cache hit signal CH is at "H", and the corresponding data register of data register circuit 14 is selected in accordance with the column address signal CA.
When the CPU address does not designate the data stored in data register circuit 14 the cache hit signal CH is at the "L" state. At a time of a cache miss, the external controller once raises the signals /RAS and /CAS to "H", then lowers the row address strobe signal /RAS to "L", extracts row address signal RA from the CPU address and applies the same to the semiconductor memory device.
In the semiconductor memory device, row selecting operation in memory cell array i is carried out by row address buffer 2, row decoder 6 and word driver 8 in accordance with the applied row address signal RA, and the data of the memory cell connected to the selected row is detected, amplified and latched by sense amplifier group 10. In parallel with these operations, column address strobe signal /CAS is lowered to "L", and the column address signal CA is extracted from the CPU address and applied to the semiconductor memory device. In the semiconductor memory device, since the cache hit signal CH is at "L", block decoder 18 is activated and the block address signal of the applied column address signal is applied to the block decoder 18.
Block decoder 18 decodes the block address, and turns on all transfer gates provided corresponding to the memory block indicated by the block address. Consequently, in the selected memory block, data latched by the sense amplifier SA is transmitted to data register DR (#1 or #2). In parallel, column decoder 20 carries out column selecting operation, renders conductive the transfer gate TG included in IO gate circuit 16, and connects the data register DR to internal data transmission line pair IO.
Thereafter, if cache hit is continued with the row kept at the selected state in the memory array 1, data register DR (#1 or #2) is selected by the column decoder 20 to be accessed.
By dividing the memory array into blocks and driving the data registers block by block as described above, the data register can be used as a cache. In this case, as shown in FIG. 220, data registers TR#1 to TR#4 provided corresponding to the memory array blocks B#1 to B#4, respectively, can store data of different rows, thereby improving cache hit rate, and in addition, the block size of the cache can be made the same as the number of columns included in the memory block, realizing appropriate size of the cache block.
In the semiconductor memory device such as described above, the DRAM array is used as a main memory, and the data register circuit can be used as a cache. Since data transfer between the main memory and the cache is effected on block by block basis, data can be transferred at high speed.
An application of the semiconductor memory device as described above, that is, a CDRAM to graphic data processing will be discussed.
FIG. 221 shows a structure of a general graphic data processing system. Referring to FIG. 221, the system includes a CPU 30 as a processing device, a CDRAM 32, a CRT 34 as a display, and a CRT controller 36 for controlling data transfer between CDRAM 32 and CRT 34. CPU 30, CDRAM 32 and CRT 34 are connected to an internal data bus 38. Data transfer is carried out through internal data bus 38.
CDRAM 32 stores both graphic data to be displayed and data utilized by CPU 30 which are not displayed. When the graphic data is to be displayed on CRT 34, data transfer between CDRAM 32 and CRT 34 is carried out under the control of CRT controller 36. Data read from CDRAM 32 is applied to CRT 34 through data bus 38, and is displayed on a display screen of a display, not shown.
When data stored in CDRAM 32 is to be processed, CPU 30 accesses CDRAM 32. At that time, CPU 30 can access CDRAM 32 at high speed in accordance with the result of determination of cache hit/cache miss, and therefore data can be processed at high speed. The data accessed by the CPU 30 should preferably be stored in the cache region of CDRAM 32. Assume that CRT controller 36 reads data in the memory array 1 of CDRAM 32 and transmits the same to CRT 34 for display.
In such a case, it is necessary in the CDRAM having the above described structure that row selecting operation and the column selecting operation are carried out under the control by the CRT controller 36. Data in the memory array 1 is read through data register circuit 14. Therefore, in this case, data stored in the data register circuit to be used as a cache may be rewritten by data to be displayed on CRT 34. When image data generated from a video camera (not shown) or the like is to be written to CDRAM 32, cache data stored into data register circuit 14 is rewritten by the image data applied for writing to the main memory of the CDRAM 32, in this case also.
Therefore, in the above described CDRAM, writing and reading of data of the main memory cannot be carried out unless the data for the cache is changed. Accordingly, it is difficult to store both the graphic data and the data such as application programming which is not displayed, in the CDRAM.
In the conventional structure of the CDRAM, block division arrangement is employed when a DRAM main memory having large storage capacity is used. In that case, a block structure in which the memory array shown in FIG. 218 or 220 is used as one block is utilized. In the block division structure, only that block which includes a selected word line is activated, and other blocks are maintained at the inactive state. Accordingly, the number of available data registers is small correspondingly, which lowers the efficiency of use of the cache.
When there is only one row of data registers as in the structure of the CDRAM shown in FIG. 218, the mapping method which can be implemented is only the direct mapping method. In order to implement mapping of set associative method, it necessary to provide a plurality of rows of data registers. The direct mapping method and the set associative method cannot both be met. Only one of this mapping can be implemented.
In the CDRAM having the above described structure, access to 1 bit of data register can be carried out in parallel with data transfer from the DRAM array to the data register. However, unlike a common dual port video RAM, DRAM portion cannot be accessed in parallel with the access to the SRAM without affecting the access to the SRAM array by driving the DRAM portion and the SRAM portion independent from each other.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a CDRAM having a novel structure allowing data reading and writing at high speed.
Another object of the present invention is to provide a CDRAM which has particular applicability to graphic data processing.
A yet another object of the present invention is to provide a CDRAM allowing data writing and reading to and from the DRAM without affecting cache data.
The semiconductor memory device in accordance with the present invention includes a DRAM including a plurality of dynamic memory cells arranged in a matrix of rows and columns, an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns, and data transfer means for simultaneously carrying out data transfer between a plurality of selected memory cells of the DRAM and a plurality of selected memory cells of the SRAM array. The semiconductor memory device of the present invention further includes control means for independently effecting control of operation related to the DRAM array and control of operation related to the SRAM array, and means for externally and directly accessing the data transfer means.
Further, the semiconductor memory device of the present invention includes novel structure for realizing various characteristic functions.
Briefly stated, in the semiconductor memory device in accordance with the present invention, data transfer between the DRAM array and the SRAM array can be carried out by using a page mode of the DRAM in order to drive the DRAM array and the SRAM array independent from each other. Since direct access to the data transfer means is possible, in other words writing of data to and reading of data from the data transfer means can be carried out not through the SRAM array, writing and reading of data in the DRAM array can be carried out without any influence to the cache data stored in the SRAM array, and therefore the graphic data and the cache data can both be stored in the DRAM array.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a whole structure of a semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 2 shows, in a table, correspondence between the states of control signals of the semiconductor memory device and the operation modes carried out at that time.
FIG. 3 is a diagram of waveforms showing the operation of a SRAM power down mode of the semiconductor memory device shown in FIG. 1.
FIG. 4 is a diagram of signal waveforms showing the operation of a deselect SRAM mode of the semiconductor memory device shown in FIG. 1.
FIG. 5 shows a structure of a SRAM control portion of the semiconductor memory device shown in FIG. 1.
FIG. 6 shows an example of a structure of a buffer circuit receiving external signals in the semiconductor memory device shown in FIG. 1.
FIG. 7 shows a structure of a buffer circuit receiving a chip enable signal in the semiconductor memory device shown in FIG. 1.
FIG. 8 is a diagram of signal waveforms showing an SRAM read mode of the semiconductor memory device shown in FIG. 1.
FIG. 9 shows data flow in the SRAM read mode operation.
FIG. 10 is a diagram of signal waveforms showing an SRAM write mode operation.
FIG. 11 shows the flow of data in the SRAM write mode operation.
FIG. 12 is a diagram of signal waveforms showing a buffer read transfer mode operation.
FIG. 13 shows the flow of data in the buffer read transfer mode operation.
FIG. 14 is a diagram of waveforms showing a buffer write transfer mode operation.
FIG. 15 shows the flow of data in the buffer write transfer mode.
FIG. 16 is a diagram of signal waveforms showing a buffer read transfer/SRAM read mode operation.
FIG. 17 shows the flow of data in the buffer read transfer and SRAM read mode operation.
FIG. 18 is a diagram of waveforms showing the buffer write transfer and SRAM write operation mode.
FIG. 19 shows the flow of data at the buffer write transfer and the SRAM write operation mode.
FIG. 20 is a diagram of waveforms showing the buffer read mode operation.
FIG. 21 shows the flow of data in the buffer read mode operation.
FIG. 22 is a diagram of signal waveforms showing the buffer write mode operation.
FIG. 23 shows the flow of data in the buffer write mode operation.
FIG. 24 shows, in a table, the operations related to the DRAM of the semiconductor memory device shown in FIG. 1 and the states of control signals for implementing these operations.
FIG. 25 is a diagram of waveforms showing a DRAM power down mode operation.
FIG. 26 is a diagram of signal waveforms showing a DRAM NOP mode.
FIG. 27 is a diagram of signal waveforms showing the DRAM read transfer mode operation.
FIG. 28 shows the flow of data in the DRAM read transfer mode operation.
FIG. 29 is a diagram of signal waveforms showing the DRAM write transfer mode operation.
FIG. 30 shows the flow of data in the DRAM write transfer mode operation.
FIG. 31 shows a structure for controlling operations related to the DRAM portion in the semiconductor memory device shown in FIG. 1.
FIG. 32 shows a chip layout of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 33 shows a structure of the SRAM array portion of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 34 shows a structure of the DRAM array portion of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 35 shows a principle structure of a bi-directional data transfer circuit.
FIG. 36 is a diagram of waveforms showing the principle of data transfer operation from the DRAM array to the SRAM array in the semiconductor memory device shown in FIG. 1.
FIGS. 37A-37D schematically show data transfer operation from the DRAM array to the SRAM array in the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 38 is a diagram of signal waveforms showing data transfer operation from the SRAM array to the DRAM array in the semiconductor memory device in accordance with one embodiment of the present invention.
FIGS. 39A-39D schematically show data transfer operation from the SRAM array to the DRAM array in the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 40 shows a structure of an IO portion of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 41 shows an example of a specific structure of a bi-directional data transfer circuit in the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 42 shows an example of an operation sequence in the semiconductor memory device in accordance with one embodiment of the present invention.
FIGS. 43A and 43B schematically shows the operation represented by the diagram of signal waveforms of FIG. 42.
FIG. 44 shows another operation sequence of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 45 shows an example of a structure of a mask circuit for masking a transfer gate transferring data to the DRAM array.
FIG. 46 shows an example of a circuit structure for generating set and reset signals shown in FIG. 45.
FIGS. 47A and 47B schematically shows the operation of the mask circuit shown in FIG. 45.
FIG. 48 is a diagram of waveforms showing a DRAM auto refresh mode operation.
FIG. 49 is a diagram of waveforms showing a set command register mode operation.
FIG. 50 shows, in a table, command data set at the set command register mode shown in FIG. 49 and the contents set at that time.
FIG. 51 is a diagram of signal waveforms showing the operation of the mask circuit shown in FIG. 45.
FIG. 52 is a diagram of waveforms showing the operation at the time of power on of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 53 shows a structure of a portion related to set command register mode operation in the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 54 shows an example of another structure of the portion related to the set command registered mode in the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 55 shows an example of an operation sequence of the semiconductor memory device utilizing the circuit structure shown in FIG. 54.
FIG. 56 shows an example of a manner of distribution of addresses and command data to the command register and the address buffer in the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 57 shows an example of a structure of a data input/output portion in a semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 58 shows an example of a structure of the input circuit and the input control circuit shown in FIG. 57.
FIG. 59 shows an example of the structure of the output circuit shown in FIG. 57.
FIG. 60 shows a specific example of the structure of the latch circuit shown in FIG. 59.
FIG. 61 shows an example of the structure of the output control circuit shown in FIG. 57.
FIG. 62 is a diagram of waveforms showing a latched output mode operation.
FIG. 63 is a diagram of waveforms showing a registered output mode operation.
FIGS. 64A and 64B are diagrams of signal waveforms showing a transparent output mode operation.
FIGS. 65A and 65B show output timings of output data in the transparent output mode.
FIGS. 66A and 66B show output timings of output data in the registered output mode.
FIGS. 67A and 67B show data output timings in the latched output mode.
FIG. 68 shows required conditions of external signals of the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 69 shows an appearance and pin arrangement of a package accommodating the semiconductor memory device in accordance with one embodiment of the present invention.
FIG. 70 shows a whole structure of a semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 71 shows a structure of the K buffer and the mask circuit shown in FIG. 70.
FIG. 72 shows an example of a structure of the DRAM control circuit and the SRAM control circuit shown in FIG. 70.
FIG. 73 shows a structure of a data input/output portion of the semiconductor memory device shown in FIG. 70.
FIG. 74 shows an example of a data output operation sequence of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 75 shows an example of a structure of a memory system in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 76 shows advantages of the DQ control used in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 77 shows correspondence between the cache and the main memory of the memory system shown in FIG. 76.
FIG. 78 shows a structure when a memory system having a bank structure is formed by using the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 79 shows correspondence between the cache memory and the main memory in the memory system shown in FIG. 78.
FIG. 80 shows another example of the structure of the memory system in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 81 shows correspondence between the cache and the main memory of the memory system shown in FIG. 80.
FIG. 82 shows a structure for generating the DQ control when the memory system shown in FIG. 80 is formed.
FIG. 83 shows functional structure of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 84 is a block diagram showing a structure of the bi-directional data transfer circuit in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 85 shows, in a table, correspondence between states of control signals related to the SRAM portion of the semiconductor memory device and the operation realized at that time in accordance with another embodiment of the present invention.
FIG. 86 shows the flow of data in the SRAM read mode operation.
FIG. 87 shows the flow of data in the SRAM write mode operation.
FIG. 88 shows the flow of data in the buffer read transfer mode.
FIG. 89 shows the flow of data in the buffer write transfer mode operation.
FIG. 90 shows the flow of data in the buffer read transfer and read mode operation.
FIG. 91 shows the flow of data in the buffer write transfer and write mode operation.
FIG. 92 shows the flow of data in the buffer read mode operation.
FIG. 93 shows the flow of data in the buffer write mode operation.
FIG. 94 shows, in a table, correspondence between operations related to the DRAM array and the control signals realizing these operations.
FIG. 95 shows the flow of data at the DRAM read transfer mode operation.
FIG. 96 is a diagram of waveforms showing the operation at the time of DRAM write transfer mode designation.
FIG. 97 shows an example of a structure of a data processing system utilizing the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 98 shows the flow of data in the DRAM write transfer 1 mode operation.
FIG. 99 shows the flow of data in the DRAM write transfer 1/read mode operation.
FIG. 100 is a diagram of waveform showing the DRAM read transfer mode operation.
FIG. 101 is a diagram of waveform showing the DRAM write transfer mode operation.
FIG. 102 shows an example of a circuit structure for generating a control signal for controlling operation of a bi-directional data transfer circuit in a semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 103 shows an example of an operation sequence of a semiconductor memory device in accordance with another embodiment of the present invention.
FIGS. 104A and 104B schematically show the flow of data in the DWT1 mode operation and in DWT2 mode operation shown in FIG. 102.
FIG. 105 is a diagram illustrating the effect of DWT2 mode shown in FIG. 104.
FIG. 106 shows state of connection to a tester at the time of function test of the semiconductor memory device.
FIG. 107 shows states of external control signals in a set command register cycle in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 108 shows a structure of the command data shown in FIG. 107.
FIG. 109 shows, in a table, correspondence between the command data shown in FIG. 108 and the operation modes designated at that time.
FIG. 110 shows a structure of a circuit system controlling internal operation of the semiconductor memory device in accordance with the command data shown in FIG. 108.
FIG. 111 shows an example of a structure of a data processing system utilizing the semiconductor memory device in accordance with another embodiment of the resent invention.
FIG. 112 is a flow chart showing a data reading sequence under the condition of no allocation in the write back mode operation of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 113 is a flow chart showing a data writing sequence under the condition of no allocation in the write back mode of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 114 is a flow chart showing data reading operation sequence under the condition of allocation in write back mode of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 115 is a flow chart showing data writing operation sequence with allocation in the write back mode of the semiconductor memory device in accordance with another embodiment of the preset invention.
FIG. 116 is a flow chart showing the data reading operation sequence with allocation in the write through mode of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 117 is a flow chart showing data writing operation sequence with allocation in the write through mode of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 118 is a flow chart showing the data reading operation sequence with the condition of no allocation in the write through mode of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 119 is a flow chart showing the data writing operation sequence under the condition of no allocation in the write through mode of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 120 shows an example of a structure of a bi-directional data transfer circuit in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 121 shows the flow of data in the buffer write mode operation of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 122 shows the flow of data in the DRAM write transfer mode operation of the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 123 is a diagram of signal waveform showing set and reset operations of the mask register in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 124 is a diagram of signal waveform showing the set/reset operation of mask data of the mask register in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 125 shows a specific structure of a write data transfer buffer circuit in the bi-directional data transfer circuit used in the semiconductor memory device in accordance with the present invention.
FIG. 126 is a diagram of signal waveforms showing the operation of the write data transfer buffer circuit shown in FIG. 125.
FIG. 127 shows a specific structure of a read data transfer buffer circuit in the bi-directional data transfer circuit used in the semiconductor memory device in accordance with another embodiment of the present invention.
FIG. 128 is a diagram of signal waveforms showing the operation of the read data transfer buffer circuit shown in FIG. 127.
FIG. 129 shows a structure for generation control signals used in the data transfer buffer circuits shown in FIGS. 125 and 127.
FIG. 130 shows chip arrangement of the CDRAM in accordance with a third embodiment of the present invention.
FIG. 131 shows internal functional structure of the CDRAM in accordance with the third embodiment of the present invention.
FIG. 132 shows, in a table, external control signals of the CDRAM shown in FIG. 131 and commands designated correspondingly.
FIG. 133 shows, in a table, external control signals of the CDRAM shown in FIG. 131 and operations carried out correspondingly.
FIG. 134 is a timing chart showing the operation at a data reading of the CDRAM shown in FIG. 131.
FIG. 135 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 136 is a timing chart showing the operation at data reading of the CDRAM shown in FIG. 131.
FIG. 137 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 138 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 139 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 140 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 141 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 142 is a timing chart showing data reading operation of the CDRAM shown in FIG. 131.
FIG. 143 is a timing chart showing data writing operation of the CDRAM shown in FIG. 131.
FIG. 144 is a timing chart showing data writing operation of the CDRAM shown in FIG. 131.
FIG. 145 is a timing chart showing data writing operation of the CDRAM shown in FIG. 131.
FIG. 146 is a timing chart showing data writing operation of the CDRAM shown in FIG. 131.
FIG. 147 is a timing chart showing operation sequence at the time of power on of the CDRAM shown in FIG. 131.
FIG. 148 is a timing chart showing an operation at the time of CPU reset of the CDRAM shown in FIG. 131.
FIG. 149 is a timing chart showing the operation in the sleep mode of the CDRAM shown in FIG. 131.
FIG. 150 is a timing chart showing the operation when the sleep mode is released in the CDRAM shown in FIG. 131.
FIG. 151 is a timing chart showing command register read/write operation of the CDRAM shown in FIG. 131.
FIG. 152 shows state transition of the CDRAM shown in FIG. 131.
FIGS. 153A and 153B show a truth stable of external control signals for carrying out command register read/write of the CDRAM and the command register read/write operation of the CDRAM shown in FIG. 131.
FIG. 154 shows the function and structure of command register 00h.
FIG. 155 shows structure and function of command register 01h.
FIG. 156 shows structures and functions of command registers 02h and 03h.
FIG. 157 shows structures and functions of command registers 04h and 05h.
FIG. 158 shows structures and functions of command registers 06h and 07h.
FIG. 159 shows structures and functions of command registers 10h and 16h.
FIG. 160 shows structures and functions of command registers 17h and 1Ch.
FIG. 161 shows, in a table, latencies at the time of reading/writing of the CDRAM shown in FIG. 131.
FIG. 162 shows various parameters of input signals to the CDRAM shown in FIG. 131.
FIG. 163 shows various parameters of output signals of the CDRAM shown in FIG. 131.
FIG. 164 shows a structure of a memory system constituted by the CDRAM.
FIGS. 165A and 165B schematically shows the structure and operation of a data signal output portion of the CDRAM shown in FIG. 164.
FIG. 166 shows a structure of an improved signal output portion of the present invention.
FIG. 167 is a diagram of signal waveforms showing the operation of the signal output portion shown in FIG. 166.
FIG. 168 shows a circuit structure for generating the control signals shown in FIG. 166.
FIG. 169 shows a modification of the circuit shown in FIG. 168.
FIG. 170 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 169.
FIG. 171 is a timing chart showing the operation when a special mode is set.
FIG. 172 is a timing chart showing the operation when a special mode is set.
FIG. 173 shows a structure of a test mode setting circuit.
FIG. 174 shows another structure of the test mode setting circuit.
FIG. 175 shows an example of a structure of a counter shown in FIGS. 173 and 174.
FIG. 176 is a timing chart showing the operation of the counter shown in FIG. 175.
FIG. 177 shows a structure of a memory system having a synchronous self refresh function in accordance with the present invention.
FIG. 178 shows structures of portions related to refreshing of the CDRAM shown in FIG. 177.
FIG. 179 is a diagram of signal waveforms showing the operation of the master portion of FIG. 178.
FIG. 180 is a diagram of signal waveforms showing the operation of the slave portion of FIG. 178.
FIG. 181 shows a structure for generating a precharge completion signal shown in FIG. 178.
FIG. 182 is a diagram of a signal waveforms showing the operation of the circuit shown FIG. 181.
FIG. 183 shows a modification of the circuit shown in FIG. 181.
FIG. 184 shows an example of the first arbiter structure shown in FIG. 178.
FIG. 185 shows an example of the second arbiter structure shown in FIG. 178.
FIG. 186 shows an example of a structure of the RAS buffer and the refresh control circuit shown in FIG. 178.
FIG. 187 shows a structure of another embodiment of the refresh control system.
FIG. 188 shows another example of the structure of the memory system having the synchronous self refresh function.
FIG. 189 shows an example of data transfer operation between the DRAM array and the SRAM array.
FIG. 190 shows a second step of data transfer operation between the DRAM array and the SRAM array.
FIG. 191 shows a third step of data transfer operation between the DRAM array and the SRAM array.
FIG. 192 shows the fourth step of data transfer operation between the DRAM array and the SRAM array.
FIG. 193 shows the fifth step of data transfer operation between the DRAM array and the SRAM array.
FIG. 194 shows a sixth step of data transfer operation between the DRAM array and the SRAM array.
FIG. 195 shows the seventh step of data transfer operation between the DRAM array and the SRAM array.
FIG. 196 shows the eighth step of data transfer operation between the DRAM array and the SRAM array.
FIG. 197 shows the ninth step of data transfer operation between the DRAM array and the SRAM array.
FIG. 198 shows the tenth step of data transfer operation between the DRAM array and the SRAM array.
FIG. 199 shows the eleventh step of data transfer operation between the DRAM array and the SRAM array.
FIG. 200 shows the twelfth step of data transfer operation between the DRAM array and the SRAM array.
FIGS. 201A and 201B are a timing chart showing data transfer sequence between the DRAM array and the SRAM array.
FIGS. 202A and 202B show data transfer sequence between the DRAM array and the SRAM array.
FIGS. 203A and 203B are a timing chart of the data transfer operation sequence between the DRAM array and the SRAM array.
FIGS. 204A and 204B are a timing chart showing data transfer operation sequence between the DRAM array and the SRAM array.
FIG. 205 shows an example of correspondence between the read transfer instruction and the external control signals.
FIG. 206 shows another example of the structure of the data transfer circuit from the SRAM array to the DRAM array.
FIG. 207 shows an example of the image processing system employing the CDRAM in accordance with the present invention.
FIG. 208 schematically shows the operation of the image processing system shown in FIG. 207.
FIG. 209 is a timing chart showing the access sequence of the CDRAM in the image processing system shown in FIG. 207.
FIG. 210 is a timing chart showing the access sequence of the CDRAM in the image processing system shown in FIG. 207.
FIGS. 211(a)-211(c) is a timing chart showing an operation sequence of writing video data to the CDRAM.
FIGS. 212(a)-212(c) is a timing chart showing video data writing operation to the CDRAM and the DRAM.
FIGS. 213(a)-213(c) is a timing chart showing an operation of reading video data of the SDRAM and CDRAM.
FIGS. 214(a)-214(c) is a timing chart showing an operation of video data writing to the SDRAM and CDRAM.
FIGS. 215(a)-215(c) is a timing chart showing read modify write operation on the video data of the SDRAM and CDRAM.
FIGS. 216(a)-216(c) is a timing chart showing operation of writing the video data to the SDRAM/DRAM and the CDRAM.
FIG. 217 shows a whole structure of a conventional semiconductor memory device containing a cache.
FIG. 218 shows a structure of a main portion of the semiconductor memory device shown in FIG. 217.
FIG. 219 is a diagram of waveform showing the operation sequence of the conventional semiconductor memory device containing a cache.
FIG. 220 schematically shows data transfer in the conventional semiconductor memory device containing a cache.
FIG. 221 shows an example of a structure of a data processing system including a display, using a semiconductor memory device containing a cache.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[Embodiment 1]
FIG. 1 is a block diagram showing a whole structure of a semiconductor memory device in accordance with one embodiment of the present invention. The semiconductor memory device includes a DRAM portion and an SRAM portion which SRAM portion is used as a cache memory, and therefore it will be referred to as a semiconductor memory device containing a cache (CDRAM) in the following description.
Referring to FIG. 1, a CDRAM 100 includes a DRAM array 102 including a plurality of dynamic memory cells arranged in a matrix of rows and columns, an SRAM array 104 including a plurality of static memory cells arranged in a matrix of rows and columns, and a data transfer circuit 106 for transferring data between DRAM array 102 and SRAM array 104. CDRAM 100 has a structure allowing input/output of data on 4 bits by 4 bits basis, and therefore DRAM array 102 includes four memory planes 102a,
102b, 102c and 102d. Memory planes 102a to 102d of the DRAM array correspond respectively to different bits of data bits which are input/output at one time.
SRAM array 104 similarly includes four memory planes 104a, 104b, 104c and 104d. Data transfer circuit 106 also includes four planes 106a, 106b, 106c and 106d in order to transfer data between the DRAM array memory planes 102a to 102d and the SRAM array memory planes 104a to 104d, plane by plane. CDRAM 100 includes a DRAM address buffer 108 receiving externally applied DRAM addresses Ad0 to Ad11 for generating internal addresses, a row decoder 110 receiving internal row addresses ROW0 to ROW11 from DRAM address buffer 108 for selecting a corresponding row of the DRAM array 100, a column block decoder 112 receiving prescribed bits of the internal column address signals from the DRAM address buffer, that is, column block addresses Col4 to
9 for simultaneously selecting a plurality of columns (in this embodiment, 16 bits of memory cells) in the DRAM array, a sense amplifier for detecting and amplifying data of the memory cells selected in the DRAM array, and an IO control for transferring data between the selected memory cell in the DRAM array 102 and the data transfer circuit, in order to drive the DRAM array. In FIG. 1, the sense amplifier and the IO control are represented by one block 114 in FIG. 1.
DRAM address buffer 108 receives in multiplexed manner the row and column addresses. 4 bits of data of the addresses Ad0 to Ad3 are used as commands for designating data transfer mode in the data transfer circuit and for designating set/reset of mask data when masking is to be effected.
CDRAM 100 further includes an SRAM address buffer 116 receiving externally applied SRAM address signals As0 to As11 for generating internal addresses; a row decoder 118 decoding addresses As4 to As11 from SRAM address buffer 116 for selecting a corresponding row of SRAM array 104; a column decoder 120 for decoding column addresses As0 to As3 from SRAM address buffer 116 for selecting a corresponding column of SRAM array 104 and for selecting a corresponding transfer gate of data transfer circuit 106; and an IO circuit for detecting and amplifying data of the selected memory cell of SRAM array 104 and for connecting the selected column of the SRAM array 104 and the selected gate to internal data bus by an output from column decoder 120.
The sense amplifier and IO circuit for the SRAM is shown by a block 122. One row of SRAM array 104 includes 16 bits. Data transfer is simultaneously carried out between 16 bits of one selected row of the SRAM array and data transfer circuit 106
including 16 transfer gates. Namely, in the CDRAM, transfer of 16 bits of data is carried out for one memory plane, and therefore a total of 64 bits of data can be transferred simultaneously.
CDRAM further includes a K buffer 124 for receiving an externally applied clock K which is, for example, a system clock for generating an internal clock; a clock mask circuit 126 for providing a mask in accordance with an externally applied mask signal CMd on the internal clock from K buffer 124; a DRAM control circuit 128 taking in externally applied control signals RAS#, CAS# and DTD# in synchronization with the clock signal from clock mask circuit 126 for generating necessary control signals in accordance with the states of respective signals; a clock mask circuit 130 for providing a mask on the internal clock signal from K buffer 124 in accordance with an externally applied control signal CMs; an SRAM control circuit 132 for taking in external control signals E#, WE#, CC1# and CC2# in accordance with the internal clock signal from clock mask circuit 130 for generating a control signal for controlling operations of data transfer circuit 106, SRAM array 104 and an input/output portion, which will be described later, in accordance with the combinations of the states of respective control signals; a main amplifier circuit 130 which is activated in synchronization with an externally applied control signal G# for generating an external read data from data on internal data bus 123; a Din buffer circuit 134 for taking in external write data in synchronization with the clock signal under control of the SRAM control circuit 132 for generating internal write data; and a mask set circuit 136
for taking in externally applied mask data for providing a mask on transmission of write data from Din buffer circuit 134 to internal data line 123. Mask set circuit 136 further takes in the mask data in synchronization with the clock signal under the control of SRAM control circuit 132.
CDRAM 100 can change the structure of data input/output. It has a DQ separation structure in which input data (write data) D and output data Q are transmitted through separate pin terminals, and a mask write mode in which write data D and read data (output data) Q are transmitted through the same pin terminal. Masking of the write data is possible only in the mask write mode in which data input and data output are carried out through the same pin terminal. Pin terminals to which write data D0 to D3 are applied in DQ separation arrangement are used as pin terminals for receiving mask data (mask enable) M0 to M3 in the mask write mode. Though not explicitly shown in the drawings for the sake of simplicity, setting of pin terminals is effected by a command register, which will be described later.
[Definitions of External Control Signals]
In CDRAM 100 shown in FIG. 1, input of data and taking of external control signals are all carried out in synchronization with the external clock K. External control signals are all applied in the form of pulses. The operation mode is determined dependent on the combination of states of the external control signals at a rising edge of the external clock signal. Input of the external control signal G# only is carried out asynchronously with the clock K. Various external control signals will be described in the following.
Master clock K: the master clock K determines the basic timing, that is the timing for taking the input signals and operating clock frequency of the CDRAM 100. Timing parameters of each of the necessary external signals (except for G#, which will be described later) are defined using the rising or falling edge of the master clock K as a reference.
DRAM clock mask CMd: the DRAM clock mask CMd controls transmission of an internal DRAM master clock generated from K buffer 124. When DRAM clock mask is in an active state at a rising edge of external clock K, generation of the internal DRAM master clock in the next clock cycle is stopped. Accordingly, the operation for taking in control signals of the DRAM portion in the next cycle are stopped, thus reducing power consumption in the DRAM portion.
Row address strobe RAS#: the row address strobe RAS# is used with the master clock K (dependent on the states of signals CMd, CAS# and DTD# at that time) to activate the DRAM portion. More specifically, it triggers latching the DRAM row address, selecting a row in the DRAM 102, and starting a precharge cycle for setting the DRAM portion to the initial state, and it can also be used for transferring data between the DRAM and the data transfer circuit, setting of data in the command registers, starting the auto refresh cycle, generating a DRAM NOP cycle and stopping the operation (power down) of the DRAM portion. Namely, the row address strobe RAS# determines basic operation cycle in the DRAM portion.
Column address strobe CAS#: column address strobe CAS# is used together with the master clock K for latching the column address for the DRAM. When the row address strobe RAS# has been previously applied in the DRAM access cycle, data transfer from the data transfer circuit to the DRAM array or data transfer from the DRAM array to the data transfer circuit is carried out in accordance with a control signal DTD#, which will be described later, by the successively applied column address strobe CAS#.
Data transfer designation DTD#: data transfer designation DTD# determines data transfer and the direction thereof between the DRAM array 102 and data transfer circuit 106. If the row address strobe RAS# is at "L" in the preceding cycle, then a DRAM write transfer cycle in which data transfer from the data transfer circuit to the DRAM array is carried out when the column address strobe CAS# and the data transfer designation DTD# are both at "L" at the rising edge of the master clock K. If the data transfer designation DTD# is at "H", data transfer from the DRAM array to the data transfer circuit is carried out. When the data transfer designation DTD# falls to "L" in synchronization with the row address strobe RAS#, the DRAM enters the precharge mode, and access to every DRAM portion is inhibited until the completion of the precharge cycle.
DRAM address Ad0 to Ad11: DRAM array 102 has a storage capacity of 16M (mega) bits. One DRAM memory plane has a structure of 4K row.times.64 columns.times.16 blocks. One block includes 64 columns. DRAM address bits Ad0 to AD11 are applied as the DRAM row address and the DRAM column address in a multiplexed manner. When the row address strobe RAS# is at "L" at the rising edge of the master clock K, DRAM address bits Ad0 to Ad11 are taken as a row address, designating a row of the DRAM array. When the column address strobe CAS# is at "L" at the rising edge of the master clock K, DRAM address bits Ad4 to Ad9 are used as a block address for designating 16 bits of memory cells (one bit from each of the 16 blocks) of the DRAM array. When the row address strobe RAS is at "L" at the rising edge of the master clock K, the refresh address when the refresh is instructed may be designated.
SRAM clock mask CMs: the SRAM clock mask controls transmission of an internal SRAM master clock (generated from a K buffer 124). When the SRAM clock mask is at an active state at the rising edge of the master clock K, the internal SRAM master clock is stopped in the next cycle, and the SRAM portion maintains the state of the previous cycle. The SRAM clock mask is also used for continuously maintaining the same input/output data.
Chip enable E#: chip enable E# controls the operation of the SRAM portion. When the chip enable E# is at "H" at the rising edge of the master clock K, the SRAM portion is set to the non-selected state (standby state) in that cycle. When the chip enable E# is at "L" at the rising edge of the master clock K (provided that the SRAM clock mask is "L" in the previous cycle), the SRAM portion is activated in that cycle. When the output enable (which will be described later) G# is at "L", chip enable E# controls the output impedance, and writing and reading of data in a common IO structure can be carried out.
Write enable WE#: write enable WE# controls data write and read operations in the SRAM portion and the data transfer circuit. When the chip enable E# is at "L" at the rising edge of the master clock K, reading of data from the data transfer circuit, and reading of data from the SRAM array and/or data transfer from the data transfer circuit to the SRAM array are carried out by the write enable WE# at "H" (determined dependent on the states of control signals CC1# and CC2#, which will be described later). When the write enable WE# is at "L" at this time, any of writing of data to the data transfer circuits, writing of data to the selected memory cells of the SRAM array, and transfer of data from the SRAM array to the data transfer circuit is carried out (determined by control signals CC1# and CC2#).
Control clocks CC1#, CC2#: these control clocks CC1# and CC2# control access to the SRAM portion and access to the data transfer circuit. When the chip enable E# is at "L" at the rising edge of the master clock K, the operation mode to be carried out is determined by the control clocks CC1# and CC2#. The operation mode will be briefly described below, and the details will be described later.
CC1#=CC2#="L"; a buffer read/write (WE#=H/L) cycle is carried out, and reading of data from the data transfer circuit/writing of data to the data transfer circuit is carried out.
CC1#="L" and CC2#="H"; a buffer read/write transfer and SRAM read/write cycle (WE#=H/L). In this cycle, data transfer is carried out between the data transfer circuit and the SRAM array, and reading or writing of data from or to SRAM array is carried out. Writing operation and reading operation are determined dependent on whether the write enable WE# is at "H" or "L".
CC1#="H", CC2#="L", buffer read/write transfer cycle (WE#=H/L) is carried out. Data transfer between the SRAM array and the data transfer circuit is carried out.
CC1#=CC2#="H"; SRAM read/write (WE#=H/L) cycle is carried out. Data reading/writing operation for the SRAM array is carried out.
SRAM addresses As0 to As11; SRAM array includes four memory planes each including memory cells arranged in 256 rows and 16 columns. When the SRAM array is used as a cache memory, the block size of the cache is 16.times.4 (4 bits of IO). SRAM address bits As0 to As3 are used as a block address for selecting 1 bit in one cache block, while SRAM address As4 to As11 are used as a row address for selecting a row in the SRAM array.
Output enable G#: the output enable G# only is applied in non-synchronization with the master clock K. When the output enable G# attains "H", the output is set to a high impedance state both in the DQ separation mode and the common DQ mode.
Input/output DQ0 to DQ3: input/output DQ0 to DQ3 are the data of the CDRAM when the common DQ mode is selected by the command register. State of each data is controlled by output enable G# in non-synchronization with the master clock K. Output of data is carried out in any of the transparent mode, the latched mode and the registered mode, dependent on the content of the command register (which will be described later).
Inputs D0 to D3: These are input data when DQ separation mode is set by the command register. In data writing such as in the write buffer cycle or the write SRAM mode, input data D0 to D3 are latched at the rising edge of the master clock K.
Mask enable M0 to M3; These are enabled when the common DQ mode is set in the command register. Mask enable M0 to M3 correspond to input/output data DQ0 to DQ3, and determine whether or not the corresponding DQ bits are to be masked. Setting of the mask data is determined by the states of the mask enable M0 to M3 at the rising edge of the master clock K. Desired input data can be masked at the time of data writing to the data transfer circuit or to the SRAM array in the SRAM write cycle or in the buffer write cycle.
As is apparent from the above description of the control signals, control of operations related to the DRAM portion and control of the operations related to the SRAM portion of the CDRAM 100 are carried out independent from each other. Direct data writing and direct data reading to and from the data transfer circuit are possible. Therefore, the DRAM portion and the SRAM portion can be driven independent from each other to facilitate control. Data transfer utilizing a high speed mode such as the page mode of the DRAM can be implemented, access time can be reduced at the time of a cache miss, and the burst mode can be realized.
Since the data transfer circuit 106 can be externally access directly, the data stored in the SRAM array 104 is not influenced at all at the time of direct access from the outside to the data transfer circuit. Therefore, both graphic data and cache data (data used by the CPU, which is an external processing unit) can be stored in the DRAM array 102.
Referring again to FIG. 1, data transfer circuit 106 includes 16 transfer gates. Each transfer gate includes a read transfer buffer 104 for transferring data from the DRAM array 102 to the SRAM array or to an input/output portion; a temporary register 142 for storing write data on the SRAM array 104 or on the internal data bus 123; a write transfer buffer 144 for transferring data stored in the temporary register 142 to the DRAM array; and a mask register 146 for masking data transfer from the write transfer buffer 144 to the DRAM array.
In FIG. 1, CDRAM 100 receives the ground potential Vss and the supply potential Vcc. The supply potential Vcc may be utilized as an internal operational supply voltage of the CDRAM, or the supply voltage lowered internally may be used as the internal operational supply voltage. Various operations carried out by the CDRAM will be described in the following, followed by detailed description of the structures of various portions of the CDRAM.
FIG. 2 shows, in a table, states of control signals for determining operations related to the SRAM portion. FIG. 2 shows states of various control signals at the rising edge of the master clock K and operation cycles (modes) carried out at that time. In FIG. 2, the reference character "X" shows an arbitrarily state. As is apparent from FIG. 2, when operation related to the SRAM array is to be controlled, the states of control signals CMd, RAS#, CAS#, and DTD# which control operations related to the DRAM array are not defined but arbitrarily set. The control of operations related to the SRAM array is effected by SRAM control circuit 132 shown in FIG. 1. The operation cycles related to the SRAM array includes an SRAM power down cycle for stopping 1 cycle of the SRAM master clock; a deselect SRAM cycle for setting the output portion at a high impedance state; an SRAM read cycle for reading data from the SRAM array; and an SRAM write cycle for writing data to the SRAM array.
The operations related to the SRAM portion further includes a buffer read transfer cycle, a buffer read transfer and read cycle and a buffer write transfer and write cycle for transferring data between the SRAM array and the data transfer circuit, a buffer read cycle and a buffer write cycle for directly accessing the data transfer circuit. Each of the operation cycles shown in the table of FIG. 2 will be described.
SRAM System
[SRAM Power Down]
In the SRAM power down cycle, the SRAM master clock is stopped for the period of 1 cycle. Taking of control signals in synchronization with the clock in the SRAM control circuit 132 is not carried out. The SRAM sense amplifier maintains the state of the previous cycle. The output buffer maintains the state at that time. Data can be continuously output.
For the SRAM power down cycle, the SRAM clock mask CMs is set to "H" at a rising edge of the master clock K. In the next clock cycle, the SRAM enters the SRAM power down cycle. When the SRAM clock mask CMs is at "L" at the rising edge of the master clock K and the chip enable E# is set to "L", and the write enable WE# and control clocks CC1# and CC2# are both set to "H" at the rising edge of the master clock K of the next cycle, the SRAM read mode is set. In this case, the data of the SRAM is read at the rising edge of the next master clock K. The data read at this time is continuously output when the SRAM power down mode is entered at that time.
More specifically, referring to FIG. 3, when the SRAM clock mask CMs is set to "H" in the first cycle of the master clock K, SRAM power down mode starts from the second cycle of the master clock K. In the first cycle of the master clock K, the SRAM has not yet entered the power down mode, and therefore dependent on the combination of the chip enable signal E#, the write enable WE# and the control clocks CC1# and CC2# at that time, the SRAM read mode is designated, selection of the memory cell in the SRAM array is carried out in accordance with the SRAM address As0 to As11 applied to the SRAM address buffer 116 at that time, and the data of the selected memory cell is established at the rising edge of the master clock K. Since the SRAM enters the power down mode from the second cycle of the master clock K and the SRAM master clock is not supplied, the internal operation is halted and the state thereof is maintained. The output buffer (main amplifier) maintains this state until the application of the next SRAM master clock, and therefore the data Q1 which has been established at the rising edge of the second cycle of the master clock K is continuously output.
By setting the SRAM clock mask CMs at "L", at the rising edge of the fourth cycle of the master clock K, the SRAM is released from the power down mode in the cycle starting from the rising edge of the fifth cycle of the next master clock K.
By the combination of the states of the chip enable E#, the write enable WE# and the control clocks CC1# and CC2# at the rising edge of the fifth cycle of the master clock X, the SRAM read cycle is designated again. Since it is released from the power down mode in the fifth cycle of the master clock K, the output buffer (the main amplifier in FIG. 1) which has continuously output the same data Q1 so far is once set to the output high impedance state by the application of the clock K. The timing of appearance of the output data will be described in detail later.
In accordance with the SRAM address As0 to As11 applied in the fifth cycle of the master clock K, memory cells are selected in the SRAM array and data is read from the selected memory cells.
At the rising edge of the sixth cycle of the master clock K, the output data Q is set to an established state. At the rising edge of the fifth cycle of the master clock K, the SRAM clock mask CMs is at "H", and the cycle defined by the sixth cycle of the master clock K is subject to power down mode. Accordingly, the output data Q2 is continuously output. This state is kept as long as the SRAM clock mask CMs is at "H". By lowering the SRAM clock mask CMs to "L" at a rising edge of the 13th cycle of the master clock K, the 14th cycle of the master clock K is released from the power down mode. Thus the output data Q is set to the high impedance state.
As described above, by utilizing the SRAM power down mode, the operation of the SRAM portion can be stopped, and current consumption caused by the operation in synchronization with the clock K in the SRAM portion can be reduced.
[Deselect SRAM
The deselect SRAM sets the output buffer (main amplifier 138 of FIG. 1) to the output high impedance state. For the deselect SRAM mode, the SRAM clock mask CMs is set to "L" at a rising edge of the master clock K, and the chip enable E# is set to "H" at the rising edge of the next master clock K. Thus it enters the deselect SRAM mode from the next cycle, data transfer and data input/output of the SRAM array are all disabled, and it is set to the output high impedance state. By the deselect SRAM mode, the output impedance can be set to the high impedance state with the SRAM portion being effectively at the non-selected state (inoperable state). Therefore, erroneous writing of data read in the previous cycle upon switching from data reading to the data writing operation to the SRAM can be prevented, and erroneous data writing caused by collision of newly applied write data and the read data can be prevented.
Referring to the diagram of operation waveforms shown in FIG. 4, the SRAM clock mask CMs is at "L" at the rising edge of the first cycle of the master clock K. At this time, the chip enable E# is at "L", the write enable WE# and the control clocks CC1# and CC2# are all at "H", and therefore the SRAM read mode is designated. The SRAM address bits As0 to As11 applied in the first cycle of the master clock K are taken in, and data Q1 of the memory cell corresponding to the address (represented as C1 in FIG. 4) is read.
When the chip enable E# is raised to "H" in the second cycle of the master clock K, the SRAM enters the deselect SRAM mode. In this state, the SRAM portion is set to non-selected state, and the output is set to high impedance state in the third clock of the mater clock K.
When the chip enable E# is lowered to "L", the deselect SRAM mode is released, the SRAM read mode is controlled in accordance with the states of other control signals WE#, CC1# and CC2# at that time, data is read in accordance with the SRAM address (C2 in FIG. 4) applied at that time, and output data Q2 is provided.
When E# attains "H" in the sixth cycle of the master clock K, the SRAM enters the deselect SRAM mode from the fifth cycle of the master clock K. The deselect SRAM mode is kept as long as the chip enable E# is at "H" (assuming that the SRAM clock mask CMs is at "L"), and the output high impedance state is maintained.
More specifically, in the deselect SRAM mode, the SRAM portion is set to the non-selected state for the period of 1 cycle of the master clock K.
FIG. 5 shows structures of portions related to the SRAM power down mode and the deselect SRAM mode. The structure shown in FIG. 5 corresponds to the structure of the SRAM control circuit 132 and the main amplifier 138 of the clock mask circuit
130 of the structure shown in FIG. 1. Referring to FIG. 5, SRAM control circuit 132 includes a K buffer 124 receiving the master clock K and generating an internal clock Ki, and a mask circuit 130 responsive to the internal clock Ki and the SRAM clock mask CMs for generating an SRAM master clock SK.
Mask circuit 130 includes a shift register 152 responsive to the internal clock Ki for providing a delay of 1 clock cycle period to the SRAM clock mask CMs, and a gate circuit 164 responsive to the clock mask CMsR from shift register 152 for selectively passing the internal clock Ki. Gate circuit 164 is formed of, for example, a transfer gate including a p channel MOS transistor. When the clock mask SMsR is at "H", transmission of the internal clock Ki is inhibited. Gate circuit 164 may be formed by using a logic gate. The SRAM master clock SK is generated from mask circuit 130.
SRAM control circuit 132 includes an E buffer 154 responsive to the SRAM clock SK for latching the chip enable E#, a WE buffer 156 responsive to the SRAM master clock SK and the internal chip enable E from the E buffer for latching the write enable WE# and generating an internal write enable WE, and CC1 buffer 158 and a CC2 buffer 160 responsive to the internal chip enable E and the SRAM master clock SK for latching control clocks CC1# and CC2# for generating internal control clocks CC1 and CC2, respectively.
SRAM control circuit 132 further includes a control signal generating circuit 166 which is activated in response to the internal chip enable E from the E buffer 154, of which timing is defined by the SRAM master clock SK, for generating necessary control signals in accordance with combination of states of the write enable WE and the control clocks CC1 and CC2 applied from buffers 156, 158 and 160.
The control signal generating circuit 166 generates an SRAM array driving control signal for driving the SRAM array, and a data transfer drive control signal for driving the data transfer circuit. At the time of data transfer between the SRAM array and the data transfer circuit, the period of transfer is defined by the master clock, so as to surely transfer the data.
The CDRAM further includes a G buffer 162 receiving an output enable G# for generating an internal output enable G, and an output control circuit 168 responsive to the internal output enable G and a control signal from the control signal generating circuit 166 for controlling main amplifier 138. In the structure shown in FIG. 1, output control circuit 168 is included in the SRAM control circuit 132. Output control circuit 168 includes a gate circuit 176 receiving the internal output enable G from G buffer 162 and the enable signal E1 from the control signal generating circuit, and a gate circuit 178 receiving an output from gate circuit 176 and the clock mask CMsR from shift register 152. The gate circuit 176 generates a signal at "H" when signals applied to both input thereof are at "L". Gate circuit 178 generates a signal at "H" when at least one of the input thereof attains "H".
Main amplifier 138 includes an inverter circuit 172 for inverting a signal on an internal data bus 123a (1 bit data line of the internal data bus 123 being shown in FIG. 1), a 3-state inverter circuit 170 which is enabled in response to an output from output control circuit 168, an inverter circuit 174, and a connection gate 173 for connecting the output of inverter circuit 170 with the input of inverter circuit 174 in accordance with the internal clock mask CMsR. The output from inverter circuit 174 is applied to an input of 3-state inverter circuit 170. When the clock mask CMsR is at "H", inverter circuit 170 and inverter circuit 174 constitute a latch circuit.
The operation will be briefly stated. A clock mask CMsR delayed by one clock cycle is output from shift register 152. In response to this clock mask CMsR delayed by one clock cycle, gate circuit 164 passes the internal clock Ki. Accordingly, when the SRAM clock mask CMs is generated externally, transmission of the SRAM master clock SK to the SRAM control circuit 132 is inhibited in the next clock cycle. The control signal generating circuit 166 has its operation timing defined by the SRAM master clock SK and generates necessary internal control signals. Buffer circuits 154, 156, 158 and 160 are effecting latching of applied data in accordance with the internal chip enable E and the SRAM master clock SK. When there is no SRAM master clock SK applied, each buffer does not effect a new latching operation.
Similarly, when the chip enable E is not generated, the buffers do not operate. When the chip enable E is at "H" indicating the non-selected state, buffers 156, 158 and 160 do not operate. At this time, the control signal generating circuit 166
does not operate, either.
The SRAM master clock SK is masked by the clock mask CMs from the next cycle from the generation of the mask clock CMs. Therefore, when the SRAM clock mask CMs is applied externally, the internal chip enable E and the SRAM master clock SK are generated in that cycle, and therefore an operation in accordance with the applied control signals is carried out. In the next cycle, internal control signal is not generated and control signal generating circuit 166 maintains the state of the previous cycle. Control signal generating circuit 166 delays chip enable E by a prescribed time period and generates an internal chip enable E1. Thus, the output timing can be accurately set (as the timing of generating is defined by SRAM master clock SK).
When clock mask CMsR is at "H", 3-state inverter circuit 170 is at the operative state, and connection gate 173 is also rendered conductive. Thus a latch circuit is formed by inverter circuits 170 and 174. While the output from G buffer 162 is at the active state, the output data DQ continues to hold the same data by the inverter circuit 170 and 174. When chip enable E# falls to "L", internal chip enable E also falls to "L", control signal generating circuit 166 initializes chip enable E1 to "H", and after a prescribed time period, lowers the same to "L". Therefore, when the clock mask CMsR is at "L", the inverter circuit 170 is set to the output high impedance state, and when the internal output enable G is at "L" after the lapse of a prescribed time period, the inverter circuit 170 is set to the operative state in accordance with the internal chip enable E1, resulting in appearance of a new output data.
As described above, the output impedance state can be set by the clock mask CMsR and the chip enable E#.
FIG. 6 shows an example of the structure of the buffer circuit shown in FIG. 5. FIG. 6 shows a structure of the SRAM address buffer which is not shown in FIG. 5. Buffers 156, 158 and 160 have the same structure as the buffer shown in FIG. 6. Referring to FIG. 6, a buffer 116 includes a 3-state inverter circuit 7011 the output state of which is determined by the SRAM master clock K; an inverter circuit 7013 receiving an output from inverter circuit 7011; and a 3-state inverter circuit 7014
which is set to the output enable state in response to the internal chip enable E. Inverter circuit 7013 has its output connected to an input of inverter circuit 7014. Inverter circuit 7014 has its output connected to an input of inverter circuit 7013. An internal address signal int. As is generated from inverter circuit 7013. The operation will be described briefly.
3-state inverter circuit 7011 is set to the active state when the internal SRAM master clock SK is at "L", and inverts an externally applied address As and passes the same. When the SRAM master clock SK is at "H", inverter circuit 7011 is set to the output high impedance state. Therefore, inverter circuit 7011 takes in the address As which has been applied by that time at the rising edge of the SRAM master clock SK.
Inverter circuit 7014 is set to the enable state when the internal chip enable E is at "L" indicating the chip selected state, while it is set to the output high impedance state when the chip enable E is at "H" indicating the chip non-selected state. Therefore, when the chip enable E is at "L" at the rising edge of the internal clock SK, the address As which has been applied to inverter circuit 7011 by that time is latched by inverter circuits 7013 and 7014, and an internal SRAM address is generated.
FIG. 7 shows a structure of the E buffer shown in FIG. 5. Referring to FIG. 7, the E buffer 154 includes a p channel MOS transistor Tr700 having its source connected to the supply potential Vcc, and receiving the SRAM master clock Sk at its gate, a p channel MOS transistor Tr701 having its source connected to the drain of p channel MOS transistor Tr700 and its gate receiving the chip enable E#, an N channel MOS transistor Tr702 having its gate receiving the chip enable E# and its drain connected to the drain of MOS transistor Tr701, and an n channel MOS transistor Tr703 having its drain connected to the source of MOS transistor Tr702, its source connected to the ground potential Vss and its gate receiving an inverted signal/SK of the SRAM master clock. The E buffer 154 is set to the high impedance state when the SRAM master clock SK is at "H" (transistors Tr700 and Tr703 are both off), and when the SRAM master clock SK is at "L", it inverts the chip enable E# and generates an inverted signal/E of the internal chip enable E. Therefore, the chip enable E# can be taken in accordance with the SRAM master clock SK.
By utilizing the structures of the SRAM control circuit and the main amplifier circuit 138 as described above, the SRAM power down mode and the deselect SRAM mode can be readily realized.
[SRAM Read]
The SRAM read mode is an operation mode for reading data from the SRAM array. In this operation mode, as shown in FIG. 8, the chip enable E# is set to "L", and the write enable W# and the control clocks CC1# and CC2# are set to "H" at the rising edge of the master clock K. In the following description, it is assumed that the SRAM clock mask SMs is at "L". At this time, memory cell selecting operation is carried out under the control of SRAM control circuit 132 (see FIG. 1) in accordance with the simultaneously taken SRAM address bits As0 to As1, and the data of the selected memory cell of the SRAM array is transmitted to the internal data bus 123 (see FIG. 1). When the output enable G# is at "L" at this time, an established data is output at the rising edge of the next clock signal. The SRAM operates at high speed. Therefore, by setting the SRAM read mode at each rising edge of the master clock K, the established data can be output at the rising edge of the next clock cycle (provided that the output enable G# is at "L").
When the output enable G# is set to "H", main amplifier circuit 138 is set to the output high impedance state.
FIG. 9 shows the data flow in the SRAM read mode. At this time, a drive 118a corresponding to the SRAM row decoder 118 shown in FIG. 1 decodes SRAM address bits As4 to As11 and selects one row in the SRAM array 104. In the SRAM array 104, 16
bits of memory cells are connected to one row. One of these 16 bits of memory cells is selected by a column decoder 120. Column decoder 120 decodes SRAM address bits As0 to S3 and selects one of the 16 bits of memory cells. An SA+IO control circuit
122 reads the data of the selected memory cell of the SRAM array 104.
[SRAM Write]
The SRAM write mode is an operation mode for writing data to the memory cells of the SRAM array. For the SRAM write mode, the chip enable E# and the write enable WE# are both set to "L" and control clock CC1# and CC2# are both set to "H" at the rising edge of the master clock K as shown in FIG. 10. In this case also, the SRAM clock mask CMs is set at "L" in the previous cycle. This condition applies to the following descriptions, and it is assumed that the SRAM mask clock CMs is at "L" unless indicated otherwise. In FIG. 10, mask data M0 to M3 are used, and operation waveforms in the SRAM read mode and the SRAM write mode at the common DQ pin arrangement state are shown.
Referring to FIG. 10, when the chip enable E# is set to "L" and the write enable WE# and the control clocks CC1# and CC2# are set to "H" at the rising edge of the first cycle of the master clock K, the SRAM read mode is set. If the output enable G#3 is at "L", data is read at the rise of the next clock K.
In order to switch from the SRAM read mode to the SRAM write mode, the chip enable E# is raised to "H" at the rising edge of the third cycle of the master clock K. Consequently, deselect SRAM mode for the SRAM portion is set, and the SRAM memory cell data designated in the second cycle of the clock K is set to the established state at the rising edge of the third clock of the master clock K, and then set to the output high impedance state.
When the chip enable E# and the write enable WE# are both set to "L" and the control clocks CC1# and CC2# are set to "H" at the fourth cycle of the master clock K, the SRAM write mode is set. The SRAM address bits As0 to As11 applied at this time are taken in, and the mask data MO to M3 (labeled as M3 in FIG. 10) and the internal write data D3 at this time are taken in. A prescribed bit of the write data D3 is masked for writing in accordance with the masked data M3. Thereafter, as long as the chip enable E# and the write enable WE# are at "L" and the control clocks CC1# and CC2# are at "H" at the rising edge of the master clock K, the SRAM write mode is repeated, write data D and mask data M are taken in at the rising edge of the clock K, and the data is written.
By setting the chip enable E# to the "L" and the write enable WE# and the control clocks CC1# and CC2# to "H" at the ninth cycle of the master clock K, the SRAM read mode is set. When the output enable G# is at "L", data Q8 and Q9 read in the SRAM read mode are respectively set to the established state at the rising edges of the tenth and eleventh cycles of the master clock K, if the output enable G# is at "L". When the output enable G# is set to "H" earlier than the rising edge of the master clock 12, the input/output pin DQ is set to the high impedance state provided that the write enable WE# is at "H".
As the access to the SRAM array is done at high speed as mentioned above, writing of data is completed in 1 cycle of the clock K.
As can be seen from FIG. 10, by utilizing the deselect SRAM mode, at the time of switching from the reading operation to the writing operation, writing of data can be surely carried out while the read data (Q2) does not affect the write data (D3) of the next cycle.
FIG. 11 shows the data flow in the SRAM write mode. Referring to FIG. 11, a word line driving circuit 118a is driven to carry out the row selecting operation in the SRAM 109, and the column decoder 120 operates to select one memory cell of the SRAM array 104. Data is written to the selected memory cell of SRAM array 104 through a block 122.
As shown in FIGS. 9 and 11, in the SRAM read mode and the SRAM write mode, writing of data to the SRAM array and reading of data from the SRAM array are carried out regardless of the operation of the data transfer circuit and the DRAM array. Therefore, at the time of accessing to the SRAM array, data transfer between the data transfer circuit and the DRAM array can be carried out in parallel therewith. Such operation is possible since the DRAM control circuit 128 and the SRAM control circuit 132 are provided separately as shown in FIG. 1.
[Buffer Read Transfer]
The buffer read transfer mode is an operation mode for transferring data from the read transfer buffer to the SRAM. In this mode, 16 bits of data are simultaneously transferred from the data transfer circuit to the SRAM array. As shown in FIG.
12, the buffer read transfer mode is realized by setting the chip enable E# and the control clock CC2# to "L" and by setting the write enable WE# and the control clock CC1# to "H", at the rising edge of the master clock K. Other operation modes are also shown in FIG. 12.
In the buffer read transfer mode, the data transfer operation is ensured by setting the SRAM address bits As0 to As3 applied at this time to "L". By setting the SRAM column address bits As0 to As3 to "L", simultaneous data transfer operation of
16 bits is assured. The operation of the buffer read transfer mode as well as other operation modes will be described with reference to FIG. 12.
Referring to FIG. 12, the SRAM read mode is set at the rising edge of the first cycle of the master clock K. The SRAM reading operation is carried out in accordance with the SRAM address Cl applied at that time, and the output data Q1 is set to the established state as the rising edge of the second cycle of the master clock K. Since the chip enable E# is at "H" at the rising edge of the second cycle of the master clock K, the second cycle of the master clock K is in the deselect SRAM mode, and at the rise of the third clock of the master clock K, the output is at the high impedance state. At this time, the chip enable E# and the control clock CC2# are set to "L" while the write enable WE# and the control CC1# are set to "H" at the rising edge of the third cycle of the master clock K also. Consequently, the buffer read transfer mode is set. At this time, the SRAM address bits As0 to As3 are set to "L". A row selecting operation is carried out in the SRAM array in accordance with the SRAM address bits As4 to As11. 16 bits of SRAM memory cells are connected to one row. Data are simultaneously transferred from the read transfer buffer 140 to these 16 bits of connected SRAM memory cells.
The SRAM array does not require such operation as bit line precharging. The SRAM array can be accessed immediately after the transfer of data from the read transfer buffer. In FIG. 12, at the rising edge of the fourth cycle of the master clock K, the chip enable E# is set to "L", the write enable WE# and the control clocks CC1# and CC2# are set to "H", and thus the SRAM read mode is set. Accordingly, data is read from the RAM memory cell at the rising edge of the fifth cycle of the master clock K.
Thereafter, by setting the chip enable E# to "H", at the rising edge of the fifth cycle of the master clock K, the deselect SRAM mode is set, the SRAM is set to a non-selected state in the fifth cycle and after the lapse of a prescribed time period, the output is set to the high impedance state.
At the rising edge of the master clock K in the sixth cycle, the chip enable E# and the control clock CC2# are both set to "L" and the write enable WE# and the control clock CC1# are set to "H", setting the buffer read mode. Consequently, 16
bits of memory cells are selected in the SRAM array, and data are transferred from the read transfer buffer 140 to the selected 16 bits of SRAM memory cells. Then, in the seventh cycle of the master clock K, the chip enable E# and the write enable WE# are set to "L" and the control clocks CC1# and CC2# are both set to "H", the SRAM write mode is set. Data D5 applied at that time is written to the selected memory cell of the SRAM in accordance with the mask data M5.
In the eighth cycle of the master clock K, the chip enable E# is set to "L", the write enable WE# and control clock CC1# and CC2# are all set to "H", and thus the SRAM read mode is set. However, since the output enable G# is at "H" at this time, output high impedance state is set outside the device.
In the ninth cycle of the master clock K, the buffer read transfer operation is again carried out, and data is transferred from the read transfer buffer to the SRAM array.
In the tenth cycle of the master clock K, the SRAM write mode is set, and data is written to the selected memory cells of the SRAM array in this tenth cycle.
By setting the buffer read transfer mode as described above, it becomes possible to transfer the cache block collectively to the SRAM array at high speed at the time of a cache miss, and therefore the access time can be significantly reduced at the time of a cache miss. The reason for this is that the SRAM array can be accessed at high speed after the data transfer to the SRAM array in accordance with the buffer read transfer mode.
FIG. 13 shows the data flow in the buffer read transfer mode. In the buffer read transfer mode, a word line driving circuit 118a selects one row of the SRAM array 104, and 16 bits of data are simultaneously transmitted to the selected one row (16 bits) from the read transfer buffer 140. Read data transfer buffer 140, which will be described in detail later, includes 16 buffers so as to allow simultaneous transfer of 16 bits of data.
[Buffer Write Transfer Mode]
The buffer write transfer mode is an operation mode for transferring data from the SRAM array to a write data transfer buffer (including a temporary buffer) included in the data transfer circuit. States of control signals in the buffer write transfer mode are shown in FIG. 14.
The buffer write transfer mode is designated by setting the chip enable E#, the write enable WE# and the control clock CC2# to "L" and by setting the control clock CC1# to "H" at the rising edge of the master clock K. In the buffer write transfer mode, the SRAM address bits As0 to As3 must be all set to "L" so as to fully carry out the data transfer operation. In the buffer write transfer mode, the mask bits (masked data) included in mask register 146 are all set to the reset state ("0" state). This is because it is necessary to transfer all the data which have been transferred from the SRAM array to the write transfer buffer 144 to the DRAM array.
The operation including the buffer write transfer mode will be described with reference to FIG. 14. Referring to FIG. 14, at the rising edge of the first cycle of the master clock K, the SRAM read mode is designated. Selection of a memory cell of the SRAM is carried out, and the data of the selected memory cell is established at the rising edge of the second cycle of the master clock K.
At the rising edge of the second cycle of the master clock K, the chip enable E# is raised to "H", the deselect SRAM mode is designated, the SRAM is set to the non-selected state and the output is set to the high impedance state. In the third cycle of the master clock K, the chip enable E#, the write enable WE# and the control clock CC2# are set to "L", while the control clock CC1 is set to "H", so that the buffer write transfer mode is designated. In the buffer write transfer mode, the SRAM address bits As0 to As3 are all set to "L". By using the remaining SRAM address bits As4 to As11, one row (16 bits) is selected in the SRAM array, and the data of the selected 16 bits of SRAM memory cells are simultaneously transferred to the write transfer buffer (latched in the temporary buffer).
In the fourth cycle of the master clock K, the SRAM read mode is designated, memory cell selecting operation in accordance with the SRAM address bits As0 to As11 is carried out, and the data of the selected memory cell is read. In the fifth cycle of the master clock K, the deselect SRAM mode is again designated, the SRAM is kept at the non-selected state in the fifth cycle of the master clock K, and the output is set to the high impedance state.
In the seventh cycle of the master clock K, the SRAM write mode is designated. At this time, the output enable G# is at "H", and writing of data in accordance with the mask data M5 (mask bits M0 to M3) is carried out for the SRAM array.
In the ninth cycle of the master clock K, the buffer write transfer mode is designated, one row of the SRAM array is selected, and data of the memory cells connected to the selected one row are transferred to the write data transfer buffer. In the tenth cycle of the master clock K, the SRAM write mode is designated, and writing of data to the SRAM array is carried out.
FIG. 15 shows the data flow in the buffer write transfer mode. Referring to FIG. 15, the word line driving circuit 118a is driven, one row of the SRAM array 104 is selected, and data of the memory cells connected to the selected one row are transferred to the write data transfer buffer. Here, the write data transfer buffer includes a temporary buffer for temporarily storing applied data, and the data is actually latched in the temporary buffer 142. By this structure in which the data transferred from the SRAM array 104 is once latched by the temporary buffer 142, data can be retrieved from the SRAM array 104 (at the time of a cache miss) and in parallel therewith, the cache data can be transferred from the DRAM array through the read data transfer buffer 140. Therefore, data transfer at the time of a cache miss can be carried out at high speed, reducing the access time. In the following description also, the data transfer from the SRAM array to the write data transfer buffer corresponds to the state in which data is stored in the temporary buffer.
[Buffer Read Transfer/SRAM Read]
The buffer read transfer and SRAM read mode (hereinafter referred to as the buffer read transfer/SRAM read), data is transferred from the read data transfer buffer to the SRAM array and further, 1 bit (if the device has.times.4 bits structure, a total of 4 bits) of the transferred data is output from the SRAM array in accordance with the SRAM address.
The buffer read transfer/SRAM read mode is set by setting the chip enable E# and the control clock CC1# to "L" and setting the write enable WE# and the control clock CC2 to "H" at the rising edge of