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United States Patent
6157210
Zaveri , ; et al.
December 5, 2000
Title
Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits
Abstract
A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.
Inventors:
Zaveri; Ketan
(San Jose,
CA
)
, Lane; Christopher F.
(Campbell,
CA
)
, Reddy; Srinivas T.
(Fremont,
CA
)
, Lee; Andy L.
(San Jose,
CA
)
, McClintock; Cameron R.
(Mountain View,
CA
)
, Pedersen; Bruce B.
(San Jose,
CA
)
Assignee:
Altera Corporation
(San Jose,
CA
)
Appl. No.:
082867
Filed:
May 21, 1998
Current U.S. Class:
326/40
326/41
365/201
714/725
714/726
714/729
714/730
714/733
714/734
326/37
326/38
326/39
Field of Search:
326/37-41 365/201 714/725,726,733,734,724,727,729,730,30
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Other References
Hu, S.C., "Cellular Synthesis of Synchronous Sequential Machines," IEEE Transactions on Computers, vol. C-21, No. 12, pp. 1399-1405 (Dec. 1972). .
Page, III, E.W. "Programmable Array Realization of Sequential Machines," Doctoral Dissertation, Dept. of Electrical Engineering, Duke University (May 10, 1973). .
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C. Brown, "Overview of In-Circuit Reconfiguration and Reprogramming for the FLEXlogic iFX8160," Intel Corporation, Mar. 1994. .
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Primary Examiner:
Tokar; Michael
Assistant Examiner:
Tan; Vibol
Attorney, Agent or Firm:
Fish & Neave Jackson; Robert R. Treyz; G. Victor
Parent Case Text
This application claims the benefit of U.S. provisional application Ser. No. 60/062,079, filed Oct. 16, 1997.
Claims
What is claimed is:
1. A programmable logic device having circuitry for observing logic signals from programmable logic elements, comprising:
a plurality of programmable logic elements arranged in rows and columns;
a plurality of sense lines each associated with a different one of the columns of programmable logic elements and each extending past plural rows of programmable logic elements;
a plurality of access transistors each associated with a different one of the programmable logic elements for connecting that programmable logic element to one of the sense lines;
a plurality of access transistor control lines each associated with a different one of the rows of programmable logic elements and each connected to the access transistors in that row for controlling those access transistors;
a test register to which each of the sense lines is connected; and
decoder circuitry connected to the access transistor control lines for selectively turning on the access transistors in a given row using a corresponding one of the access transistor control lines so that signals from the programmable logic elements in the given row are provided to the test register.
2. A programmable logic device having circuitry for observing logic signals from programmable logic elements, comprising:
a plurality of programmable logic elements arranged in rows and columns;
a plurality of sense lines each associated with a different one of the columns of programmable logic elements;
a plurality of access transistors each associated with a different one of the programmable logic elements for connecting that programmable logic element to one of the sense lines;
a plurality of access transistor control lines each associated with a different one of the rows of programmable logic elements and each connected to the access transistors in that row for controlling those access transistors;
a test register to which each of the sense lines is connected; and
decoder circuitry connected to the access transistor control lines for selectively turning on the access transistors in a given row using a corresponding one of the access transistor control lines so that signals from the programmable logic elements in the given row are provided to the test register,
wherein the programmable logic elements further comprise registers and the signals that are provided to the test register comprise registered signals.
3. The programmable logic device defined in claim 2 wherein the registers further comprise clock terminals to which a clock signal is applied, the clock signal being frozen before the access transistors in the given row are turned on so that a snapshot of the signals from the programmable logic elements in that row may be taken.
4. The programmable logic device defined in claim 1 further comprising address register circuitry for directing the decoder circuitry to select the given row of programmable logic elements.
5. The programmable logic device defined in claim 4 further comprising a test data input for providing data to the address register circuitry.
6. The programmable logic device defined in claim 1 wherein the test register further comprises a test data output with which the signals are provided from the test register.
7. The programmable logic device defined in claim 1 wherein the programmable logic elements further comprise combinatorial logic and the signals that are provided to the test register comprise combinatorial signals.
8. The programmable logic device defined in claim 1 further comprising a plurality of logic array blocks each formed from a group of the programmable logic elements.
9. The programmable logic device defined in claim 1 further comprising circuitry for continuously observing signals from a selected one of the programmable logic elements in real time.
10. The programmable logic device defined in claim 1 further comprising:
a plurality of column select transistors each connected between a respective one of the sense lines and a common output; and
column select logic for turning the column select transistors on and off, so that signals from a given one of the programmable logic elements may be observed by turning on one of the rows of access transistors with the decoder circuitry and by turning on one of the column select transistors with the column select logic.
11. The programmable logic device defined in claim 1 wherein the programmable logic elements comprise combinatorial logic and register logic, the programmable logic device further comprising a plurality of multiplexers each of which is associated with one of the programmable logic elements and which has one input connected to the combinatorial logic in that programmable logic element and another input connected to the register logic in that programmable logic element and which has an output coupled to the access transistor associated with that programmable logic element, the multiplexer being configurable to direct a selected one of its two inputs to its output so that signals from either the combinatorial logic or the register logic may be observed.
12. The programmable logic device defined in claim 1 wherein the programmable logic elements comprise combinatorial logic and registered logic, the programmable logic device further comprising:
additional sense lines associated with the programmable logic elements; and
additional access transistors associated with each of the programmable logic elements, each additional access transistor being connected to one of the additional sense lines, the access transistor and the additional access transistor associated with each programmable logic element selectively passing signals simultaneously from both the combinatorial logic and the register logic of that logic element to the sense line and additional sense line respectively, so that signals from both the combinatorial logic and the register logic may be observed simultaneously.
13. The programmable logic device defined in claim 1 further comprising:
local lines; and
driver circuitry for providing signals from the programmable logic elements to the local lines.
14. The programmable logic device defined in claim 1 further comprising:
global lines; and
driver circuitry for providing signals from the programmable logic elements to the global lines.
15. The programmable logic device defined in claim 1 wherein the programmable logic elements each include at least one look-up table for providing combinatorial logic signals.
16. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having circuitry for observing logic signals from programmable logic elements including:
a plurality of programmable logic elements arranged in rows and columns;
a plurality of sense lines each associated with a different one of the columns of programmable logic elements and each extending past plural rows of programmable logic elements;
a plurality of access transistors each associated with a different one of the programmable logic elements for connecting that programmable logic element to one of the sense lines;
a plurality of access transistor control lines each associated with a different one of the rows of programmable logic elements and each connected to the access transistors in that row for controlling those access transistors;
a test register to which each of the sense lines is connected; and
decoder circuitry connected to the access transistor control lines for selectively turning on the access transistors in a given row using a corresponding one of the access transistor control lines so that signals from the programmable logic elements in the given row are provided to the test register.
17. The digital processing system defined in claim 16 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
18. The digital processing system defined in claim 16 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
19. The digital processing system defined in claim 16 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
20. A programmable logic device having circuitry for observing logic element signals, comprising:
a plurality of logic elements;
a plurality of logic element registers, each contained in a respective one of the logic elements and each having a logic element register output;
logic element logic in each logic element that provides logic signals;
a switching circuit associated with each logic element that has at least one logic element input connected to the logic element logic for receiving the logic signals, a scan chain input, and a switching circuit output for providing signals to the logic element register contained in that logic element; and
a plurality of scan chain conductors each connecting the logic register output of a logic register in one of the logic elements to the scan chain input of the switching circuit associated with a successive one of the logic elements to form a continuous scan chain, wherein during normal operation each switching circuit is configured to connect its logic element input to its switching circuit output so that the logic signals are stored in the logic element registers and during register observation each switching circuit is configured to connect its scan chain input to its switching circuit output so that the logic signals stored in the registers may be scanned out of the registers through the continuous scan chain.
21. The programmable logic device defined in claim 20 further comprising an input coupled to the scan chain input of one of the switching circuits for supplying initialization data to the registers through the scan chain.
22. The programmable logic device defined in claim 21 wherein the input is a JTAG TDI input.
23. The programmable logic device defined in claim 20 further comprising:
at least one memory block;
a plurality of memory block registers associated with the memory block, each memory block register having a memory block register output;
a memory block switching circuit associated with each memory block register that has at least one memory block switching circuit input for receiving memory block signals, a memory block scan chain input, and a memory block switching circuit output for providing signals to the associated memory block register; and
a plurality of memory block scan chain conductors each connecting the memory block register output of one of the memory block registers to the memory block scan chain input of a memory block switching circuit associated with a successive one of the memory block registers to form a continuous scan chain, wherein during normal operation each memory block switching circuit is configured to connect its memory block switching circuit input to its memory block switching circuit output so that the memory block signals are stored in the memory block registers and during register observation each memory block switching circuit is configured to connect its memory block scan chain input to its memory block switching circuit output so that the memory block signals stored in the registers may be scanned out of the registers through the continuous scan chain.
24. The programmable logic device defined in claim 23 further comprising an input coupled to the memory block scan chain input of one of the memory block switching circuits for supplying initialization data to the memory block registers through the scan chain.
25. The programmable logic device defined in claim 20 further comprising a JTAG TDO output coupled to the scan chain through which the logic signals stored in the registers may be scanned out.
26. The programmable logic device defined in claim 20 further comprising a plurality of logic array blocks, each of which contains a number of the logic elements.
27. The programmable logic device defined in claim 20 further comprising:
a plurality of logic array blocks, each of which contains a number of logic elements; and
a plurality of groups of logic array blocks each of which contains a number of the logic array blocks.
28. The programmable logic device defined in claim 20 further comprising:
a plurality of logic array blocks, each of which contains a number of logic elements; and
a plurality of groups of logic array blocks each of which contains a number of the logic array blocks, the groups of logic array blocks being arranged in a plurality of rows, each row containing a corresponding set of switching circuits and scan chain conductors so that a separate scan chain of logic element registers may be formed in each row.
29. The programmable logic device defined in claim 20 further comprising:
a plurality of logic array blocks, each of which contains a number of the logic elements; and
a plurality of memory blocks, each of which contains a memory circuit.
30. The programmable logic device defined in claim 20 further comprising:
a plurality of logic array blocks, each of which contains a number of logic elements;
a plurality of memory blocks; and
a plurality of groups of logic array blocks each of which contains a number of the logic array blocks and one of the memory blocks.
31. The programmable logic device defined in claim 20 further comprising:
a plurality of logic array blocks, each of which contains a number of logic elements;
a plurality of memory blocks, each memory block having associated memory block registers, each memory block register having an associated memory block switching circuit and memory block scan chain conductor for forming a scan chain; and
a plurality of groups of logic array blocks each of which contains a number of the logic array blocks and one of the memory blocks, the groups of logic array blocks being arranged in a plurality of rows, each row containing a corresponding set of switching circuits, memory block switching circuits, scan chain conductors, and memory block scan chain conductors so that a separate scan chain of logic element registers and memory block registers may be formed in each row.
32. The programmable logic device defined in claim 20 wherein each switching circuit has two logic element inputs, a scan chain input, and a switching circuit output.
33. The programmable logic device defined in claim 20 wherein the registers are provided with initialization data through the scan chain during an initialization mode, the programmable logic device further comprising clock and clear control logic for ensuring that data in the logic element registers is not corrupted during transitions between the initialization mode and normal operation.
34. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having:
a plurality of logic elements;
a plurality of logic element registers, each contained in a respective one of the logic elements and each having a logic element register output;
logic element logic in each logic element that provides logic signals;
a switching circuit associated with each logic element that has at least one logic element input connected to the logic element logic for receiving the logic signals, a scan chain input, and a switching circuit output for providing signals to the logic element register contained in that logic element; and
a plurality of scan chain conductors each connecting the logic register output of a logic register in one of the logic elements to the scan chain input of the switching circuit associated with a successive one of the logic elements to form a continuous scan chain, wherein during normal operation each switching circuit is configured to connect its logic element input to its switching circuit output so that the logic signals are stored in the logic element registers and during register observation each switching circuit is configured to connect its scan chain input to its switching circuit output so that the logic signals stored in the registers may be scanned out of the registers through the continuous scan chain.
35. The digital processing system defined in claim 34 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
36. The digital processing system defined in claim 34 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
37. The digital processing system defined in claim 34 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
38. A programmable logic device having circuitry for observing logic element signals comprising:
a plurality of programmable logic circuits;
a plurality of memory cells each having an output that is applied to a respective one of the logic circuits for configuring logic in that programmable logic circuit; and
a plurality of programmable logic elements each containing a logic element register, the memory cells and the logic element registers being connected to form a scan chain through which signals from both the memory cells and the logic element registers are unloaded.
39. The programmable logic device defined in claim 38 wherein each memory cell has a memory cell output and the logic element registers each comprise a master latch having a master latch input and a slave latch, the programmable logic device further comprising circuitry for connecting the output of each memory cell to the master latch input of a successive logic element register in the scan chain.
40. The programmable logic device defined in claim 39 wherein the circuitry for connecting comprises a pass transistor.
41. The programmable logic device defined in claim 38 wherein each memory cell has a memory cell output and the logic element registers each comprise a master latch and a slave latch having a slave latch input, the programmable logic device further comprising circuitry for connecting the output of each memory cell to the slave latch input of a successive logic element register in the scan chain.
42. The programmable logic device defined in claim 41 wherein the circuitry for connecting comprises a pass transistor.
43. The programmable logic device defined in claim 38 further comprising a test register for receiving logic element signals from the scan chain.
44. The programmable logic device defined in claim 38 wherein the logic element registers each include a clock input for receiving clock signals, the programmable logic device further comprising clock control logic for controlling the clock signals applied to the clock input.
45. The programmable logic device defined in claim 44 wherein the clock control logic further comprises user clock control logic that is driven by a global freeze signal.
46. The programmable logic device defined in claim 44 wherein the clock control logic further comprises address line clock control logic that is driven by an address line signal.
47. The programmable logic device defined in claim 38 further comprising a plurality of pass transistors each connected between the output of one of the memory cells and one of the logic element registers.
48. The programmable logic device defined in claim 38 wherein the programmable logic device has a programming mode, a user mode, and a verify mode, and wherein the logic element registers each include a clock input for receiving clock signals, the programmable logic device further comprising clock control logic for controlling the clock signals applied to the clock input so that there is no possibility of data corruption when entering the user mode from the programming mode and so that there is no possibility of data corruption when leaving the user mode to enter the verify mode.
49. A method for observing logic element signals in a programmable logic device having a plurality of programmable logic circuits, a plurality of memory cells each having an output, and a plurality of programmable logic elements each containing a logic element register, the memory cells and the logic element registers being connected to form a scan chain, the method comprising the steps of:
applying the output of each memory cell to a respective one of the programmable logic circuits to configure logic in that programmable logic circuit; and
unloading logic signals from both the memory elements and the logic element registers using the scan chain.
50. The method defined in claim 49 wherein each memory cell has a memory cell output and the logic element registers each comprise a master latch having a master latch input and a slave latch, the method further comprising the step of providing the output of each memory cell to the master latch input of a successive logic element register in the scan chain.
51. The method defined in claim 50 wherein the programmable logic device comprises pass transistors, the step of providing further comprising the step of providing the output of each memory cell to the master latch input of a successive logic element register using one of the pass transistors.
52. The method defined in claim 49 wherein each memory cell has a memory cell output and the logic element registers each comprise a master latch and a slave latch having a slave latch input, the method further comprising the step of providing the output of each memory cell to the slave latch input of a successive logic element register in the scan chain.
53. The method defined in claim 52 wherein the programmable logic device comprises pass transistors, the step of providing further comprising the step of providing the output of each memory cell to the slave latch input of a successive logic element register in the scan chain using one of the pass transistors.
54. The method defined in claim 49 wherein the programmable logic device further comprises a test register, the method further comprising the step of receiving logic element signals from the scan chain with the test register.
55. The method defined in claim 49 wherein the logic element registers each include a clock input and each have associated clock control logic, the method further comprising the steps of:
receiving clock signals with the clock inputs; and
controlling the clock signals applied to the clock inputs with the control logic.
56. The method defined in claim 55 further comprising the step of driving the clock control logic with a global freeze signal.
57. The method defined in claim 55 wherein the clock control logic further comprises address line clock control logic, the method further comprising the step of driving the address line clock control logic with an address line signal.
58. The method defined in claim 49 wherein the programmable logic device further comprises a plurality of pass transistors each connected between the output of one of the memory cells and one of the logic element registers in the scan chain, the method further comprising the step of unloading logic signals from both the memory elements and the logic element registers in the scan chain using the pass transistors.
59. The method defined in claim 49 wherein the programmable logic device has a programming mode, a user mode, and a verify mode, and wherein the logic element registers each include a clock input for receiving clock signals, the programmable logic device further comprising clock control logic, the method further comprising the step of controlling the clock signals applied to the clock input with the clock control logic so that there is no possibility of data corruption when entering the user mode from the programming mode and so that there is no possibility of data corruption when leaving the user mode to enter the verify mode.
60. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having:
a plurality of programmable logic circuits;
a plurality of memory cells each having an output that is applied to a respective one of the logic circuits for configuring logic in that programmable logic circuit; and
a plurality of programmable logic elements each containing a logic element register, the memory cells and the logic element registers being connected to form a scan chain through which signals from both the memory cells and the logic element registers are unloaded.
61. The digital processing system defined in claim 60 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
62. The digital processing system defined in claim 60 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
63. The digital processing system defined in claim 60 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
64. A programmable logic device having circuitry for observing logic element signals comprising:
a plurality of logic element registers having outputs, the logic element registers receiving signals and providing corresponding logic element signals at the outputs;
a plurality of programmable logic circuits;
a plurality of regular memory cells arranged in a first-in-first-out chain, each regular memory cell providing a memory cell output signal that is applied to a respective one of the programmable logic circuits for configuring logic in that programmable logic circuit;
a plurality of shadow memory cells arranged in a first-in-first out chain that are not directly connected to any programmable logic circuits to configure logic in those programmable logic circuits;
a plurality of load transistors, each connected between one of the register outputs and one of the shadow memory cells for selectively conveying logic element signals to be observed from the registers to the shadow memory cells; and
a test register that is connected to the first-in-first-out chain of shadow memory cells for receiving the logic element signals to be observed from the shadow memory cells and that is connected to the first-in-first-out chain of regular memory cells.
65. The programmable logic device defined in claim 64 wherein the first-in-first-out chain of shadow memory cells further comprises a plurality of regular memory cells.
66. The programmable logic device defined in claim 65 wherein at least some of the shadow memory cells in the first-in-first-out chain of shadow memory cells are interspersed between respective ones of the regular memory cells.
67. The programmable logic device defined in claim 64 wherein each of the logic element registers further comprises a feedback terminal, the programmable logic device further comprising a plurality of preload transistors, each connected between one of the shadow memory cells and the feedback terminal of one of the logic element registers for selectively conveying preload data from that shadow memory cell to that logic element register.
68. The programmable logic device defined in claim 64 wherein the shadow memory cells in the first-in-first-out chain of shadow memory cells are connected to each other without intervening regular memory cells.
69. The programmable logic device defined in claim 64 wherein the logic element registers have data inputs, the programmable logic device further comprising programmable logic circuits connected to the data inputs.
70. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having:
a plurality of logic element registers having outputs, the logic element registers receiving signals and providing corresponding logic element signals at the register outputs;
a plurality of programmable logic circuits;
a plurality of regular memory cells arranged in a first-in-first-out chain, each regular memory cell providing a memory cell output signal that is applied to a respective one of the programmable logic circuits for configuring logic in that programmable logic circuit;
a plurality of shadow memory cells arranged in a first-in-first out chain that are not directly connected to any programmable logic circuits for configuring logic in those programmable logic circuits;
a plurality of load transistors, each connected between one of the register outputs and one of the shadow memory cells for selectively conveying logic element signals to be observed from the registers to the shadow memory cells; and
a test register that is connected to the first-in-first-out chain of shadow memory cells for receiving the logic element signals to be observed from the shadow memory cells and that is connected to the first-in-first-out chain of regular memory cells.
71. The digital processing system defined in claim 70 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
72. The digital processing system defined in claim 70 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
73. The digital processing system defined in claim 70 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
74. A programmable logic device having circuitry for observing logic signals comprising:
a plurality of programmable logic circuits for providing logic signals;
a plurality of memory cells arranged in an array of rows and columns, each memory cell having an output connected to one of the programmable logic circuits for configuring programmable logic in that programmable logic circuit;
a plurality of address lines, each associated with one of the columns of memory cells for addressing the memory cells in that column;
a plurality of data lines, each associated with one of the rows of memory cells for providing programming data to the memory cells in that column;
a test register;
at least one debug output line connected to the test register; and
a plurality of pass transistors, each controlled by one of the data lines and each coupled to one of the programmable logic circuits and connected to the debug output line for selectively passing the logic signals from the programmable logic circuits to the debug output line, the debug output line passing those logic signals to the test register.
75. The programmable logic device defined in claim 74 further comprising a plurality of interconnect drivers, each of which provides logic signals from one of the programmable logic circuits to one of the pass transistors.
76. The programmable logic device defined in claim 75 further comprising additional debug lines connected to the test register.
77. The programmable logic device defined in claim 76 further comprising additional pass transistors connected to the additional debug lines, each of the additional pass transistors being cor oiled by one of the data lines.
78. The programmable logic device defined in claim 77 further comprising additional interconnect drivers connected to the additional pass transistors.
79. The programmable logic device defined in claim 75 wherein the programmable logic circuits comprise programmable logic elements and at least some of the interconnect drivers comprise local line drivers.
80. The programmable logic device defined in claim 75 wherein the programmable logic circuits comprise programmable logic elements and at least some of the interconnect drivers comprise global horizontal line drivers.
81. The programmable logic device defined in claim 75 wherein the programmable logic circuits comprise programmable logic elements and at least some of the interconnect drivers comprise horizontal line drivers.
82. The programmable logic device defined in claim 75 wherein the programmable logic circuits comprise programmable logic elements and at least some of the interconnect drivers comprise vertical line drivers.
83. The programmable logic device defined in claim 74 further comprising:
a plurality of debug lines connected to the test register;
a plurality of pass transistors connected to the debug lines, each of the pass transistors being controlled by one of the data lines and each data line controlling more than one of the pass transistors;
a plurality of interconnect drivers connected to the pass transistors, wherein when one of the data lines is activated, a number of the pass transistors are turned on at the same time and data from the interconnect drivers connected to those pass transistors is passed by the debug lines connected to those pass transistors to the test register.
84. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having:
a plurality of programmable logic circuits for providing logic signals;
a plurality of memory cells arranged in an array of rows and columns, each memory cell providing a memory cell output signal that is applied to one of the programmable logic circuits for configuring programmable logic in that programmable logic circuit;
a plurality of address lines, each associated with one of the columns of memory cells for addressing the memory cells in that column;
a plurality of data lines, each associated with one of the rows of memory cells for providing programming data to the memory cells in that column;
a test register;
at least one debug output line connected to the test register; and
a plurality of pass transistors, each controlled by one of the data lines and each coupled to one of the programmable logic circuits and connected to the debug output line for selectively passing the logic signals from the programmable logic circuits to the debug output line, the debug output line passing those logic signals to the test register.
85. The digital processing system defined in claim 84 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
86. The digital processing system defined in claim 84 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
87. The digital processing system defined in claim 84 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
88. A programmable logic device having circuitry for observing logic signals from programmable logic circuits comprising:
a plurality of programmable logic circuits arranged in rows and columns for providing logic signals;
a plurality of memory cells arranged in an array of rows and columns, each memory cell having an output connected to one of the programmable logic circuits for configuring programmable logic in that programmable logic circuit;
a plurality of address lines, each associated with one of the columns of memory cells for addressing the memory cells in that column;
a plurality of data lines, each associated with one of the rows of memory cells for providing programming data to the memory cells, at least some of the data lines being associated with particular rows of the programmable logic circuits;
a test register;
a plurality of sense lines, each associated with one of the columns of the programmable logic circuits;
a plurality of access transistors, each controlled by one of the data lines that is associated with one of the rows of programmable logic circuits and each being connected between one of the programmable logic circuits in a given column and the sense line associated with that column; and
circuitry for routing signals to the test register from the sense lines, wherein signals from programmable logic circuits to which the access transistors associated with a given data line are connected are routed to the test register via the sense lines and the circuitry for routing when the given data line is activated to turn on those access transistors.
89. The programmable logic device defined in claim 88 wherein the circuitry for routing further comprises a plurality of multiplexers, each having a first input connected to one of the data lines and a second input connected to one of the sense lines and having an output connected to the test register.
90. The programmable logic device defined in claim 89 wherein the circuitry for routing further comprises multiplexer control circuitry for directing the multiplexers to connect their second inputs to their outputs when it is desired to observe signals from a given one of the rows of programmable logic circuits.
91. The programmable logic device defined in claim 89 wherein the circuitry for routing further comprises multiplexer control circuitry for directing the multiplexers to connect their first inputs to their outputs when it is desired to connect the data lines that are connected to the multiplexers to the test register.
92. The programmable logic device defined in claim 88 further comprising preload drivers for receiving preload data from the test register.
93. The programmable logic device defined in claim 92 further comprising circuitry connecting the preload drivers to the sense lines to pass preload data from the preload drivers to the sense lines.
94. The programmable logic device defined in claim 93 wherein the preload data is passed from the preload drivers to the sense lines, the programmable logic device further comprising a plurality of preload transistors, each preload transistor being controlled by one of the data lines and being connected between one of the sense lines and an associated one of the programmable logic circuits for passing the preload data passed to the sense lines to the programmable logic circuits when the data line connected to that preload transistor is activated.
95. The programmable logic device defined in claim 94 further comprising data line control circuitry for activating multiple data lines to simultaneously turn on a plurality of the preload transistors connected to a given sense line.
96. The programmable logic device defined in claim 88 wherein the programmable logic circuits comprise programmable logic elements.
97. The programmable logic device defined in claim 88 wherein the programmable logic circuits comprise logic elements each of which contains a logic element register and a logic element look-up table.
98. The programmable logic device defined in claim 88 further comprising data line control circuitry for activating one of the data lines to turn on the access transistors controlled by that data line.
99. The programmable logic device defined in claim 88 further comprising circuitry for preloading data into the programmable logic circuits.
100. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having:
a plurality of programmable logic circuits arranged in rows and columns for providing logic signals;
a plurality of memory cells arranged in an array of rows and columns, each memory cell having an output connected to one of the programmable logic circuits for configuring programmable logic in that programmable logic circuit;
a plurality of address lines, each associated with one of the columns of memory cells for addressing the memory cells in that column;
a plurality of data lines, each associated with one of the rows of memory cells for providing programming data to the memory cells, at least some of the data lines being associated with particular rows of the programmable logic circuits;
a test register;
a plurality of sense lines, each associated with one of the columns of the programmable logic circuits;
a plurality of access transistors, each controlled by one of the data lines that is associated with one of the rows of programmable logic circuits and each being connected between one of the programmable logic circuits in a given column and the sense line associated with that column; and
circuitry for routing signals to the test register from the sense lines, wherein signals from programmable logic circuits to which the access transistors associated with a given data line are connected are routed to the test register via the sense lines and the circuitry for routing when the given data line is activated to turn on those access transistors.
101. The digital processing system defined in claim 100 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
102. The digital processing system defined in claim 100 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
103. The digital processing system defined in claim 100 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
104. A programmable logic device having circuitry for observing logic signals from programmable logic circuits comprising:
a plurality of programmable logic circuits for providing logic signals;
a plurality of memory cells arranged in an array of rows and columns, each memory cell providing a memory cell output signal that is applied to one of the programmable logic circuits for configuring programmable logic in that programmable logic circuit;
a plurality of address registers connected in at least one chain, the plurality of address registers containing at least one debug address register;
a plurality of data lines, each associated with one of the rows of memory cells for providing programming data to the memory cells, at least some of the data lines being associated with particular ones of the programmable logic circuits;
a plurality of access transistors, each associated with one of the particular programmable logic circuits and connected between an output of that programmable logic circuit and one of the data lines associated with the particular programmable logic circuits;
a test register to which at least the data lines that are associated with the particular programmable logic circuits are connected; and
circuitry for conveying signals from the debug address register to at least one of the access transistors for controlling that access transistor, wherein the signals that are conveyed from the debug address register to that access transistor turn on that access transistor when it is desired to observe logic signals from the programmable logic circuit connected to that access transistor so that those logic signals are provided to the test register by the data lines connected to that access transistor.
105. The programmable logic device defined in claim 104 further comprising:
data line control circuitry to which at least the data lines that are associated with the particular programmable logic circuits are connected;
at least one preload address register connected to the plurality of address registers;
a plurality of preload transistors each associated with one of the particular programmable logic circuits and connected between a given one of the data lines associated with that programmable logic circuit and an input of that programmable logic circuit; and
circuitry for conveying signals from the preload address register to the preload transistors for controlling the preload transistors, wherein the signals that are conveyed from the preload address register to the preload transistors turn on the preload transistors to preload signals from the data line control circuitry into at least one of the programmable logic circuits via at least one of the data lines and at least one of the turned on preload transistors.
106. The programmable logic device defined in claim 105, wherein the circuitry for conveying signals from the preload address register further comprises a preload address line.
107. The programmable logic device defined in claim 106 further comprising verify control logic between the preload address register and the preload address line for selectively connecting the preload address register to preload address line.
108. The programmable logic device defined in claim 105 wherein the circuitry for conveying signals from the preload address register turns on the preload transistors in parallel to preload signals from the data line control circuitry into the programmable logic circuits in parallel via the data lines and the preload transistors that are turned on.
109. The programmable logic device defined in claim 104 wherein the circuitry for conveying signals from the debug address register further comprises a debug address line.
110. The programmable logic device defined in claim 104 wherein the circuitry for conveying signals from the debug address register further comprises circuitry for conveying signals to a plurality of the access transistors in parallel.
111. The programmable logic device defined in claim 104 wherein the circuitry for conveying signals from the debug address register further comprises a debug address line connected to a plurality of the access transistors in parallel.
112. The programmable logic device defined in claim 105 further comprising at least one preload address register connected to the plurality of address registers.
113. The programmable logic device defined in claim 105 further comprising a plurality of preload transistors each associated with one of the particular programmable logic circuits and connected between an input of that programmable logic circuit and one of the data lines associated with the particular programmable logic circuits.
114. The programmable logic device defined in claim 105 further comprising:
at least one preload address register connected to the plurality of address registers;
a plurality of preload transistors each associated with one of the particular programmable logic circuits and connected between an input of that programmable logic circuit and one of the data lines associated with the particular programmable logic circuits; and
circuitry for conveying signals from the preload address register to the plurality of preload transistors for controlling the plurality of preload transistors in parallel, wherein the signals that are conveyed from the preload address register to the preload transistors turn on the preload transistors in parallel when it is desired to preload signals from the data lines connected to the preload transistors into the programmable logic circuits with which the preload transistors are associated.
115. The programmable logic device defined in claim 105 further comprising data line control circuitry to which at least the data lines that are associated with the particular programmable logic circuits are connected.
116. A digital processing system comprising:
a processor;
a memory coupled to the processor; and
a programmable logic device coupled to the processor and the memory, the programmable logic device having:
a plurality of programmable logic circuits for providing logic signals;
a plurality of memory cells arranged in an array of rows and columns, each memory cell providing a memory cell output signal that is applied to one of the programmable logic circuits for configuring programmable logic in that programmable logic circuit;
a plurality of address registers connected in at least one chain, the plurality of address registers containing at least one debug address register;
a plurality of data lines, each associated with one of the rows of memory cells for providing programming data to the memory cells, at least some of the data lines being associated with particular ones of the programmable logic circuits;
a plurality of access transistors, each associated with one of the particular programmable logic circuits and connected between an output of that programmable logic circuit and one of the data lines associated with the particular programmable logic circuits;
a test register to which at least the data lines that are associated with the particular programmable logic circuits are connected; and
circuitry for conveying signals from the debug address register to at least one of the access transistors for controlling that access transistor, wherein the signals that are conveyed from the debug address register to that access transistor turn on that access transistor when it is desired to observe logic signals from the programmable logic circuit connected to that access transistor so that those logic signals are provided to the test register by the data lines connected to that access transistor.
117. The digital processing system defined in claim 116 further comprising a circuit board on which the memory, the processor, and the programmable logic device are mounted.
118. The digital processing system defined in claim 116 further comprising input/output circuitry coupled to the programmable logic device, the processor, and the memory.
119. The digital processing system defined in claim 116 further comprising peripheral drivers coupled to the programmable logic device, the processor, and the memory.
Description
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices. More particularly, this invention relates to observing logic signals at the outputs of various programmable logic circuits on programmable logic devices and preloading data into such programmable logic circuits.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. As programmable logic devices become more complex, it is becoming desirable to observe the logic signals on internal device nodes in order to determine whether a device is functioning properly. The ability to observe such logic signals (e.g., at the outputs of logic elements or other programmable logic circuits) reduces test costs by reducing test development time and test run time during manufacturing. The ability to observe these logic signals also helps to reduce the time needed to successfully debug a given design for a programmable logic device. Being able to preload data into certain programmable logic circuits also reduces test costs and helps to reduce the time needed to debug a design.
It is therefore an object of the present invention to provide arrangements for observing logic signals from various programmable logic circuits on a programmable logic device.
It is another object of the present invention to provide arrangements for preloading data into certain programmable logic circuits on a programmable logic device.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing programmable logic devices that contain circuitry for observing logic signals from programmable logic circuits during device testing. The programmable logic devices may also contain circuitry for preloading test signals into the programmable logic circuits.
The programmable logic circuits each contain programmable logic that may be configured using configuration signals applied from memory cells or other suitable control elements in which programming data has been stored. If desired, the programmable logic circuits may be programmable logic elements that contain combinatorial logic such as look-up table logic and that contain register logic. Programmable logic elements are typically arranged in at least one column or row, and on some programmable logic devices are arranged in arrays containing both columns and rows.
Programmable logic elements may be organized in groups of logic called logic array blocks. Each logic array block may be part of a larger logic region called a group of logic array blocks. Interconnection conductors of various lengths may be used to interconnect the logic in regions of different sizes.
One aspect of the invention involves using an array of addressable access transistors to observe logic signals. In an array of programmable logic elements, each programmable logic element may be provided with an associated access transistor at its combinatorial or registered output. Decoder logic may be used to turn on a given row of the access transistors. Turning on the access transistors allows signals from the logic elements to be passed to a test register.
If desired, additional logic may be used to select a given column of logic elements from which it is desired to observe logic signals. A snapshot may be taken of the logic element signals at a given point in time by freezing the clock applied to the logic elements. Sense lines may be used to route logic signals from the access transistors to the test register. Each logic element may be connected to a pair of sense lines by a pair of respective access transistors (e.g., one access transistor used to observe combinatorial signals and one access transistor used to observe registered signals).
Another aspect of the invention involves the use of registers on a programmable logic device that may be connected in a scan chain by switching circuits (i.e., multiplexers) when it is desired to observe logic element signals. The switching circuits have logic element inputs that receive signals from logic elements. The switching circuits also have scan chain inputs. The outputs of the switching circuits are connected to the registers. During normal operation, the switching circuits are configured to connect their logic element inputs to their outputs so that the logic signals from the logic elements are stored in the registers. During register observation, the switching circuits are configured to connect their scan chain inputs to their outputs so that the logic signals stored in the registers may be scanned out of the registers through the scan chain. The registers can also be initialized using the scan chain. Clock and clear control logic may be used to prevent data corruption during transitions between modes (i.e., during the transition between register initialization and normal operation and during the transition between normal operation and register observation).
Similar switching circuits may also be provided to observe memory block signals that are stored in the input and output registers of a programmable logic device memory block and to initialize those registers if desired. The programmable logic device may have rows and columns of groups of logic array blocks. Each group of logic array blocks may contain a plurality of logic array blocks, each of which contains a plurality of memory elements, and a memory block. The switching circuits associated with the logic elements and the memory block switching circuits may be connected to form a number of scan chains, each of which is associated with a separate row of the groups of logic array blocks. This allows the registers in each row to be initialized in parallel and for logic signals in each row to be observed in parallel.
Another aspect of the invention involves programmable logic device arrangements in which logic signals may be observed by making logic element registers part of first-in-first-out (FIFO) programming chains that are used on the device to program certain programmable logic circuits. The logic element registers may be incorporated into the FIFO chains by connecting the output of a memory cell in the chain to either the master latch input or slave latch input of the register.
The memory cells in the chain may be programmed with programming data to configure programmable logic within the programmable logic circuits to which the memory cells are connected. During normal operation of the programmable logic device, the logic element registers that are connected in the FIFO chain are used to register signals in the logic elements.
The programmable logic device may be operated in a programming mode (when programming data is placed in the memory cells), a user mode (when the device is operating normally) and a verify mode (when the device is being tested). The logic element registers each have a clock input. The programmable logic device is provided with clock control logic for controlling the clock signals applied to the clock input to ensure that there is no possibility of data corruption when entering the user mode from the programming mode or when leaving the user mode to enter the verify mode.
Another aspect of the invention involves arrangements for observing register signals on a programmable logic device using a chain of shadow memory cells. The shadow memory cells may be made part of a first-in-first-out chain of regular memory cells that are used to apply programming data to configure logic in various programmable logic circuits on the programmable logic device. The shadow memory cells are not directly connected to any programmable logic circuits for configuring the logic in those circuits. Shadow memory cells may be interspersed between respective regular memory cells in the first-in-first-out programming chain. If desired, the shadow memory cells may be arranged in a chain that contains only shadow memory cells. After the logic element register data that is to be observed has been loaded into the shadow memory cells in the chain, the data may be unloaded from the chain into a test register.
The outputs of the shadow memory cells may be applied to feedback terminals for the logic element registers using preload transistors. Preload data may be shifted into the shadow memory cells using the first-in-first-out chain. The registers may then be preloaded by turning on the preload transistors so that the preload data from the shadow memory cells passes to the logic element registers.
Another aspect of the invention relates to observing logic signals from programmable logic circuits on a programmable logic device in which programming data for the programmable logic circuits is stored in an array of memory cells. The programming data may be provided to the array using data lines. Each data line may be associated with a separate row of the memory cells. Memory cells may be addressed using address lines, each of which may be associated with a column of the memory cells.
The programmable logic circuits may be programmable logic elements that are organized in logic array blocks and groups of logic array blocks. Data from the programmable logic circuits may be provided to interconnect drivers such as local line drivers, global horizontal line drivers, vertical line drivers, and horizontal line drivers. A number of pass transistors may be provided for selectively connecting the interconnect drivers to debug output lines. The data to be observed from the programmable logic circuits is provided to a test register by the debug output lines.
Another aspect of the invention relates to observing programmable logic circuit logic signals on a programmable logic device using sense lines each of which is associated with a different column of programmable logic circuits. The programmable logic device has memory cells that may be programmed with programming data to configure programmable logic within the programmable logic circuits. Data lines may be used to provide the programming data to the memory cells. Address lines may be used to address particular memory cells when the programming data is being stored in the memory cells.
Access transistors are associated with each programmable logic circuit for selectively conveying the logic signals from that programmable logic element to the associated sense line. Routing circuitry is provided that routes the signals that are to be observed from the access transistors to a test register. The routing circuitry may contain a number of multiplexers each of which has one input connected to one of the data lines and another input connected to one of the sense lines. The outputs of the multiplexers are connected to the test register. The multiplexers may be configured to connect their sense line inputs to their outputs when it is desired to pass the logic signals that are to be observed from the access transistors to the test register. The multiplexers may also be configured to connect their data line inputs to their outputs when it is desired to connect the data lines to the test register.
The programmable logic device contains preload circuitry for preloading data into the programmable logic circuits. A preload transistor that is controlled by one of the data lines may be associated with each of the programmable logic circuits. Preload data may be provided to the test register. Preload drivers and routing circuitry may be used to provide the preload data to the preload transistors. When the data line that controls a given preload transistor is activated, the preload transistor is turned on and the preload data provided to the preload transistors is preloaded into the associated programmable logic circuit.
Logic signals may be observed from all of the programmable logic circuits in a row simultaneously by turning on all of the access transistors in a row that are controlled by a given data line in that row. Similarly, preload data may be provided to all of the programmable logic circuits in a row simultaneously by turning on all of the preload transistors that are controlled by a given data line in that row.
Another aspect of the invention relates to observing programmable logic circuit logic signals on a programmable logic device using an arrangement in which a debug address register is provided as part of an address register chain. The output of the debug address register controls access transistors that are connected to the outputs of various programmable logic circuits. When a suitable debug address bit is shifted into the debug address register, the access transistors connected to that debug address register are turned on. This causes the logic signals from the programmable logic circuits connected to the turned on access transistors to be provided to associated data lines. The data lines convey the logic signals to a test register for observation and analysis.
Data may be preloaded into the programmable logic circuits using preload transistors connected between data lines associated with the programmable logic circuits and inputs to the programmable logic circuits. Preload transistors may be controlled by signals from a preload address register provided in a chain of address registers. The chain of address registers in which the preload address register is provided and the chain of address registers in which the debug address register is provided may be either the same chain or different chains.
Memory cells on the programmable logic device receive programming data via the data lines. The outputs of the memory cells are applied to the programmable logic circuits to configure programmable logic in the programmable logic circuits. The regular address registers in each address register chain are used to store address signals that are applied to the memory cells via address lines. The address signals selectively direct the programming data that is provided on the data lines into desired memory cells during device programming.
Further features of the invention and its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of an illustrative programmable logic device having programmable logic elements arranged in logic array blocks and groups of logic array blocks in accordance with the present invention.
FIG. 2 is a diagram of illustrative circuitry for observing logic element signals with an array of access transistors and associated sense lines in accordance with the present invention.
FIG. 3 is a diagram of illustrative circuitry for observing logic element logic signals with an array of column-addressable access transistors and associated sense lines in accordance with the present invention.
FIG. 4 is a diagram of an illustrative logic element from which registered logic signals may be observed using a sense line in accordance with the present invention.
FIG. 5 is a diagram of an illustrative logic element from which combinatorial or registered logic signals may be observed using a sense line in accordance with the present invention.
FIG. 6 is a diagram of an illustrative logic element from which both registered and combinatorial logic signals may be observed simultaneously using two sense lines in accordance with the present invention.
FIG. 7a is a diagram of illustrative circuitry for observing logic element signals using switching circuits to selectively connect logic element registers into a chain from which the logic element signals may be shifted in accordance with the present invention.
FIG. 7b is a diagram of more illustrative circuitry for observing logic element signals using switching circuits to selectively connect logic element registers into a chain from which the logic element signals may be shifted in accordance with the present invention.
FIG. 7c is a diagram illustrating how memory block registers may be interconnected by switching circuits to form chains in accordance with the present invention.
FIG. 7d is a diagram illustrating how input/output registers, logic element registers, and memory block registers can be connected to form a chain in accordance with the present invention.
FIG. 7e is a diagram illustrating how the logic array blocks (LABs) and embedded array blocks (EABs) in the groups of logic array blocks (GOLs) in a row may be interconnected to form a chain in accordance with the present invention.
FIG. 8 is a diagram of a conventional first-in-first out chain of memory cells whose outputs are used to configure programmable logic within various programmable logic elements.
FIG. 9 is a diagram of a portion of an illustrative first-in-first-out programming chain into which a logic element register has been incorporated so that logic signals from that register may be observed in accordance with the present invention.
FIGS. 10a and 10b are diagrams of conventional register circuitry of a type that may be used with the present invention.
FIG. 10c is a diagram of the NCLK signal used in operating the register circuitry of FIGS. 10a and 10b.
FIG. 11 is a diagram of illustrative register circuitry that may be used in a first-in-first-out programming chain in accordance with the present invention.
FIG. 12 is a timing diagram illustrating the operation of the circuitry of FIG. 11 in accordance with the present invention.
FIG. 13 is a table of attributes associated with using positive edge triggered register circuitry and negative edge triggered register circuitry in a first-in-first-out programming chain using the FIG. 11 register circuitry arrangement in accordance with the present invention.
FIG. 14 is a diagram of additional illustrative register circuitry that may be used in a first-in-first-out programming chain in accordance with the present invention.
FIG. 15 is a timing diagram illustrating the operation of the circuitry of FIG. 14 in accordance with the present invention.
FIG. 16 is a table of attributes associated with using positive edge triggered register circuitry and negative edge triggered register circuitry in a first-in-first-out programming chain using the FIG. 14 register circuitry arrangement in accordance with the present invention.
FIG. 17 is a diagram of additional illustrative register circuitry that may be used in a first-in-first-out programming chain in accordance with the present invention.
FIG. 18 is a timing diagram illustrating the operation of the circuitry of FIG. 17 in accordance with the present invention.
FIG. 19 is a diagram showing the operation of the FIG. 17 arrangement at time t=2 in accordance with the present invention.
FIG. 20 is a diagram showing the operation of the FIG. 17 arrangement at time t=5 in accordance with the present invention.
FIG. 21 is a diagram showing the operation of the FIG. 17 arrangement at time t=11 in accordance with the present invention.
FIG. 22 is a diagram of illustrative circuitry in which a first-in-first-out chain having shadow memory cells is used for observing programmable logic circuit signals on a programmable logic device in accordance with the present invention.
FIG. 23 is a flow chart of illustrative steps involved in using the FIG. 22 arrangement to observe logic signals in accordance with the present invention.
FIG. 24 is a diagram of illustrative circuitry in which a first-in-first-out chain having shadow memory cells is used for observing logic signals from programmable logic circuits and for preloading preload data into the programmable logic circuits on a programmable logic device in accordance with the present invention.
FIG. 25 is a diagram of illustrative register circuitry suitable for use in the arrangement of FIG. 24 in accordance with the present invention.
FIG. 26 is a flow chart of illustrative steps involved in preloading data into the registers of the FIG. 24 arrangement and observing logic signals from those registers in accordance with the present invention.
FIG. 27 is a diagram of illustrative circuitry in which a first-in-first-out chain having only shadow memory cells is used for observing logic signals from programmable logic circuits and for preloading preload data into the programmable logic circuits on a programmable logic device in accordance with the present invention.
FIG. 28 is a diagram of illustrative circuitry for observing logic signals from programmable logic circuits in which the data lines that are used for providing data to an array of programming memory cells are also used to control access transistors that are connected between drivers associated with the programmable logic circuits and various debug output lines in accordance with the present invention.
FIG. 29 is a diagram of illustrative programmable logic element circuitry that may be used for the programmable logic circuits of FIG. 28 in accordance with the present invention.
FIG. 30 is a diagram of illustrative circuitry for observing logic signals from programmable logic circuits arranged in an array with associated data lines and sense lines in accordance with the present invention.
FIG. 31 is a flow chart of illustrative steps involved in preloading data into the programmable logic circuits of FIG. 30 in accordance with the present invention.
FIG. 32 is a flow chart of illustrative steps involved in observing logic signals from the programmable logic circuits of FIG. 30 in accordance with the present invention.
FIG. 33 is a diagram of illustrative circuitry for observing programmable logic circuit logic signals on a programmable logic device in which access transistors are controlled by signals stored in debug address registers that are part of a chain of memory cell address registers in accordance with the present invention.
FIG. 34 is a flow chart of illustrative steps involved in preloading data into the programmable logic circuits of FIG. 33 in accordance with the present invention.
FIG. 35 is a flow chart of illustrative steps involved in observing logic signals from the programmable logic circuits of FIG. 33 in accordance with the present invention.
FIG. 36 is a diagram of an illustrative system in which the programmable logic device arrangements of the present invention may be used.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention relates to schemes for observing logic signals from programmable logic circuits on programmable logic devices and for preloading data into various programmable logic circuits. The ability to observe logic signals and the ability to preload data is useful when debugging a programmable logic device during development.
One aspect of the invention involves using a Joint Test Action Group (JTAG) test access port to access internal nodes. The JTAG test access port is a standard type of test access port specified in "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993. JTAG ports use a relatively small number of pins such as TMS (test mode select), TCK (test clock), TDI (test data in), and TDO (test data out) to perform various boundary scan tests. Conventional boundary scan testing involves observing a small subset of the observable nodes in a device using special boundary scan cells arranged in a chain throughout the device.
In accordance with the present invention, JTAG test access ports may be used to supply test data to various portions of programmable logic circuitry on the device and to route signals from probed internal nodes off of the device. The JTAG test access port may be used when observing internal nodes on any suitable type of programmable logic device. The testing schemes of the present invention are primarily described in connection with the use of programmable logic devices of the type shown in FIG. 1 to simplify the presentation of this material. The internal nodes of any other suitable type of programmable logic device or logic integrated circuit may be observed in a similar fashion if desired.
Programmable logic device 10 of FIG. 1 has a number of programmable logic elements (LEs) 12, each of which contains one or more registered nodes 14 and one or more combinatorial nodes 16 from which logic signals are to be observed. Logic elements 12 (sometimes referred to as macrocells) may be any suitable type of programmable logic device logic elements, such as logic elements based on look-up table logic, product term logic, or any other suitable type of logic. A typical combinatorial node 16 may be the output of a look-up table. The look-up table may feed a register whose output may be one of the registered nodes 14.
Logic elements 12 may be arranged in groups of elements called logic array blocks (LABs). The logic elements 12 in each logic array block 18 may be interconnected by local lines 20. Multiple logic array blocks 18 may be arranged as a group of LABs (GOL). Within each GOL 22, signals may be routed between LABs 18 via global horizontal (GH) lines 24. Signals may be vertically routed between GOLs 22 in a column by vertical (V) lines 26. Signals may be horizontally routed between GOLs 22 in a row by horizontal (H) lines 28. Other suitable programmable logic device arrangements may use different types of conductors, such as global vertical (GV) conductors to vertically connect LABs 18 that are arranged in columns within a GOL 22. Interconnection conductors such as local lines 20, GH lines 24, horizontal lines 28, and vertical lines 26 may include fractional length conductors (e.g., half-length, quarter-length, eighth-length conductors, etc.).
Programmable logic device 10 may have a JTAG test access port made up of a multiple-pin interface 30 connected to test circuitry 32 containing JTAG block 34. Interface 30 may contain a test data in pin 36, a test data out pin 38, a test clock pin 40, and a test mode select pin 42. Test data in pin 36 is used to apply test signals to device 10. Test data out pin 38 is used to read out logic signals from device 10. Test clock pin 40 is used to supply a test clock to test registers on device
10. Test mode select pin 42 is used to control the mode of device 10 (e.g., to isolate logic to be tested from surrounding circuitry). JTAG block 34 contains hardware and software based components 44, 46, 48, and 50 for providing JTAG functions.
An approach for monitoring internal device nodes that allows a snapshot of the logic signals on the monitored nodes to be taken is shown in FIG. 2. In the illustrative programmable logic device 52 of FIG. 2, logic element outputs 54 are shown as being registered nodes (i.e., outputs 54 are located at the output of logic element registers 56, which are part of logic elements such as logic element 58). However, outputs 54 may be combinatorial nodes if desired. Multiple logic elements (e.g., eight logic elements) such as logic elements 58 may be part of a logic array block such as logic array block 74.
When a snapshot of the logic signals at outputs 54 is to be taken, the clock signal applied to clock inputs 57 of registers 56 is frozen. X decoder 60 then takes a selected one of access transistor control lines 62 high, thereby turning on the access transistors 64 in that row. This causes the logic signals on the outputs 54 in the row to be provided to test register 66 via sense lines 67. The captured signals may then by scanned out of test register 66 via test data out pin 68. If desired, test register 66 may be the test register normally used for unloading programming data supplied to first-in-first-out (FIFO) programming chains of memory cells on the programmable logic device during testing of these FIFO chains (e.g., under conditions of different temperature, power supply voltage, etc.).
Signals supplied to x decoder 60 using JTAG address register 70 and test data in pin 72 may be used to determine which of the access transistor control lines 62 are taken high by x decoder 60. The use of JTAG address register 70 to store these signals reduces the number of test pins required to supply such signals to access transistor control lines 62. If desired, the clock signal applied to clock inputs 57 may be frozen, the signals examined, and the clock signal subsequently restarted. In the arrangement of FIG. 2 and in the other arrangements described herein, the use of the JTAG test access port may be desirable, but is not required. Any suitable test interface may be used.
Another approach for observing logic signals from logic elements on a programmable logic device that allows a snapshot of the signals to be taken is shown in FIG. 3. In programmable logic device 76 of FIG. 3, outputs 78 are shown as being registered nodes (i.e., nodes that are located at the output of logic element registers 80, which are part of logic elements such as logic elements 82). If desired, outputs 78 may be combinatorial nodes. Multiple logic elements (e.g., eight logic elements) such as logic elements 82 may be part of a logic array block such as logic array block 102.
When a snapshot of the state of outputs 78 is to be taken, the clock signal applied to clock inputs 81 of registers 80 is frozen. X decoder 84 then takes a selected one of access transistor control lines 86 high, thereby turning on the access transistors 88 in that row. This causes the logic signals on the outputs 78 in the row to be provided to test register 90 via sense lines 91. The signals are captured by test register 90. The signals may then be scanned out of test register 90 via line 92, multiplexer 94, and test data out pin 96. If desired, test register 90 may be the test register normally used for unloading programming data supplied to first-in-first-out (FIFO) programming chains of memory cells on the programmable logic device. The state of multiplexer 94 is controlled by control signals provided from a JTAG block such as JTAG block 34 of FIG. 1, so that the signals on line 92 are connected to test data out pin 96.
Signals supplied to x decoder 84 using JTAG address register 98 and test data in pin 100 may be used to determine which of the access transistor control lines 86 are taken high by x decoder 84. The use of JTAG address register 98 to store these signals reduces the number of test pins required to supply such signals to access transistor control lines 86. If desired, the clock signal applied to clock inputs 81 may be frozen, the signals examined, and the clock signal subsequently restarted.
In addition to snapshot measurements of the signals on outputs 78, the arrangement of device 76 allows the signals on outputs 78 to be continuously monitored in real time. The user may select a given output to observe by using x decoder 84 to turn on a given row of access transistors 88 and by simultaneously using column select logic 104 to turn on a selected one of column select transistors 106, 108, and 110 using the appropriate column select line 112, 114, or 116. For example, to observe logic signals at output 78a, x decoder 84 takes the access transistor control line 86 that is in the second row of logic elements 80 and access transistors 88 high, thereby turning on all of the access transistors 88 in that row. This connects the nodes
78 in that row to lines 118, 120, and 122, respectively, via sense lines 91. While x decoder 84 turns on the appropriate row of access transistors 88, column select logic 104, which is controlled by signals received from JTAG address register 98, turns on access transistor 110 by taking column select line 116 high, so that the signal on the sense line 91 that is associated with output 78a is routed to common output 123 and input 124 of multiplexer 94. The state of multiplexer 94 is controlled by control signals provided from a JTAG block such as JTAG block 34 of FIG. 1, so that the signals on input 124 are connected to test data out pin 96. The user can continuously monitor the signals on test data out pin 96 (which are real-time logic signals from output 78a) to aid in debugging device 76.
The arrangements of FIGS. 2 and 3 provide wide-scale observability of the logic signals on the programmable logic device, because the outputs of all or nearly all of the logic elements on the device may be monitored if desired. In contrast, standard JTAG boundary scan schemes only allow users to observe signals at a relatively small number of scan cells, which are located around the periphery of a region of logic. The arrangements of FIGS. 2 and 3 also allow logic elements to be addressed by row. Both arrangements allow snapshot monitoring. The arrangement of FIG. 3 also allows nodes to be continuously monitored in real time. Because the JTAG test access port is used in both arrangements, testing is possible using standard programmable logic device test equipment.
Various approaches may be used for connecting access transistors such as access transistors 64 of FIG. 2 and access transistors 88 of FIG. 3 to the programmable logic device nodes of interest. One such approach is shown in FIG. 4. In the FIG. 4
arrangement, access transistor 126 is connected to registered node 128 via driver 130. Logic element 132 has a combinatorial node 134 at the output of look-up table 136, but the FIG. 4 arrangement does not allow the signal at that node to be monitored directly. To monitor the logic element output signal at node 128, the user takes access transistor control line 138 high to turn on access transistor 126 and thereby connect node 128 to sense line 140. Sense line 140 and access transistor control line
138 may be connected to circuitry such as the circuitry shown in FIGS. 2 and 3.
Other circuitry shown in the illustrative logic element 132 of FIG. 4 includes bypass multiplexer 142, and output drivers 144 and 146. Multiplexers 148 and 150 are used to select the desired output signals for output drivers 144 and 146. Output driver 144 may drive logic element output signals onto global lines such as global horizontal line 24 of FIG. 1. Output driver 146 may drive logic element output signals onto local lines such as local lines 20 of FIG. 1. Other drivers (not shown in FIG. 4) may be used to drive logic element output signals onto vertical and horizontal lines such as V lines 26 and H lines 28 of FIG. 1.
Another arrangement for connecting the access transistor to the node of interest is shown in FIG. 5. The FIG. 5 arrangement allows logic element output signals at both registered node 152 and combinatorial node 154 to be observed. When multiplexer 156 is configured to connect combinatorial node 154 to global lines 155, signals at node 154 may be provided to access transistor 158 via drivers 160 and 162. When multiplexer 156 is configured to connect registered node 152 to global lines
155, signals at node 152 may be provided to access transistor 158 via drivers 160 and 162.
With the arrangement shown in FIG. 6, logic element signals at combinatorial node 164 and registered node 166 can both be observed simultaneously. For example, when multiplexer 168 is configured to connect combinatorial node 164 to global lines
170 via driver 172, the signal on combinatorial node 164 may be observed by turning on access transistor 174 with access transistor control line 176. This causes the signal on node 164 to be applied to sense line 178 via multiplexer 168, driver 172, driver 180, and access transistor 174. If, at the same time, multiplexer 182 is configured to connect registered node 166 to local lines 184 via driver 186, the signal on registered node 166 may be observed simultaneously by turning on access transistor
188 with access transistor control line 176. This causes the signal on node 166 to be applied to sense line 190 via multiplexer 182, driver 186, driver 192, and access transistor 188.
Similarly, signals from node 164 can be observed at sense line 190 while signals from node 166 are simultaneously observed at sense line 178, provided that multiplexers 168 and 182 are configured appropriately. However, if multiplexers 168 and
182 are configured so that logic element output signals from the same node (i.e., either combinatorial node 164 or registered node 166) are applied to both global lines 170 and local lines 184 at the same time, then only signals from that single node may be observed.
Another programmable logic device arrangement for observing programmable logic element output signals is shown in FIG. 7a. In the arrangement of FIG. 7a, logic element registers 194 are connected in a scan chain using switching circuits (multiplexers) 196. Registers 194 are the registers used for providing registered logic element output signals (i.e., registers 194 generally operate like the logic element registers shown in FIGS. 4-6). Each switching circuit 196 has at least one logic element input 198 and a scan chain input 200. Logic elements 201 may be arranged in logic array blocks 203 each of which may contain, e.g., eight logic elements 201.
During normal programmable logic device operation, the logic element input 198 of each switching circuit 196 receives logic signals from logic element logic 202 (e.g., logic of the general type shown in the logic element arrangements of FIGS.
4-6). Each switching circuit 196 directs the signal from its input 198 to its output 204. The signals on switching circuit outputs 204 are registered by logic element registers 194 and provided to logic element outputs 206. The signals on logic element outputs 206 are routed by driver circuitry to local lines, global horizontal (GH) lines, V lines, and H lines. A normal clock signal is applied to clock inputs 208 of registers 194 during normal operation.
During register observation, a suitable instruction is provided (e.g., with a JTAG TAP controller such as JTAG TAP controller 44 of FIG. 1) that freezes the state of the device by stopping the normal clock and reconfiguring switching circuits 196
to form a continuous scan chain by connecting scan chain inputs 200 to outputs 204. Scan chain conductors 210 connect the outputs of each register 194 to the scan chain input 200 of a successive switching circuit 196 in the chain. A scan clock is applied to clock inputs 208 of registers 194 to scan the contents of registers 194 out of the scan chain using test data output 212.
If desired, registers 194 may be initialized by loading registers 194 with data provided at test data input 214 when registers 194 are in the scan chain configuration. During initialization, an initialization clock is applied to clock inputs
208. After the registers have been loaded with initialization data, the device can be operated normally.
Both test data input 214 and test data output 212 are preferably coupled to pins that are part of a JTAG test access port such as the JTAG test access port shown in FIG. 1.
Because the arrangement of FIG. 7a requires only a relatively small amount of additional circuitry to provide test coverage, the FIG. 7a arrangement is a cost-effective way in which to provide wide-scale observability of the logic signals on a programmable logic device. If desired, an arrangement similar to the arrangement shown in FIG. 7a may be implemented by using programmable logic resources to form the scan chain conductor connections.
As shown in FIG. 7b, the switching circuits may have more than one logic element input. Switching circuit 196' in logic element 18' has logic element input 198a, which is a combinatorial output of look-up table logic 199, and logic element input
198b, which is a signal line that bypasses look-up table logic 199. To form a scan chain, gate 203a is turned on using control line 205a while gates 203b and 203c are turned off using control lines 205b and 205c. This connects scan in line 201a to the scan out line of a preceding logic element in the chain. Scan out line 201b is connected to the scan in line of the next logic element in the chain. Accordingly, when gate 203a is turned on, initialization data may be scanned into registers 207 using an initialization clock provided at initialization clock line 209a.
During normal operations, either gate 203b or gate 203c is turned on while gate 203a is turned off. This allows logic signals from logic element logic 202 to be provided to register 207 via switching circuit output 204', while a normal clock is provided at normal clock line 209b.
To observe logic signals in registers 207 after a period of normal operation, gate 203a is turned on while gates 203b and 203c are turned off. This forms a scan chain of registers 207 that allows logic signals to be scanned out of the registers
207 using a scan clock provided at scan clock line 209c.
Care must be taken during the transition from initialization mode to normal mode and during the transition from normal mode to scan out mode to avoid corrupting the register data. For example, during the transition from initialization mode to normal mode, the initialization clock applied to registers 207 must be replaced by the normal clock while ensuring that sufficient time is allowed for logic element signals on inputs 198a and 198b to settle and for the gates in switching circuit 196' to switch completely. During transitions from normal mode to register observation mode, the normal clock applied to registers 207 must be replaced by the scan clock. The register clear must be held inactive during these transitions.
If testing is being performed by a manufacturer, the manufacturer may use automated test equipment to ensure that appropriate clock and clear signals are applied to registers 207 to avoid data corruption. Logic such as clock and clear control logic 211 may be provided on the device if it is desired for users without access to such test equipment to be able to test the device. Clock and clear control logic 211 receives information on the state of switching circuit 196' via line 213. Clock and clear control logic 211 also receives control signals via line 215 that may be used to instruct clock and clear control logic when to apply the clocks received via lines 209a, 209b, and 209c to clock line 217. Clock and clear control logic 211
distributes clear signals to registers 207 on clear line 219. Clock and clear control logic 211 also ensures that the clear signal on clear line 219 is held inactive during transitions and ensures that the clock signals provided to clock line 217 are such that the contents of registers 207 are not corrupted during transitions. Moreover, clock and clear control logic 211 ensures that the clear signals applied to line 219 are held inactive during intialization and scan mode.
As shown in FIG. 7c, switching circuits 196" can be used to form one or more chains of memory block input registers 219a and memory block output registers 219b. Memory block 221 contains memory circuit 223 which contains a memory array. Memory block registers 219a and 219b may be the registers used at the inputs and outputs of memory circuit 223.
Memory block scan chain conductors are used to connect the output of each memory block register to the memory block scan chain input of a memory block switching circuit associated with a successive one of the memory block registers, thereby forming a continuous scan chain. During normal operation, each memory block switching circuit 196" is configured to connect its memory block switching circuit input to its memory block switching circuit output so that memory block signals are stored in the memory block registers. During register observation each memory block switching circuit is configured to connect its memory block scan chain input to its memory block switching circuit output so that the memory block signals stored in the registers may be scanned out of the registers through the continuous scan chain. Initialization data may also be supplied through the scan chain if desired.
FIG. 7d shows how a scan chain using the switching circuits of the type shown in FIGS. 7a, 7b, and 7c may be formed from input/output registers 225, logic element registers 207, and memory block registers 219.
When a memory block such as memory block 221 of FIG. 7c is provided in a GOL such as one of GOLs 22 of FIG. 1, the memory block may sometimes be referred to as an embedded array block (EAB). As shown in FIG. 7e, test chains may be formed by connecting the logic element registers in the logic array blocks 18 and embedded array blocks 221' that are contained in the GOLs 22 in a particular row on a programmable logic device. If a number of such chains are formed, each in a row of GOLs 22, testing (i.e., both initialization and logic signal observation) may be performed in each of the rows in parallel, thereby increasing testing throughput.
Another aspect of the invention relates to using the first-in-first-out (FIFO) programming memory cell chains on a programmable logic device to either load initialization data or to scan out logic signals for observation during testing. Programmable logic device FIFO chains are used for configuring programmable logic devices to perform desired logic functions. A user may load programming data into the FIFO chains using a programmer. The programming data in each memory cell in the chain causes that cell to turn on or to turn off an associated programmable connector (e.g., a transistor). By providing all such FIFO cells with appropriate programming data, the user may configure the programmable logic device.
A small portion of a typical programmable logic device FIFO chain is shown in FIG. 8. FIFO chain 216 contains FIFO memory cells such as random access memory (RAM) cells 218 or other suitable memory cells. RAM cells 218 are interconnected by transistors such as transistors 220 and 222, which control the loading of data provided at input pin 224. At time t=0, transistors 220 and 222 are on, so that the first bit of programming data applied to input 224 is stored in memory cell RAM 3. Transistor 222 is then turned off (t=1), so that the next bit of programming data applied to input 224 is stored in memory cell RAM 2. At time t=2, transistor 220 is turned off, so that the next bit of programming data applied to input 224 is stored in memory cell RAM 1. After each of the memory cells 218 has been loaded with programming data, the programming process is complete. The programming data stored in each cell produces a corresponding output signal (i.e., a logical high if a one is stored or a logical low if a zero is stored). The output signals from each memory cell 218 are applied to an associated region of programmable logic 226 via an output line 228. Programmable logic 226 contains programmable components (e.g., transistors) that are configured (e.g., turned on or off) based on the programming data applied via lines 228. Programmable logic devices typically have a large number of memory cells such as memory cells 218 arranged in a number of FIFO chains passing through various regions of the device. When it is desired to unload programming data from cells 218 (e.g., to verify the programming data and thereby test the chain), transistors 222 and 220 are activated in reverse order and the data is provided at output 229.
As shown in FIG. 9, a programmable logic device FIFO chain may be modified in accordance with the present invention to incorporate logic element registers (such as register MS 1) into the existing FIFO chain (shown as memory cells RAM 1 and RAM
2). Logic signals from the registers may be observed by scanning these signals out through the FIFO chain. An advantage of this approach for logic signal observation is that it makes use of the FIFO programming resources that already exist on the device.
Only a short bottom portion of a FIFO chain is shown in FIG. 9 to avoid over-complicating the drawings. However, numerous memory cells and programmable logic element registers are typically connected in the chain. It is not necessary or typical that there be a programmable logic element register 242 between each pair of memory cells. Rather, the number of programmable logic element registers 242 that are inserted into the FIFO chain depends on the number of programmable logic element registers
242 relative to the number of FIFO cells used on a given programmable logic device. Any suitable number of programmable logic element registers may be connected in the chain.
In circuitry 230 of FIG. 9, FIFO memory cells 232 and 234 are connected to associated programmable logic circuits 236 via output lines 238. Programmable logic circuits 236 may be any suitable type of programmable logic that may be configured by a programmable memory cell bit. The outputs of FIFO memory cells 232 and 234 configure programmable logic circuits 236 (e.g., by turning on or off transistors contained in logic circuits 236).
The outputs of the FIFO memory cells are also generally applied to programmable logic circuitry within programmable logic element 240 to configure the logic functions performed by logic element 240. Logic element 240 may be any suitable type of programmable logic device logic element that contains an appropriate register 242. For example, logic element 240 may be interconnected (via outputs 244 and 246) with various global and local conductors in a programmable logic device arrangement such as shown in FIG. 1. If desired, logic element 240 may contain a look-up table and multiplexing circuitry of the type shown in the logic element arrangements of FIGS. 4-6.
Logic element register 242 is made part of the programming FIFO chain containing memory cells 232 and 234 by routing signals from memory cell RAM 1 to logic element register 242 via buffer 244 and transistor 246. Transistor 246 is used with transistors 248 and 250 when loading programming data into the FIFO chain made up of memory cell RAM 1, register MS 1, and memory cell RAM 2. Data is loaded into this FIFO chain from input 251. Data is loaded into memory cell RAM 2 when transistors A1, A2, and A3 are on, into register MS 1 when A1 and A2 are on, and into memory cell RAM 1 when A1 is on. Data (including the contents of register MS 1 that is to be observed) may be unloaded from the FIFO chain of FIG. 9 into test register 253 at output (verify node) 252 by activating transistors 248, 246, and 250 in the reverse order of that used when loading programming data into the chain.
The basic operation of an illustrative register 254 suitable for use as register MS 1 is shown in FIGS. 10a and 10b. The register design shown in FIGS. 10a and 10b is in itself well known. As shown in FIG. 10a, when signal NCLK goes high in this type of register (edge 256 in FIG. 10c), data at input 258 is passed through gate 260 to master latch 262 (as shown by dotted line portion 264 in FIG. 10a). At the same time, data previously stored in slave latch 266 (FIG. 10a) is provided at output 268. When NCLK falls to zero (edge 270 in FIG. 10c), the data shown as dotted line portion 264 in FIG. 10a is passed to slave 266, as shown by dotted line portion 272 in FIG. 10b. When NCLK rises again (edge 274 in FIG. 10c), the data shown as dotted line portion 272 in FIG. 10b is passed to output 268.
Register MS 1 of FIG. 9 may be connected to the chain of FIFO memory cells in different ways. One suitable way in which to connect register MS 1 is shown in FIG. 11. In the FIG. 11 arrangement, the output of RAM 1 (FIG. 9) is applied to master latch 276 of register MS 1 of FIG. 11 at node 278 using buffer 244 and pass transistor 246.
FIG. 12 is a timing diagram showing the operation of the FIG. 11 arrangement. At t=0, register MS 1 of FIG. 11 is in a power-up state, waiting to be programmed (initialized). At t=1, preparations are made for programming by taking NCLK to zero and applying data to input 251 of FIG. 9. Because transistors A1, A2, and A3 are on (as indicated by the ones associated with these transistors in the t=1 column), the data applied to input 251 passes through memory cell RAM 1 and register MS 1 into memory cell RAM 2. This is indicated by the entry D3 in the row for RAM 2 in the t=1 column of FIG. 12.
During times t=2, t=3, and t=4, the rest of the FIFO chain of FIG. 9 using the FIG. 11 arrangement for register MS 1 is programmed by progressively turning off transistors A3, A2, and A1. The resulting respective data entries D1, D2, and D3 for RAM 1, MS 1, and RAM 2 are shown in the column for t=4 in FIG. 12. At time t=5 a transition to user mode is made. From t=6 to t=10 the device is in user mode and operates normally. (The time t=10 at the end of user mode is illustrative only--any suitable number of user mode clock cycles may exist between time t=6 and the end of user mode.)
The entries in the column for t=10 in FIG. 12 represent the state of the FIFO chain at the end of user mode. Note that the data in register MS 1 at time t=10 (D2') may be different than the data in register MS 1 at time t=5 (D2).
At time t=11, register MS 1 is isolated by taking NCLK to zero. In addition, NCLR (an active low signal) is taken to one, so that register MS 1 is not cleared.
Verify mode begins at time t=12. At times t=13, t=14, and t=15 data is unloaded from the FIFO chain (i.e., from memory cell RAM 1, register MS 1, and RAM 2) via output (verify node) 252 (FIG. 9) by progressively turning on transistors A3, A2, and A1.
There may be some data loss with the arrangement of FIG. 11 when leaving user mode (i.e., when entering verify mode). In particular, because the state of NCLK is not known at time t=10, it is possible that data D2' in register MS 1 will not be valid at time t=11. If NCLK at t=10 is zero, then data D2' at time t=11 will be valid. If NCLK at t=10 is one (i.e., user clock is one), then data D2' at time 11 will be corrupted. This is indicated in box 280 in the table of FIG. 13. Box 280 appears under the heading "negative edge triggered" because the foregoing discussion of the FIG. 11 arrangement pertains to a negative edge triggered register. Data loss will also be experienced upon entering verify mode using a positive edge triggered register whenever NCLK at t=10 is one (i.e., user clock is zero), as shown in box 282.
Another suitable way in which register MS 1 may be connected to the FIFO chain is shown in FIG. 14. In the FIG. 14 arrangement, data from RAM 1 is applied to the slave latch portion of register MS 1 at node 284 via pass transistor A2 and buffer
244.
FIG. 15 is a timing diagram showing the operation of the FIG. 14 arrangement. At t=0, register MS 1 of FIG. 14 is in a power-up state, waiting to be programmed (initialized). At t=1, preparations are made for programming by taking NCLK to one and applying data to input 251 of FIG. 9. Because transistors A1, A2, and A3 are on (as indicated by the ones associated with these transistors in the t=1 column), the data applied to input 251 passes through memory cell RAM 1 and register MS 1 into memory cell RAM 2. This is indicated by the entry D3 in the row for RAM 2 in the t=1 column of FIG. 15.
During times t=2, t=3, and t=4, the rest of the FIFO chain of FIG. 9 using the FIG. 14 arrangement for register MS 1 is programmed by progressively turning off transistors A3, A2, and A1. The resulting respective data entries D1, D2, and D3 for RAM 1, MS 1, and RAM 2 are shown in the column for t=4 in FIG. 15. At time t=5 a transition to user mode is made. From t=6 to t=10 the device is in user mode and operates normally. (The time t=10 at the end of user mode is illustrative only--any suitable number of user mode clock cycles may exist between time t=6 and the end of user mode.)
The entries in the column for t=10 in FIG. 15 represent the state of the FIFO chain at the end of user mode. Note that the data in register MS 1 at time t=10 (D2') may be different than the data in register MS 1 at time t=5 (D2).
At time t=11, register MS 1 is isolated by taking NCLK to one. In addition, NCLR (an active low signal) is taken to one, so that register MS 1 is not cleared.
Verify mode begins at time t=12. At times t=13, t=14, and t=15 data is unloaded from the FIFO chain (i.e., from memory cell RAM 1, register MS 1, and RAM 2) via output (verify node) 252 (FIG. 9) by progressively turning on transistors A3, A2, and A1.
There may be some data loss with the arrangement of FIG. 14 when entering user mode. In particular, because the state of NCLK is not known at time t=5, it is possible that data D2 in register MS 1 will not be valid at time t=5. If NCLK at t=5
is held at one, then data D2 at time t=5 will be valid. If NCLK at t=5 is taken to zero (i.e., user clock is zero), then data D2 at time t=5 will be corrupted. This is indicated in box 286 of FIG. 16. Box 286 appears under the heading "negative edge triggered" because the foregoing discussion of the FIG. 14 arrangement pertains to a negative edge triggered register. Data loss will also be experienced upon entering user mode using a positive edge triggered register whenever NCLK at t=5 is zero (i.e., user clock is one), as shown in box 288.
The scheme of FIG. 14 inserts data from the FIFO chain into the slave portion of master-slave register MS 1, rather than into the master portion as in the FIG. 11 scheme. As a result, NCLK must be forced to one in the