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United States Patent6150837
Beal , ; et al.November 21, 2000
Title
Enhanced field programmable gate array
Abstract
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
Inventors:Beal; Samuel W. (Mountain View, CA), Kaptonoglu; Sinan  (San Carlos, CA), Lien; Jung-Cheun  (San Jose, CA), Shu; William  (Palo Alto, CA), Chan; King W.  (Los Altos, CA), Plants; William C.  (Santa Clara, CA)
Assignee:Actel Corporation (Sunnyvale, CA)
Appl. No.:807455
Filed:February 28, 1997
Current U.S. Class:326/39 326/40 326/37 326/38 
Field of Search:326/39,40,41,38,37
U.S. Patent Documents
4195352March 1980Tu et al.
4458163July 1984Wheeler et al.
4527115July 1985Mehrotra et al.
4609986September 1986Hartmann et al.
4631686December 1986Ikawa et al.
4638187January 1987Boler et al.
4677318June 1987Veenstra
4684830August 1987Tsui et al.
4691161September 1987Kant et al.
4713792December 1987Hartmann et al.
4718057January 1988Venkitakrishnan et al.
4721868January 1988Cornell et al.
4758745July 1988Elgamal et al.
4758747July 1988Young et al.
4771285September 1988Agrawal et al.
4772811September 1988Fujioka et al.
4774421September 1988Hartmann et al.
4783606November 1988Goetting
4847612July 1989Kaplinsky
4857774August 1989El-Ayat et al.
4873459October 1989El Gamal et al.
4910466March 1990Kiuchi et al.
4912345March 1990Steele et al.
4928023May 1990Marshall
4930097May 1990Ledenbach et al.
4931671June 1990Agrawal
4933577June 1990Wong et al.
4933898June 1990Gilberg et al.
4940909July 1990Mulder et al.
4952934August 1990Chiriatti
4963768October 1990Agrawal et al.
4969121November 1990Chan et al.
4978905December 1990Hoff et al.
4983959January 1991Breuninger
4992680February 1991Benedetti et al.
5023484June 1991Pathak et al.
5027011June 1991Steele
5028821July 1991Kaplinsky
5045726September 1991Leung
5068603November 1991Mahoney
5083293January 1992Gilberg et al.
5085885February 1992El Gamal et al.
5107146April 1992El-Ayat
5137393August 1992El Gamal et al.
5140193August 1992Freeman et al.
5151623September 1992Agrawal
5153462October 1992Agrawal et al.
5166557November 1992Chen et al.
5172014December 1992El Ayat et al.
5187392February 1993Allen
5191242March 1993Agrawal et al.
5198705March 1993Galbraith et al.
5208491May 1993Ebeling et al.
5220213June 1993Chan et al.
5221865June 1993Phillips et al.
5225719July 1993Agrawal et al.
5231588July 1993Agrawal et al.
5258891November 1993Sako
5301143April 1994Ohri et al.
5311080May 1994Britton et al.
5313119May 1994Cooke et al.
5317212May 1994Wahlstrom
5317698May 1994Chan
5323069June 1994Smith, Jr.
5329181July 1994Ridgeway
5336950August 1994Popli et al.
5341040August 1994Garverick et al.
5343406August 1994Freeman et al.
5349249September 1994Chiang et al.
5357153October 1994Chiang et al.
5367208November 1994El Gamal et al.
5375086December 1994Wahlstrom
5377124December 1994Mohsen
5381058January 1995Britton et al.
5394031February 1995Britton et al.
5402014March 1995Ziklik et al.
5404033April 1995Wong et al.
5414638May 1995Verheyen et al.
5424589June 1995Dobbelaere et al.
5424655June 1995Chua
5426335June 1995Agrawal et al.
5426378June 1995Ong
5426379June 1995Trimberger
5438166August 1995Carey et al.
5440453August 1995Cooke et al.
5444394August 1995Watson et al.
5448493September 1995Topolewski et al.
5451887September 1995El-Avat et al.
5452229September 1995Shankar et al.
5457409October 1995Agrawal et al.
5457410October 1995Ting
5457644October 1995McCollum
5469003November 1995Kean
5477167December 1995Chua
5485104January 1996Agrawal et al.
5488317January 1996Webster et al.
5490042February 1996Perkins
5493239February 1996Zlotnick
5498886March 1996Hsu et al.
5500609March 1996Kean
5504354April 1996Mohsen
5504439April 1996Tavana
5509128April 1996Chan
5521529May 1996Agrawal et al.
5528176June 1996Kean
5530378June 1996Kucharewski, Jr. et al.
5534798July 1996Phillips et al.
5537341July 1996Rose et al.
5539692July 1996Kajigaya et al.
5543730August 1996Cliff et al.
5544069August 1996Mohsen
5548228August 1996Madurawe
5548552August 1996Madurawe
5550839August 1996Buch et al.
5552722September 1996Kean
5557136September 1996Gordon et al.
5559447September 1996Rees
5559465September 1996Shah
5563526October 1996Hastings et al.
5563528October 1996Diba et al.
5563592October 1996Cliff et al.
5565792October 1996Chiang et al.
5565793October 1996Pedersen
5568081October 1996Lui et al.
5570040October 1996Lytle et al.
5572148November 1996Lytle et al.
5572409November 1996Nathan et al.
5576554November 1996Hsu
5577050November 1996Bair et al.
5581198December 1996Trimberger
5581501December 1996Sansbury et al.
5583450December 1996Trimberger et al.
5583452December 1996Duong et al.
5583749December 1996Tredennick et al.
5587669December 1996Chan et al.
5590305December 1996Terrill et al.
5592509January 1997McClear et al.
5592632January 1997Leung et al.
5594365January 1997Agrawal et al.
5594367January 1997Trimberger et al.
5594690January 1997Rothenberger et al.
5598108January 1997Pedersen
5600263February 1997Trimberger et al.
5600264February 1997Duong et al.
5600265February 1997El Gamal et al.
5600267February 1997Wong et al.
5600597February 1997Kean et al.
5625301April 1997Plants et al.
5631577May 1997Freidin et al.
5633830May 1997Sung et al.
5635851June 1997Tavana
5640106June 1997Erickson et al.
5640308June 1997Osann, Jr. et al.
5642058June 1997Trimberger et al.
5642262June 1997Terrill et al.
5644496July 1997Agrawal et al.
5646544July 1997Iadanza
5650734July 1997Chu et la.
5652529July 1997Gould et al.
5652904July 1997Trimberger
5654564August 1997Mohsen
5654649August 1997Chua
5661409August 1997Mohsen
5661685August 1997Lee et al.
5671234September 1997Philips et al.
5671432September 1997Bertolet et al.
5680061October 1997Veenstra et al.
5682106October 1997Cox et al.
5687325November 1997Chang
5701027December 1997Gordon et al.
5744979April 1998Goetting
5744980April 1998McGowan et al.
5744981April 1998Sasaki et al.
5748009May 1998Bertolet et al.
5751162May 1998Mehendale et al.
5760607June 1998Leeds et al.
5764583June 1998Cliff et al.
5801546September 1998Pierce et al.
5808479September 1998Sasaki et al.
5815003September 1998Pedersen
5815004September 1998Trimberger et al.
5821776October 1998McGowan
5825200October 1998Kolze
5825201October 1998Kolze
5825202October 1998Tavana et al.
5825662October 1998Trimberger
5828230October 1998Young
5828538October 1998Apland et al.
5831448November 1998Kean
5835998November 1998Pedersen
5838167November 1998Erickson et al.
5838584November 1998Kazarian
5838954November 1998Trimberger
5847441December 1998Cutter et al.
5847577December 1998Trimberger
5848005December 1998Cliff et al.
5850151December 1998Cliff et al.
5850152December 1998Cliff et al.
5850564December 1998Ting et al.
5859542January 1999Pedersen
5859543January 1999Kolze
5859544January 1999Norman
5861761January 1999Kean
5869981February 1999Agrawal et al.
5870586February 1999Baxter
5880492March 1999Duong et al.
5880597March 1999Lee
5880598March 1999Duong
5883526March 1999Reddy et al.
5883850March 1999Lee et al.
Foreign Patent Documents
0 069 762Jan., 1983EP
0 181 917Jun., 1983EP
0 358 501Mar., 1990EP
0 394 575Oct., 1990EP
0 415 542Mar., 1991EP
0 415 542 A2Jul., 1990EP
0 499 383Dec., 1996EP
0 583 872Feb., 1994EP
0 584 910Mar., 1994EP
0 584 911Mar., 1994EP
0 585 119Mar., 1994EP
0 592 111Apr., 1994EP
0 612 154Aug., 1994EP
0 617 513Sep., 1994EP
0 639 816Feb., 1995EP
0 678 985Oct., 1995EP
0 746 106Dec., 1996EP
0 748 051Dec., 1996EP
0 756 383Jan., 1997EP
0 759 662Feb., 1997EP
0 780 846Jun., 1997EP
0 785 630Jul., 1997EP
0 786 871Jul., 1997EP
0 790 706Aug., 1997EP
0 806 836 A2Nov., 1997EP
0 818 891 A2Jan., 1998EP
0 889 593 A1Jan., 1999EP
2 045 488Oct., 1980GB
3-183154Sep., 1991JP
6-209045Oct., 1994JP
6-275718Sep., 1994JP
60-059599May., 1985JP
7-170038Jul., 1995JP
7-211820Aug., 1995JP
7-297291Nov., 1995JP
8-051356Feb., 1996JP
85/01390Mar., 1985WO
85/03804Aug., 1985WO
85/03805Aug., 1985WO
93/06559Apr., 1993WO
94/10754May., 1994WO
94/23500Oct., 1994WO
95/04404Feb., 1995WO
96/35263Nov., 1996WO
97/03444Jan., 1997WO
WO 93/12638Jun., 1993EP
WO 95/16993Jun., 1995WO
WO 96/20534Jul., 1996WO
WO 96/31950Oct., 1996WO
WO 96/37047Nov., 1996WO
Other References
"Mixture of Field and Factory Programmed Logic Cells in a Single Device," IBM Technical Disclosure Bulletin, vol. 38, No. 04, Apr. 1995, p. 499. .
Brown, Chappell, "Data-flow Architecture Runs on FPGA", Nov. 4, 1996, EE Times, Issue 926, pp. 41-42. .
Bursky Dave, "Programmable Arrays Mix FPGA and ASIC Blocks", Oct. 14, 1996, Electronic Design, pp. 69-74. .
Cypress, "Getting to Grips with FPGAs", Aug. 1996, Australian Electronics Engineering, pp 46, 48. .
Fawcett et al., "Reconfigurable Processing with Field Programmable Gate Arrays", 1996 IEEE, International Conference on Application-Specific Systems, Architectures and Processors, pp. 293-302. .
Ristelhueber, Robert, "A Marriage of Convenience--Integration of PLDs and ASICs promises big gains, risks for chip vendors", Jan. 1997, Electronic Business Today, pp. 63-64. .
Tchoumatchenko, et al., "FPGA Design Migration: Some Remarks", Sep. 23-25, 1996, 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, Proceedings, pp. 405-409. .
Wilson, Ron, "Actel Unveils FPGA Family", Oct. 28, 1996, Electronic Engineering Times, Issue 925, pp. 88, 92. .
Won, Martin S.,et al., "Building FIR Filters in Programmable Logic", Aug. 1996, Embedded Systems Programming, pp. 48-50, 52, 54, 56, 58-59. .
Actel, "A 10M20A Mask Programmed Gate Array", Jan., 1992, pp. 1-195 to 1-223. .
Actel, "Array Architecture for ATG with 100% Fault Coverage", Jan., 1992, pp. 1-225 to 1-235. .
Altera, "Altera Targets High-End ASIC Designs with FLEX 10K Architecture", Mar. 20, 1995. .
Bogdan, "An Electrically Programmable Silicon Circuit Board", pp. 472-476. .
Carmel, U.S. application No. 06/754,653, now abandoned, filed Jul. 15, 1985. .
Computer Design, Embedded Programmable Architecture Targets Mainstream ASIC Designers, Apr. 1995, pp. 80, 96. .
El-Ayat, "A CMOS Electrically Configurable Gate Array", Jun., 1989, IEEE Journal on Solid-State Circuits, vol. 24, No. 3, pp. 752-761. .
El Gamal, "An Architecture for Electrically Configurable Gate Arrays", Apr., 1989, IEEE Journal of Solid-State Circuits, vol. 24, No. 2, pp. 394-398. .
Gray, "Configurable Hardware: A New Paradigm for Computation", pp. 279-295. .
Haines, "Field-Programmable Gate Array with Non-Volatile Configuration", Jun., 1989, Butterworth & Co. (Publishers) Ltd., vol. 13, No. 5, pp. 305-312. .
Hamilton, "Design Issues from FPGA and PLD Architectural Differences", Mar. 1992, Electronic Engineering, No. 783. .
Hartmann, "EPROM-Based Logic Chip Opens Its Gates To All Flip-Flop Types, Clocks", Electronic Design, Jul. 11, 1985, pp. 109-118. .
Hedlund, "Systolic Architectures-A Wafer Scale Approach", 1984, IEEE, pp. 604-610. .
Hedlund, "WASP-A Wafer-Scale Systolic Processor", 1985, IEEE Intl. Conf. on Computer Design, pp. 665-671. .
Hsia, "Adaptive Wafer Scale Integration", 1980, Japanese Journal of Applied Physics, vol. 19, Supp. 19-1, pp. 193-202. .
Jigour, "PEEL Array Architectures Increase Logic Density, Flexibility and Performance", Nov., 1990, Wescon Conference Record, vol. 34, pp. 316-321. .
Johnson, "Silicon Interconnect Technology", 1987, Conference Record, Los Angeles, pp. 1-7. .
Kawana, "An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array", 1990, IEEE, Custom Integrated Circuits Conference, pp. 31.3.1-31.3.4. .
National Semiconductor, "Programmable Logic Devices Databook and Design Guide", 1990. .
Patil, "A Programmable Logic Approach for VLSI", Sep. 1979, IEEE Transactions on Computers, vol. C-28, No. 9, pp. 594-601. .
Skokan, "Programmable Logic Machine (A Programmable Cell Array)", Oct. 1983, IEEE JSSC, vol. SC-18, No. 5, pp. 572-578. .
Smith, "Intel's FLEXlogic FPGA Architecture", 1993, IEEE, pp. 378-384. .
Snyder, "Intro. to the Configurable, Highly Parallel Computer", Nov. 1980, Revised, May, 1981. .
Snyder, "The Role of the ChiP Computer in Signal Processing", pp. 170-177. .
Trimberger, "Field-Programmable Gate Arrays", Sep. 1992, IEEE Design & Test of Computers, No. 3, pp. 3-5. .
Vij, "Eliminating Routing Bottlenecks in High Density programmable Architectures", Nov. 1992, Wescon Conference Record, pp. 107-110. .
Wahlstrom, "An 11000-Fuse Electrically Erasable Programmable Logic Device (EEPLD) with an Extended Macrocell", Aug., 1988, IEEE, JSSC, vol. 23, No. 4, pp. 916-922. .
Wilson, "Altera Puts Memory Into Its Flex PLDs", E.E. Times. .
Wilton, "Architecture of Centralized Field-Configurable Memory", pp. 97-103. .
Wong, "A 5000-Gate CMOS EPLD with Multiple Logic . . . ", 1989, IEEE,CICC, pp. 5.8.1-5.8.4..~
Primary Examiner: Tokar; Michael
Assistant Examiner: Tan; Vibol
Attorney, Agent or Firm:Schafer; Jonathan H.
Claims

What is claimed is:
1. An integrated circuit device comprising:
at least one field programmable gate array region and at least one mask programmable gate array region;
an I/O system including I/O pads and associated driver circuits;
a user-programmable interconnect architecture for selectively making connections between said at least one field programmable gate array region, said at least one mask-programmable gate array region and said I/O system; and
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region, wherein the at least one circuit interface region is user programmable.

2. An integrated circuit device having a plurality of regions comprising:
at least one field programmable gate array region;
at least one mask-programmable gate array region;
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region;
at least one input/output region for providing input/output to the integrated circuit device; and
wherein the at least one mask programmable gate array region comprises at least one decryption circuit that produces a decrypted configuration data signal from an encrypted configuration data signal received as an input and wherein the at least one field programmable gate array region comprises at least one configuration control circuit that utilizes the decrypted configuration data signal to configure the at least one field programmable gate array region to perform a user programmed function.

3. An integrated circuit device having a plurality of regions comprising:
at least one field programmable gate array region;
at least one mask-programmable gate array region;
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region;
at least one input/output region for providing input/output to the integrated circuit device; and
wherein the at least one mask programmable gate array region comprises at least one dynamic reprogramming circuit to allow selective portions of the at least one field programmable gate array region to be reprogrammed.

4. An integrated circuit device having a plurality of regions comprising:
at least one field programmable gate array region;
at least one mask-programmable gate array region;
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region;
at least one input/output region for providing input/output to the integrated circuit device; and
wherein the at least one mask programmable gate array region comprises at least one logic function for providing a built-in test sequence to the at least one field programmable gate array region.

5. An integrated circuit device having a plurality of regions comprising:
at least one field programmable gate array region;
at least one mask-programmable gate array region;
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region;
at least one input/output region for providing input/output to the integrated circuit device; and
wherein the at least one mask programmable gate array region comprises at least one local area network interface circuit for providing a link between an external user system and the at least one field programmable gate array region.

6. An integrated circuit device having a plurality of regions comprising:
at least one field programmable gate array region;
at least one mask-programmable gate array region;
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region;
at least one input/output region for providing input/output to the integrated circuit device; and
wherein the at least one mask programmable gate array region comprises at least one microprocessor controller.

7. An integrated circuit device having a plurality of regions comprising:
at least one field programmable gate array region;
at least one mask-programmable gate array region;
at least one circuit interface region which provides communication between the at least one field programmable gate array region and the at least one mask-programmable gate array region;
at least one input/output region for providing input/output to the integrated circuit device;
means for programming at least one function into the field programmable gate array region; and
means for programming at least one connection into the circuit interface region wherein the at least one connection provides communication between the field programmable gate array region and the mask-programmable gate array region.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of Field Programmable Gate Arrays (FPGAs). In particular it relates to a method and apparatus of extending the functionality of FPGAs by providing a means for the inclusion of user-specified functions through inclusion of other functional circuitry on the integrated circuit die with the FPGA circuitry, and particularly with such circuitry implemented as mask programmable circuit regions on the integrated circuit.

2. The Prior Art

An integrated circuit uses a network of metal interconnects between the individual semiconductor components which are patterned with standard photolithographic processes during wafer fabrication. Multiple levels of metallized patterns may be used to increase the flexibility of the interconnects.

It has long been recognized that a user-programmable interconnect technique or manufacturer programmability just prior to shipment would allow lower tooling costs and faster delivery time. To such an end, gate array circuits were developed.

A gate array circuit is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the wiring channels and appropriate connections are programmed to implement the necessary wiring connections that form the circuit function.

A gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers, then through the circuit, and finally back out to the user's system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation, or hysteresis.

If the wiring channels and appropriate connections are programmed by the manufacturer according to the construction masks, then the gate array circuit is described as a mask-programmable gate array.

If the wiring channels and appropriate connections are programmed by the user according to programmable circuit elements, then the gate array circuit is described as an FPGA.

There are essentially two configurations of programmable circuit elements used to provide flexibility to the user for programming the FPGA. In the first configuration, an example of which is disclosed by El Gamal, et al. in U.S. Pat. No.
4,758,745, the FPGA can be permanently programmed by the user. In the second configuration, an example of which is disclosed by Freeman in U.S. Pat. No. 4,870,302, the FPGA can be changeably programmed by the user.

By comparison, a mask-programmable gate array offers higher functionality and performance and more efficient use of space while an FPGA offers lower design costs and greater user flexibility. Also, a mask-programmable gate array can implement any variety of I/O function and often at a higher speed than an FPGA. Other dedicated functional circuitry may also offer higher functionality and performance than its equivalent configured from FPGA components.

OBJECTS AND ADVANTAGES OF THE INVENTION

Accordingly, it is an object of the present invention to provide an improved FPGA which is capable of yielding the functionality, performance, and efficiency of a mask-programmable gate array while maintaining the lower design costs and user flexibility of an FPGA.

It is a further object of the present invention to provide an FPGA with the enhanced input/output capabilities offered by a mask-programmable gate array.

Yet another object of the present invention is to combine FPGA integrated circuit technology with that of other functional circuitry on the same integrated circuit die.

These and many other objects and advantages of the present invention will become apparent to one of ordinary skill in the art from a consideration of the drawings and ensuing description of the invention.

SUMMARY OF THE INVENTION

In accordance with the present invention, an enhanced FPGA is disclosed. A portion of an integrated circuit die includes dedicated functional circuitry or mask-programmable circuitry to provide critical circuit functions that cannot adequately or cost effectively be implemented using only Field Programmable manufacturing techniques.

A FPGA integrated circuit according to the present invention comprises a plurality of logic cells or logic modules placed in an array or matrix. The array has a set of vertical wiring channels and a set of horizontal wiring channels that are programmed by the user to interconnect the various logic cells to implement the required logic functions.

Connections to the wiring channels are made by user-programmable interconnect elements situated at the intersection of any two wires to be connected. To make a connection, the user-programmable interconnect element is programmed, resulting in a low impedance electric connection between the two wires. Various types of user-programmable interconnect elements, such as antifuses, pass transistors, memory cells, non-volatile memory including flash, EEPROMs and EPROMs, may be employed in the architecture of the present invention.

To provide more efficient utilization of the wiring channels, a plurality of these programmable elements are used to segment the vertical and horizontal channels into shorter wire lengths. These segments may be joined together to form longer wire connections by programming the programmable elements or left as is to provide independent segment wire lengths and allow the same wiring channel position to be used several times for different circuit connections.

Programming circuitry is typically situated at the edge of the array. Programming and connectivity information is shifted into the programming circuit, and appropriate voltages applied to effect the desired connection patterns. The same vertical and horizontal channels that are used for wiring channels in normal operations may be used for programming the various interconnections and to provide complete testing of the array modules and wiring paths. Alternately, direct programming of individual elements may be performed. The various circuits and processes for programming user-programmable interconnect elements are well known in the art and are not a part of the present invention. Details of programming are not presented here in order to avoid unnecessarily complicating the disclosure.

The logic modules used in the FPGA portion of the array may be universal logic elements, which are very efficient in its implementation of random logic functions defined by the use of selected user-programmable elements. Persons of ordinary skill in the art will appreciate that numerous different modules are available.

At least one portion of the array is not populated by logic modules but instead includes other circuitry. In one embodiment of the invention, the other circuitry comprises a mask-programmable circuit, such as a mask-programmable gate array. Other specific embodiments of the invention include circuits such as analog blocks (A/D, D/A, voltage reference, op amps, comparators, PLL, DPLL, DLL, crystal oscillators), specialized digital blocks (SRAM, DRAM, ROM, PROM, EPROM, EEPROM, FIFO, multiplexers, microprocessors, embedded controllers, ALU, floating point processor, DSP. array processor), and specialized 11O functions (GTL, PECL, LVDS, bus controllers for PCI, ISA, EISA, RAMBUS, etc., network transceivers, high speed serial connections).

Interface circuitry allows connections to be made between the mask-programmable circuit, the logic modules in the array, and I/O circuitry connecting to I/O pins on the integrated circuit. According to one aspect of the present invention, one or more logic module locations at or near the interface between the FPGA portion and the mask-programmable portion of the integrated circuit are populated by interface circuits for making connections between FPGA portion and the mask-programmable portion of the integrated circuit.

The end user chooses from a wide range of functions and specifies them to the manufacturer. The manufacturer in turn programs some functions into the integrated circuit using mask-programmable techniques, leaving the user to program other functions into the integrated circuit using the field programmable portion of the integrated circuit.

In one embodiment of the present invention, the mask-programmable portion of the integrated circuit contains a gate array for implementing a wide range of functions. The mask-programmable gate array is connected to the FPGA via a circuit interface portion of the integrated circuit. The circuit interface can contain either mask-programmable or Field Programmable circuits for controlling and processing the signals passing from and to both the mask-programmable gate array and the FPGA. Each of the mask-programmable gate array, the FPGA, and the circuit interface are connected to an I/O portion of the integrated circuit. The I/O portion of the integrated circuit can contain either mask-progranmmable or Field Programmable circuits for controlling and processing the signals passing into the integrated circuit from external sources or out of the integrated circuit to external sources.

In an alternative embodiment of the present invention, the mask-programmable portion of the integrated circuit contains I/O circuits for implementing a wide range of functions for controlling and processing the signals passing into the integrated circuit from external sources or out of the integrated circuit to external sources. The mask-programmable I/O circuits are connected to the FPGA via a circuit interface portion of the integrated circuit. The circuit interface can contain either mask-programmable or Field Programmable circuits for controlling and processing the signals passing from and to the FPGA. Both the circuit interface and the FPGA can also receive signals from and send signals to external sources directly.

Those skilled in the art will recognize the general applicability of the mask-programmable enhanced FPGA disclosed herein to other types of circuits, both analog and digital.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a preferred embodiment of the present invention having both an FPGA region and a mask-programmable gate array region.

FIG. 2 is a block diagram of a preferred embodiment of an interface circuit according to the present invention interposed between the FPGA region, the mask-programmable region, and an I/O driver of the integrated circuit.

FIG. 3 is a schematic diagram of a presently preferred embodiment of the interface circuit of FIG. 2.

FIG. 4 is a block diagram of an embodiment of the present invention having both an FPGA region and a mask-programmable gate array region showing an illustrative I/O routing arrangement.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

One of ordinary skill in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such a skilled person from an examination of the within disclosure.

Referring first to FIG. 1, a block diagram of a preferred embodiment of an enhanced FPGA integrated circuit 10 is shown. The integrated circuit 10 is shown to comprise a number of blocks. The number, size, and location of the blocks as shown in FIG. 1 is not critical to the operation of the present invention and the layout shown in FIG. 1 is only for purposes of illustration. Persons of ordinary skill in the art will realize that a large number of alternative implementations are possible which are included within the scope of the present invention.

First, the integrated circuit 10 contains an FPGA portion 12. The FPGA 12 includes an array of logic function modules and uncommitted wiring channels which are connectable together and to I/O of the integrated circuit 10 via user-programmable interconnect elements as is known in the art. The end user may configure the FPGA 12 to perform a wide range of functions into the integrated circuit 10. The techniques used to implement user defined functions employing an FPGA are well known to persons of ordinary skill in the art and will not be further disclosed herein.

In addition, the integrated circuit 10 includes regions 14 and 16 of other circuitry. For disclosure of the illustrative embodiment disclosed herein, the other circuitry is a mask-programmable gate array. Persons of ordinary skill in the art will recognize from this disclosure that many other types of circuitry can be employed in regions 14 and 16, subject only to compatibility with the FPGA fabrication process. The number of other types of circuit functions which could be employed in regions 14 and 16 is thus virtually unlimited. Persons of ordinary skill in the art will also appreciate that while two regions 14 and 16 are shown in the block diagram of FIG. 1, one such region, or more than two regions could be included in an integrated circuit according to the present invention.

The mask-programmable gate arrays in regions 14 and 16 includes an array of uncommitted gates with uncommitted wiring channels. During manufacturing, these gates are connected together within the mask-programmable gate array regions 14 and 16 to implement any of a wide range of functions into the integrated circuit 10. The functions programmed into the mask-programmable gate array regions 14 and 16 are generally dictated by the user or reflect an industry standard. The techniques used to implement functions employing a mask-programmable gate array are well known to one of ordinary skill in the art and will not be further disclosed herein.

The integrated circuit 10 includes an interface region 18. The interface region 18 includes any number and variety of elements which provide communication between the FPGA portion 12, the mask-programmable gate array regions 14 and 16, and the I/O of the integrated circuit 10. The circuit interface elements can be as simple as a direct interconnect between the FPGA region 12 and the mask-programmable gate array regions 14 and 16 or as complicated as a logic module that controls and/or conditions the communication between the FPGA region 12 and the mask-programmable gate array regions 14 and 16. The choice of circuit interface elements is generally dictated by the nature of the circuitry disposed in regions 14 and 16 and in the FPGA region 12. The techniques used to implement the circuit interface elements are dictated in part by the techniques used to implement the functions in the FPGA 12 and the mask-programmable gate array regions 14 and 16. The techniques used to implement the circuit interface elements are well known to one of ordinary skill in the art and will not be further disclosed herein.

A distributed approach is preferably taken for placement of the I/O connections to the regions 14 and 16 through the matrix of logic modules in the software library used to configure the FPGA portion 12 of integrated circuit 10. In some implementations, fixed locations, i.e., logic modules, are defined to be connectable to the regions 14 and 16 in as even a manner as the layout will allow. In other implementations, FPGA routing resources may be brought out to be connectable to the regions 14 and 16 in as even a manner as the layout will allow.

The integrated circuit 10 also includes an I/O section 20. The I/O section 20 provides the necessary elements for communication between the integrated circuit 10 and other components in an external system. While I/O section 20 is shown at a single location in the block diagram of FIG. 1, persons of ordinary skill in the art will recognize that for efficient use, the I/O 20 may be distributed around the area of the die on which integrated circuit 10 is fabricated.

The physical connection with the external user is provided through bonding pads 22a, 22b, 22c, and 22d. One of ordinary skill in the art will realize that the number and location of the bonding pads 22a, 22b, 22c, and 22d can vary widely with the particular application necessary for the operation of the present invention.

The bonding pads 22a, 22b, 22c, and 22d are connected to the I/O section 20. I/O section 20 is connected to I/O interface 24 which includes any number and variety of mask-programmable and/or field programmable elements which provides communication between the external user and any or all of the FPGA region 12, the mask-programmable gate array regions 14 and 16, and the circuit interface 18 located on the integrated circuit 10. The I/O interface elements can be as simple as a direct interconnect between the external user and the integrated circuit 10 or as complicated as a logic module that controls and/or conditions the communication between the external user and the integrated circuit 10. The choice of I/O interface elements is generally dictated by the user or reflect an industry standard. The techniques used to implement the I/O interface elements are well known to one of ordinary skill in the art and will not be further disclosed herein.

The increase in performance and functionality of the mask-programmable enhanced FPGA as shown in FIG. 1 is such that a broad range of uses are possible. Some specific uses will now be disclosed, but they by no means represent the full extent of those uses that are possible within the present invention.

For example, three-state buffers can be programmed into the circuit interface 18 by either Field Programmable or mask-programmable techniques. These three-state buffers can then be utilized to isolate the FPGA region 12 from the mask-programmable gate array 14 and/or vice versa during test or normal operation as desired.

Alternatively, transistors such as high voltage pass gates can be programmed into the circuit interface 18 and used for isolation. In either case, the state of the isolation can be determined by the external user through the I/O section 20 by selectively turning the isolation on or off.

Another use for either one of mask-programmable gate array regions 14 or 16 is to configure it as a decryption circuit. This decryption circuit receives encrypted configuration data from the external user, decrypts this data, and passes the decrypted data on to the FPGA region 12. Those of ordinary skill in the art will appreciate that, for this purpose, mask-programmable gate array region 14 or 16 may be configured as one of numerous known decryption circuits.

If one of mask-programmable gate array regions 14 or 16 has been configured as a decryption circuit, the FPGA region 12 of the integrated circuit is programmed with a configuration control circuit that receives the decrypted configuration data and utilizes it to configure the programmable elements of the FPGA 12 to perform the function desired by the external user. In this way, the configuration of the FPGA 12 can be maintained in confidence from everyone except the persons who generated the encrypted configuration data. This is especially useful if the FPGA 12 employs any of the known user re-programmable interconnect elements.

The ability to reprogram the changeably programmable circuit elements in the FPGA 12 is another use that the mask-programmable gate array regions 14 and 16 can be programmed to fulfill. First, this enables a function performed by the FPGA region
12 to be changed based on established criteria. Second, this allows the FPGA region 12 to be programmed in such a way that a function performed by the mask-programmable gate array 14 is changed.

In addition to reprogramming the FPGA 12, the mask-programmable gate array regions 14 and 16 can be programmed with a built-in test sequence for testing the FPGA 12 on command from the external user or automatically on startup. Numerous such test circuits are known to persons of ordinary skill in the art.

The mask-programmable gate array regions 14 and 16 can also be employed to provide a standardized interfaces between the external user and the FPGA 12. First, the mask-programmable gate array regions 14 and 16 can perform bus interface functions such as PCI, VME, or USB. Second, the mask-programmable gate array regions 14 and 16 can perform local area network (LAN) functions such as Ethernet, Frame Relay, and ATM.

Another use for either one of the mask-programmable gate array regions 14 and 16 is to configure it to be a microprocessor or embedded controller such as one of the numerous popular designs in use in the industry.

In the situation where the FPGA 12 has been programmed with a high fanout load, the mask-programmable gate array regions 14 and 16 can be programmed with a high drive, low skew clock driver for connecting to the high fanout load. Low skew clock driver circuits are well known in the art.

The process employed to create and to program the mask-programmable enhanced FPGA as shown in FIG. 1 is based on a combination of techniques that are well known to one of ordinary skill in the art. The general process is outlined below.

To begin with, the general need that the integrated circuit 10 is to fulfill is determined. This may be based entirely on specifications supplied by a user or group of users or on a decision made solely by the manufacturer based upon market analysis.

Next the manufacturer lays out the details of the integrated circuit 10 making sure to allow as much flexibility as possible. This involves selecting the relative sizes of the blocks of the integrated circuit 10 and the logic circuits that will be available within each block. The manufacturer then fabricates the integrated circuit 10 and programs some functions into the integrated circuit 10 using mask-programmable techniques. These functions can be as simple as an interconnect or as complicated as a standard interface or microprocessor.

The integrated circuit 10 is then either shipped to the user who programs additional functions into the integrated circuit 10 using the user-programmable interconnect elements. Persons of ordinary skill in the art will appreciate that the mask programming step could be performed to individual user specifications. The result of the programming is an integrated circuit 10 that contains a circuit that will perform an enhanced user defined function.

If the integrated circuit 10 includes reconfigurable user-programmable elements, the final configuration of the integrated circuit can be changed by either the manufacturer or the user and the resulting function may also be changed. This results in a more flexible integrated circuit.

According to another aspect of the present invention, the regions 14 and 16 may be programmed to operate in one of a number of predefined modes by configuring them. In a programming mode, one or more I/O pins of the integrated circuit may be used to configure the function of the regions 14 and 16. In an operating mode, these I/O pins may be used for normal I/O functions. Assigning dual functions to I/O pins is well known in the art.

In addition, the regions 14 and 16 may be disabled, allowing the integrated circuit to be sold as an FPGA alone. If these regions are not recognized as being present by the programming software, no circuitry appears in the net list describing the integrated circuit.

Referring now to FIG. 2, a block diagram is presented of a preferred embodiment of an interface circuit 30 according to the present invention for use between the FPGA region 12, one of mask-programmable regions 14 or 16, and an I/O driver 32 of the integrated circuit. Interface circuit 30 may be used for each I/O pin 34 which has direct access to the mask-programmable regions 14 or 16.

I/O pad 34 is driven from or drives pad driver circuit 32 depending on whether the I/O pad 34 is functioning as an input or an output of the integrated circuit 10. As will be appreciated by those of ordinary skill in the art, pad driver circuit
32 comprises a bidirectional buffer including input buffer 38 and tri-stateable output buffer 40. The three signal lines associated with pad driver circuit 32 are pad input (PI) line 42, pad output (PO) line 44, and pad enable (PE) line 46. PI line 42
carries input signals from the output of input buffer 38, PO line 44 carries output signals to the input of output buffer 40, and PE line 46 is the tri-state control for output buffer 40. The operation of pad driver circuit 32 is well known in the art.

According to the present invention, interface circuit 30 provides a way to allow pad driver circuit 32 to communicate with both FPGA portion 12 and mask-programmable regions 14 or 16 of integrated circuit 10. Each of FPGA portion 12 and mask-programmable regions 14 or 16 has three signal lines associated with it. FPGA portion 12 has signal input (FI) line 48, signal output (FO) line 50, and signal enable (FE) line 52. FI line 48 carries input signals into FPGA portion 12, FO line 50
carries output signals from FPGA portion 12, and FE line 52 is a tri-state control line. Mask-programmable regions 14 and 16 have three signal lines associated with them: signal input (GI) line 54, signal output (GO) line 56, and signal enable (GE) line
58. GI line 54 carries input signals into mask programmable region 14 or 16, GO line 56 carries output signals from mask programmable region 14 or 16, and GE line 58 is a tri-state control line. Persons of ordinary skill in the art will recognize that an interface 30 may be provided for each I/O of the integrated circuit 10.

Referring now to FIG. 3. a schematic diagram of a presently preferred embodiment of the interface circuit 30 of FIG. 2 is presented. A first multiplexer 60 has a control input driven by a control signal Q0, a first data input driven by the FE signal, a second data input driven by the GE input signal, and an output presenting the PE signal. A second multiplexer 62 has a control input driven by the control signal Q0, a first data input driven by the FO signal, a second data input driven by the GO input signal, and an output presenting the PO signal. A third multiplexer 64 has a control input, a first data input driven by the PI signal, a second data input driven by the GO input signal, and an output presenting the FI signal. A fourth multiplexer 66 has a control input, a first data input driven by the PI signal, a second data input driven by the FO input signal, and an output presenting the GI signal.

First through fourth multiplexers 60, 62, 64, and 66 are preferably formed using tri-state buffers rather than pass transistors. The use of these tri-state buffers allows for driving long lines.

A fifth multiplexer 68 has a control input driven by a control signal Q1, a first data input driven by the PE signal, a second data input driven by a control signal Q2, and an output driving the control input of the third multiplexer 64. A sixth multiplexer 70 has a control input driven by a control signal Q3, a first data input driven by the PE signal, a second data input driven by the Q4 input signal, and an output driving the control input of the fourth multiplexer 66.

Control bit Q0 allows either the FPGA region 12 or the mask-programmable region 14 or 16 to control the tri-stateable output buffer 40 by selecting either the FO and FE lines or the CO and GE lines as the source for the PO and PE lines, respectively.

Control bits Q1 and Q2 allow the FI Input to the FPGA region 12 to be sourced by either the GO or the PI signal. If Q1=1, the selection is static depending on the state of the Q2 control bit. If Q1=0, the FI source selection is dynamic depending on the value of PE. This is useful when Q0=1 (i.e., the mask programmable gate array region 14 or 16 is programmed to control the tri-stateable output buffer 40), because it allows the FPGA region 12 to monitor external data which may be brought into the integrated circuit by means of input buffer 38 and PI when the tri-stateable output buffer 40 is disabled (PE=0) and to monitor internal data which may be leaving the integrated circuit by means of GO and tri-stateable output buffer 40
when it is enabled (PE=I).

In a similar manner, control bits Q3 and Q4 allow the G1 input to the mask-programmable gate array region 12 to be sourced by either the FO or the P1 signal. If Q3=1, the selection is static depending on the state of the Q4 control bit. If Q3=0, the GI source selection is dynamic depending on the value of PE. This is useful when Q0=0 (i.e., the FPGA region 12 is programmed to control the tri-stateable output buffer 40), because it allows the mask-programmable region 14 or 16 to monitor external data which may be brought into the integrated circuit by means of input buffer 38 and PI when the tri-stateable output buffer 40 is disabled (PE=0) and to monitor internal data which may be leaving the integrated circuit by means of FO and tri-stateable output buffer 40 when it is enabled (PE=I).

The Q0 through Q4 control bits may be controlled by user-programmable interconnect elements which may be selectively programmed during FPGA device programming by the end user. For example, each of the Q0 through Q4 nodes may separately be actively or passively pulled up unless pulled down by programming a user-programmable interconnect element associated therewith.

Thus, node Q0 is illustratively shown connected to VDD through pullup device 72 and to ground through user-programmable interconnect element shown as a circle identified by reference numeral 74. Node Q1 is illustratively shown connected to VDD through pullup device 76 and to ground through user-programmable interconnect element shown as a circle identified by reference numeral 78. Node Q2 is illustratively shown connected to VDD through pullup device 80 and to ground through user-programmable interconnect element shown as a circle identified by reference numeral 82. Node Q3 is illustratively shown connected to VDD through pullup device 84 and to ground through user-programmable interconnect element shown as a circle identified by reference numeral 86. Node Q4 is illustratively shown connected to VDD through pullup device 88 and to ground through user-programmable interconnect element shown as a circle identified by reference numeral 90.

Tables 1 and 2 are truth tables defining the operation of the interface 30.

TABLE 1 ______________________________________ FI OPERATION Q0 Q1 Q2 COMMENTS ______________________________________ 0 0 0 Unused 0 0 1 Unused 0 1 0 FPGA input FI always from I/O pad input PI 0 1 1 FPGA input FI always from gate array output GO 1 0 0 Tri-state signal controlled from gate array; FPGA monitors GO when output, PI when input 1 0 1 Unused 1 1 0 FPGA input FI always from I/O pad input PI 1 1 1 FPGA input FI always from gate array output ______________________________________ GO

TABLE 2 ______________________________________ GI OPERATION Q0 Q3 Q4 COMMENTS ______________________________________ 0 0 0 Tri-state signal controlled from Gate Array; FPGA monitors GO when output, PI when input 0 0 1 Unused 0 1 0 Gate array input GI always from I/O pad input PI 0 1 1 Gate array input GI always from FPGA output FO 1 0 0 Unused 1 0 1 Unused 1 1 0 Gate Array input GI always from I/O pad input PI 1 1 1 Gate array input GI always from FPGA output ______________________________________ FO

The Q0 through Q4 control signals may also be controlled from registers so as to alter the signal path definitions as a function of time as is known in the art.

FIG. 4 is a block diagram of a preferred embodiment of an integrated circuit 100 according to the present invention having both an FPGA region 102 and another circuit region 104 which may be, for example, a mask-programmable gate array region. FIG. 4 shows another illustrative I/O routing arrangement for use in the present invention.

A plurality of I/O pads 106a through 106j are disposed about the periphery of the integrated circuit die as is well known in the art. Those of ordinary skill in the art will recognize that I/O buffers (not shown in FIG. 4) may be provided.

In addition, a plurality of wiring channels is disposed on the integrated circuit. Each wiring channel includes a plurality of interconnect conductors. Several such wiring channels are shown in FIG. 4 disposed in both the horizontal and vertical directions. Those of ordinary skill in the art will recognize, however, that many more wiring channels than are shown in FIG. 4 will typically exist in an integrated circuit fabricated according to the teachings of the present invention.

For example, three horizontal wiring channels are shown. The uppermost horizontal wiring channel includes interconnect conductors 108a through 108d. The center horizontal wiring channel includes interconnect conductors 100a through 110d. The lower horizontal wiring channel includes interconnect conductors 112a through 112d.

In addition, two vertical wiring channels are shown in FIG. 4. The leftmost vertical wiring channel includes interconnect conductors 114a through 114d. The rightmost vertical wiring channel includes interconnect conductors 116a through 116d.

Although not shown in the figure, persons of ordinary skill in the art will appreciate that the interconnect conductors can have varying lengths. Some run the full length (or width) of the array and some are segmented into at least two segments in order to maximize the interconnect capability of the integrated circuit 100.

According to the aspect of the invention depicted in FIG. 4, some of the I/O pads 106a through 106j are hardwired to interconnect conductors and some are programmably connectable to interconnect conductors. I/O pads 106a, 106c, 106f, 106h and
106j are hardwired to interconnect conductors 108a, 116d, 112b, 112a, and 114d, respectively. I/O pads 106b, 106d, 106e, 106g, and 106i are programmably connectable to any of the interconnect conductors in the wiring channels that their conductors intersect. For example, I/O pad 106b is connectable to any of interconnect conductors 108a through 108d via individual user-programmable interconnect elements shown as small circles at the regions where the I/O pad conductor intersects the interconnect conductors.

In addition, the individual interconnect conductors in intersecting wiring channels are programmably connectable to one another via individual user-programmable interconnect elements shown as small circles at the regions where the interconnect conductors intersect one another. For example, interconnect conductors 108a through 108d are programmably connectable to any of interconnect conductors 114a through 114d or any of interconnect conductors 116a through 116d.

Inputs and outputs of individual logic function modules in the FPGA portion 102 of integrated circuit 100 are programmably connectable to the interconnect conductors in the same manner as described above. Illustrative inputs or outputs 118, 120,
122, 124, 126, 128, and 130 are shown intersecting various wiring channels and are shown connectable to individual interconnect conductors contained therein via user-programmable interconnect elements shown as small circles.

The inputs and outputs of other circuit region 104 of integrated circuit 100 has two types of connectivity to the I/O pads 106a through 106j. For example, input/output 132 is hardwired to an interconnect conductor 112b, which is hardwired to I/O pad 106f. Input/output 134 is programmably connectable to any one of interconnect conductors 112a through 112d and thus is also programmably connectable to I/O pad 106e via user-programmable interconnect elements.

Input/outputs 136 and 138 of other circuit region 104 are hardwired to interconnect conductors 110a and 110d, respectively, and input/outputs 140 and 142 of other circuit region 104 are programmably connectable to any one of interconnect conductors 110a through 110d, all via user-programmable interconnect elements.

While illustrative embodiments and applications of this invention have been shown and described, it would be apparent to one of ordinary skill in the art that many more modifications than have been mentioned above are possible without departing from the inventive concepts set forth herein. The invention, therefore, is not to be limited except in the spirit of the appended claims.

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