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United States Patent6046935
Takeuchi , ; et al.April 4, 2000
Title
Semiconductor device and memory system
Abstract
A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.
Inventors:Takeuchi; Ken (Tokyo, JP), Tanaka; Tomoharu  (Yokohama, JP)
Assignee:Kabushiki Kaisha Toshiba (Kawasaki, JP)
Appl. No.:238186
Filed:January 27, 1999
Foreign Application Priority Data
Mar 18, 1996 [JP] 8-061445
Apr 19, 1996 [JP] 8-098627
Oct 29, 1996 [JP] 8-302335
Current U.S. Class:365/185.03 365/185.18 365/189.05 365/221 
Current International Class:G11C 11/56 (20060101)
Field of Search:365/185.03,185.18,221,189.05,189.01
U.S. Patent Documents
5163021November 1992Mehrotra et al.
5521865May 1996Ohuchi et al.
5602789February 1997Endoh et al.
5677869October 1997Fazio et al.
5708600January 1998Hakozaki et al.
5796652August 1998Takeshima et al.
Foreign Patent Documents
0 740 305Oct., 1996EP
Other References
Partial European Search Report dated Dec. 18, 1998 from European Patent Application No. 97 10 4597..~
Primary Examiner: Dinh; Son T.
Attorney, Agent or Firm:Banner & Witcoff, Ltd.
Parent Case Text


This application is a divisional application of prior application Ser. No. 08/819,484, filed Mar. 17, 1997 now U.S. Pat. No. 5,903,495.
Claims

What is claimed is:
1. A semiconductor memory device comprising:
memory cells capable of storing multi-bit data items; and
a data circuit for holding a data item to be written into a memory cell,
wherein each of said multi-bit data items contains an upper bit and a lower bit, the upper bit being written into the memory cell after a first write data item is inputted from an external device and temporarily held in said data circuit, and the lower bit being written into the memory cell after a second write data item is inputted from the external device and temporarily held in said data circuit.

2. A semiconductor memory device according to claim 1, wherein the lower bit is written into the memory cell after the second write data item inputted from the external device and the upper bit read from the memory cell are held in said data circuit.

3. A semiconductor memory device comprising:
a plurality of memory cells capable of storing multi-bit data items, said memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page;
a data circuit for holding a data item to be written into a memory cell,
wherein each of said multi-bit data items contains an upper bit to be written first into each memory cell and a lower bit to be written next into each memory cell, the upper bit being first written into a memory cell of one group constituting an upper page, and the lower bit being then written into a memory cell of another group constituting a lower page.

4. A semiconductor memory device according to claim 3, wherein said upper page is written after a first data item is inputted to said data circuit from an external device and temporarily held in said data circuit, and said lower page is then written after a second data item is inputted to said data circuit from the external device and temporarily held in said data circuit.

5. A semiconductor memory device according to claim 3, wherein said memory cells are divided into groups, and said data circuit is one of a plurality of data circuits, each data circuit provided for one group of memory cells.

6. A semiconductor memory device comprising:
memory cells capable of storing multi-bit data items;
a data circuit for holding a write data item to be written into a memory cell;
programming means for programming said memory cells according to the write data item held in said data circuit; and
verify means for detecting whether said programming means has written the write data item held in said data circuit, into said memory cell, and for making said programming means repeatedly apply a programming voltage to the memory cell until said programming means sufficiently programs said memory cell,
wherein each of said multi-bit data items contains an upper bit and a lower bit, said programming means first writes said upper bit into the memory cell until said verify means detects that said programming means has sufficiently programmed said memory cell, and next said programming means writes said lower bit into the memory cell.

7. A semiconductor memory device according to claim 6, wherein said lower bit is written into the memory cell after said upper bit has been written into the memory cell and after said data circuit holds a write data item inputted from an external device and the upper bit read from the memory cell.

8. A semiconductor memory device comprising:
a plurality of memory cells, each capable of storing a multi-bit data item, said memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page;
a data circuit for holding a data item to be written into a memory cell,
programming means for programming said memory cell according to the data item held in said data circuit; and
verify means for detecting whether said programming means has written the data item held in said data circuit, into said memory cell, and for making said programming means repeatedly apply a programming voltage to the memory cell until said programming means sufficiently programs said memory cell,
wherein each of said multi-bit data items contains an upper bit and a lower bit, said programming means first writes the upper bit into a memory cell of a group constituting an upper page until said verify means detects that said programming means has sufficiently programmed the memory cell of the group constituting the upper page, and next said programming means writes the lower bit into a memory cell of another group constituting a lower page.

9. A semiconductor memory device according to claim 8, wherein said lower bit is written into the memory cell after said upper bit has been written into the memory cell and after said data circuit holds a data item inputted from an external device and the upper bit read from the memory cell.

10. A semiconductor memory device according to claim 8, wherein said data circuit is one of a plurality of data circuits, each data circuit provided for one group of memory cells.
Description


BACKGROUND OF THE INVENTION

The present invention relates to an electrically erasable and programmable semiconductor memory device and a memory system, and more particularly a semiconductor memory device which stores multi-value data and a memory system which incorporates this semiconductor memory device.

Known as one type of an electrically erasable and programmable read-only memory (EEPROM) which can store a great amount of data is a multi-value data memory EEPROM. In the multi-value data memory EEPROM, each memory cell stores a data item having one of n values (n.gtoreq.3).

Recently, the demand for EEPROMs has been increasing, because EEPROMs hold data even after they are switched off. A flash memory is a nonvolatile semiconductor memory from which data can be erased at once. Each memory cell of the flash memory suffices to have only one transistors, unlike byte-type nonvolatile semiconductor memory in which each memory cell has the two-transistor. The cells of the flash memory can therefore be small. It follows that a flash memory can have a memory capacity and can therefore be used in replace of a magnetic disk which has a great memory capacity.

Of various types of flush memories, the NAND-type EEPROM is considered most advantageous in terms of integration density. A NAND-type EEPROM comprises a plurality of memory cells arranged in, for example, columns. Each memory cell is of n-channel FETMOS structure, having a floating gate (i.e., charge-storage layer) and a control gate. The memory cells forming a one column are connected, each with its source connected to the drain of the next memory cell. The memory cells thus connected in series constitute a unit cell-group, or a NAND cell. Hence, the NAND-type EEPROM has a plurality of NAND cells. The NAND cells are connected to bit lines.

FIG. 1A is a plan view of a NAND cell, and FIG. 1B is a circuit diagram thereof. FIGS. 2A and 2B are sectional view of NAND cell shown in FIGS. 1A and 1B. FIG. 2A is a sectional view, taken along line 2A--2A in FIG. 1A. FIG. 2B is a sectional view, taken along line 2B--2B in FIG. 1A.

An element region is provided in a p-type substrate 11 (or in a p-type well formed in an n-type substrate). An element isolation oxide film 12 surrounds the element region. Provided in the element region is a NAND cell which is constituted by eight memory cells M1 to M8 connected in series. The cells M1 to M8 have an n-channel FETMOS structure. As best shown in FIG. 2B, each cell comprises a first gate insulating film 13, floating gates 14 (14-1, 14-2, . . . , 14-8), a second gate insulting film 15, and control gates 16 (16-1, 16-2, . . . , 16-8). The first gate insulating film 13 is provided on the p-type silicon substrate 11. The floating gate 14 is mounted on the insulating film 13. The second gate insulating film 15 is provided in the floating gate 14. The control gate 16 is provided on the insulating film 15. Each of n-type diffusion layers 19 in an n-channel FETMOS structure serves as the source of one memory cell and also as the drain of the adjacent memory cell. The memory cells M1 to M8 are thereby connected in series, constituting the NAND cell.

The NAND gate thus constituted has select gates 14-9 and 16-9 at the drain side and select gates 14-10 and 16-10 at the source side. The select gates 14-9, 16-9, 14-10 and 16-10 have been formed by the same process as the floating gates 14-1 to
14-8 and control gates 16-1 to 16-8 of the memory cells M1 to M8. The select gates 14-9 and 16-9 are electrically connected at desired portions. Similarly, the select gates 14-10 and 16-10 are electrically connected at desired portions. An interlayer-insulating film 17 covers the top of the p-type silicon substrate 11 in which the NAND cell is provided. Formed on the interlayer-insulating film 17 is a bit line 18. The bit line 18 contacts the n-type diffusion layer 19 which is located at the drain side of the NAND cell. Thus, the NAND cell has its drain connected to the bit line 18 by the select gates 14-10 and 16-10.

An NAND-type EEPROM comprises many identical NAND cells of the type shown in FIGS. 1A and 1B, arranged side by side. Those memory cells of the NAND cells which form a row have their control gates 14 commonly connected, forming control gate lines. The control gate lines CG1 to CG8 are so-called "word lines" which extend in the row direction. That is, the control gate 14 of each memory cell is connected to one word line. In each NAND cell, the select gates 14-9 and 16-9 form a select gate line SG1, and the select gates 14-10 and 16-10 form a select gate line SG2. The select gate lines SG1 and SG2 extend in the row direction.

FIG. 3 is a circuit diagram illustrating a NAND-cell array. As FIG. 3 shows, control gate lines CG1 to CG8 and select gate lines SG1 and SG2 extend in the row direction. As in most HAND-type EEPROMs, the memory cells M which are connected by one control gate line (i.e., word line) form one page, and the pages located between a drain-side select gate line (i.e., select gates 14-9 and 16-9) and a source-side select gate (i.e., select gates 14-10 and 16-10) form what is generally known as "NAND block" or "block." One page contains, for example, 256 bytes having (256.times.8) memory cells. The memory cells of each page are programmed, almost at the same time. One block contains, for example, 2048 bytes, having (2048.times.8) memory cells. Data is erased from the memory cells of each block, almost at the same time.

An operation of a NAND-type EEPROM having the NAND-cell array shown in FIG. 3 will be explained. In each NAND cell, data is written first into the memory cell which is the furthest from a bit line, then into the memory cell which is the second furthest therefrom, and so forth. More precisely, a write voltage Vpp (=about 20V) is applied to the control gate of any memory cell selected, while an intermediate potential (=about 10V) is applied to the control gates of the memory cells not selected and also to the first select gate. 0V (i.e., "0" programming voltage) or the intermediate potential (i.e., "1" programming voltage) is applied to the bit line. The potential of the bit line is thereby applied to the selected memory cell. Thus, when write data is "0," a high voltage is applied between the p-type substrate and the floating gate of the selected memory cell. In this case, electrons are injected from the p-type substrate into the floating gate by virtue of tunnel effect, and the threshold voltage of the transistor of the cell increases. The threshold voltage of the transistor does not change at all when the write data is "1."

As indicated above, data is erased from the memory cells of each block, almost at the same time. All control gates and all select gates provided in the block from which to erase data are set at 0V, and a voltage VppE (=about 20V) is applied to the p-type substrate and the p-type well provided in an n-type substrate. At the same time, the voltage VppE is also applied to the control gates and select gates provided in the blocks from which to erase no data. In each memory cell incorporated in the block from which to erase data, electrons are released from the floating gate. These electrons are injected into the p-type substrate or the p-type well provided in the n-type substrate. The threshold voltage of the transistor of the memory cells therefore decreases.

At data read operation from a memory cell, the bit line is precharged, thereafter floating the bit line. Then, the control gate of the memory cell is programmed to 0V, the control gate and select gate of any other memory cell are set at the power-supply voltage Vcc (e.g., 3V), and the source line is programmed to 0V. The data in the memory cell is read by detecting the potential of the bit line by means of a sense amplifier (not shown) to determine whether a current flows in the memory cell. More specifically, if the cell stores data "0" (that is, if the memory-cell transistor has a threshold voltage Vth less than 0V), the transistor is turned off and the bit line maintains the precharge potential. If the cell stores data "1" (that is, if the memory-cell transistor has a threshold voltage Vth more than 0V), the transistor is turned on and the bit-line potential falls from the precharge potential by value .DELTA.V. Hence, the sense amplifier can detect whichever potential the bit line has, thereby to read the data from the memory cell.

The NAND-type EEPROM described above is still inferior to a magnetic disk in view of cost effectiveness. It is much desired that the NAND-type EEPROM acquire a large memory capacity to have its per-bit cost reduced. Recently, technology of storing multi-value data has been proposed which may be applied to an electrically erasable and programmable, nonvolatile memory such as the NAND-type EEPROM. Various multi-value memory cells are known, each capable of storing a data item having one of n values (n.gtoreq.3).

How a four-value cell, for example, which can store a data item having one of four different values, operate will be explained. FIG. 4 is a diagram which represents the relation between the threshold voltage of the transistor of the four-value cell and the four data items of different values the cell can store. As can be understood from FIG. 4, the memory-cell transistor has, for example, a negative threshold voltage while the cell is storing data "1," as in the case data has been read from the cell. The memory-cell transistor has a threshold voltage of, for example, 0.5 to 0.8V while the cell is storing data "2," a threshold voltage of, for example, 1.5 to 1.8V while the cell is storing data "3," and a threshold voltage of, for example,
2.5 to 2.8V while the cell is storing data "4."

When a read voltage VCG3R is applied to the control gate of the four-value cell, the transistor of the cell is turned on or off. If the transistor is turned on, data "1" or data "2" is detected. If the transistor is turned off, data "3" or "4" is detected. Then, read voltages VCG4R and VCG2R are applied to the control gate, whereby data "1," "2," "3," or "4" is detected. The read voltages VCG2R, VCG3R and VCG4R are 0V, 1V and 2V, respectively.

In FIG. 4, VGC2V, VGC3V and VGC4V represent verify voltages, which are applied to the control gate of each memory cell in order to determine whether or not the memory cell has been sufficiently programmed. The verify voltages VGC2V, VGC3V and VGC4V are 0.5V, 1.5V and 2.5V, respectively.

FIG. 5 is a diagram explaining how a four-value cell is programmed. FIG. 6 is a diagram showing which data items are written into which memory cells constituting one page. As shown in FIG. 6, a two-bit address is assigned to each memory cell MC. More precisely, address bits A0 and A1 are assigned to the memory cell MC1, address bits A2 and A3 to the first memory cell MC2, address bits A4 and A5 to the second memory cell MC3, and so forth. In accordance with two addresses, write data supplied externally is written into each memory cell MC.

To write data into, for example, the first memory cell MC1, the address bits A0 and A1 are temporarily stored in the data circuit associated with the memory cell MC1. In accordance with these bits A0 and A1, data "1", "2", "3" or "4" is written into the memory cell MC1 as is illustrated in FIG. 5. In a similar way, data "1", "2", "3" or "4" is written into any other memory cell MC2, MC3, . . . , or MC128 in accordance with two address bits A2 and A3, A4 and A5, . . . , or A254 and A255. To write data "1" into one memory cell is to maintain the memory cell in an erased (unwritten) state.

In the data-programming described above, it takes longer to write "3" into a four-value cell than to write "2" thereinto. (Writing "2" into a four-value cell is equivalent to writing "0" into a binary cell.) It takes still longer to write "4" into a four-value cell than to write "3" thereinto. Whether a four-value cell has been sufficiently programmed to each data item "2", "3" or "4" must be checked in verify mode. Much time is required to determine whether the memory cell has been sufficiently programmed. Hence, to program the memory cells of one page almost at the same time, a considerably long time will be required to write the data, in its entirety, into all the memory cells. In short, the programming time of the NAND-type EEPROM, defined as the time required to write data into the cells of one page, is inevitably long.

How to read data from a four-value cell will be explained, with reference to FIGS. 7A and 7B.

FIG. 7A is a diagram representing the distribution of threshold voltages of a four-value cell. FIG. 7B is a flowchart for explaining the conventional method of reading data from a four-value cell.

First, a voltage Vt1 intermediate between two voltages corresponding to data values "1" and "2" is applied to the word line to which the memory cell is connected (Step A1). If the memory cell is turned on, it is known that the cell stores value "0" or "1." If the memory cell is turned off, it is determined that the cell stores value "2" or "3." Next, a voltage Vt2 is applied to the word line, thereby detecting that the memory cell stores "3" or any other value "0", "1" or "2" (Step A2). Then, a voltage Vt3 is applied to the word line, determining that the memory cell stores "0" or any other value "1", "2" or "3" (Step A3). As a result, the two-bit data (a four-value data) is read from the memory cell (Step A4) and ultimately from the NAND-type EEPROM chip.

Another conventional method of reading data from a four-value cell will be explained, with reference to FIGS. 8A and 8B. FIG. 8A is a diagram representing the distribution of threshold voltages of a four-value cell. FIG. 8B is a flowchart for explaining this conventional data-reading method.

At first, a voltage Vts1 intermediate between two voltages corresponding to data values "0" and "1" is applied to the word line to which the memory cell is connected (Step B1). If the memory cell is turned on, it is known that the cell stores value "0." If the memory cell is turned off, it is determined that the cell stores value "1", "2" or "3." Next, a voltage Vts2 is applied to the word line, thereby detecting that the memory cell stores "0" or "1", or "2" or "3" (Step B2). Then, a voltage Vts3 is applied to the word line, determining that the memory cell stores "3" or any other value "0", "1" or "2" (Step B3). As a result, the two-bit data (a four-value data) is read from the memory cell (Step B4) and is ultimately output to an external device from the NAND-type EEPROM chip.

As described above, more steps must be performed to determine the threshold voltage of each memory cell in a multi-value data storing memory than in a binary storing memory. This means that the multi-value data storing memory has a lower read speed than a binary data storing memory.

In a four-value data storing memory, for example, the voltage of a word line must be changed three times to detect the threshold voltage of any memory cell connected to the word line. The read time of the four-value data storing memory is about three times as long as that of a binary data storing memory.

In an electrically erasable and programmable, nonvolatile memory such as the NAND-type EEPROM, data may be lost as electrons leak from the floating gate (i.e., a charge-storage layer) of each memory cell. Lost of data is likely to occur, particularly in multi-value data storing semiconductor memories. When data corresponding to a high threshold level is written into a memory cell, the charge in the floating gate of the cell most likely leaks, in an increasing amount, into the substrate because a strong electric field is generated between the substrate and the floating gate. The charge thus leading from the floating gate changes the threshold voltage of the memory cell. No matter how small is the change in the threshold voltage, the data is lost in the memory cell.

Therefore, multi-value data storing semiconductor memories cannot be put to practical use unless they acquire reliability against data destruction.

As mentioned above, the conventional multi-value data storing semiconductor memories are inferior to the binary data storing memories in terms of not only read time but also programming time. Further, the memories cannot be programmed sufficiently or reliably. Consequently, the conventional multi-value data storing semiconductor memories have not ever been put to practical use.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a multi-value data storing semiconductor memory device which operate reliably and which has a short read time and a short programming time.

Another object of the invention is to provide a memory system incorporating this semiconductor memory device.

According to a first aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number); and a data circuit having m latch circuits for holding data items read from the memory cells, wherein data items read from the memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from the memory cells are held in the remaining (m-k) latch circuits, during data-reading operation. In the semiconductor memory device, the data circuit holds data items to be written into the memory cells. The data circuit is provided in plurality.

According to the first aspect of the invention, there is provided another semiconductor memory device comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing 2n-value data (n is 1 or a greater natural number) and having a first threshold voltage to store "1," a second threshold voltage higher than the first threshold voltage to store "2," and so forth, and having a 2nth threshold voltage higher than the (2n-1)th threshold voltage to store "2n"; and a data circuit having m latch circuits for holding data items read from the memory cells, wherein during data-reading operation, it is determined whether the threshold voltage of each memory cell is substantially equal to or lower than a voltage corresponding to "n," and whether the threshold voltage of each memory cell is substantially equal to or higher than a voltage corresponding to "n+1," and data items read from the memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from the memory cells are held in the remaining (m-k) latch circuits.

According to the first aspect of the invention, there is provided still another semiconductor memory device comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number); and t data circuits, each having m latch circuits (m is 2 or a greater natural number) for holding data items to be written into the memory cells and data items read from the memory cells, wherein, of the data items to be written into the memory cells, the first t data items are loaded into the first latch circuits of the data circuits, the next t data items are loaded into the second latch circuits of the data circuits, and so forth, and the last t data items, the first of which is the (i.times.t+1)th data item, are loaded into the (i+1)th latch circuits of the data circuits (1.ltoreq.i.ltoreq.m-1, i is a natural number). In this semiconductor memory device, during data-reading operation, a read data item held in the first latch circuit of each data circuit is output before the other m-1 latch circuits hold read data items, a read data item held in the second latch circuit of each data circuit is output before the other (m-2) latch circuits hold read data items, and a read data item held in the j-th latch circuit (1.ltoreq.j.ltoreq.m; j is a natural number) of each data circuit is output before the other m-j latch circuits hold read data items, during data-reading operation, a read data item held in the m-th latch circuit of each data circuit is output before the other m-1 latch circuits hold read data items, a read data item held in the (m-1)th latch circuit of each data circuit is output before the other m-2
latch circuits hold read data items, and a read data item held in the p-th latch circuit (1.ltoreq.p.ltoreq.m; p is a natural number) of each data circuit is output before the other p-1 latch circuits hold read data items, during data-reading operation, data items read from the memory cells and held in k latch circuits of each data circuit (k<m) are output before the other m-k latch circuits hold data items read from the memory cells, or during data-reading operation, data items read from the memory cells and held in d latch circuits of each data circuit (d<m-k) are output before the other m-k-d latch circuits hold data items read from the memory cells.

According to the first aspect of the invention, there is provided a further semiconductor memory device comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number); and t data circuits, each having m latch circuits (m is 2 or a greater natural number) for holding data items to be written into the memory cells and data items read from the memory cells, wherein, of the data items to be written into the memory cells, the first t data items are loaded into the first latch circuits of the data circuits, the next t data items are loaded into the second latch circuits of the data circuits, and so forth, and the last t data items, the first of which is the (i.times.t+1)th data item, are loaded into the (i+1)th latch circuits of the data circuits (1.ltoreq.i.ltoreq.m-1, i is a natural number); and no write data items are input to f latch circuits of each data circuit (f<m), thereby to program the memory cells, in which f latch circuits hold write data, within the shortest possible time.

Any semiconductor memory device according to the first aspect of the invention can have a short read time, though it has multi-value data storing memory cells.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein the memory cells are programmed "1," "2," . . . , "k-1," "k," (k>m) according to write data items input from an external device and data items held in the memory cells when the memory cells hold "1," "2," . . . , "m-1" and "m" (m is 2 or a greater natural number).

According to a second aspect of the present invention, there is provided another semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number) in a first programming operation according to a write data item input from an external device, and when each memory cell is programmed to a threshold voltage corresponding to "1," "2," . . . "m-1," or "m," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "k-1" or "k" (k is a natural number greater than m) in a second programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value .DELTA.Vpp1 by which the bias increases in the first programming operation is less than a step-up value .DELTA.Vpp2 by which the bias increases in the second programming operation (.DELTA.Vpp1<.DELTA.Vpp2). In the semiconductor memory device, each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," "3," . . . , "m-1" or "m" in the memory cell is narrower than the threshold voltage distribution width of "m+1," "m+2".

According to the second aspect of the invention, there is provided still another semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein when each memory cell holds "1," "2," . . . , "2.sup.m-1 -1" or "2.sup.m-1 " (m is a natural number satisfying n=2.sup.m), the memory cell comes to store "1," "2," . . . , "2.sup.m -1" or "2.sup.m " according to a write data item input from an external device and a data item held in the memory cell, or another semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein each memory cell has a threshold voltage changed to store "1" or "2" in a first programming operation according to a write data item input from an external device and the threshold voltage of the memory cell when the memory cell has a threshold voltage corresponding to "1", and has a threshold voltage changed to "1," "2," . . . , "2.sup.m -1" or "2.sup.m " (m is a natural number satisfying n=2.sup.m) in the m-th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell when the memory cell has a threshold voltage corresponding to "1," "2," . . . , "2.sup.m-1 -1" or "2.sup.m-1,"; and a step-up value .DELTA.Vpp1 by which the bias increases in the first programming operation is less than a step-up value .DELTA.Vppm by which the bias increases in the m-th programming operation (.DELTA.Vpp1<.DELTA.Vppm). In this memory device, the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "2.sup.m-1 +1," "2.sup.m-1 +2" . . . , "2.sup.m-1
" or "2.sup.m " in the memory cell, and each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," "3," . . . , "2.sup.m-1 -1" or "2.sup.m-1 " in the memory cell is narrower than the threshold voltage distribution width of "2.sup.m-1 +1," "2.sup.m-1 +2" . . . , "2.sup.m-1 " or "2.sup.m " in the memory cell.

According to the second aspect, there is provided still another semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or greater than n), wherein when each memory cell holds "1" or "2," the memory cell comes to store "1," "2," "3," or "4" according to a write data item input from an external device and a data item held in the memory cell, or a semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," the threshold voltage is changed to a threshold voltage corresponding to "1" or "2" in a first programming operation according to a write data item input from an external device; when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," "3," or "4" in the second programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value .DELTA.Vpp1 by which the bias increases in the first programming operation is less than a step-up value .DELTA.Vpp2 by which the bias increases in the second programming operation (.DELTA.Vpp1<.DELTA.Vpp2). In the semiconductor memory device, each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4".

According to the second aspect of the invention, there is provided another semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein when each memory cell holds "1," "2," . . . , "r-1" or "r" (r is 2 or a greater natural number), the memory cell comes to store "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r) according to a write data item input from an external device and a data item held in the memory cell; and when each memory cell holds "1," "2," . . . , "s-1" or "s," the memory cell comes to store "1," "2," . . . , "t-1" or "t" (t is a natural number greater than s) according to a write data item input from an external device and a data item held in the memory cell, or a semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," 2," . . . , "r-1" or "r" (r is 2 or a greater natural number), the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r) in the j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and threshold voltage of the memory cell; when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," . . . , "s-1" or "s," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "t-1," or "t" (t is a natural number greater than s) in the (j+1)th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value .DELTA.Vppj by which the bias increases in the j-th programming operation is less than a step-up value .DELTA.Vpp(j+1) by which the bias increases in the (j+1)th programming operation (.DELTA.Vppj<.DELTA.Vpp(j+1)). In this semiconductor memory device, the threshold voltage distribution width of "r+1," "r+2," . . . , "s-1" or "s" in the memory cell is narrower than the threshold voltage distribution width of "s+1," "s+2," . . . , "t-1," "t." Each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," . . . , "r-1" or "r" in the memory cell is narrower than the threshold voltage distribution width of "r+1," "r+2," . . . , "s-1," "s."

According to the second aspect of the invention, there is provided a further semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein when each memory cell holds "1," "2," . . . , "2.sup.k-1 -1" or "2.sup.k-1 " (k is 2 or a greater natural number), the memory cell comes to store "1," "2," . . . , "2.sup.k -1" or "2.sup.k " according to a write data item input from an external device and a data item held in the memory cell; and when each memory cell holds "1," "2, "2.sup.k -1" or "2.sup.k," the memory cell comes to store "1," "2," . . . , "2.sup.k+1 -1" or "2.sup.k+1 " according to a write data item input from an external device and a data item held in the memory cell, or a semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," "2," . . . , "2.sup.k-1 -1" or 2.sup.k-1
" (k is 2 or a greater natural number), the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "2.sup.k -1" or "2.sup.k " in the k-th programming operation according to a write data item input from an external device and threshold voltage of the memory cell; when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," . . . , "2.sup.k -1" or "2.sup.k," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," . . . , "2.sup.k+1 -1," or "2.sup.k+1 " in the (k+1)th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value .DELTA.Vppk by which the bias increases in the kth programming operation is less than a step-up value .DELTA.Vpp(k+1) by which the bias increases in the (k+1)th programming operation (.DELTA.Vppk<.DELTA.Vpp(k+1)). In the memory device, the threshold voltage distribution width of "2.sup.k-1 +1" or "2.sup.k-1 +2," . . . , "2.sup.k -1" and "2.sup.k " in the memory cell is narrower than the threshold voltage distribution width of "2.sup.k +1," "2.sup.k +2," . . . , "2.sup.k+1 -1" or "2.sup.k+1." Each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "1," "2," . . . , "2.sup.k-1 -1" or "2.sup.k-1 " in the memory cell is narrower than the threshold voltage distribution width of "2.sup.k-1 +1," "2.sup.k-1 +2," . . . , "2.sup.k -1" or "2.sup.k." Each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3," "4," . . . , "2.sup.k-1 -1" or "2.sup.k-1."

According to the second aspect, there is provided another semiconductor memory device semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" in the input data is a (2k-1)th logic level and stores "A+2.sup.k-1 " in the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number), or a semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" in the input data is a (2k-1)th logic level and stores "A+2.sup.k-1 " in the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number); and a step-up value .DELTA.Vpp1 by which the bias increases in the first mode for performing the first programming operation is less than a step-up value .DELTA.Vppk by which the bias increases in the kth programming operation for performing the k-th programming operation (.DELTA.Vpp1<.DELTA.Vppk). In this memory device, each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "A+2.sup.k-1." The threshold voltage distribution width of "A" in the memory cell is narrower than the threshold voltage distribution width of "A+2.sup.k-1."

According to the second aspect of the invention, there is a further semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level; during the second programming operation, each memory cell stores "1" in the input data is a third logic level or stores "3" in the input data is a fourth logic level in the case where the memory cell has been storing "1" during the first programming operation; and during the second programming operation, each memory cell stores "2" in the input data is the third logic level or stores "4" in the input data is the fourth logic level in the case where the memory cell has been storing "2" during the first programming operation, or a semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level; during the second programming operation, each memory cell stores "1" in the input data is a third logic level or stores "3" in the input data is a fourth logic level in the case where the memory cell has been storing "1" during the first programming operation; during the second programming operation, each memory cell stores "2" in the input data is the third logic level or stores "4" in the input data is the fourth logic level in the case where the memory cell has been storing "2" during the first programming operation; and a step-up value .DELTA.Vpp1 by which the bias increases in the first mode for performing the first programming operation is less than a step-up value .DELTA.Vpp2 by which the bias increases in the second programming operation for performing the second programming operation (.DELTA.Vpp1<.DELTA.Vpp2). In this memory device, each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4." The third threshold voltage is higher than the second threshold voltage. A difference between threshold voltage distributions corresponding to "2" and "4" is equal to a difference between threshold voltage distributions corresponding to "2" and "3." A difference between threshold voltage distributions corresponding to "2" and "4" is greater than a difference between threshold voltage distributions corresponding to "2" and "3." The third threshold voltage is lower than the second threshold voltage. A difference between threshold voltage distributions corresponding to "3" and "4" is equal to a difference between threshold voltage distributions corresponding to "2" and "3." A difference between threshold voltage distributions corresponding to "3" and "4" is greater than a difference between threshold voltage distributions corresponding to "2" and "3."

According to the second aspect of the invention, there is provided another semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level; during the second programming operation, each memory cell stores "1" in the input data is a third logic level and according to the data item held in the memory cell, and stores "3" in the input data is a fourth logic level and according to the data item held in the memory cell, in the case where the memory cell has been storing "1" during the first programming operation; and during the second programming operation, each memory cell stores "2" in the input data is the third logic level and the data item held in the memory cell, and stores "4" in the input data is the fourth logic level and the data item held in the memory cell, in the case where the memory cell has been storing "2" during the first programming operation, or a semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into the memory cells, wherein each memory cell stores "1" when a first write data item held in the data circuit is at a first logic level and stores "2" when the first write data item is at a second logic level; and after the data circuit holds a second write data item input from an external device and a data item read from each memory cell, the memory comes to store "1" when the memory cell stores "1" and the data circuit holds the second write data item of a third logic level, comes to store "3" when the memory cell stores "1" and the data circuit holds the second write data item of a fourth logic level, comes to store "2" when the memory cell stores "2" and the data circuit holds the second write data item of the third logic level, comes to store "4" when the memory cell stores "2" and the data circuit holds the second write data item of the fourth logic level. In the memory device, the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

According to the second aspect of the invention, there is provided still another semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into the memory cells, wherein when each memory cell stores "1," "2," . . . , "m-1," "m" (m is a natural number greater than 2), the memory cell stores "1," "2," . . . , "k-1" or "k" (k is a natural number greater than m) according to a write data item input from an external device and also a data item read from the memory cell and held in the data circuit, or a semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into the memory cells, programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein when each memory cell is at a threshold voltage to store "1," the memory cell is programmed to a threshold voltage to store "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number) in a first programming operation according to a write data item input from an external device and held in the data circuit; when each memory cell is at a threshold voltage to store "1," "2," . . . , "m-1" or "m," the memory cell is programmed to a threshold voltage to store "1," "2," . . . , "k-1" or "k" (k is a natural number greater than m) in a second programming operation according to a write data input from the external device and also a data item read from the memory cell and held in the data circuit; and a step-up value .DELTA.Vpp1 by which the bias increases in the first programming operation is less than a step-up value .DELTA.Vpp2 by which the bias increases in the second programming operation (.DELTA.Vpp1<.DELTA.Vpp2). In the memory device, each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," "3,", . . . , "m-1" or "m" in the memory cell is narrower than the threshold voltage distribution width of "m+1," "m+2," . . . , "k-1" or "k."

According to the second aspect, there is provided another semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into the memory cells, wherein when each memory cell stores "1" or "2," the memory cell is programmed to "1," "2," "3" or "4" according to a write data item input from an external device and also a data item read from the memory cell and held in the data circuit, or a semiconductor memory device comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into the memory cells, programming means for applying a bias to each of the memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether the programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing the programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, the bias increasing stepwise each time the bias is applied to the memory cell, wherein when each memory cell is at a threshold voltage to store "1," the memory cell is programmed to a threshold voltage to store "1" or "3" in a first programming operation according to a write data item input from an external device and held in the data circuit; when each memory cell is at a threshold voltage to store "1" or "2," the memory cell is programmed to a threshold voltage to store "1," "2," "3" or "4" in a second programming operation according to a write data input from the external device and also a data item read from the memory cell and held in the data circuit; and a step-up value .DELTA.Vpp1 by which the bias increases in the first programming operation is less than a step-up value .DELTA.Vpp2 by which the bias increases in the second programming operation (.DELTA.Vpp1<.DELTA.Vpp2). In the memory device, each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4."

According to the second aspect of the invention, there is provided still another semiconductor memory device comprising: memory cells capable of storing multi-bit data items; and a data circuit for holding an data item to be written into the memory cells, wherein each of the multi-bit data item contains upper bit and lower bit; the upper bit is written into each memory cell after a first write data item is input from an external device and temporarily held in the data circuit; and the lower bit is written into the memory cell after a second write data item is input from the external device and temporarily held in the data circuit. In the memory device, the lower bit is written in each memory cell after the second write data item input from the external device and the upper bit read from the memory cell is held in the data circuit.

According to the second aspect of the invention, there is provided a further semiconductor memory device comprising: a plurality of memory cells, each capable of storing multi-bit data item, the memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page; a data circuit for holding data items to be written into the memory cells, wherein each of the multi-bit data item contains upper bit to be written first into each memory cell and lower bit to be written next into each memory cell, the upper bit is first written into the memory cells of one group constituting an upper page, and the lower bits are then written into the memory cells of another group constituting a lower page. In this semiconductor memory device, the upper page is written after a first data item is input to the data circuit from an external device and temporarily held in the data circuit, and the lower page is then written after a second data item is input to the data circuit from the external device temporarily held in the data circuit. The memory cells are divided into groups, and the data circuit is provided in plurality, each provided for one group of memory cells.

According to the second aspect of the invention, there is provided another semiconductor memory device comprising: memory cells capable of storing multi-bit data items; a data circuit for holding a write data item to be written into the memory cells; programming means for programming the memory cells according to the write data item held in the data circuit; and verify means for detecting whether the programming means has written the write data item held in the data circuit, into the memory cells, and for causing the programming means to repeatedly applying the bias to the memory cell until the programming means sufficiently programs the memory cells, wherein each of the multi-bit data item contains upper bit and lower bit; the programming means writes the upper bit into each memory cell after the verify means detects that the programming means has sufficiently programmed and the programming means writes the lower bits into the memory cell. In the memory device, lower bit is written into the memory cell after the upper bit has been written into the memory cell and after the data circuit holds a write data item input from an external device and the upper bits read from the memory cell.

According to the second aspect, there is provided still another semiconductor memory device comprising: a plurality of memory cells, each capable of storing multi-bit data item, the memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page; a data circuit for holding data items to be written into the memory cells, programming means for programming the memory cells according to the write data item held in the data circuit; and verify means for detecting whether the programming means has written the write data item held in the data circuit, into the memory cells, and for causing the programming means to repeatedly applying the bias to the memory cell until the programming means sufficiently programs the memory cells, wherein each of the multi-bit data item contains upper bit and lower bit, the programming means writes the upper bit into the memory cells of a group constituting an upper page after the verify means detects that the programming means has sufficiently programmed the memory cell of the group constituting the upper page, and the programming means writes the lower bits into the memory cells of another group constituting a lower page. In this memory device, the lower bit is written into the memory cell after the upper bit has been written into the memory cell and after the data circuit holds a write data item input from an external device and the upper bit read from the memory cell. The data circuit is provided in plurality, each provided for one group of memory cells.

According to the second aspect, there is provided still another semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each capable of storing multi-bit data item, a page block containing said memory cells; wherein a memory cell of a first page block is programmed in the p-th programming operation (p is 1 or a greater natural number), and a memory cell of a first page block is programmed in the (p+1)th programming operation after the first and the second page blocks have been programmed in the p-th programming operation, or a semiconductor memory device comprising: a plurality of memory cells, each capable of storing multi-bit data item, a page block containing memory cells; a data circuit for holding data items to be written into the memory cells, programming means for programming the memory cells according to the write data item held in the data circuit; and verify means for detecting whether the programming means has written the write data item held in the data circuit, into the memory cells, and for causing the programming means to repeatedly applying the bias to the memory cell until the programming means sufficiently programs the memory cells, wherein a memory cell of a first page block is programmed in the p-th programming operation (p is 1 or a greater natural number), and a memory cell of a first page block is programmed in the (p+1)th programming operation after the first page and the second page blocks have been programmed in the p-th programming operation. In the memory device, the (p+1)th programming operation is performed on the second page after the (p+1)th programming operation has been performed on the first page. The programming means performs the p-th programming operation on the second memory after the verify means detects that the first memory is sufficiently programmed in the p-th programming operation. The programming means performs the (p+1)th programming operation on the first memory after the verify means detects that the second memory is sufficiently programmed in the p-th programming operation. The p-th programming operation is first programming operation, and the (p+1)th programming operation is the second programming operation. Each of the memory cells is an n-value memory cell (n is 3 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," the first programming operation is performed in a first programming operation according to a write data item input from an external device, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number); when each memory cell is at a threshold voltage to store "1," "2," . . . , "m-1" or "m," the second programming operation is performed in a second programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to the memory cell at a threshold voltage to store "1," "2," . . . , "k-1," "k," (k>m). Each of the memory cells is an n-value memory cell (n is 4 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," "2,", . . . , "r-1" or "r" (r is 2 or a greater natural number), the p-th programming operation is performed in a j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r); when each memory cell is at a threshold voltage to store "1," "2," . . . , "s-1" or "s," the (p+1)th programming operation is performed in a (j+1)th programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "t-1," or "t" (t is a natural number greater than s).

According to the second aspect, there is provided a further semiconductor memory device comprising: n-value memory cells (n is 3 or a greater natural number), each capable of storing multi-bit data item, a page block containing memory cells; wherein the (p+1)th programming operation (p is 1 or a greater natural number) is performed on the memory cells constituting the first page block after the p-th programming operation has been performed on the memory cells constituting the first page block and after the p-th programming operation has been performed on the memory cells constituting the second page block, or a semiconductor memory device comprising: a plurality of memory cells, each capable of storing multi-bit data item, a page block containing memory cells; a data circuit for holding data items to be written into the memory cells, programming means for programming the memory cells according to the write data item held in the data circuit; and verify means for detecting whether the programming means has written the write data item held in the data circuit, into the memory cells, and for causing the programming means to repeatedly applying the bias to the memory cell until the programming means sufficiently programs the memory cells, wherein the (p+1)th programming operation (p is 1 or a greater natural number) is performed on the memory cells constituting the first page block after the p-th programming operation has been performed on the memory cells constituting the first page block and after the p-th programming operation has been performed on the memory cells constituting the second page block. In the memory device, (p+1)th programming operation is performed on the memory cells constituting the second page block after the (p+1)th programming operation has been performed on the memory cells constituting the first page block. The programming means performs the p-th programming operation on the memory cells constituting the second page block after the verify means detects that all memory cells constituting the first page block are sufficiently programmed in the p-th programming operation. The programming means performs the (p+1)th programming operation on the memory cells constituting the first page block after the verify means detects that all memory cells constituting the second page block are sufficiently programmed in the p-th programming operation. The p-th programming operation is the first programming operation, and the (p+1)th programming operation is the second programming operation. Each of the memory cells is an n-value memory cell (n is 3 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," the first programming operation is performed in a first programming operation according to a write data item input from an external device, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number); when each memory cell is at a threshold voltage to store "1," "2," . . . , "m-1" or "m," the second programming operation is performed in a second programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to the memory cell at a threshold voltage to store "1," "2," . . . , "k-1," "k" (k>m).. Each of the memory cells is an n-value memory cell (n is 4 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," "2,", . . . , "r-1" or "r" (r is 2 or a greater natural number), the p-th programming operation is performed in a j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r); when each memory cell is at a threshold voltage to store "1," "2," . . . , "s-1" or "s," the (p+1)th programming operation is performed in a (j+1)th programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "t-1" or "t" (t is a natural number greater than s). The the (p+1)th programming operation is performed on the memory cells constituting the first page block after the p-th programming operation has been performed on all the memory cells provided in the device. The number of times the (p+1)th programming operation has been performed on each page block is recorded, and the order in which the page blocks are to be programmed is determined according to the number of times recorded.

According to the third aspect of the invention, there is provided a memory system comprising: a plurality of semiconductor memory devices, each having memory cells capable of storing multi-bit data item; wherein the (p+1)th programming operation (p is 1 or a greater natural number) is performed on the memory cells provided on a first semiconductor memory device after the p-th programming operation has been performed on the memory cells provided in the first semiconductor memory device and after the p-th programming operation has been performed on the memory cells provided in the second semiconductor memory device. In the memory system, the (p+1)th programming operation is performed on the memory cells provided in the second semiconductor memory device after the (p+1)th programming operation is performed on the memory cells provided in the first semiconductor memory device. The (p+1)th programming operation is performed on the memory cells provided in the second semiconductor memory device after the (p+1)th programming operation is performed on only a part of the memory cells provided in the first semiconductor memory device. The p-th programming operation is the first programming operation, and the (p+1)th programming operation is the second programming operation. Each of the memory cells is an n-value memory cell (n is 3 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," the first programming operation is performed in a first programming operation according to a write data item input from an external device, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "m-1" or "m" (m is 2 or a greater natural number); when each memory cell is at a threshold voltage to store "1," "2," . . . , "m-1" or "m," the second programming operation is performed in a second programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to the memory cell at a threshold voltage to store "1," "2," . . . , "k-1," "k" (k>m). Each of the memory cells is an n-value memory cell (n is 4 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," "2,", . . . , "r-1" or "r" (r is 2 or a greater natural number), the p-th programming operation is performed in a j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "s-1" or "s" (s is a natural number greater than r); when each memory cell is at a threshold voltage to store "1," "2," . . . , "s-1" or "s," the (p+1)th programming operation is performed in a (j+1)th programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," . . . , "t-1" or "t" (t is a natural number greater than s). The (p-1)th programming operation is performed on the memory cells provided in the first semiconductor device after the p-th programming operation has been performed on all the memory cells provided in all semiconductor devices. The memory system further comprises control means for controlling the semiconductor memory devices. The control means controls the order in which memory cells are programmed. The order is determined in units of memory cells that share the same word line. The order is determined in units of semiconductor memory devices.

In any memory device according to the second aspect of the invention and in the memory system according to the third aspect of the invention, each memory cell can be programmed to store, for example, a four-value data item. In the first programming operation, either "1" or "2" is written into the memory cell. In the second programming operation, "1" is maintained in the memory cell or "3" is written into the memory cell, or "2" is maintained in the memory cell or "4" is written into the memory cell. Thus, each memory cell is programmed to store a four-value data item by performing programming operation two times.

That is, the first programming operation is effected, almost in the same way as is performed on binary memory cells. The second operation is achieved, almost in the same way as is performed on three-value cells. As a result, the memory cells can be programmed at high speed by a simple programming circuit.

The memory cells may be those designed to store multi-value data items other than four-value data items. If so, each multi-value data item is divided into bits, and the bit are sequentially written into one memory cell by repeating the programming operation. In this case, too, the memory cells can be programmed at high speed.

As mentioned above, the present invention provides a multi-value data storing semiconductor memory device, in which the memory cells are programmed in a specific manner at high speed and by a simple programming circuit, and which operates with high reliability.

Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the present invention in which:

FIG. 1A is a plan view of a NAND cell, and FIG. 1B is a circuit diagram thereof;

FIG. 2A is a sectional view, taken along line 2A--2A in FIG. 1A, and FIG. 2B is a sectional view, taken along line 2B--2B in FIG. 1A;

FIG. 3 is a circuit diagram illustrating a NAND-cell array;

FIG. 4 is a diagram representing the relation between the threshold voltage of the transistor of a conventional four-value cell and the four data items of different values the cell can store;

FIG. 5 is a diagram explaining how data is written into a conventional four-value cell;

FIG. 6 is a diagram illustrating the relation between conventional memory cells and the addresses thereof;

FIG. 7A is a diagram representing a distribution of threshold voltages of a conventional four-value cell, and FIG. 7B is a flowchart for explaining a conventional method of reading data from the four-value cell;

FIG. 8A is a diagram depicting another distribution of threshold voltages of the four-value cell, and FIG. 8B is a flowchart for explaining another conventional data-reading method;

FIG. 9 is a block diagram showing a multi-value data storing NAND-type flash memory according to a first embodiment of the present invention;

FIG. 10 is a circuit diagram showing the memory cell arrays and column series circuit which are incorporated in the flash memory shown in FIG. 9;

FIG. 11 is a diagram representing a distribution of the threshold voltages of each four-value cell MC provided in the flash memory of FIG. 9;

FIG. 12 is a block diagram illustrating the data circuits in detail, which are incorporated in the flash memory of FIG. 9;

FIG. 13A is a diagram showing another distribution of the threshold voltages of each four-value cell MC provided in the flash memory of FIG. 9, and FIG. 13B is a flowchart for explaining a method of reading data from each of the memory cells MC provided in the flash memory of FIG. 9;

FIG. 14A is a diagram showing still another distribution of threshold voltages of each four-value cell MC provided in the flash memory of FIG. 9, and FIG. 14B is a flowchart for explaining another method of reading data from each of the memory cells MC provided in the flash memory of FIG. 9;

FIG. 15 is a circuit diagram of one of the identical data circuits incorporated in a NAND-type flash memory according to a second embodiment of the present invention;

FIG. 16 is a timing chart explaining how data is read from the NAND-type flash memory which is the second embodiment;

FIG. 17 is a table showing the data items the flip-flops provided in the NAND-type flash memory may sense and latch at a specific time;

FIG. 18 is a table presenting the data items to be read from the memory, which the flip-flops may sense and latch in the second embodiment;

FIG. 19 is a table presenting the data items to be written into the memory, which the flip-flops may sense and latch in the second embodiment;

FIG. 20 is a timing chart explaining how data is written into the NAND-type flash memory which is the second embodiment;

FIGS. 21 and 22 are a timing chart explaining how verify read is performed in the second embodiment;

FIG. 23 is a timing chart explaining how verify read operation is performed in another method in the second embodiment;

FIG. 24 is a circuit diagram of another type of a data circuit which may be used in place of the data circuit shown in FIG. 15;

FIG. 25 is a circuit diagram of still another type of a data circuit which may be used in place of the data circuit shown in FIG. 15;

FIG. 26 is a timing chart explaining how data is read from a NAND-type flash memory according to a third embodiment of the invention;

FIGS. 27A to 27C are diagrams showing the distribution of threshold voltages of each memory cell provided in a multi-value data memory EEPROM which is a fourth embodiment of the invention, and explaining how data is output from the EEPROM;

FIGS. 28A to 28C are diagrams showing the distribution of threshold voltages of each memory cell provided in a multi-value data memory EEPROM which is a fifth embodiment of this invention;

FIG. 29 is a diagram for explaining how data is written into and read from a multi-value data memory EEPROM according to a sixth embodiment of the present invention;

FIG. 30 is a diagram for explaining how data is written into and read from a multi-value data memory EEPROM according to a seventh embodiment of this invention;

FIG. 31 is a diagram for explaining how data is written into and read from a multi-value data memory EEPROM according to an eighth embodiment of the present invention;

FIG. 32 is a diagram for explaining how data is written into and read from a multi-value data memory EEPROM according to a ninth embodiment of the invention;

FIG. 33 is a circuit diagram showing an EEPROM which has a modified column arrangement;

FIG. 34 is a circuit diagram illustrating a memory cell array comprising NOR-type cells MC;

FIG. 35 is a circuit diagram showing a memory cell array comprising NOR-type cells MC of another type;

FIG. 36 is a diagram showing a memory cell array comprising ground-array cells MC;

FIG. 37 is a circuit diagram depicting a memory cell array comprising ground-array cells MC of another type;

FIG. 38 is a diagram illustrating a memory cell array comprising alternate ground-array cells MC;

FIG. 39 is a circuit diagram showing a memory cell array comprising alternate ground-array cells MC of another type;

FIG. 40 is a diagram representing a memory cell array comprising DINOR (DIvided NOR)-type cells;

FIG. 41 is a circuit diagram showing a memory cell array comprising AND-type cells;

FIG. 42 is a diagram representing the relation the memory cells have with addresses in an EEPROM according to a tenth embodiment of the present invention;

FIGS. 43A and 43B are diagrams for explaining how an upper page is programmed in the tenth embodiment;

FIGS. 44A to 44C are diagrams for explaining how the memory cells are programmed in the tenth embodiment is programmed;

FIGS. 45A and 45B are diagrams for explaining how a lower page is programmed in the tenth embodiment;

FIGS. 46A to 46C are diagrams for explaining how data is read from the memory cells of the tenth embodiment;

FIGS. 47A to 47C are diagrams explaining another method of reading data from the memory cells of the tenth embodiment;

FIG. 48 is a block diagram of the tenth embodiment;

FIG. 49 is a diagram for explaining how the memory cells are programmed in the tenth embodiment;

FIG. 50 is a diagram explaining how data items are read from the memory cells of the tenth embodiment;

FIGS. 51A to 51D are circuit diagrams showing various types of memory-cell units for use in the tenth embodiment;

FIGS. 52A to 52G are circuit diagrams illustrating other types of memory-cell units for use in the tenth embodiment;

FIG. 53 is a diagram showing the memory cell array and data circuits, which are incorporated in an NAND-type flash memory according to an eleventh embodiment of the present invention;

FIG. 54 is a diagram showing the distribution of threshold voltages which each memory cell has in the eleventh embodiment;

FIG. 55 is a block diagram illustrating the data circuits in detail, which are incorporated in the eleventh embodiment;

FIGS. 56A and 56B are diagrams for explaining how data is read from the eleventh embodiment;

FIG. 57 is a circuit diagram showing one of the identical data circuits provided in the eleventh embodiment;

FIGS. 58A and 58B are a diagram and a table, for explaining how an upper page is programmed in the eleventh embodiment;

FIG. 59 is a timing chart explaining how the upper page is programmed in the eleventh embodiment;

FIG. 60 is a timing chart explaining how the upper page is read from the eleventh embodiment in verify read mode;

FIG. 61A is a diagram and FIGS. 61B and 61C are tables, for explaining how the upper page is read and inverted before a lower page is programmed in the eleventh embodiment;

FIG. 62 is a timing chart explaining how to read and invert the upper page before the lower page is programmed in the eleventh embodiment;

FIGS. 63A and 63B are a diagram and a table, for explaining how the lower page is programmed in the eleventh embodiment;

FIGS. 64A and 64B are a diagram and a table, showing the potentials which various nodes have when the lower page is programmed in the eleventh embodiment;

FIG. 65 is a timing chart explaining how the lower page is programmed in the eleventh embodiment;

FIG. 66 is a circuit diagram showing another type of a data circuit for use in the eleventh embodiment;

FIG. 67 is a timing chart explaining another method of programming the lower page in the eleventh embodiment;

FIG. 68 is a timing chart for explaining how the lower page is verify-read from the eleventh embodiment;

FIGS. 69A and 69B are a timing chart explaining how data is read from the eleventh embodiment;

FIG. 70 is a table representing various potentials which the nodes in a flip-flop have to read data from the eleventh embodiment;

FIG. 71 is a table showing various potentials which the nodes in each data circuit has to read data from the eleventh embodiment;

FIG. 72 is a table showing various potentials the nodes have to read data from the eleventh embodiment;

FIGS. 73A and 73B are a diagram and a table showing various potentials which the nodes in a data circuit have to program a lower page in a memory device according to a twelfth embodiment of the present invention;

FIG. 74 is a timing chart explaining how the lower page is programmed in the twelfth embodiment;

FIG. 75 is a timing chart for explaining how the lower page is verify-read from the twelfth embodiment;

FIGS. 76A and 76B are a diagram and a table showing the data to be programmed in a memory device according to a thirteenth embodiment of the present invention;

FIG. 77 is a timing chart for explaining how an upper page is programmed in the thirteenth embodiment;

FIGS. 78A and 78B are a diagram and a table showing a lower page to be programmed in a memory device according to a thirteenth embodiment of the present invention;

FIGS. 79A and 79B are a diagram and a table showing various potentials which the nodes in a data circuit have to program the lower page in the thirteenth embodiment of the present invention;

FIG. 80 is a timing chart explaining how the lower page is programmed in the thirteenth embodiment;

FIG. 81 is a timing chart for explaining how the lower page is verify-read from the twelfth embodiment;

FIG. 82 is a timing chart explaining another method of programming the lower page in the thirteenth embodiment;

FIG. 83 is a timing chart explaining another method of Verify-Read Operation the lower page from the thirteenth embodiment;

FIGS. 84A and 84B are diagrams for explaining a method of programming the four-value cells provided in a memory device according to a fourteenth embodiment of the invention;

FIG. 85 is a block diagram showing one of the identical data circuits used in the fourteenth embodiment and designed to hold data items to be written into or read from four-value cells;

FIGS. 86A to 86C are diagrams for explaining how each eight-value cell is programmed in the fourteenth embodiment;

FIG. 87 is a block diagram showing one of the identical data circuits used in the fourteenth embodiment and designed to hold data items to be written into or read from eight-value cells;

FIGS. 88A to 88D are diagrams for explaining how each 16-value cell is programmed in the fourteenth embodiment;

FIG. 89 is a block diagram showing one of the identical data circuits used in the fourteenth embodiment and designed to hold data items to be written into or read from 16-value cells;

FIGS. 90A to 90E are diagrams for explaining how each 2m-value cell is programmed in the fourteenth embodiment;

FIG. 91 is a block diagram showing one of the identical data circuits used in the fourteenth embodiment and designed to hold data items to be written into or read from 2m-value cells;

FIGS. 92A and 92B are flowcharts explaining how an upper page and a lower page are programmed in a memory device according to a fifteenth embodiment of the invention;

FIG. 93 is a diagram showing the distribution of threshold voltages which each memory cell has in the fifteenth embodiment;

FIG. 94 is a diagram representing the waveform of a pulse signal supplied to each memory cell provided in the fifteenth embodiment;

FIGS. 95A to 95E are diagrams illustrating the various distributions of threshold voltages which each memory cell has in the fifteenth embodiment;

FIGS. 96A to 96D are diagrams showing the waveforms of various pulse signals supplied to each memory cell provided in the fifteenth embodiment;

FIGS. 97A and 97B are diagrams showing the waveforms of two different pulse signals supplied to each memory cell provided in the fifteenth embodiment;

FIGS. 98A to 98E are diagrams representing other distributions of threshold voltages which each memory cell may have in the fifteenth embodiment;

FIGS. 99A and 99B are diagrams showing still other distributions of threshold voltages which each memory cell may have in the fifteenth embodiment;

FIGS. 100A and 100B are diagrams showing other distributions of threshold voltages which each memory cell may have in the fifteenth embodiment;

FIG. 101 is a diagram illustrating the distribution of threshold voltages each memory cell has in a memory device according to a sixteenth embodiment of the invention;

FIG. 102 is a timing chart for explaining a method of Verify-Read Operation a lower page from the sixteenth embodiment;

FIGS. 103A and 103B are a timing chart explaining how data is read from the sixteenth embodiment;

FIG. 104 is a diagram illustrating the memory cell array incorporated in a memory device according to a seventeenth embodiment of the invention;

FIG. 105 is a diagram showing a memory cell array comprising conventional four-value cells;

FIGS. 106A and 106B are diagrams showing a memory cell array in which "2" and "4" are respectively programmed in every memory cell;

FIGS. 107A and 107B are diagrams showing two memory cell arrays, each programmed to 70% of the memory capacity;

FIG. 108 is a diagram illustrating a memory system according to an eighteenth embodiment of the invention;

FIG. 109 is a diagram showing the memory system which is programmed to 50% of the memory capacity; and

FIG. 110 is a diagram showing the memory system which is programmed to 70% of the memory capacity.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described, with reference to the accompanying drawings.

The first embodiment of the invention is a multi-value data storing NAND-type flash memory. The flash memory will be described, with reference to FIG. 9.

As FIG. 9 shows, the first embodiment has a so-called open-bit structure. The multi-value data storing NAND-type flash memory comprises two memory cell arrays 1A and 1B, a two row series circuits 2A and 2B, and a column series circuit 3**. The arrays 1A and 1B have each a plurality of memory cells which are arranged in rows and columns, forming a matrix. The row series circuits 2A and 2B are provided for the memory cell arrays 1A and 1B, respectively. The column series circuit 3** is provided for both memory cell arrays 1A and 1B.

Each row series circuit includes a row decoder and a word line driving circuit. The row decoder receives an address signal from an address input circuit (i.e., an address buffer) 4 and selects one memory-cell row provided in the associated memory cell array, in accordance with the address signal. The word line driving circuit drives one word line in accordance with the output of the row decoder. If the NAND-type flash memory is a NAND-type EEPROM, the word line driving circuit is a control gate/select gate driving circuit. This is because the word lines are the select gate SG (SGA or SGB) and control gate CG (CGA or CGB).

The column series circuit 3** provided for both memory cell arrays 1A and 1B includes a column decoder and a column selecting line driving circuit. The column decoder receives an address signal from the address buffer 4 and selects one memory-cell column provided in each memory cell array. The column selecting line driving circuit drives a column selecting line for selecting one memory-cell column provided in each memory cell array.

The column series circuit 3 further comprises a bit line control circuit (i.e., data circuit). The bit line control circuit is designed to temporarily hold the data which is to be written into memory cells or the data which has been read therefrom. The bit line control circuit is connected to a data input/output buffer (i.e., a data input/output circuit) 5 by a data input/output line IO. It is connected also to the memory cells of the array 1A by bit lines BLa and to the memory cells of the array 1B by bit liens BLb.

The bit-line control circuit receives data from the data input/output buffer 5 and supplies the data to the memory cells, thereby to write the data into the memory cells. It receives data from the memory cells and supplies the data to the data input/output buffer 5, in order to read the data.

The data input/output buffer 5 is provided to control the data transfer to and from the memory core which is constituted by the memory cell arrays 1A and 1B, row series circuits 2A and 2B and column series circuit 3**. In other words, the buffer
5 supplies data output from an external device to the memory core and supplies data read from the memory core to the external device.

Like the data input/output buffer 5, a write completion detection circuit 18 is provided outside the memory core. The circuit 18 receives the output of the bit-line control circuit and detect whether the memory cells have been sufficiently programmed, from the output of the bit-line control circuit.

The memory cell arrays 1A and 1B and the column series circuit 3** will be described in detail, with reference to FIG. 10.

As shown in FIG. 10, the memory cell arrays 1A and 1B have a plurality of memory cells MC arranged, forming a matrix. The column series circuit 3** has m data circuits (i.e., bit-line control circuits) 6**. Each data circuit 6 is connected one bit line BLa and one bit line BLb.

FIG. 11 is a diagram showing four threshold values.

The transistor of each memory cell provided in the cell arrays 1A and 1B must have so that the memory cell may store four-value data. If the NAND-type flash memory is an EEPROM which stores four-value data items, each memory-cell transistor M must assume one of four different write state. These write states are defined by four threshold voltages the transistor M may have.

Assume the power-supply voltage VCC of the EEPROM is 3V. As shown in FIG. 11, the memory-cell transistor M has, for example, a negative threshold voltage while the cell is storing data "0," as in the case data has been read from the cell. The memory-cell transistor has a threshold voltage of, for example, 0.5 to 0.8V while the cell is storing data "1," a threshold voltage of, for example, 1.5 to 1.8V while the cell is storing data "2," and a threshold voltage of, for example, 2.5 to 2.8V while the cell is storing data "3."

To read data from the memory-cell transistor M, read voltages VCG2R, VCG3R and VCG1R are applied to the control gate CG of the transistor M, one after another.

First, the read voltage VCG2R is applied to the control gate CG of the memory-cell transistor M. If the transistor M is turned on, it is determined that the memory cell stores either "0" or "1." If the transistor M is turned off, it is determined that the cell stores either "2" or "3." Next, the read voltage VCG3R is applied to the control gate CG of the memory-cell transistor M. If the transistor M is turned on, it is determined that the memory cell stores "2"; if the transistor M is turned off, it is determined that the cell stores "3." Finally, the read voltage VCG1R is applied to the control gate CG of the memory-cell transistor M. If the transistor M is turned on, it is determined that the memory cell stores "0; if the transistor M is turned off, it is determined that the cell stores "1" The read voltages VCG2R, VCG3R and VCG4R are, for instance, 0V, 1V and 2V, respectively.

Shown in FIG. 11 are verify read voltages VGC1V, VGC2V and VGC3V, which are used to check to see whether the four-value cells have been sufficiently programmed. The verify voltages VGC1V, VGC2V and VGC3V are applied to the control gate of each memory cell after programming operation has been performed on the memory cell, in order to effect verification, or to determine whether or not the memory cell is sufficiently programmed or not. If the memory-cell transistor M is turned on when a verify voltage is applied to the memory cell MC, it is detected that the transistor M has its threshold voltage changed to the value corresponding to the data just written into the memory cell MC. If the transistor M is turned off when the verify voltage is applied to the memory cell MC, it is detected that the transistor M has its threshold voltage not changed to the value corresponding to the data to be written into the cell MC. The verify voltages VGC1V, VGC2V and VGC3V are 0.5V, 1.5V and 2.5V, respectively.

FIG. 12 is a block diagram illustrating the data circuits 6 (FIG. 10), in greater detail.

As seen from FIG. 12, each of the data circuits 6** incorporates two latch circuits. Two 2-bit data items are held in the first and second latch circuits, respectively, before they are written into one memory cell MC. Four-value data read from the memory cell MC is stored in the latch circuits before it is output from the memory chip through data input/output lines IO1 and IO2.

It will be explained how 512-bit data (at column addresses A0, A1, A2, . . . , A510, and A511) is written into and read from the NAND-type flash memory (i.e., the first embodiment).

<Programming>

First, the data item to be written at the start address A0 is input to the first latch circuit RT1-0 of the data circuit 6-1 and held in the circuit RT1-0. Then, the data items to be written at the addresses A1, A2, . . . A254 and A255 are input to and held in the latch circuits RT1-1, RT1-2, . . . , RT1-254 and RT1-255 of the data circuits 6-1, 6-2, . . . , 6-254 and 6-255, respectively. Further, the data items to be written at the addresses A256, A257, . . . A510 and A511 are input to and held in the latch circuits RT2-1 to RT2-255 of the data circuits 6-1 to 6-255, respectively. Thereafter, data is written into the memory cells MC according to the two-bit data items stored in the data circuits 6-1 to 6-255.

If the data contains less than 512 bits, the write data is input to the first latch circuit of every data circuit, but no data is input to the second latch circuit thereof. In this case, it suffices to store such data in the second latch circuit as would the memory cell MC stores either data "0" or data "1" which corresponds to a low threshold voltage of the memory-cell transistor.

<Data-Reading>

One method of reading 512-bit data from the NAND-type flash memory will be explained, with reference to FIGS. 13A and 13B. FIG. 13A shows a distribution of threshold voltages of each four-value cell MC. FIG. 13B is a flowchart for explaining how data is read from each memory cell MC.

At first, a voltage Vp1 intermediate between two voltages corresponding to data values "1" and "2" is applied to the word line to which the memory cell MC is connected (Step C1). If the memory cell is turned on, it is known that the cell stores value "0" or "1." If the memory cell is turned off, it is determined that the cell stores value "2" or "3."

Next, a voltage Vp2 is applied to the word line, thereby detecting that the memory cell MC stores "3," or "0," or "1" or "2." The data read from the cell MC is held in the second latch circuit (Step C2). In the meantime, the data held in the first latch circuit (corresponding to the column address A0, A1, A2, . . . , A254, or A255) is output from the memory chip through the data input/output line IO1 (Step C3).

Then, a voltage Vp3 is applied to the word line, determining that the memory cell MC stores "0" or any other value "1", "2" or "3. The two-bit data held in the memory cell MC is thereby read out. The data read out and corresponding to the column address A256, A257, . . . , A510, A511 is held in the second latch circuit (Step C4). After the data held in the first latch circuit and corresponding to the column address A0, A1, A2, . . . , A254, A 255 is output from the memory chip, the data held in the second latch circuit and corresponding to the column address A256, A257, . . . , A510 or A511 is output from the memory chip through the data input/output line IO2 (Step C5).

In this data-reading method, the data read from any memory cell is first held in the first latch circuit and then output from the memory chip immediately. The read time is therefore much shorter than in the conventional multi-value data storing memory, almost as short as the read time of the binary data storing memory. This is because the data is output from the memory chip after it is read from the memory cell by applying a prescribed read voltage to the word line, whereas in the conventional multi-value data storing memory, the word line voltage must be changed three times before the data stored in the memory cell is read from the memory chip.

Another method of reading 512-bit data from the NAND-type flash memory will be explained, with reference to FIGS. 14A and 14B. FIG. 14A represents a distribution of the threshold voltages of each four-value cell MC. FIG. 14B is a flowchart explaining how data is read from each memory cell MC in this method.

First, a voltage Vps1 which is intermediate between two voltages corresponding to data values "0" and "1" is applied to the word line to which the memory cell MC is connected. If the memory cell is turned on, it is known that the cell stores value "0." If the memory cell is turned off, it is determined that the cell stores value "1," "2" or "3." The data read from the memory cell MC is held in the second latch circuit (Step D1).

Next, a voltage Vps2 is applied to the word line, thereby detecting that the memory cell MC stores "0" or "1," or "2" or "3." The data read from the cell MC, which corresponds to the column address A0, A1, A2, (Step D2). Thereafter, the data held in the first latch circuit (i.e., the data corresponding to the column address A0, A1, A2, . . . , A254, or A255) is output from the memory chip through the data input/output line IO1 (Step D4).

Finally, a voltage Vps3 is applied to the word line, thereby detecting that the memory cell MC stores "3" or one of the other three values "0," "1" and "2." The two-bit data stored in the memory cell MC is thereby read out. This data, which corresponds to the column address A256, A257, . . . , A510, or A511, is held in the second latch circuit (Step D3). The data held in the second latch circuit (i.e., the data corresponding to column address A256, A257, . . . , A510, or A511) is output from the memory chip via the input/output line IO2 (Step D5).

With the first embodiment it is possible to output the data held in the first latch circuit at the same time data is read from each memory cell into the second latch circuit, once after the data read from the memory cell into the first latch circuit has been determined. That is, the NAND-type flash memory according to the first embodiment has a high read speed.

The second embodiment of the invention is also a multi-value data storing NAND-type flash memory. The second embodiment is similar in structure to the first embodiment (FIG. 9). The transistor of each memory cell incorporated in the second embodiment has four threshold voltages specified in FIG. 11 so the memory cell may store four-value data.

The NAND-type flash memory according to the second embodiment has a plurality of data circuits of the same structure, which is illustrated in FIG. 15. The data circuits are designed to process four-value data items.

As shown in FIG. 15, each data circuit 6** comprises two flip-flops FF1 and FF2. The flip-flop FF1 is constituted by n-channel MOS transistors Qn21, Qn22 and Qn23 and p-channel MOS transistors Qp9, Qp10 and Qp11. The flip-flop circuit FF2 is comprised of n-channel MOS transistors Qn29, Qn30 and Qn31 and p-channel MOS transistors Qp16, Qp17 and Qp18. The flip-flops FF1 and FF2 are provided to latch data items read from one memory cell. They function as sense amplifiers, too.

The flip-flops FF1 and FF2 cooperate to latch data "0," "1," "2," or "3" before the data is written into one memory cell and to sense and latch data "0," "1," "2," or "3" before the data is output from the memory chip.

The flip-flop FF1 is connected to data input/output lines IOA and IOB by an n-channel MOS transistors Qn28 and Qn27, respectively. Similarly, the flip-flop FF2 is connected to data input/output lines IOC and IOD by an n-channel MOS transistors Qn35 and Qn36, respectively. The data input/output lines IOA, IOB, IOC and IOD are connected the input/output buffer 5 (FIG. 9). The gates of the n-channel transistors Qn27 and Qn28 are connected to the output of a column address decoder which comprises a NAND logic circuit G3 and an inverter I3. The data held in the flip-flop FF1 is output to the data input/output lines IOA and IOB when a column enable signal CENB1 is activated. The gates of the n-channel MOS transistors Qn35 and Qn36 are connected to a column address decoder which comprises a NAND logic circuit and an inverter I4. The data held in the flip-flop FF2 is output to the data input/output lines IOC and IOD when a column enable signal CENB2 is activated.

Signals ECH1 and ECH2 are supplied to the n-channel MOS transistors Qn26 and Qn34, respectively. These transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 when the signals ECH1 and ECH2 rise to "H" level. n-channel MOS transistors Qn24, Qn25, Qn32 and Qn33 are provided. The transistor Qn24 connects the flip-flop FF1 to or disconnects the same from a MOS capacitor Qd1. The transistor Qn32 connects the flip-flop FF2 to or disconnects the flip-flop FF2 from the MOS capacitor Qd1. The transistor Qn25 connects the flip-flop FF1 to or disconnects the flip-flop FF1 from a MOS capacitor Qd2. The transistor Qn33 connects the flip-flop FF2 to or disconnects the same from the MOS capacitor Qd1.

P-channel MOS transistors Qp12C and Q13C constitute a circuit, which changes the gate voltage of the MOS capacitor Qd1 according to the data held in the flip-flop FF1, in the input data is a activation signal VRFYBAC. P-channel MOS transistors Qp14C and Q15C constitute a circuit, which changes the gate voltage of the MOS capacitor Qd2 according to the data held in the flip-flop FF2, in the input data is a activation signal VRFYBBC. The p-channel MOS transistor Qp12C and p-channel MOS transistors Qp19C and Qp20C constitute a circuit, which changes the gate voltage of the MOS capacitor Qd1 according to the data items held in the flip-flops FF1 and FF2, in the input data is an activation signal VRFYBA2C. The p-channel MOS transistor Qp14C and p-channel MOS transistors Qp21C and Qp22C constitute a circuit, which changes the gate voltage of the MOS capacitor Qd2 according to the data items held in the flip-flops FF1 and FF2, in the input data is an activation signal VRFYBB2C. N-channel MOS transistors Qn1C and Qn2C constitute a circuit, which changes the gate voltage of the MOS capacitor Qd1 according to the data held in the flip-flop FF2, in the input data is an activation signal VRFYBA1C. N-channel MOS transistors Qn3C and Qn4C constitute a circuit, which changes the gate voltage of the MOS capacitor Qd2 according to the data held in the flip-flop FF2, in the input data is an activation signal VRFYBB1C.

The MOS capacitors Qd1 and Qd2 are constituted by a depletion n-channel MOS transistor each. They have a capacitance much less than the bit-line capacitance. An n-channel MOS transistor Qn37 charges the MOS capacitor Qd1 to a voltage VA when it receives a signal PREA. An n-channel MOS transistor Qn38 charges the MOS capacitor Qd2 to a voltage VB when it receives a signal PREB. N-channel MOS transistors Qn39 and Qn40 connects the data circuit 6 to or disconnects the same from bit lines BLa and BLb in the input data is signals BLCA and BLCB, respectively. The n-channel MOS transistors Qn37 and Qn38 constitute a circuit, which controls the voltages of the bit lines BLa and BLb.

It will be explained how the NAND-type flash memory (the second embodiment) described above operates when the control gate CG2A is selected.

<Data-Reading>

First, it will be described how data is read from the flash memory, with reference to the timing chart of FIG. 16.

At time t1RC, the voltages VA and VB are set at 1.8V and 1.5V, whereby the bit lines BLa and BLb are set at 1.8V and 1.5V, respectively. As a result, the signals BLCA and BLCB falls to "L" level. The bit lines BLa and BLb are thereby disconnected from the MOS capacitors Qd1 and Qd2, respectively, and assumes floating state. The signals PREA and PREB fall to "L" level, setting the nodes N1 and N2, or the gates of the MOS capacitors Qd1 and Qd2, into floating state. Then, at time t2RC, the control gate CG2A in the block selected by a control gate/select gate driving circuit is programmed to 0V, while the control gates CG1A, CG3A and CG4A,