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United States Patent
5996029
Sugiyama , ; et al.
November 30, 1999
Title
Information input/output control apparatus and method for indicating which of at least one information terminal device is able to execute a functional operation based on environmental information
Abstract
There is disclosed an information input/output control device and a method therefor which displays a list of identification informations indicating an information terminal device with which a functional operation can be executed in response to an acquired environmental information of the information terminal device and in accordance with an input of an indication information which instruct to execute the functional operation.
Inventors:
Sugiyama; Mitsumasa
(Kawasaki,
JP
)
, Sugiura; Susumu
(Atsugi,
JP
)
, Yokomizo; Yoshikazu
(Yokohama,
JP
)
, Mita; Yoshinobu
(Kawasaki,
JP
)
, Takaoka; Makoto
(Yokohama,
JP
)
, Kobayashi; Shigetada
(Tokyo,
JP
)
, Shishizuka; Junichi
(Kawasaki,
JP
)
, Negishi; Tsutomu
(Tokyo,
JP
)
, Yamada; Osamu
(Yokohama,
JP
)
, Toda; Yukari
(Yokohama,
JP
)
, Saito; Kazuhiro
(Yokohama,
JP
)
, Toda; Masanari
(Yokohama,
JP
)
, Hashimoto; Yasuhiko
(Tokyo,
JP
)
, Fukuda; Yasuo
(Yokohama,
JP
)
Assignee:
Canon Kabushiki Kaisha
(Tokyo,
JP
)
Appl. No.:
730462
Filed:
October 15, 1996
Current U.S. Class:
710/15
703/24
709/217
Field of Search:
395/159,180,892,500.44-500.49 710/15-19,62-74 909/217-318
U.S. Patent Documents
4931922
June 1990
Baty et al.
4953165
August 1990
Jackson
5123017
June 1992
Simpkims et al.
5187592
February 1993
Sugiyama et al.
5241482
August 1993
Iida et al.
5251020
October 1993
Sugiyama
5353399
October 1994
Kuwamoto et al.
5361265
November 1994
Weinberger et al.
Primary Examiner:
Shin; Christopher B.
Attorney, Agent or Firm:
Fitzpatrick, Cella, Harper & Scinto
Parent Case Text
This application is a conitinuation of application Ser. No. 08/182,600 filed Jan. 18, 1994, now abandoned.
Claims
What is claimed is:
1. An information processing apparatus connected to at least one terminal control device via a network, a plurality of terminal devices being connected to the at least one terminal control device, each terminal device executing a functional operation, said information processing apparatus comprising:
acquiring means for acquiring status information on a status of each of the plurality of terminal devices;
first input means for inputting an instruction on a desired functional operation;
second input means for inputting a selection instruction for selecting one of the at least one terminal control device; and
display control means for controlling a display to display identification information of one or more of the plurality of terminal devices on the basis of the status information acquired by said acquiring means, wherein said display control means controls the display to display the identification information of one or more of the terminal devices which are connected to the one terminal control device selected through the selection instruction and which can execute the desired functional operation in response to said second input means inputting the selection information.
2. An apparatus according to claim 1, further comprising:
third input means for inputting a further selection instruction for selecting one of the terminal devices whose identification information is displayed on the display; and
output means for outputting a functional operation execution command to the one terminal control device selected through the first-mentioned selection instruction in response to said third input means inputting the further selection instruction.
3. An apparatus according to claim 1, wherein the status information of each terminal device indicates whether the terminal device is operable.
4. An apparatus according to claim 1, wherein each functional operation comprises one of a printing operation and a scanning operation.
5. An apparatus according to claim 1, wherein said display control means controls the display to display the identification information of the one or more of the plurality of terminal devices distinguishably from identification information of the other terminal devices.
6. An information processing method operative in an information processing apparatus connected to at least one terminal control device via a network, a plurality of terminal devices being connected to the at least one terminal control device, each terminal device executing a functional operation, said information processing method comprising:
an acquiring step of acquiring status information on a status of each of the plurality of terminal devices;
a first input step of inputting an instruction on a desired functional operation;
a second input step of inputting a selection instruction for selecting one of the at least one terminal control device; and
a display control step of controlling a display to display identification information of one or more of the plurality of terminal devices on the basis of the status information acquired in said acquiring step, wherein said display control step control the display to display the identification information of one or more of the terminal devices which are connected to the one terminal control device selected through the selection instruction and which can execute the desired functional operation in response to said second input step inputting the selection instruction.
7. A method according to claim 6, further comprising:
a third input step of inputting a further selection instruction for selecting one of the terminal devices whose identification information is displayed on the display; and
an output step of outputting a functional operation execution command to the one terminal control device selected through the first-mentioned selection instruction in response to said third input step inputting the further selection instruction.
8. A method according to claim 6, wherein the status information of each terminal device indicates whether the terminal device is operable.
9. A method according to claim 6, wherein each functional operation comprises one of a printing operation and a scanning operation.
10. A method according to claim 6, wherein said display control step controls the display to display the identification information of the one or more of the plurality of terminal devices distinguishably from identification information of the other terminal devices.
11. A computer-readable storage medium storing a program for executing an information processing method operative in an information processing apparatus connected to at least one terminal control device via a network, a plurality of terminal devices being connected to the at least one terminal control device, each terminal device executing a functional operation, said information processing method comprising:
an acquiring step of acquiring status information on a status of each of the plurality of terminal devices;
a first input step of inputting an instruction on a desired functional operation;
a second input step of inputting a selection instruction for selecting one of the at least one terminal control device; and
a display control step of controlling a display to display identification information of one or more of the plurality of terminal devices on the basis of the status information acquired in said acquiring step, wherein said display control step control the display to display the identification information of one or more of the terminal devices which are connected to the one terminal control device selected through the selection instruction and which can execute the desired functional operation in response to said second input step inputting the selection instruction.
12. A medium according to claim 11, said method further comprising:
a third input step of inputting a further selection instruction for selecting one of the terminal devices whose identification information is displayed on the display; and
an output step of outputting a functional operation execution command to the one terminal control device selected through the first-mentioned selection instruction in response to said third input step inputting the further selection instruction.
13. A medium according to claim 11, wherein the status information of each terminal device indicates whether the terminal device is operable.
14. A medium according to claim 11, wherein each functional operation comprises one of a printing operation and a scanning operation.
15. A medium according to claim 11, wherein said display control step controls the display to display the identification information of the one or more of the plurality of terminal devices distinguishably from identification information of the other terminal devices.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information input/output control device and a method therefor which displays a list of identification information indicating an information terminal device with which a functional operation can be executed in a network environment under which plural kinds of information terminals are available to be used.
2. Related Background Art
There has been conventionally no method for using a network scanner with which scanning operations are performed by a remote host device connected to a network.
Accordingly, the host device requesting a scanning operation must be fed a video image signal from a scanner connected to the host device. Alternatively, the video image signal was transferred to the host device through the network.
When the video image fed by the scanner is printed out together with the other information, such as characters, drawings etc., the scanned video image and the other information are usually synthesized in the host device requesting the printing operation and output to a printer connected to the network.
There have been the following kinds of data processing methods in a conventional server device.
(1) The video image data expanded into a bit image format in the host is transferred from the host to the printer through an exclusive use interface. The host takes care of all the interface operations with the network. This method has been mainly utilized in an intelligent host, such as a work station.
(2) The host transmits only a page description language. The printer incorporating an interpreter function converts it into a bit image format, which is so called as a network printer.
(3) The device, which converts a page description language transmitted from the host into an exclusive use bit image, further transmits the image data to a printer through an exclusive use interface.
In a printer which forms a video image, with an output video image information being generated from the input data written in page description language, in particular, in a full colour printer which can form a colour video image based on colour video image data such as RGB, red (R), green (G) and blue (B) data corresponding to each input picture element are input and converted into yellow (Y), magenta (M), cyanic (C) and black (B) data, thereby being printed with ink or developer corresponding to each colour in order to output a full colour video image.
However, in order to satisfy a video image input/output request of host computers each of which is supervised by its own different operation system (OS), a plurality of interpreters are necessitated for executing data communication processing which meets each OS so that be data processing load will become heavier on a server device, which causes an increase cost of the device.
Further, when a plurality of host computers which are connected to the network control a plurality of terminal devices, video image input/output requests created by each host computer occur irregularly and sometimes concurrently with each other. In this moment, when a preceding or waiting print or scan job exists, the succeeding print or scan job cannot precede, thereby aggravating a problem in the speed of video input/output processing.
In addition, colour terminals utilized in these kinds of networks are relatively expensive in price in comparison with monocolour terminals and interface devices utilized to interface with the host are extremely expensive in price in comparison with the monocolour devices. A main reason for this is that an enormous amount of video image data is created when a colour video image is processed. Further, data must be abstracted in transmission of a colour video image.
That is, an encoding, a coding and a vectorizing are required for video image data, character data and graphic data, respectively.
These procedures can realize the data to be described in a form independent of the output terminal device by abstracting document and video image data as much as possible, thereby eliminating the data amount. On the other hand, in the receiving side which receives the data described above, the interface device utilized for converting the above described data into bit image data most suitable for each receiving device will become complicated and expensive in price.
However, under the circumstance that the colour terminal devices are utilized, it is feared that the whole device will become very expensive if each host computer employs both of a colour interface device and a colour terminal device.
On the contrary, if a supply access to a single scanner/printer which is connected to the network by a plurality of machines is non-restrictively permitted, the request of group users cannot be satisfied who are willing to use restrictively the scanners/printers connected to the network so that an access request to the scanners/printers by the specific group users will be kept waiting for a considerably long time.
The conventional video image terminal into which a communication function is incorporated executes the scanning and printing functions in accordance with an access input order from each host. While a scanner/printer server device incorporating a memory means for storing video image input/output instructions from a plurality of users is waiting, without executing input/output procedures, with stored therein an instruction designating a specific printer or a video image input device (scanner), it happens that the designated printer or scanner becomes inoperable due to, for example, a paper feed jam of a printer or a break down of an exposure lamp.
Even though, in this case, operable terminals are available, waiting and usable, they cannot start input/output processings until the first designated terminal is recovered, because they have not been designated, which reduces remarkably efficiency of the terminal devices.
Further, terminal devices, particularly printers, have not necessarily provided high quality printing because they simply execute video image output processing in accordance with input data, such as a page description language or the like. For example, in a printer which compresses image data created by a video image generator, stores its one page of data into a video image memory, and then expands it for printing so as to cope with a high speed of the printer, it has sometimes compressed with a compression rate higher than necessary because the memory in which the compressed image data is stored is limited in capacity, which results in a quality aggravation of the video image. In other words, when the compression is performed with an adequate compression rate so as to store the compressed data in the memory in full, the aggravation can be minimized. However, in the JPEG (Joint Photographic Expert Group) compression, which is a standard compression method for a colour video image, it is difficult to predict a post-compressed data amount prior to compression if information about the colour video image which is to be compressed is not available.
As the result, the compression has been performed with a higher compression rate than necessary to securely store the compressed data, which has caused an aggravation of the video image.
Furthermore, high speed and high quality printing has not necessarily been available in printing out from a binary printer by digitizing the video image information created by a video image generator.
In digitizing, for example, it is better to use an error diffusion method with which a relatively clear-cut line can be achieved for a document having much area for characters and drawings whereas it is better to use a dither method with which a relatively short processing time for digitizing can be achieved for a document having almost all its area for images.
However, in a conventional device, since the video image processor simply forms image data, a printer has been printing using only a single digitizing method regardless of the video image.
Further in a printer in which a video image created by the video image generator is colour-converted by the video image output circuit, a high quality printing has not necessarily been achieved.
In general, it is suitable to employ a colour conversion with much more black ink to make the black colour clear in a document containing many characters and drawings therein whereas it is suitable to employ a colour conversion with less black ink to make the image naturalized in a document containing many images therein.
However, in a conventional device, since the video image output circuit simply forms image data, a printer has been printing using only a single digitizing method regardless of the video image, thereby high quality printing having not necessarily been available.
The data processing format which is described by the host varies on company by company and the Quick Draw (commercial name) type, GDI (commercial name) type and the like have been available (later will be described in detail).
There are various types of page description languages (PDL) to control a printer environment, that is, a printer, such as Post Script (commercial name), ESC/P (commercial name), LIPS (commercial name), CaPSL (commercial name) and the like.
The host executes an output information with a data format which depends on an activatable application program.
Accordingly, if the data format of the output device to be connected thereto is mismatched with that depending on the above application program, the application program must be amended in order to output the data through the output device, whereby the selection range of the output device to be connected will be narrowed.
Further, in the case of amending each application program, the developing cost for each application will become heavier, thereby decreasing the customer's interest in purchasing the application programs.
SUMMARY OF THE INVENTION
The present invention is made to overcome the foregoing problems. Therefore, it is an object of the present invention to provide an information input/output control device and a method therefor which displays a list of identification informations indicating an information terminal device with which a functional operation can be executed in response to an acquired environmental information of the information terminal device and in accordance with an input of an indication information which instruct to execute the functional operation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a system block diagram illustrating a schematic view of a server device of the first embodiment in accordance with the present invention;
FIG. 2 is comprised of FIGS. 2A and 2B showing system block diagrams illustrating a schematic view of a network system to which the server device shown in FIG. 1 is applied;
FIG. 3 is a view illustrating a network structure between a server device according to the present invention and its host device;
FIG. 4 is a circuit diagram illustrating a detailed structure of a main CPU board circuit shown in FIG. 1;
FIG. 5 is a block diagram illustrating a detailed structure of a memory clear controller shown in FIG. 4;
FIG. 6 is an explanatory view illustrating a band expansion process of video image information to a band memory shown in FIG. 5;
FIG. 7 is an explanatory view illustrating a band expansion process of video image information to a band memory shown in FIG. 5;
FIG. 8 is a block diagram illustrating a detailed structure of an image drawing processor circuit shown in FIG. 5;
FIG. 9 is a block diagram illustrating an internal structure of the first interface circuit shown in FIG. 1;
FIG. 10 is a block diagram illustrating an example of a detailed structure of a real time Compression/Expansion circuit shown in FIG. 9;
FIG. 11 is a view illustrating an example of a zigzag scan path made by a zigzag scanner shown in FIG. 10;
FIG. 12 is a block diagram illustrating a partial schematic structure of the first SP interface circuit shown in FIG. 1;
FIG. 13 is comprised of FIGS. 13A and 13B showing circuit diagrams illustrating a detailed internal structure of the first SP interface circuit shown in FIG. 1;
FIG. 14 is a circuit diagram illustrating a detailed internal structure of the first SP interface circuit shown in FIG. 1;
FIG. 15 is a circuit diagram illustrating a detailed internal structure of the first SP interface circuit shown in FIG. 1;
FIG. 16 is a circuit diagram illustrating a detailed internal structure of the second SP interface circuit shown in FIG. 1;
FIG. 17 is an explanatory view illustrating an image recording process of a scanner/printer shown in FIGS. 2A and 2B;
FIGS. 18A to 18C are explanatory views illustrating a document scanning operation of a scanner/printer shown in FIGS. 2A and 2B;
FIG. 19 is an explanatory view illustrating a band document scanning operation of a scanner/printer shown in FIGS. 2A and 2B;
FIG. 20 is a view illustrating an example of an interface signal between a server device according to the present invention and a printer;
FIG. 21 is a circuit diagram illustrating an example of an interface between a server device according to the present invention and a printer;
FIG. 22 is a timing chart illustrating an operation of the circuit shown in FIG. 21;
FIG. 23 is a flowchart illustrating an example of a signal processing procedure in a host of a Centronics I/F circuit shown in FIG. 21;
FIG. 24 is a flowchart illustrating an example of a signal processing procedure in a printer of a Centronics I/F circuit shown in FIG. 21;
FIG. 25 is a view illustrating a program structure between a server device according to the present invention and a host computer;
FIG. 26 is a flow chart illustrating an example of a total control procedure in a server device according to the preset invention;
FIG. 27 is a view illustrating a main portion of a code system applied with necessary modifications to a page description language in a server device according to the present invention;
FIG. 28 is a view illustrating a substitutional procedure into an intermediate code conducted by a layouter in a server device according to the present invention;
FIG. 29 is an explanatory view illustrating an expanding procedure of a graphic information to a band memory in a server device according to the present invention;
FIG. 30 is an explanatory view illustrating a structure of a single picture element expanded with a page description language in a server device according to the present invention;
FIG. 31 is a view illustrating a data processing path for explaining an operation of a scanner shown in FIGS. 2A and 2B;
FIG. 32 is a block diagram illustrating a data processing state between a server device according to the present invention and a color laser copier;
FIG. 33 is a block diagram illustrating a data processing state between a server device according to the present invention and a color laser copier;
FIG. 34 is a block diagram illustrating a data processing state between a server device according to the present invention and a thermal jet color copier;
FIG. 35 is a block diagram illustrating a structure of a network system in which a server device according to the present invention is incorporated;
FIG. 36 is a flowchart illustrating an example of a procedure with which an abnormally generated job is processed in a server device according to the present invention;
FIG. 37 is a flowchart illustrating an example of a procedure with which a retrial job is processed;
FIGS. 38A to 38E are timing charts illustrating a job control state in a server device according to the present invention;
FIG. 39 is a view illustrating a processed state of a total system control program in a server device according to the present invention;
FIG. 40 is a flowchart illustrating an example of an event processing procedure performed by a total system control program shown in FIG. 39;
FIG. 41 is a view illustrating a job administration state in a server device according to the present invention;
FIG. 42 is a flowchart illustrating an example of a job execution procedure in a server device according to the present invention;
FIG. 43 is a flowchart illustrating an example of a status check procedure in a server device according to the present invention;
FIG. 44 is a flowchart illustrating an example of a status check procedure with a top priority order in a server device according to the present invention;
FIG. 45 is a flowchart illustrating an example of a interface check procedure in a server device according to the present invention;
FIG. 46 is a flowchart illustrating an example of a job initiation procedure in a server device according to the present invention;
FIG. 47 is a timing chart illustrating a job processing transfer state in a server device according to the present invention;
FIG. 48 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 49 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 50 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 51 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 52 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 53 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 54 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 55 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 56 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 57 is a table illustrating a content of a job table in response to a job processing in a server device according to the present invention;
FIG. 58 is a block diagram illustrating a structure of a server device of the second embodiment according to the present invention;
FIG. 59 is an explanatory view illustrating a printed layout synthesized by an SP server device shown in FIG. 58;
FIG. 60 is comprised of FIGS. 60A and 60B showing flow charts illustrating an example of the first input/output control procedure in a server device according to the present invention;
FIG. 61 is comprised of FIGS. 61A and 61B showing flow charts illustrating an example of the second input/output control procedure in a server device according to the present invention;
FIG. 62 is a block diagram illustrating a communication control structure between a video image terminal and a server device according to the embodiment of the present invention;
FIG. 63 is a view illustrating a network connection structure of a server device according to the embodiment of the present invention;
FIG. 64 is a flow chart illustrating an example of a user identification processing step in a server device according to the embodiment of the present invention;
FIG. 65 is a block diagram illustrating a communication control structure between a video image terminal and a server device according to another embodiment of the present invention;
FIG. 66 is a view illustrating a structural example of a control data of a spooler shown in FIG. 65.
FIG. 67 is a flow chart illustrating an example of a print task processing step in a server device according to the present invention;
FIG. 68 is a block diagram illustrating a communication control structure between a video image terminal device and a server device according to the other embodiment of the present invention;
FIG. 69 is a flow chart illustrating an example of a print data generation processing step in a server device according to the present invention;
FIG. 70 is a flow chart illustrating an operational example of a compression circuit shown in FIG. 68;
FIG. 71 is a flow chart illustrating an example of another print data generation processing step in a server device according to the present invention;
FIG. 72 is a block diagram illustrating a video image processing structure in a server device according to the embodiment of the present invention;
FIG. 73 is a conceptional view illustrating a structure of a video image memory shown in FIG. 72;
FIG. 74 is a conceptional view illustrating a structure of a supplemental information memory shown in FIG. 72;
FIG. 75 is a flow chart illustrating an example of a receiving data processing step in a video image generation circuit shown in FIG. 72;
FIG. 76 is a flow chart illustrating an example of a colour printing processing step in a video image output circuit shown in FIG. 72;
FIG. 77 is a block diagram illustrating another video image processing structure in a server device according to the embodiment of the present invention;
FIG. 78 is a block diagram illustrating a video image processing structure in a server device according to the embodiment of the present invention;
FIG. 79 is a block diagram illustrating another video image processing structure in a server device according to the embodiment of the present invention;
FIG. 80 is a block diagram illustrating another video image processing structure in a server device according to the embodiment of the present invention;
FIG. 81 is a view illustrating an example of an output video image sample in accordance with a rasterized processing into a band memory shown in FIG. 29;
FIG. 82 is a view illustrating a structure of a page description command transmitted from each host computer shown in FIGS. 2A and 2B;
FIG. 83 is an explanatory view illustrating a structure of a page description command transmitted from each host computer shown in FIGS. 2A and 2B;
FIG. 84 is an explanatory view illustrating a band unit rasterizing procedure in a server device according to the present invention;
FIG. 85 is an explanatory view illustrating a page description command transmitted from each host computer shown in FIGS. 2A and 2B;
FIG. 86 is an explanatory view illustrating a page description command transmitted from each host computer shown in FIGS. 2A and 2B;
FIG. 87 is a flow chart illustrating an example of a mode designation processing step of a scanner/printer from a host computer to an SP server device according to the present invention;
FIG. 88 is a view illustrating an example of an SP server designation window commonly viewed in each station shown in FIGS. 2A and 2B;
FIG. 89 is a view illustrating an example of an SP server designation window commonly viewed in each station shown in FIGS. 2A and 2B;
FIG. 90 is a view illustrating an example of an SP server designation window commonly viewed in each station shown in FIGS. 2A and 2B;
FIG. 91 is a view illustrating an example of an SP server designation window commonly viewed in each station shown in FIGS. 2A and 2B;
FIG. 92 is a flow chart illustrating an example of an SP server designation control step commonly utilized in each station shown in FIGS. 2A and 2B;
FIG. 93 is comprised of FIGS. 93A and 93B showing flow charts illustrating an example of an SP server designation control step commonly utilized in each station shown in FIGS. 2A and 2B; and
FIG. 94 is a flow chart illustrating an example of a data transfer processing step in an information processing method according to the embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
A detailed description of the preferred embodiment will be made hereinafter referring to a server device to as an example of an information processing device according to the present invention to which a plurality of terminal devices executing scanning and printing functions are connected through a predetermined interface and is communicably connected to a plurality of host devices through a predetermined network.
Although the description will be further made referring to a data transmission procedure between the host computer communicably connected to the server device and its application, the present invention can be, needless to say, applicable to a host computer communicably connected to the server device which is further communicably connected to a plurality of host computers through a predetermined network and also connected to a plurality of output terminal devices executing the printing function through a predetermined interface.
FIG. 1 is a system block diagram schematically illustrating a server device according to the first embodiment of the invention. A detailed system block diagram will be explained later.
A scanner/printer (SP) server not shown in FIG. 1 will be explained later. This system briefly comprises a main CPU circuit 1, an Ethernet circuit 2, JPEG compression/expansion (hereinafter as called "compansion") circuit 3 and a scanner/printer interface circuit 4.
When plural scanners and printers are necessary to be connected to the scanner/printer (SP) server, the necessary number of scanner/printer interface circuits 4 have to be installed. To facilitate increase or decrease the number, the scanner/printer interface circuit 4 is constituted on an independent board and connected to its main body through a VME bus 16 which will be described later. The remaining three circuits 1, 2 and 3 are constituted on a single board and coupled each other through a local bus.
The reference numeral 4-1 denotes a first scanner/printer interface circuit (hereinafter called as the first SP interface circuit) and serves as an interface between a digital color copier 100 (laser beam color copier), for example, "CLC-500" (product name) and the VME bus 16.
The reference numeral 4-2 denotes a second scanner/printer interface circuit (the second SP interface circuit) and serves as an interface between a digital color copier 200 (thermal jet color copier), for example, "Piccel Jet" (product name) and the VME bus 16.
The main CPU circuit 1 is constituted of a CPU 5, for example, R3000 (product name) and a memory 6, which constitutes an operating system "OS." For example, under the control of VxWorks (product name), all programs are executed. A hard disk 7 is provided as an auxiliary device for the memory 6. The numeral 8 denotes a SCSI interface. The Ethernet circuit 2 comprises an Ethernet transceiver 9 and a DMA controller 10 which transfers data to the memory 6 in a DMA mode.
The Ethernet transceiver 9 is connected to an "Ethernet Local Area Network" (product name: LAN) 11.
The JPEG compansion circuit 3 comprises a JPEG compression, expansion controller 12 and an FIFO memory 13. A local bus, which couples the main CPU circuit 1, Ethernet circuit 2 and the JPEG compansion circuit 3 interrelatedly, is connected to the VME bus 16 through a VME bus transceiver 15-1.
The first SP interface circuit 4-1 comprises a page memory 17 and a first control circuit 18. Although the page memory 19 requires one page size memory area, this is because when the digital color copier 100 initiates printing or scanning functions, the flow control cannot be possible any more. The memory 17 is constituted as a compression memory because its price is very expensive.
An ADCT compression technique, which can achieve non-reversible, high compression rate compression, is employed on the memory 17 in view of the fact that the data stored in the memory 17 is only those rasterized by the memory 6. An ADCT compression chip not shown in FIG. 1 can be used with the same chip used in the JPEG compansion controller 12.
The compression data stored in the page memory 17 by using the ADCP compression technique is only used in a closed circuit herein and is not output herefrom so that no normalization is necessary. In fact, an improved JPEG is utilized as an effective method.
The first control circuit 18 is constituted of a CPU, for example, "Z-80" (product name) and used to send and receive control signals other than video signals to/from the copier 100.
A control command is serially transmitted in order to reduce a number of the interface.
The first SP interface circuit 4-1 is connected through the VME bus transceiver 15-2 to the VME bus 16.
The second SP interface circuit 4-2 which comprises a data direction converter 19, a buffer memory 20, a video processing circuit 21 and a second controller 22, is connected to the VME bus 16 through the bus transceiver 15-3. The data direction converter 19 converts a video data format into a vertical direction relative to the scanning direction in printing and converts a video data format which is a vertical direction relative to the scanning direction into the scanning direction, for which the buffer memory 20 is utilized.
The video processing circuit 21 is employed to supplement a video processing function which is lacked on the copier 200. The second controller 22, which provides the same functions as those of the first controller 18, is constituted of a CPU, for example, "Z-80" (product name).
Hereinafter, operations will be explained. The first example is how to execute a network printing.
A page description language i.e., "CaPSL" (product name) input from LAN 10 through the Ethernet transceiver 9 is stored directly into a specific region (receiving buffer) of the memory 6 by the DMA controller 10, and converted into a raster image by a page description language interpreter program, which will be described later.
Although the JPEG compression video image signal can be expanded by the page description language (hereinafter called as PDL), the JPEG compansion circuit 3 is utilized for expanding in a high speed.
In the first server device constituted above, the first video output control circuit (i.e., main CPU circuit 1) controls outputs, to the respective terminal devices, of the first video information signal input from the respective host through the network, the second video information signal read from the respective terminal devices (copier 100, 200) in accordance with instructions from the respective hosts and the third video information signal combined the first video information with the second one in accordance with instructions of the respective hosts, in accordance with flow charts shown in FIGS. 60 and 61. Accordingly, either of the first to third video information signals can be directly produced and directly output from the respective terminal devices in accordance with instructions of the respective hosts.
Further, since the second video output control circuit controls the second video information signal being output to the first host which requests the information or to the second host which is designated by the first host, the second video information fed from the respective terminal devices in response to instructions from the hosts can be directly transferred to the other host including its own host.
Since the memory 6 does not have enough capacity due to economical reasons to store one page data created by rasterizing a video plane, is employed a bunding method which executes partially the PDL, for example CaPSL for one time and proceeds multiple times in total. The rasterized data is transferred to either the first SP interface circuit 4-1 or the second interface circuit 4-2 and then output to the respective printers. A network scanning procedure will be described later.
FIGS. 2A and 2B are system block diagrams schematically illustrating a network system in which the server device shown in FIG. 1 is incorporated.
The network system in the embodiment is so constructed that a small number of scanners or printers connected thereto through the network can be commonly utilized from application softwares of the commercialized host computers, such as Macintosh (product name), IBM-PC (product name), SUN (product name), etc.
The network system shown in FIGS. 2A and 2B is divided into four blocks, namely from the left, Macintosh work station ST1, IBM-PC work station ST2, SUN work station ST3 and a color SP server SP1. Three work stations ST1-ST3 are commercialized host computers and the color SP server SP1 is an interface unit designed by the inventors of the present invention.
These blocks are mutually connected through a local area network 96, for example, Ethernet (product name). Numerals 94 and 95 denote a first color scanner/printer and a second color scanner/printer, respectively.
Macintosh work station ST1, IBM-PC work station ST2, SUN work station ST3 and the color SP server SP1 employ a common communication interface for mutual communication.
Numerals 51, 61, 71, and 81 denote Ethernet transceivers which are used for communication with the local area network (LAN) 96. Numerals 52, 62, 72, and 82 denote communication programs TCP/IP (product name) which are constructed on the LAN 96
and standards of U.S. Department of Defense.
The TCP/IP program provides an error-free data communication service (function) in End-to-End. Numerals 53, 63, 73, and 83 denote communication programs which provides services (functions) for special purposes to be utilized commonly from either Macintosh work station ST1, IBM-PC work station ST2 or SUN work station ST3. Numerals 53 and 63 denote communication programs to provide a client type service as an S/P client program and numeral 83 denotes a communication program to provide a server type service as an S/P server program.
Now, an Explanation will be made how to print on the first color scanner/printer 94 from Macintosh station ST1. In order to print the document produced by a commercialized application program 56, the "OS" called as Printing Manager 55 undertakes partially the control and initiates the control for printing.
The data format is standardized as "Quick Draw" (product name) in case of Macintosh.
Printing Manager 55 calls image drawing function groups of the conversion program 54 in a manner as they are written in the document.
The conversion program 54 consecutively converts Quick Draw into, for example, CaPSL (Canon Printing System Language) codes in the call and stores them into an unshown memory.
The communication program 53 transfers the obtained CaPSL codes to the color SP server SP1 in accordance with TCP/IP program 52 through Ethernet transceiver 51, LAN 96, Ethernet transceiver 81, TCP/IP program 82 and the communication program 83. The conversion programs 54, 64, 74, the communication programs 53, 63, 73, the scanner interface programs 57, 67, TCP/IP programs 52, 62, 72 can be supplied to the host computers either in a form of a floppy disk or an Ethernet transceiver, for example, a board circuit.
The whole operations of the color SP server (S/P server device) SP1 are controlled by a system control program 93. A receipt of the CaPSL codes is also informed to the system control program 93. The system control program 93 requests a PDL interpreter program 84, which will be described later, to rasterize the CaPSL coded document into a bit map video image.
The video image data rasterized into the bit map video image is transferred to a device driver 86 and further transferred to the first color scanner/printer 94 from the video interface Video I/F through, for example, the first printer control board 91 to be printed.
Although similar data flow is made when printed by using IBM-PC station ST2, a data format of the printed document is standardized as "GDI" (product name). The conversion program 64 mainly serves as GDI/CaPSL conversion program.
When printed by using SUN work station ST3, since the functions corresponding to the conversion programs 54, 64 are not standardized, communications are directly made by the application program 75 through the communication program 73.
In order to print by using a commercialized application program, for example, "Frame Maker" (product name), the conversion program 74 for MIF/CaPSL conversion is provided therebetween.
In case of scanning (reading) by using, for example, Macintosh station ST1, a scan request is issued by the scanner application program 58 through the scanner interface program 57. Then, the communication program 53 keeps an End-to-End communication route to the communication program 83 through Ethernet transceiver 51, LAN 96, Ethernet transceiver 81 and TCP/IP program 82. The scan instruction is also transferred to the system control program 93 and the system control program 93
requests the scanner control program to scan the first color scanner/printer 94.
The video image data of the scanned document is reversely transmitted from the first control board 91, through the device driver 86, the communication program 83. TCP/IP program 82, Ethernet transceiver 81, LAN 96. Ethernet transceiver 51, TCP/IP program 52, the communication program 53, the device driver 57, to the application program 58.
When scanned by using IBM-PC station ST2, a similar function will be made.
However, when scanned in SUN work station ST3, since the functions corresponding to the device driver 57 and the scanner interface program 67 are not standardized, communications are directly made by the scanner application program 76 through the communication program 73.
The scanner interface programs 57, 67 perform data control between the scanner application and the communication program.
The color SP server SP1 is connected to another scanner/printer, the second color scanner/printer 95, which controls the second color scanner/printer 95 as well through the second control board 92.
All programs including the system control program 93 of the color server SP1 work under control of the operating system "OS", for example, VxWorks (commercial name).
In order to receive requests from the UNIX work stations in which no such special programs such as the communication program 73 and the conversion program 74 are installed, there is installed a quasi-standard lpr/lpd communication program 90 in parallel with the communication program 83.
FIG. 3 is a view illustrating a network structure between a server device according to the invention and its host computers.
In the drawing, either Macintosh (commercial name), IBM-PC (commercial name) or SUN (commercial name) computer each "OS" of which controls its own data processing can be used as each of host computers HOST 1-N.
Each of the host computers HOST 1-N respectively incorporates an Ethernet interface board 97, a video image compansion (ADCP) board 98, and a CPU board 99 to communicate with LAN 96.
ADCT board 98 can be replaced by a software which realizes the same function on a memory.
In case of not using a compression/expansion technique at the time of input/output of the video image data, there is unnecessary to provide the ADCP board 98. Although the embodiment employs "Ethernet" as the LAN 96, the other alternative "Apple talk" (commercial name), or "Taken Ring" (commercial name) can be also utilized.
This invention is also applicable to a system employing OS1 or IPX (both commercial names) instead of the communication program TCP/IP program.
FIG. 4 is a circuit block diagram illustrating a detailed structure of a board circuit constituted of the main CPU circuit 1, the Ethernet circuit 2 and the JPEG compression circuit 3 shown in FIG. 1.
In the drawing, a CPU 101 which is constituted of, for example, IDT 79R3051 (commercial name) controls whole operations of the board circuit. A real time OS is incorporated on the board circuit.
The CPU 101 activates the communication program 83, the system control program 93, the scanner control program 85, and PDL interpreter program 84, all of which have been activated under the above OS's and controls all operations in multi-processes.
A main memory 102 serves as a work memory of the CPU 101. When the system turns on, the programs stored in an EPROM 107, in an auxiliary memory device such as a hard disk connected to a SCSI port 112, or in a host computer in the network are down loaded and arranged into the memory 102. Therefore, the program itself of each processes is located on the main memory 102 and works there.
A band memory 103 can store a few lines of video image data in use of a raster method. The band memory 103 expands the PDL data into a bit map data. Although PDL usually delivers one page bit map data to a printer engine, this system employs a method that one page is divided into a few bands and expanded into a bit map data.
This can be realized in that the PDL interpreter program 84 rearranges the PDL data. The bit map data expanded into the band memory 103 is delivered to a printer. Then, the next band is expanded and delivered again to a printer.
One page printing can be accomplished by repetition of the above operations.
The video image data read from the scanner, is also temporarily stored in the band memory. The CPU 101, or a block transfer function of a direct memory access (DMA) which is not described in the system, can read the video image data from the band memory 103 and delivers it to the host computer through a hard disk connected to the SCSI port 112 or the network connected to the Ethernet port 114. When one band data is delivered, next band scan data is input and repeated in the same way described above.
A memory access controller 104 controls access and refresh functions of the main memory 102 and a DRAM constituting the band memory 103.
Though there are usually several kinds of methods for accessing DRAMs; a method for accessing word (8, 16, 32, . . . bits) by word; a method for accessing serially with a predetermined bit length (page READ, Write); and an interleave method in which divided DRAM banks are alternatively accessed and addresses are generated in advance, all the above methods can be applied so as to speed up the memory access. When the main memory 102 and the band memory 103 are constituted of SRAMs, it is not required to refresh. A memory clear controller 105 clears the data in the band memory 103 in a high speed.
FIG. 5 is a block diagram illustrating a detailed structure of the memory clear controller 105 shown in FIG. 4.
In the drawing, an address generator 201 outputs addresses to be cleared at an address buffer 203 in response to a clear start signal. A data latch 202 outputs the clear data at a data buffer 204.
In the board circuit constituted of the main CPU circuit 1, the Ethernet circuit 2 and the JPEG compression circuit 3, when the CPU 101 confirms that the data of the band memory 103 is transferred to the other memory or interfaces, the address buffer 203 and the data buffer 204 are enabled, whereas the other access means to the band memory 103 are disabled. System initializing data, for example, "00" have been set in the data latch 202. The CPU 101 delivers a clear start signal to an address generator 201. In response to that, the address generator 201 generates consecutive addresses and the data latched at the data latch 202 is written in the band memory 103 through the memory access controller 104. After completion of writing into the whole memories, the address generator 201 sends a clear end signal to the CPU 101 and the clear operations are terminated.
A clear operation will be made after the video image data of the band memory 103 is delivered to a printer device. The video image data of the next band is expanded by the PDL interpreter program 84. On this moment, the PDL interpreter program
84 expands only the necessary portion into a bit map.
For example, as to the band expansion shown in FIG. 6 (1), (2), only the video image belonging to the area (2) is written. Accordingly, the video image data already transferred in FIG. 6, (1) remains as an unnecessary data.
If not cleared on the memory, the video image data mixing the area (1) and the area (2) stays in the band memory 103.
For that reason, the memory clear procedure is necessary. The memory clear controller 105 is constituted of hardware to proceed the memory clear procedure so that a high speed procedure can be realized.
The image drawing processor 106 is constructed in order to support with hardware drawing functions of the PDL interpreter program 84. The PDL interpreter program 84 requires relatively much time to draw lines and paint drawings.
In order to paint, for example, the area enclosed with drawings (1) to (3) shown in FIG. 7, the painting procedure is performed in a direction shown as arrows in FIG. 7.
FIG. 8 is a block diagram illustrating a detailed structure of the image drawing processor 106 shown in FIG. 5.
In the drawing, an address generator 106A delivers an address to be cleared to an address buffer 106C in response to a drawing start signal. A data latch 106B delivers a drawing data to a data buffer 106D.
In the board circuit constructed above, the CPU 101 instructs the image drawing processor 106 in view of the executed result by the PDL interprogram 84 when there exists drawing of lines or painting of drawings in the present band width.
The drawing data is firstly latched in the data latch 106B. Then, a start address and a count number (one line drawing volume) are set on the address generator 106A. The count number may be replaced by an end address. Next, the address buffer
106C and the data buffer 106D are enabled. In the contrary, the other access means to the band memory 103 are disabled. The CPU 101 delivers the drawing start signal to the address generator 106A. In response to that, the address generator 106A generates a series of sequential addresses from the start address value and the data latch 106B delivers its storing data to the band memory 103 through the memory controller 104.
When the counted number reaches to the predetermined number (end address), memory writing stops and the drawing end signal is delivered.
The memory writing will be restarted after the next start address and count number are determined and repeated up until the band is completely drawn.
The drawing operations are speeded up by employing hardware as the clearing operations are as well. Other structures can be employed wherein the specialized LSI undertakes the drawing procedure so that the supplemental operation of the CPU 101
is reduced.
In FIG. 4, the EPROM 107 in which above mentioned various programs for controlling the system are stored is firstly accessed by the CPU 101 when the power turns on.
There can be two methods for memorizing into the EPROM 107. The first method is to memorize in a manner that the programs can be executed as they are, whereas the second method is to compress and memorize the whole programs reversibly and to rearrange in the main memory 102 by expanding them when the power turns on.
The first method can save the main memory 102 then the method rearranging on the main memory 102 because the EPROM 107 can be executed without further ado. However, the first method has the shortcomings, that is, it requires much memory size of the EPROM 107 and an access time of the EPROM is relatively slow.
The second method can store a lot of programs in the EPROM 107 so that the memory size of the EPROM 107 can be reduced. And, since rearrangement is made on the main memory, an access time becomes relatively faster. However, it requires much memory size of the main memory 102.
In this embodiment, the second method is employed.
An EEPROM 108 is a device which does not loose the stored data even if the power turns off and can be rewritten data when the power turns on. Accordingly, it is well utilized for memorizing addresses on the network and for memorizing setting parameters of scanners and printers.
A time adjustable clock circuit (RTC) 109 is employed and time progresses even when the power turns off because it contains an internal battery, whereby real time can be known and utilized an information for scanning and printing. A timer 110 is an interval timer. Programs of the system are operated with a multi-program mode and its control is made by a real time OS.
The timer 110 informs the CPU 101 of interval time with a few milliseconds.
Each programs are assigned to the CPU 101 in accordance with the timer 110 and a priority order scheduler.
A SCSI controller 111 controls a SCSI which is a standard for a peripheral device interface. A SCSI port 112 is a parallel input/output I/F port for connecting a peripheral device.
An Ethernet controller 113 connects the system with LAN 96, which is one of the network systems, and functions as a controller for data communications.
The Ethernet controller 113, in which a small buffer memory is incorporated, takes time matching between the nonsynchronous CPU and the synchronous network.
The data transferred from the network is stored in the buffer memory and the data to be transferred to the network is also delivered from the buffer memory.
The Ethernet controller 113 performs a control of electric timings and a control of data transmission and receipt. TCP/IP communication program 82 is controlled by the CPU 101 by utilizing the Ethernet controller 113.
The Ethernet 114 is made of a thick coaxial cable 114a, the interface I/F of which is constituted of a connector having 15 pins. The twist pain type port 114b is made of four line medium, the interface I/F of which is constituted of a modular jack having 8 pins. These ports are utilized for connection with the Ethernetwork. An ADCT compression/expansion circuit 115 compresses or expands intermediate tone data (each color has 8 bit length) which are constituted of RGB (RED, GREEN, BLUE) by employing a JPEG algorithm standardized in CCITT.
In case of compression of color intermediate tone data read from a scanner, real video image data read from the scanner is compressed by the ADCT compression/expansion circuit 115 to reduce the memory size.
Accordingly, speed up of network transfer and reduction of stored memories can be realized.
The compressed video image data transferred through the network is expanded by the ADCT compression/expansion circuit 115 into color intermediate tone data and stored in the band memory 103. Then, they are transferred to a printer interface I/F to be printed by a printer device.
An FIFO memory 116 is used for transmitting or receiving compressed video image data to/from the ADCT compression/expansion circuit 115. The FIFO memory 116 is used for absorbing a data transfer timing gap due to data volume difference between compressed data and expanded data (real video image data) in compression and expansion operations.
An RS232C controller 117 controls a standard serial interface I/F. An RS232C port having two ports, A channel 118a and B channel 118b, has one port used for connecting terminal devices to display or to input data from a key board. Another port is used for connecting with a device having a serial interface, to which a character printer, like a laser beam printer, or a simple type scanner can be connected.
In this system, A channel is used for terminal devices and is used to receive command inputs or to change parameters. This system also employs a quasi terminal function in which a similar function of A channel can be achieved by making r-login from a host computer in the network.
Centronics I/F controller 119 performs an I/F control for connecting a printer with a modified Centronics type I/F.
If, in fact, outputs 8 bits data after confirming the status (BUSY/non) of a device to be connected. By repeating the above operation, data is delivered. The controller 119 performs other signal controls based on the modified Centronics I/F. Centronics I/F port 120 is electrically connected to a printer with a cable.
A VME controller 121 controls the CPU 101 of the system to access the other board having a modified VME bus standard. The VME bus standard permits address buses A16, A24, A32 and data buses D8, D16, D24, D32 be accessed. A bus usage right is given in accordance with an arbitration method. The circuit further realizes a control suitable for the VME bus standard.
A VME bus port 122 is electrically connected to a double height VME bus. The VME bus port 122 is constituted of two connector having 6 pins, among which an address bus and a data bus are disposed.
A reset switch 123 is finally depressed to restart the system when a system error occurred. Although the reset switch 123 is constituted of a hardware switch mechanism in this embodiment, a program RESET (warm RESET) can be employed which resets by using programs from a terminal connected to the above mentioned RS232C port 118 or a quasi terminal r-logged-in from the network.
An LED 124 is constituted of an LED 124a which indicates power ON, an LED 124b which indicates the CPU 101 is executing and an LED 124c which can be turned on by each program. An operator can visually confirm that the system is turned on when the LED 124a is turned on. An operator can also visually confirm that the CPU 101 is executing when the LED 124b is turned on and that the CPU 101 is waiting when the LED 124b is turned off.
When the LED 124c turns on frequently, an operator can visually confirm that any procedure is currently executing. An operator can identify the program with which the LED is turned on by watching a duration time, a turning on interval and a turning on number.
A detailed description of a data flow will be made hereinafter under a process of a request for printing issued by a host computer in the network.
When the network, that is, the host computer connected with LAN 96 desires to print data, it transmits to a SP server system information designating the data and an output destination.
In this instance, when a hard disk is connected to the SCSI port, the data is temporarily stored (spooled) in the hard disk. When a hard disk is not connected, the data is temporarily stored in the main memory 102. Transferred data formats are shown hereunder as (1) to (3). (1) data with a PDL format, (2) data revealing a real video image and (3) data revealing a compressed video image.
In case of (1) the data with a PDL format, the PDL interpreter program 84 is activated and each band is expanded into a bit map which is written in the band memory 103. When the band memory fills the data, it transmits them to the printer and next band is expanded into a bit map.
In case of (2) the data revealing a real video image, the band memory 103 stores the data of each band width and transfers them to a designated printer. Then, the data of next band width is prepared. Since the data revealing a real video image contains much data volume, the host computer does not transfer all the data in the lump but transfers with being divided.
Accordingly, a job receiving the data from the network has been proceeded during the time of printing.
Further, in case of (3) the data revealing a compressed video image, the compressed video image data is stored in the FIFO memory 116 and converted by the ADCT expansion circuit 115 into a real video image data. The expanded data of each band width is stored in the band memory 103 and transferred to a designated printer. Hereinafter, the similar procedure will be repeated.
In some cases, the data format of video image data happens to be not a single format but a complexed format combining the above described data formats. In case of (1) data format and (2) data format or (1) data format and (3) data format both in combination the above described procedures are applied.
There are three cases in using an interface I/F of a printer device which transfers a video image data. The first case is to be connected through an interface board construct on the VME bus 122.
The second case is to be connected with the RS232C port 118. The third case is to be connected with the Centronics I/F port 120. The host computer determines its destination depending on which interface I/F connected to printers is used for printing.
Whenever the data of each band width in the band memory 103 is transferred the band clear controller 105 clears the memory. After that, the PDL expansion is again performed, with making the band width uniform, so that the data is transferred to an interface circuit designated by a printer and output at the printer under a control of an interface circuit (control board) by the device driver 86. The above procedures are repeated.
When a video image data is desired to be input from a scanner, the system receives from the host computer a designated information to activate the scanner and starts a video image input. There are two cases in using an interface I/F of a scanner device, one of which is to be connected through an I/F board constructed on the VME bus 122 and the other of which is to be connected with the RS232C port 118.
The above designation will be made by the host computer.
The video image data of each band width delivered from the scanner is stored in the band memory 103. In case that the video image data from the scanner is transferred to the designated host computer, the following two processings will be made depending on the scanner control program 85.
The first processing is to form a real video image data supplemented with a tag recording a video image information, and the second processing is to form a compressed video image data.
In case of the first processing, there are two methods; one of which is to transfer the data in the band memory 103 to a designated host computer consecutively through the network; the other of which to store the data temporarily in a hard disk connected with the SCSI port 112.
Either of both methods is chosen by the designated information from the host computer.
When a tag recording a video image information is supplemented, the data is transferred together with the tag.
In case of the second processing, the data in the band memory 103 is delivered to the ADCT compression circuit 115 so as to be compressed and the compressed data is written in the FIFO memory 116. Whenever the data is read out from the FIFO memory 116, it is transferred to the host computer and the next band data is processed repeatedly to obtain a compressed video image data. In case of using a hard disk, almost the same procedure, except temporarily storing the data in the hard disk, will be conducted.
Hereinafter, referring to a circuit block diagram shown in FIG. 9, a detailed structure will be explained of the first SP interface circuit 4-1 shown in FIG. 1.
FIG. 9 is a block diagram illustrating an internal structure of the first SP interface circuit 4-1 shown in FIG. 1. Identical elements shown in FIG. 1 bear the same reference numerals.
In the drawing, a CPU 1000 controls each device connected to an internal bus 1001 of the board circuit in response to the above mentioned various control programs stored in a ROM 1002. A RAM 10003 functions as, for example, a work memory of the CPU 1000. A network controller 1004 controls an access to a station connected to the LAN 96.
A band memory 1005 stores data of each band width. A standard COMP/EXP 1006 compresses and expands a video image data. A SCSI controller 1007 is connected with a hard disk 1008.
A CPU 211 which generally controls the first SP interface circuit 4-1 control each device connected to the board internal bus in response to control programs (supplemental programs for the device driver 86) stored in the ROM 212, makes initial setting of the necessary portions of the device and transacts commands with scanners and printers. A RAM 213 functions as, for example, a work memory of the CPU 211. A DPRAM 214 which transacts commands between the first SP interface circuit 4-1 and the board circuit is constructed such that both the CPU 211 and the CPU 1000 in the board circuit are mutually and independently accessed with each other through the VME bus 16.
Buffer memories 215, 216 are provided to avoid collision between the CPU 211 and the CPU 100d.
A real time COMP/EXP 218 is provided to compress and expand a multi-value video image data in real time.
Real time means to proceed with the same speed, for example, approximately 15 MHz (32 bits) with which a video image data is transacted, i.e., inputted through the video interface 220.
A COMP memory 17 stores data compressed by the real time COMP/EXP 218. A line buffer 219 is provided to preserve eight line data of a raster direction. The line buffer 219 can be randomly accessed by the real time COMP/EXP 218 applying with
8.times.8 matrix correspondingly to ADCT compression.
A DMA controller 217 transfers data between the COMP memory 17 and the real time COMP/EXP 218 without passing through the CPU 211.
A video interface 220a is provided to have an interface with a scanner 94A and a printer 94B. A reference numeral 220b denotes a control interface.
The first to the fourth mode procedures in response to the designated information from the host computer will be hereunder described in reference to FIG. 9.
Each mode procedure is performed by executing the control program 85 for image input device stored in the ROM 1002 and the device driver 86 stored in the ROM 212.
[The first mode procedure]
In the first mode procedure (video image print mode procedure) a real video image data stored in the band memory 1005 of the main CPU circuit 1 is received through the VME bus, compressed by the real time COMP/EXP 218, and stored temporarily in the COMP memory 17 as a form of compressed video image. This operation is performed with one page. When one page (one picture) is compressed, the printer 94B is actuated. The DMA controller 217 reads out the compressed video image data temporarily stored in the COMP memory 17 as a compressed video image and delivers it to the real time COMP/EXP 218. On this moment, it is restored into an unprocessed image data by the expansion circuit. The expanded unprocessed image data is consecutively transferred from the video interface 220 to the printer 94B. The video image expansion is performed in an ultra high speed synchronized with a data processing speed of the printer 94B.
In some cases, data is transferred to the printer 94B after the video image processing to perform the printer processing.
[The second mode procedure]
In the second mode procedure (video image scan mode procedure), a video image data received from the scanner 94A through the video interface 220a is compressed by the real time COMP/EXP 218 in an ultra high speed synchronized with its speed and the output compressed video image data is temporarily stored in the COMP memory 17. After the scan of one picture is completed, the CPU 1000 of the board circuit has the compressed video image data stored in the COMP memory 17 expanded again by using the expansion circuit of the real time COMP/EXP 218 to achieve the real video image data. The real video image data is transferred to the board circuit through the VME bus 16.
The board circuit transfers the real imge data as it is to a designated host computer if the host computer is requesting it, and transfers the compressed video image data, which is achieved by compressing the real video image data, to the host computer if it is requested by the host computer.
[The third mode procedure]
In the third mode procedure (standard compressed video image print mode procedure), when the board circuit receives the compressed video image data from the host computer in the network, it transfers the compressed video image data as it is to a designated first SP interface circuit 4-1 without expanding. The first SP interface circuit 4-1 stores the compressed video image data in the COMP memory 17, activates the designated printer 94B, and expands the compressed video image data in synchronization with a printing speed of the printer 94B by using the real time COMP/EXP 218 in order to be printed.
[The fourth mode procedure]
In the fourth mode procedure (standard compressed video image scan mode procedure), a real video image data is compressed by the real time COMP/EXP 218 in an ultra high speed synchronized with a scanning speed of the scanner 94A and stored temporarily In the COMP memory 17. After the scan of one picture is completed, the CPU 1000 of the board circuit retrieves the compressed video image data as it is through the VME bus 16.
In the first and second mode procedures, since the first SP interface circuit 4-1 is interfaced with a real video image data, the standard compression/expression procedure which is necessary for video image communication is not always needed in the first SP interface circuit 4-1 so that an independent compression/expansion procedure can be employed in accordance with a high speed demand or the other purposes.
In the second and fourth mode procedures, although the data read from the scanner 94A is directly compressed, it is not restricted for the real time COMP/EXP 218 to compress the data achieved by applying video image processing such as a line density conversion, a color space conversion, etc. to the data read from the scanner.
The video image processing means may be disposed between the video image COMP/EXP and the scanner 94A/printer 94B. The video image COMP/EXP may also be disposed in the scanner 94A/printer 94B.
The structure and the function of the real time COMP/EXP 218 will be explained hereunder referring to a block diagram shown in FIG. 10.
FIG. 10 is a block diagram illustrating a detailed construction of the real time COMP/EXP 218 shown in FIG. 9. An ADCT method is, in particular, employed as a compression/expansion method in the embodiment.
In a data compression, a real video image data is firstly stored in an external line buffer 219 and transferred to a color space converter 221 in which RGB data is converted into a color space data having Y, Cr, Cb data. In some cases, Cr, Cb data is sub-sampled as color difference components to discard the redundancy of the video image. Each of 8.times.8 picture elements is converted on a frequency space by a DCT computer 222. Then, as shown in FIG. 11, a DCT coefficient is scanned by a zigzag scanner 223 and quantized by a quantizer 224.
On this moment, a quantization coefficient which corresponds to 8.times.8 DCT coefficient has been stored in a quantization table 225. The compressed video image data, which is made by codifying data temporarily stored in an internal FIFO memory
226 in a predeterming timing referring to a Huffman table 228 by a Huffman encoder 227, is stored in a CODEC register 229 which can be accessed by an external host computer.
The color space converter 221, the DCT computer 222, the zigzag scanner 223, the quantizer 224 and the quantization table 225 constitute a pipe line operational block operable at a high speed in synchronization with a timing clock. The Huffman encoder 227, the Huffman table 228 and the CODEC register 229 constitute a non-synchronous operational block operable at a not high but compatible speed with those of CPU and DMA in synchronization with a speed at which the external CPU accessed the CODEC register 229. The pipe line operational block is constructed in such a manner to be able to operate at a high speed so that it can follow a video image transfer clock of the scanner 94A/printer 94B.
Accordingly, the internal FIFO memory 226 serves an operational speed buffer between the synchronous pipe line operational block and the non-synchronous operational block.
If the compression ratio is reduced to improve the image quality, compressed data will increase, the amount of data to be processed by the nonsynchronous operating part will increase and the operating speed of the nonsynchronous operating part will be insufficient for processing. However, in processed image data interface of the color space connecter 221 can be connected to the portions other than the scanner 94A and the printer 94B and a nonsynchronous access from the CPU or the like can be received by a FIFO memory which is externally provided. In this case, the pipeline operating part can be operated at a low speed or temporarily stopped. Therefore, there will be no problem in the operating speed of the nonsynchronous operating part.
In this embodiment, a plurality of image compression/expansion parts (for example, two parts) are provided to divide unprocessed image data into a plurality of data blocks and supply these data blocks to the image compression/expansion parts, respectively, thus enabling connection to the scanner and the printer which operate at high speeds. As in compression of a plurality of image data divided as described above, the problem of the operating speed can be similarly solved.
Operation for expansion is basically a reverse process to compression and, when compressed image data is transferred to the CODEC register, the image data is reversely Huffman-coded or decoded in the Huffman encoding part 227 while referring to the Huffman table 228. The values obtained are inversely quantized in the quantizer 224 after having been speed-controlled in the FIFO memory 226. Inverse quantization is carried out by multiplying the values by a quantizing coefficient 8.times.8 of the quantizing table 225. Image data is zigzag-scanned by the zigzag scanner 223 and transferred DCT coefficient to the DCT computer 222. Then the image data is returned from Y, Cr, Cb and the like which are compressed color spaces to original RGB space or the like in the color space converter 221.
The DCT computer 222 processes DCT computation and inverse DCT computation in the same circuit only by changing parameters. Also in the color space converter 221, linear transformation can be similarly carried out by converting parameters.
In addition, the quantizer 224 carries out division for quantization and multiplication for reverse quantization. In this case, division is a kind of multiplication if the quantizing coefficient for division serves as a reciprocal and therefore compression and expansion can be done in the same circuit. The following describes in detail the operations of respective modes of the first SP interface circuit 4-1 as an example while referring to FIGS. 12 to 15.
FIG. 12 is a block diagram illustrating an outline of the partial configuration of the first SP interface circuit 4-1.
In FIG. 12, 1100 is an image processing controller which comprises a VME bus interface, image compression/expansion part and a CPU circuit. The details are shown later in FIGS. 13A and 13B. 1200 is a connection memory controller whose details are shown later in FIG. 14. 1300 is an image I/O controller which controls I/O operation to/from the scanner, the color laser copier (CLC) provided with a printer, scanner and the thermal jet color copier (BJC) with a printer. The details are shown later in FIG. 15.
FIGS. 13A to 15 are respectively a block circuit diagram illustrating the detailed interval configuration of the first SP interface circuit 4-1 shown in FIG. 1 and the same components as in FIG. 1 are given the same reference numbers.
In processing of the right-side data frame of a two-divided image from the CPU 1000 of the board circuit shown in FIG. 9, image data is written from the VME interface 301 into the FIFO memory 302 through the buffer 303. Image data is temporarily stored from the FIFO memory 302 into the RAM 305 through the buffer 304. The SRAM 305 operates synchronized with the pipe line part of the image compression/expansion part. When the data as much as 8 lines in the vertical direction of the image are stored in the RAM 305, the image compression/expansion part 306 reads every horizontal and vertical 8.times.8 units from the SRAM 305 and the compressed data obtained are sequentially written into the DRAM 308 through the DMA controller 307. At this time, the DMA controller 307 operates the address counter 309 to generate an address or counts up the address to give it to the DRAM 308 through the selector 310. In the third mode, the CPU 1000 of the board circuit issues the address through the VME interface 301 and the selector 310 and up dates the data in conjunction with the DRAM 308 through the interface converter 312. Accordingly, the compressed data can be directly sent to the DRAM 308 and standard compressed data for which the image is not divided into two portions can be processed. However, such processing is unsuitable for those data of a low compression ratio.
The DRAM 308 is always refreshed by the refresh circuit 313 and the data is maintained. The following describes the operation for outputting the data of the DRAM 308 to the printer 94B. When data is read out from the DRAM 308 to the compression/expansion part 306 in the same control as in the write operation by the DMA controller 307, unprocessed data from the buffer 304 and output data from the FIFO memory are supplied to the latch 315 since one of right and left frames of the image is s elected by the selector.
Next, the image data is gamma-converted or LOG-converted by the gamma converter. Then, masking for CG is carried out by the masking circuit 316 and masking for a natural image is carried out by the masking circuit 317, and one of these masked images is selected by the selector 321 in accordance with the nature of the image. Finally, the image is converted by the output gamma controller 322 and outputted to the printer 94B through the line driver. In this case, the output gamma controller
322 is controlled by the gamma setting register 323. The masking circuit 316 comprises a ROM and the masking circuit 317 is a logic circuit to which a black table for generating the black color is connected and a timing controller 320 is connected to its periphery so that a value of the initial data ROM 319 may be initially loaded. If the printer 94B is for the plane sequential system, expansion is carried out as many times as the number of planes and the masking circuits 316 and 317 perform masking in response to the output color.
The above describes the processing flow for the right side frame of a frame which is divided into two parts and the same processing flow is carried out for the left-side frame. In other words, 8-line image data stored in the SRAM 328 through the buffer 325, FIFO memory 302 and the buffer 327 is compressed in the image expansion part 329 and controlled by the DMA controller 331, address controller 335 and selector 334 and written as compressed data in the DRAM 332. As a matter of course, the CPU
1000 of the board circuit can directly write compressed data through the VME interface 311 to the selector 334 and the interface converter 330. A refresh circuit 333 refreshes and maintains the data of the DRAM 332. In printing an image, the data read out from the DRAM 332 is controlled by the control 331 of the DMA controller 331, expanded by the image compression/expansion part 339, supplied to the selector 314 through the SRAM 328, buffer 327 and FIFO memory 326 and outputted after having been processed as described above. The processing of mode 1 is carried out as described above.
The following describes the processing of the second mode below.
Image data which are transmitted from the scanner 94A after various image processings are received by the line receiver, and the right-side frame of the image is stored through the buffer 341 and the left-side frame, through the buffer 342 into FIFO memories 303 and 326 in sequence. Subsequent operations are the same as in the first mode. In other words, the processing of the right-side frame is such that, of image data written into the FIFO memory 302, those image data as much as eight lines are read out and stored in the SRAM 305 through the buffer 304, then compressed data is generated in the DRAM 308 by the compression/expansion part 306.
On the other hand, in the fourth mode, the CPU 1000 of the board circuit is able to directly read compressed image data through the VME interface 311, interface converter 312 and selector 310. In the second mode, however, compressed data of the DRAM 308 is expanded and transferred to the CPU 1000 of the board circuit. Compressed image data from the DRAM 308, which have been controlled through the interface converter 312 DMA controller 307, address counter 309 and selector 310 and read out in the sequence of write, are expanded in the image compression, expansion part 306, written into the SRAM 305 in terms of 8.times.8 unit, continuously read out in the horizontal direction through the buffer 304 at a timing when all data for eight lines are written and stored in the FIFO memory 302. Image data of the FIFO memory 302 is read out as unprocessed image data to the CPU 1000 of the board circuit through the buffer 303 and the VME interface 301 in accordance with the timing of the CPU 1000 of the board circuit.
The selector 321 is controlled to select one of two masking circuits 316 and 317 according to the data which is obtained by generating the addresses of positions of pixels to be processed by a horizontal direction counter 352 and a vertical direction counter 353 in response to the attribute of the image as to the CG image or the natural image which is stored in the RAM 351, stored in the RAM 351 through the selector 355 and read out for such selection. Therefore, the attribute of the image is stored in advance on the RAM 351. The interface between the scanner 94A and the printer 94B is controlled by the S/P timing controller 356.
The following describes the changeover of the right and left-side frames of the image.
A vertical direction counter 363 is for transmitting effective image signals of an effective portion of an image in the vertical direction and a delay register 364 is for setting a margin portion of the top end of the image. A length register
361 is used to set an effective length of the image and sends effective image signals to respective corresponding portions if the length of the image is within the effective length in a comparator 362. A delay register 366 is for setting a margin length in the horizontal direction in addition to the effective image range in the vertical direction is connected to generate an effective signal after the left end of the image is counted. The counter controller 367 starts a horizontal left width counter 368
when the above effective signal is received. This horizontal left width counter 368 functions as a down counter to count the width of the image and generates an enable signal of the left-side image during counting. When the counting of the left-side image is finished, the counter 368 generates an enable signal to the counter controller 372, which counts the width of the right-side image at its width counter 373 and gives the information of completion to the controller 389. The controller 389
informs the selector 314 of the end of the effective image width and clears the output. The width counter 368 causes the light pulse generator 369 to generate the signal of the effective width of the left-side image in compression, writes the scanner data of the left-side image in the FIFO memory 326 through the multiplexer 371, and supplies the read pulse of the compression/expansion part 329 through the gate 381 and the multiplexer 371.
For expansion of image data, the read pulse generator 370 receives the effective signal of the left-side image from the width counter 368 and outputs from the FIFO memory 326 to the printer 94B through the multiplexer 371.
On the other hand, a write pulse of the image compression/expansion part 329 is supplied to the multiplexer 371 through the write pulse gate 381 and expanded data is written.
For the right-side image, of course, the write pulse generator 374, read pulse generator 375, multiplexer 376 and gate 382 similarly operate as described above. In the image compression/expansion part 329, the status of the interval FIFO memory
302 is given to a start/stop logic 386 and the status of a register 385 for detecting the peripheral status is given to the start/stop logic 386. In addition, the status of the external FIFO memory 326 is given to the start/stop logic 386 through the FIFO memory controller 383 to enable to control the internal FIFO memory 302 and the external FIFO memory 326 so that an overflow or underflow does not occur therefrom and stop or start the pipe line 329 of the image compression/expansion in accordance with the situation.
Similarly, the pipeline of the compression/expansion part 306 is controlled to start or stop by the status register 387, start/stop logic 386 and FIFO controller 384. In start/stop operations, the internal FIFO memory 302 may overflow due to excessively high transmission rate of the pipeline at the time of compression, the internal FIFO memory 302 may underflow due to excessively high transmission rate of the pipeline at the time of expansion, the external FIFO memory 326 may underflow due to excessively high processing speed of the image compression/expansion part at the time of compression, and the external FIFO memory 326 may overflow due to excessively high processing speed of the image compression/expansion part at the time of expansion.
Since the external FIFO memory 326 and the internal FIFO memory 302 overflow or underflow when the processing speed of the image compression expansion part 306 delays due to excessively high operating speed of the scanner 94A and the printer 94B, the counter error controller 399 temporarily stops video signals (video=image) at the scanner 94A and the printer 94B. Simple error processing is carried out so that video signals in the unit of one line are abandoned from the scanner 94A and margin data in the unit of one line is outputted from the printer 94B to prevent of the flow of video signals from destruction due to the overflow or underflow from the FIFO memory. Accordingly, when the counter error controller transfers error information to the controller 388, the controller 389 checks a margin of one line and effective parts of left-side image and right-side image and outputs an error cancel signal at the delimitation of one line, while the controller 389 indicates other related parts to clear input/output data of the scanner 94A and the printer 94B and enables the image compression/expansion part 306 to carry out compression or expansion up to the delimiting point of one horizontal line despite that the image compression/expansion part
306 operates behind the processing of the scanner 94A and the printer 94B during processing of the error. This permits error resetting again at the delimitation of one line. However, for compression, the white line is compressed during error processing to accelerate the compression speed and, for expansion, image data is abandoned because it cannot be sent in time to the printer 94B.
Though the above description states that the CPU 1000 of the board circuit carries out almost all controls, the first SP interface circuit 4-1 according to this embodiment is provided with an internal CPU 392 which is capable of sharing the processing which can be handled in the first SP interface circuit 4-1. The first SP interface circuit 4-1 is also provided with a dual-part RAM 393 both parts of which are connected to the CPU 1000 of the board circuit through the XEM bus interface 311
and the internal CPU 392 through the internal CPU bus. Information is thus communicated to the CPU 1000 of the board circuit and the internal CPU 392 through this dual-port RAM 393.
Therefore the accesses from these CPU 1000 and CPU 392 to the VME bus in the first SP interface circuit 4-1 will not come in collision. In this case, the image compression/expansion parts 306 and 329 are interfaced by a bus convertor 394
connected to the internal bus of the CPU 392. The bus converter 394 has the same functions as the interface converters 312 and 330 to interface with the registers in the board through a register interface 395 and has also the function as the interface for the VEM bus.
In addition, the internal CPU bus has a ROM 391 for storing the programs of the CPU 392 and a serial communication part 390. A command for controlling the operation in conjunction with the scanner 94A and the printer 94B is sent to the serial communication part 390. Accordingly this embodiment is adapted so that the CPU 1000 of the board circuit shown in FIG. 9 controls the scanner 94A and the printer 94B through the internal CPU 392 shown in FIGS. 13A and 13B or directly controls the scanner 94A and the printer 94B. Control commands for the CPU 1000 include an activation command for the scanner 94A and the printer 94B as well as a status detection command and a status setting command as execution commands. The status detection commands are intended to detect the presence of print sheet, presence and size of the cassette, remaining amount of toner, and jamming of print sheet as well as current operation mode, that is, distinction of monochrome, three colors or four colors, resolution, and other parameters for image processing as to the printer 94B. These commands are almost identical to the scanner 94A, enabling to know the presence of the original on the original rest plate and wire break of a lamp.
On the other hand, the status setting command are intended to set the parameters for the image processing system such as selection of a cassette size, selection of an upper or lower stage of the cassette, operation mode, the number of print sheets and so on.
For the scanner 94A, the status setting commands similarly cover, for example, setting of the variation and magnification, setting of binary 1 multi-valued system, standard color space conversion, specific color space conversion, precision (resolution conversion), setting of area designation, and setting of gamma conversion.
In this embodiment, the scanner 94A has many image processing functions and therefore the image data is not processed on the first SP interface circuit 4-1 and is compressed. In addition, RGB data is received from the scanner 94A.
On the other hand, the input to the printer 94B is CMYK input, and masking, gamma conversion, LOG conversion and CMYK generation are processed on the first SP interface circuit 4-1 since the printer section is not provided with so many functions for image processing.
FIG. 16 is a block diagram illustrating a detailed configuration of the second SP interface circuit 4-2 shown in FIG. 1 and this second SP interface circuit 4-2 interfaces a thermal jet type scanner printer 95 (printer 95B and scanner 95A) and an S/P server unit SPI. The second SP interface circuit 4-2 is formed as an integrated interface board.
In FIG. 16, a CPU 401 receives a command from the board circuit connected to the VEM bus through the dual port RAM 403, interprets the command and internally controls the second SP interface circuit 4-2. The CPU 401 generates an interrupt of every 2 m seconds from the built-in interval timer and communicates a command to the thermal jet type printer 95B and the scanner 95A. The CPU 401 initializes and changes various parameters for image processing circuits 404, 405 and 406.
A ROM 402 for programming stores a control program (a program which supplements the device driver 86) to be executed by the CPU 401 and the initial values and the preset values of image processing circuits 404, 405 and 406.
A dual port RAM 403 functions as a work area for the CPU 401 and accesses to both the CPU 1000 of the board circuit and the CPU 401 to execute communications between these CPUS.
The image processing circuit 404 is formed as an image processing ASIC to carry out graduation conversion according to the lookup table. For example, the image processing part 404 performs LOG conversion when converting RGB data to CMYK DATA. This can be implemented by providing in advance a conversion table in the ROM 402 and transferring it to the RAM in the image processing circuit 404.
The image processing circuit 405 is formed as an image processing ASIC and carries out graduation conversion according to 4.times.5 matrix operation and a lookup table. This circuit 405 carries out NTSC-RGB color space conversion as the RGB spaces and the standard color space of the characteristics of the sensor of the scanner 95A, or conversion (referred to as masking) from CMY(K) after conversion by the image processing circuit 404 to CMYK adjusted to the characteristics of the printer
95B through this matrix operation. In addition, color balance can be adjusted by the lookup table. These processings are set by preparing various tables, storing these tables in the ROM and selecting the tables in accordance with the application as in the case of the image processing circuit 404.
The image processing circuit 406 is formed as an image processing ASIC to carry out a binary-coding processing. The binary coding algorithm used in this embodiment is an average density preserving method. A serial/parallel converter 407
converts 8-bit parallel data from the CPU 401 to serial data for communications to the scanner 95A and the printer 95B.
A DRAM 408 for images is an image memory adapted to the type of band adjusted to the number of pixels of the head of the printer 95. In the scanner 95A or the printer 95B, data flows according to the clock signals for images during one scanning and the operation cannot be stopped and therefore a buffering for the size of one band is requires. Therefore, the image data as much as are band to be scanned by the scanner 95A and printed by the printer 95B are buffered.
A scanning system is converted between a raster type access from the VME bus side and a vertical access from the printer 95B.
An address selector 409 for the DRAM which serves as a multiplexer changes over the address for the access from the VEM bus to the DRAM 408 and the access from the scanner 95A and the printer 95B to the DRAM 408. The address to the DRAM 408 is supplied as being divided to a ROW address and a COLUMN address and the. DRAM 408 carries out this multiplexing.
A timing controller 410 for the DRAM generates the signals for controlling DRAM such as RAS, CAS, WE and OE and carries out arbitration with refresh signals.
A timing circuit 411 generates a timing signal for accessing of the scanner 95A and the printer 95B. This circuit serves to generate the access timing based on a image clock and a sync signal from the scanner 95A and the printer 95B.
A refresh timing controller 412 generates a timing signal for a refresh signal to the DRAM 408. This controller utilizes an interval between the accesses by the scanner 95A and the printer 95B and controls to avoid collision of accesses of the scanner 95A and the printer 95B.
A VME timing controller 413 processes the control signals for accessing from the VME bus, including decoding of AM codes and high order addresses and interrupts.
An access address generator 414 for the scanner 95A and the printer 95B generates an address for specific access for the scanner 95A and the printer 95B to the memory contents written in the raster system for accessing from the VME bus since the accesses of the scanner 95A and the printer 95B differ from an ordinary raster system. The scanning direction is reversed in accordance with the size of band.
A VME bus interface buffer 415 accesses image data in a 32-bit width and commands in a 8-bit width.
A VME bus interface address buffer 416 accesses image data in a 24-bit address space and commands in a 16-bit address space.
A buffer 417 serves as a buffer for the parts other than the data and addresses of the VME bus interface.
A buffer 418 for an entry port to the image processing part carries out accessing from the VME bus and accessing to the DRAM in a 32-bit width. In the image processing part, processing is carried out in a 8-bit width. Therefore, 32-bit R, G, B and X data is serially converted to 8-bit data in order.
A buffer 419 for an exit of the image processing part, contrary to the buffer 418, carries out conversion of the data line of 8-bit width which varies in the sequence of colors to 32-bit wide data of four colors totally.
A buffer 420 for use after binary coding processing functions to expand one-bit data which is binary-coded by the image processing circuit 406 to 8-bit data, that is "0" to "0.times.00" and "1" to "0.times.FF".
A buffer 421 is used for bypassing binary coding processing by the image processing circuit 406, and one of outputs of the buffer 420 and the buffer 421 is selected to change over binary-coded data to multi-valued data.
A buffer 422 of the communications part is for interfacing the scanner 95A and the printer 95B.
A buffer 423 for input data is for interfacing the scanner 95A and the printer 95B.
A buffer 424 for output data is for interfacing the scanner 95A and the printer 95B.
An input buffer 425 for clock and control signals is for interfacing the scanner 95A and the printer 95B.
An output buffer 426 for clock and control signals is for interfacing the scanner 95A and the printer 95B. 429 is a clock input line.
430 is a 32-bit image data bus, 431 is a 24-bit address bus, 432 is a 8-bit image data bus, 433 is a 8-bit image data bus, 434 is a 16-bit local address bus, and 435 is a 8-bit local data bus. The following describes the operation of the printer
95B.
[Operation for Printing]
When various parameters for printing are written into the dual-port RAM 403 from the board circuit through the VME bus, the CPU 401 reads out the data and interprets and control it. For example, for printing RGB data, the CPU 401 sets a table with a through-operating characteristic which does not cause LUT data of the image processing circuit 404 to change, sets the coefficients for conversion from NTSC-RGB to 13J-RGB in the coefficient table for the matrix of the image processing circuit
405, and controls the gates of buffers 420 and 421 so as to pass through the binary coding processing of the image processing circuit 406.
In addition, parameters for data sizes are set. Parameters such as data sizes are sent to the printer 95B through the parallel/serial converter 407. Then, image data as much as one band is transferred from the board circuit to the memory 408
through the VME bus. At this time, image data from the VME bus is stored in the RGBX data format by 32-bit accessing. R, G and B are respectively image data for color components of red, green and blue, and X is control data including information of block characters. Next, a command for printing operation is transferred through the dual-port RAM 403. The CPU 401 transmits a start command for printing operation. When the start signal returns from the printer controller of the printer 95B, a timing pulse generator 411 starts accessing to the memory 408. In this case, the data is read out in a direction along the BJ head of the printer 95B and therefore the data is read out according to an address generated by the address generator 414. Data read out from the memory 408 is converted to 8-bit data in the order of R, G, B and X in the buffer 418 and entered into the image processing part. The image is processed in accordance with the predetermined parameters, and NTSC-RGB data is converted to RGB color spaces to be internally used in the printer 95B and transferred to the printer 95B through the buffer 421 and the interface 424. When the processing of one-band data is finished, next band data is received through the VME bus and the above described operation is repeated. Processing of one page data is completed after the predetermined number of times of processing. The following describes reading operation of the original by the scanner 95A according to a control program stored in the ROM 402.
[Operation in Scanning]
Various parameters for scanning operation are written from the board circuit into the dual-port RAM 403 through the VME bus. The read and interprets the data and carries out the control. For example, when binary-coded RGB data is scanned in the size of 1024.times.1024 at the position of 512.times.512, the CPU 401 sets a table with a through-operating characteristic in the LUT of the image processing circuit 404 and the coefficients for conversion from BJ-RGB to NTSC-RGB in the matrix coefficient table of the image processing circuit 406 and controls the gates of buffers 420 and 421 so as to pass through binary coding processing of the image processing circuit 406. In addition, a size of the image to be scanned is set to
1024.times.1024 and the scan start position is set to 512.times.512. These parameters are transferred to the scanner 95A through the parallel/serial converter 407. Then the CPU 401 transmits a scan start command to the scanner 95A. Image data entered from the reader part of the scanner 95A is entered into image processing circuits 404, 405 and 406 through the interface 423. Here image processing is carried out according to the predetermined parameters and 32-bit format RGBX data is stored in the memory 408 through the buffer 419. At this time, the memory 408 stores RGBX data as described above. In this example, the scanner 95A is set to scan binary-coded RGB image data and therefore X is meaning less data. Though R, G and B color components are binary-coded data. One byte is assigned to one pixel. In this case, the board circuit carrier out a processing for which data is processed in a common format requested for binary-coded image data, for example, by packing bytes to arrange RGB data in the order of raster lines. Image data stored in the memory 408 is transferred to the board circuit through the VME bus interface 415. One scanning operation is completed by repeating the above processing as many times as the number of bands.
The following describes image data processing by the scanner 94A and the printer 95B shown in FIG. 1.
In this embodiment, the color image copier is formed integral with the scanner 94A and the printer 94B and therefore only one system for image processing function is provided. If the scanner 94A and the printer 94B are separated, the system configuration includes only one of them for each processing. In addition, the scanner is provided with almost all image processing functions, and the printer 94B mainly has those functions such as variation of magnification, designation of area, color space conversion, gamma conversion, and color masking processing.
Since the scanner 94A is provided with the color space converter and the color masking processor, standard RGB (RGB for NTSC, etc.) is prepared as the mouth of the video interface and RGB data can be obtained in point sequential or parallel simultaneous scanning. Accordingly, the image data should be given as C, M, Y and K data to the printer 94B because the printer is not provided with the image processing part. Image data should be transmitted to the video interface after such image processing as conversion to C, M and Y, black color generation (K), color masking, resolution conversion and trimming have been externally finished as required. Moreover, in this case, image data should be transmitted by repeating the processing four times for C, M, Y and K colors in plane sequential scanning. In addition, both the scanner 94A and the printer 94B cannot be stopped during processing.
On the other hand, the video interface includes the horizontal sync signal, vertical sync signal and video clock signal for synchronization with video data. Moreover, status information such as ON/OFF of the power supply for the scanner and the printer are provided to enable to externally check the status. A function for command interface in serial communications is provided to permit detection and setting of the status of the scanner 94A and the printer 94B and generation of execution commands such as for activating the scanner and the printer.
The following further describes the operation of the scanner 95A and the printer 95B, referring to FIGS. 17 and 18.
FIG. 17 is a typical diagram illustrating the image recording process of the scanner/printer 95 shown in FIGS. 2A and 2B.
In FIG. 17, 101R denotes an original to be scanned and 102R denotes a print sheet for printing. These original and the print sheet are of the A4 size. 103R denotes the sensor head of the scanner and 104R denotes the print head of the printer. The print head 104R of the printer is provided with an array of nozzles from which ink is injected by the bubble jet system and comprises, for example, nozzles 108.
On the other hand, the sensor can output data of, for example, 144 pixels so that more pixels than 128 can be scanned. For colors, the sensor head of the scanner has the scanning segments for three colors R, G and B and the printer head has the printing segments for four colors C, M, Y and K. 105R denotes the image processing part which processes RGB signals entered from the scanner sensor and transmits them as binary-coded CMYK signals with the characteristics adapted to the printer head.
The image processing part 105R can transfer 8-bit RGB color data from the interface 106R on the way of the image processing system to external sources. In the scanner/printer 95, the sensor of the scanner 95A and the printer head of the printer
95B operates in synchronization, and the image processing part 105R has a pipeline arrangement to make it possible to carry out processing without requiring a large capacity image memory. Therefore, the scanning method for data to be transferred through the interface 105R is of a specific type. 107R denotes external equipment.
FIGS. 18A to 18C are typical diagrams illustrating the scanning status of the original by the scanner 95A of the scanner/printer 95 shown in FIGS. 2A and 2B.
In FIGS. 18A to 18C, 201R shows a motion of the sensor head of the scanner. The sensor head itself moves in a transversal direction main scanning direction) as shown for the original (print sheet) and the pixel segments of the sensor are arranged at right angles to this direction. Therefore data 203R is aligned to 201R. On the other hand, data is aligned as data 204R in general raster scanning systems.
FIG. 19 is a typical diagram illustrating the status of scanning of a band original by the scanner 95A of the scanner/printer 95 shown in FIGS. 2A and 2B.
In FIG. 19, 301R denotes one page, 302R denotes the first segment and the 303R denotes the second segment. In the case of the image data which is outputted from the scanner sensor and will be binary-coded through the image processing system, the segment 304R scans a larger image than for the segment 305R and the image as far as 306R is doubly scanned.
The following describes an example of the printer capable of using the Centronics interface software which can be controlled by the S/P server unit shown in this embodiment. The Centronics interface is the standard software for transfer of data from a computer to a printer developed by Centronics, Inc. in the United States, permitting inexpensive and high speed data transfer. Almost all printers are standardized according to this Centronics system.
Data transfer according to the Centronics software is carried out through three control lines for DATASTROBE signal, ACKNOWLEDGE (ACK) signal and BUSY signal and the DATA line as shown in FIG. 20.
The DATASTROBE signal indicates that data is outputted to the DATA line. The BUSY signal indicates that the printer is currently operating and the data cannot be received or that the data buffer is fully occupied.
The ACK signal indicates that reading of data is correctly completed.
Though the above three control lines are basically sufficient, the signal line for warning NO PRINT SHEET is also defined for proper control of the printer. In FIG. 20, the signal name, input/output and remarks are shown. Since the pin number varies as 36 pins, 25 pins and 14 pins, depending on the types of connectors and the definitions differ with manufacturers or deleted in some cases, the pin numbers are omitted.
FIG. 21 is a block diagram showing an example of the Centronics I/F control circuit.
In FIG. 21, a Centronics I/F control circuit 201 is provided with the data buffer 202A and the control line buffer 203A, and data is processed according to the timing chart shown in FIG. 22.
FIG. 23 is a flow chart showing an example of signal processing procedure between the host computer and the printer by the Centronics I/F control circuit shown in FIG. 21. (1)-(3) denote the steps of the procedure, particularly corresponding to the processing in the host computer.
When the BUSY signal is "L" and the ACK signal is "H" (1), data is set (2), the DATASTROBE signal is outputted (3) and the operation is returned to step (1).
FIG. 24 is a flow chart showing an example of signal processing procedure between the host computer and the printer by the Centronics I/F control circuit shown in FIG. 21. (1)-(6) denote the steps of the procedure, particularly corresp