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United States Patent5805854
ShigeedaSeptember 8, 1998
Title
System and process for memory column address organization in a computer system
Abstract
A method and circuitry for testing a memory to determine its column address organization are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes a controllable multiplexer that selects certain combinations of address bits for use as column address bits to be applied to the memory; the selection of the multiplexer is controlled by the contents of a memory array type register associated with the memory or memory bank. In operation, a first data word is written to memory using a first address, and a second data word is written to memory using a second address that is spaced apart from the first address by a specified increment related to a trial number of column address bits of the memory. If the trial number of column address bits is too large, the second data word will overwrite the first as the column address portions of the first and second addresses will coincide; if the trial number of column address bits is accurate, however, the second data word will write to a different column address, leaving the first data word properly stored. The disclosed microprocessor unit, which may be integrated onto a single integrated circuit chip with the memory controller, also has a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes configuration registers and circuitry for controlling the access thereto, including circuitry for determining memory address type and bank sizes.
Inventors:Shigeeda; Akio (Dallas, TX)
Assignee:Texas Instruments Incorporated (Dallas, TX)
Appl. No.:482057
Filed:June 7, 1995
Current U.S. Class:711/1 711/105 711/212 711/5 714/719 365/201 
Field of Search:395/497.01,497.02,497.03,307,421.02,886,401,405,431,432 365/201 371/21.1,21.2,21.3
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Primary Examiner: Gossage; Glenn
Attorney, Agent or Firm:Burton; Dana L. Kesterson; James C. Donaldson; Richard L.
Parent Case Text


This is a division of application Ser. No. 08/404,702, filed Mar. 15, 1995.
Claims

What is claimed is:
1. A process for testing a memory to determine its column address width, comprising the steps of:
writing a first datum to the memory using a first address, the first address having a column portion comprised of a selected number of bits;
writing a second datum to the memory using a second address, the second address having a column portion comprised of an equal number of bits as the column portion of the first address, the second address spaced from the first address by a selected address difference corresponding to a different most significant bit position of the column portion, and the second datum differing from the first datum;
after the writing steps, reading the contents of the memory using the first address;
responsive to the result of the reading step corresponding to the second datum, adjusting the selected number of bits in the column portion of the first and second addresses, adjusting the selected address difference, and repeating the reading and writing steps; and
responsive to the result of the reading step corresponding to the first datum, identifying the column address width as the selected number of bits in the column portion of the first and second addresses.

2. The process of claim 1, wherein the memory is arranged in a plurality of banks;
and wherein the writing, reading, adjusting and repeating, and identifying steps are repeated for each of the plurality of banks of the memory.

3. The process of claim 1 wherein the step of adjusting the selected address difference comprises reducing the address difference.

4. The process of claim 3 wherein the identifying step comprises storing, in a memory array type storage location, a memory array type code corresponding to the selected number of bits in the column portion of the first and second addresses.

5. The process of claim 4, further comprising incrementing a counter value responsive to the result of the reading step corresponding to the second datum.

6. The process of claim 5 wherein the counter value corresponds to the memory array type code;
and further comprising controlling a column address selector circuit to select the selected number of bits in the column portion of the first and second addresses, for application to the memory, responsive to the memory array type code.

7. A computer, comprising:
an user input interface;
a read/write memory;
an output interface;
program memory; and
a microprocessor unit, coupled to the user input interface, to the read/write memory, to the output interface, and to the program memory, comprising:
a memory controller for controlling read and write operations to the read/write memory; and
a central processing unit core operable, in response to instructions from the program memory, to determine a column address width of the read/write memory by performing a plurality of operations comprising:
writing a first datum to the read/write memory using a first address, the first address having a column portion comprised of a selected number of bits;
writing a second datum to the memory using a second address, the second address having a column portion comprised of an equal number of bits as the column portion of the first address, the second address spaced from the first address by a selected address difference corresponding to a different most significant bit position of the column portion, and the second datum differing from the first datum;
after the writing steps, reading the contents of the memory using the first address;
responsive to the result of the reading step corresponding to the second datum, adjusting the selected number of bits in the column portion of the first and second addresses, adjusting the selected address difference, and repeating the reading and writing steps; and
responsive to the result of the reading step corresponding to the first datum, identifying the column address width as the selected number of bits in the column portion of the first and second addresses.

8. The computer of claim 7, wherein the read/write memory is arranged in a plurality of banks;
and wherein the central processing unit core repeats the writing, reading, adjusting and repeating, and identifying steps for each of the plurality of banks of the read/write memory.

9. The computer of claim 7, wherein the program memory comprises a basic input/output system read-only memory.

10. The computer of claim 7, wherein the user input interface comprises an input connector.

11. The computer of claim 10, further comprising an input device connected to the input connector.

12. The computer of claim 7 wherein the central processing unit core performs the operation of adjusting the selected address difference by reducing the address difference.

13. The computer of claim 12 wherein the microprocessor unit further comprises a memory array type storage location;
and wherein the central processing unit core performs the identifying operation by storing, in a memory array type storage location, a memory array type code corresponding to the selected number of bits in the column portion of the first and second addresses.

14. The computer of claim 13, wherein the microprocessor unit further comprises a counter;
and wherein the plurality of operations further comprises:
incrementing a counter value stored in the counter responsive to the result of the reading step corresponding to the second datum.

15. The computer of claim 14 wherein the counter value corresponds to the memory array type code;
and wherein the memory controller further comprises a column address selector circuit for selecting the selected number of bits in the column portion of the first and second addresses, for application to the read/write memory, responsive to the memory array type code.
Description
NOTICE

(C) Copyright, *M* Texas Instruments Incorporated 1995. A portion of the disclosure of this patent document contains material which is subject to copyright and mask work protection. The copyright and mask work owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark office patent file or records, but otherwise reserves all copyright and mask work rights whatsoever.

CROSS-REFERENCE TO RELATED APPLICATIONS

The following coassigned patent applications, all filed Dec. 22, 1994, except as noted, are hereby incorporated herein by reference:

______________________________________ Serial No. Filing Date TI Case No. ______________________________________ 08/363,198 December 22, 1994 TI-18329 08/363,109 December 22, 1994 TI-18533 08/363,673 December 22, 1994 TI-18536 08/363,098
December 22, 1994 TI-18538 08/362,669 December 22, 1994 TI-18540 08/362,325 December 22, 1994 TI-18541 08/363,543 December 22, 1994 TI-18902 08/363,450 December 22, 1994 TI-19880 08/363,459 December 22, 1994 TI-20173 08/363,449 December 22,
1994 TI-20175 08/362,302 December 22, 1994 TI-20177 08/362,351 December 22, 1994 TI-20178 08/362,288 December 22, 1994 TI-20180 08/362,367 December 22, 1994 TI-20181 08/362,033 December 22, 1994 TI-20182 08/362,701 December 22, 1994 TI-20183 08/363,661 December 22, 1994 TI-20185 08/362,702 December 22, 1994 TI-20186 08/401,105 March 8, 1995 TI-20202 ______________________________________

Other patent applications and patents are incorporated herein by reference by specific statements to that effect elsewhere in this application.

FIELD OF THE INVENTION

This invention generally relates to electronic circuits, computer systems and methods of operating them.

BACKGROUND OF THE INVENTION

Without limiting the scope of the invention, its background is described in connection with computer systems, as an example.

Early computers required large amounts of space, occupying whole rooms. Since then minicomputers and desktop computers entered the marketplace.

Popular desktop computers have included the "Apple" (Motorola 680x0 microprocessor-based) and "IBM-compatible" (Intel or other x86 microprocessor-based) varieties, also known as personal computers (PCs) which have become very popular for office and home use. Also, high-end desk top computers called workstations based on a number of superscalar and other very-high-performance microprocessors such as the SuperSPARC microprocessor have been introduced.

In a further development, a notebook-size or palm-top computer is optionally battery powered for portable user applications. Such notebook and smaller computers challenge the art in demands for conflicting goals of miniaturization, ever higher speed, performance and flexibility, and long life between battery recharges. Also, a desktop enclosure called a docking station has the portable computer fit into the docking station, and improvements in such portable-computer/docking-station systems are desirable. Improvements in circuits, integrated circuit devices, computer systems of all types, and methods to address all the just-mentioned challenges, among others, are desirable, as described herein.

SUMMARY OF THE INVENTION

Generally and in one form of the invention, an electronic device on a single integrated circuit chip has a microprocessor with a processing unit operable to process digital data in accordance with computer instructions, and a first cache coupled to said processing unit. A second cache includes a write-back cache which is at least ten times smaller than the first cache, and coupled to the first cache.

Generally, another form of the invention has a memory controller circuit for generating column addresses from addresses on an address bus. The memory controller circuit includes a selector circuit having inputs for a plurality of lines of the address bus, and an output for column addresses. A control register has bits representing a particular memory array type among a plurality of memory array types. A control circuit couples the bits of the control register to the selector circuit thereby supplying the column addresses from the plurality of lines in accordance with the particular memory array type represented by the bits in the control register.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a pictorial diagram of two notebook computer embodiments, one of them being inserted into a docking station embodiment to provide a combined system embodiment;

FIGS. 2A, 2B, and 2C are, respectively, a right-side profile view, plan view, and rear elevation of the combined system of notebook and docking station of FIG. 1;

FIG. 3 is an electrical block diagram of the FIG. 1 combined embodiment system of improved notebook computer and docking station system to which the notebook computer system connects;

FIG. 4 is an electrical block diagram of another embodiment of an improved computer system for desktop, notebook computer and docking station applications;

FIGS. 5, 6 and 7 are three parts of a more detailed electrical diagram (partially schematic, partially block) of a preferred embodiment electronic computer system for use in embodiments including those of FIGS. 3 and 4, wherein FIG. 5 shows microprocessor unit (MPU) and peripheral control unit (PCU), FIG. 6 shows peripheral processor unit (PPU) and peripherals, and FIG. 7 shows display and other elements;

FIG. 8 is a plan view of a preferred embodiment apparatus having a printed wiring board and electronic components of the computer system of FIGS. 5-7;

FIG. 9 is a block diagram of a microprocessor unit (MPU) device embodiment for the system of FIGS. 5-7;

FIG. 10 is a plan view of an integrated circuit with improved topography for implementing the microprocessor unit of FIG. 9;

FIG. 11 is a block diagram of a peripheral processing unit (PPU) device embodiment for implementing the PPU in the system of FIGS. 5-7;

FIG. 12 is a block diagram of a bus-quieting circuit embodiment;

FIG. 13 is a waveform diagram representing bus-quieting method steps;

FIG. 14 is a partially block, partially schematic diagram of a bus interface embodiment of PPU 110 of FIG. 11 for bus types such as the X-bus (XD) and intelligent drive electronics (IDE) types, improved with bus quieting circuits and methods;

FIG. 15 is a state transition diagram representing an IDE bus control state machine in the embodiment of FIG. 14;

FIG. 16 is a state transition diagram representing an XD bus control state machine in the embodiment of FIG. 14;

FIG. 17 is a partially block, partially schematic diagram of the microprocessor unit MPU 102 of FIGS. 5 and 9, emphasizing a device embodiment with memory controller unit (MCU) and bus bridge for use in system embodiments according to method embodiments as described;

FIG. 18 is a schematic diagram of part of the memory controller unit (MCU) embodiment of FIG. 17;

FIG. 19 is a partially block, partially schematic diagram of a circuitry embodiment part of the bus bridge of FIG. 17;

FIG. 20 is a schematic diagram of a circuitry embodiment part of the MCU of FIG. 17, and FIG. 20 has connections which mate to lines in the bus bridge schematic of FIG. 19;

FIG. 21 is a partially block, partially schematic diagram of address comparison circuitry in the MCU of FIG. 17;

FIG. 22 is a partially block, partially schematic diagram of a DRAM control block embodiment in the MCU of FIG. 17;

FIG. 23 is a partially block, partially schematic diagram of a column and row address selector embodiment in the DRAM control block of FIG. 22 in the MCU of FIG. 17;

FIG. 24 is a method embodiment flow diagram for BIOS software for loading a Memory Array Type (MAT) register, and FIG. 24 mates with flow diagram FIG. 27;

FIG. 25 is a memory column address diagram for illustrating the operations of the method of FIG. 24;

FIG. 26 is a block diagram of a system with the MCU of FIG. 17 connected to a DRAM memory, for illustrating the operations of the method of FIG. 24;

FIG. 27 is a method embodiment flow diagram for BIOS software for loading a Top Memory Address (TMA) register, and FIG. 27 mates with flow diagram FIG. 24;

FIG. 28 is a diagram of memory address space in a particular bank for illustrating an operation of determining a value MEMTOP in the operations of the method of FIG. 27;

FIG. 29 is a diagram of a shifting process for generating a TMA value in the operations of the method of FIG. 27;

FIG. 30 is a diagram of memory address space in a whole set of memory banks for illustrating operations of determining value MEMTOP and TMA values in the operations of the method of FIG. 27;

FIG. 31 is a diagram of an microprocessor device embodiment alternative to that of FIG. 17; and

FIGS. 32-35 are schematic diagrams of a refresh control block in the MCU embodiment of FIG. 17.

Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In FIG. 1 a notebook-computer-and-docking-station system 5 has an insertable or dockable notebook computer 6 shown being inserted along a path of bold arrows into a docking station 7. A CRT (cathode ray tube) display 8, a keyboard 9 and a mouse
10 are respectively connected to mating connectors on a rear panel of docking station 7. Docking station 7 has illustratively four storage access drives, for example: 5.25 inch floppy disk drive 11, 3.5 inch floppy disk drive 12, a CD (compact disc) drive 13 and an additional floppy or CD drive 14.

Docking station 7 has a docking compartment 15 into which notebook computer 6 inserts securely against internal rear electrical connectors. Docking compartment 15 in this embodiment accepts manual insertion of notebook computer 6 along lateral guideways 16 and 17 using a minimum of mechanical elements to achieve advantageous economy in cost of the physical docking. A horizontal surface of guideway brackets or a horizontal panel as shown provide physical support for notebook computer 6. In an alternative embodiment, a motorized insertion mechanism associated with docking compartment 15 holds, rearwardly moves and seats notebook computer 6 against either rear electrical connectors, lateral connectors or both.

Docking station 7 in this embodiment occupies a volume V=LWH equal to the product of the length L, width W and height H of the form of a rectangular solid. Notebook computer 6 also has a form of a rectangular solid with volume v=l w h equal to the product of its own length l, width w, and height h. The docking station 7 in this embodiment advantageously is proportioned so that the width w of the notebook 6 exceeds at least 75% and preferably 85% of the width W of the docking station. In this way, the room left for keyboard 9 and user work space to the front of keyboard 9 is advantageously sufficient to make docking station 7 as convenient to locate as many conventional desktop computers. Drives are stacked in pairs 11, 12 and 13,14
providing extra ergonomically desirable height (user head position level, low glare) for supporting display 8, reduced length L, and efficient use of volume V. The weight distribution of the docking station 7 suits it for location on a desktop as shown, or for tower positioning with docking station 7 resting on its right side-panel. In either position, the drives 11,12 and 13,14 are suitable as shown, or alternatively are mounted with the docking compartment 15 located centrally between drives 11 and
13 on top, and drives 12 and 14 on the bottom.

Notebook computer 6 has slits 18 for advantageous lateral ventilation both in open air, and in a forced air ventilation environment of docking station 7. Notebook computer 6 features front-facing slots of a 3.5 inch floppy disk drive 19 and a card connector 20 (e.g. for flash memory, modem or other insertable cards). These slots are accessible even when the notebook computer 6 is docked.

A display panel 21 combined with a high-impact back panel is hingeably mounted rearward on a high-impact mounting base 22. Looking to the left in FIG. 1 is an identical but distinct notebook computer unit 6'. (For economy of notation, additional numerals on notebook unit 6' are not primed.)

Notebook unit 6' has display panel 21 raised to operating position relative to base 22 in the portable environment. A 3.5 inch floppy diskette 23 and a flash memory card 24 are shown near their respective insertion slits 19 and 20. A keyboard
25 mounts forwardly on base 22. To the rear of keyboard 25, and between keyboard 25 and display panel 21, lie (in order from right to left) a recessed trackball 26 in a recess 27, an ON/OFF switch 28, ventilation slits 29, a loudspeaker 30 beneath a protective grille, further ventilation slits 31, and a SUSPEND/RESUME switch 32.

A physical protuberance or stud 33 is molded integrally with display panel 21 or affixed thereon, near a hinge so that when the display panel 21 is closed against base 22, the stud 33 impinges against SUSPEND/RESUME switch 32 thereby putting the computer 6' in a Suspend mode whereby very little power is consumed. Then when the panel 21 is reopened, the computer resumes almost immediately with the current application program without rebooting. ON/OFF switch 28 has no stud associated with it, so that the user has the manual option to turn the notebook computer on or off and to reboot when desired.

In still further features, notebook computers 6 and 6' have a display brightness (e.g. backlighting) adjustment control 34 mounted low on the right side of panel 21. An optional power supply 35 is powered from a commercial power source to which an AC plug 36 connects. Power supply 35 in turn supplies battery recharge and supply voltages via a rear power connector 37 to notebook computer 6'.

An infrared (IR) emitter/detector assembly 38 on notebook computer 6 provides two-way communication with a corresponding infrared emitter/detector assembly on the back of notebook computer 6'. The two computers 6 and 6' suitably communicate directly to one another when two users are positioned opposite one another or otherwise such that the computers 6 and 6' have the IR assemblies in line-of-sight. When the two computers 6 and 6' are side-by-side, they still advantageously communicate by reflection from an IR-reflective surface 39, such as the wall of a conference room or side-panel of an overhead projector unit.

Docking station 7 has an AC power plug 40 connected to energize the docking station circuitry as well as that of notebook computer 6 when the latter is inserted into docking compartment 15. An AC Power On/Off switch 41 is manually actuated by the user on the upper right front panel of docking station 7 in FIG. 1.

Turning now to FIG. 2A, notebook computer 6 is shown inserted against a power connector 45 of docking station 7 in a right profile view of the assembly. A hard disk drive HDD and a power supply P.S. are visible in the right profile view and in the plan view of FIG. 2. A ventilation fan 46 efficiently, quietly and with low electromagnetic interference, draws a lateral air flow across a Docking PCB (Printed Circuit Board) of the docking station, as well as through the notebook computer 6 having its own printed circuit board. The ventilation flow continues through the ventilation holes of power supply P.S. whereupon heated air is exhausted by fan 46 broadside and outward from the rear panel of docking station 7, as shown in the rear elevation detail of FIG. 2C.

The Docking PCB is supported low to the bottom panel 47 of an enclosure or cabinet of the docking station 7.

As seen from the top in FIG. 2B, the enclosure has a left bay 48 for hard disk drive HDD and power supply P.S., a wider middle bay 49 having mass storage drives 11, 12, 13 and 14, and the docking PCB behind the docking compartment 15, and then a right bay 50 into which a multimedia board 51, a video teleconferencing board 52, and other boards of substantial size readily fit from top to bottom of the enclosure.

For convenience and economy, several connectors 55 are physically mounted and electrically connected to Docking PCB and are physically accessible through a wide aperture in the rear of the enclosure. As shown in rear elevation in FIG. 2C, connectors 55 include a keyboard connector KBD, a mouse connector MS, a display connector VGA, a PRINTER port, a GAME port, a local area network LAN connector, and an RJ-11 telephone jack or modem port. A Multimedia connector and a teleconferencing Camera connector are accessible at the rear of the right bay 50.

Emphasizing now the connector arrangement of the notebook computer 6 in rear elevation, a series of these connectors are physically mounted and electrically connected to an internal printed circuit board of notebook computer 6. These connectors are utilized in two docking station and system embodiments. In a first embodiment, shown in FIG. 2C, an aperture-defining rectangular edge 58 provides physical access to several of the connectors of notebook computer 6, thereby increasing the connectivity of the combined system 6,7 to peripheral units as will be discussed in connection with FIG. 3. In a second embodiment, the edge 58 is absent, and rear connectors of the docking station 7 mate to these several connectors of notebook computer
6 as will be discussed in connection with FIG. 4.

Looking from left to right in rear elevation of FIG. 2C, a power and telephone connector 45 securely mounted to docking station 7 mates to notebook computer 6. A telephone connector 59 of notebook 6 is suitably obscured in the docking compartment 15, but available for use when the notebook is used in the portable environment. A display connector 60, a printer parallel port connector 61, and a disk drive connector 62 are provided at the back of notebook 6. An optional mouse connector
63 and keyboard connector 64 are provided next to IR emitter/detector 38.

At far right rear on notebook 6, a high-speed bus connector 65 mates securely to a corresponding connector of docking station 7 so that wide-bandwidth communication, such as by a PCI (Peripheral Component Interconnect) type of bus is established between notebook 6 and docking station 7. In this way, the notebook 6 contributes importantly to the computing power of the combined system 5 comprised of notebook 6 and docking station 7.

The physical presence of connector 45 on the left rear and connector 65 on the right rear also contribute to the security of alignment and seating of the notebook 6 in the docking compartment 15. Wide snap-springs of docking compartment 15 click into shallow mating recesses of notebook 6, completing the physical security of alignment and seating of notebook 6 in docking compartment 15.

In FIG. 3, the docking station PCB has a docking station power supply 69 supplying supply voltage VCC to the components of the docking station. Power supply 69 has Power On/Off switch 41, power plug 40, and supplies operating and battery recharging power along power lines 70 through connector 45 to notebook computer 6 which has a printed circuit board and system 100 of interconnected integrated circuits therein as described more fully in connection with FIGS. 5-7 and the later Figures of drawing.

In the docking station PCB, a main bus 71, such as a high bandwidth PCI bus, interconnects via buffers 72, connector 65 and buffers 73 with a high bandwidth bus 104 in system 100 of notebook 6. A docking station microprocessor unit MPU and memory circuitry 74 preferably provides advanced superscalar computing power that is connected to bus 71. A display interface 76 receives display data and commands from bus 71 and supplies video data out to CRT display monitor 8. A SCSI interface 77
communicates with bus 71 and can receive and send data for any suitable SCSI peripheral. Video input circuit 52 receives video data from a video camera, video recorder, or camera-recorder (CAMERA) and supplies this data to bus 71 for processing. A LAN (Local Area Network) circuit 79 provides two-way communication between the docking station 7 and to n other computers having LAN circuits 79.1, . . . 79.n. Token ring, Ethernet, and other advanced LANs are accommodated. An adapter 80 having an interface chip therein provides communication with any LAN system and plugs into a single same socket regardless of the LAN protocol. Such LAN circuitry is described in coassigned U.S. Pat. No. 5,299,193 "Signal Interface for Coupling a Network Front End Circuit to a Network Adapter Circuit" issued Mar. 29, 1994 (TI-15009), which is hereby incorporated herein by reference.

A digital signal processor circuit 81 is connected to bus 71, and is adapted for voice recognition, voice synthesis, image processing, image recognition, and telephone communications for teleconferencing and videoteleconferencing. This circuit
81 suitably uses the Texas Instruments TMS320C25, TMS320C5x, TMS320C3x and TMS320C4x, and/or TMS320C80 (MVP), DSP chips, as described in coassigned U.S. Pat. Nos. 5,072,418, and 5,099,417, and as to the MVP: coassigned U.S. Pat. No. 5,212,777
"SIMD/MIMD Reconfigurable Multi-Processor and Method of Operation" and coassigned U.S. Pat. No. 5,420,809, issued May 30, 1995, and entitled "Method of Operating a Data Processing Apparatus to Compute Correlation", all of which patents and application are hereby incorporated herein by reference.

An interface chip 82, such as a PCI to ISA or EISA interface, connects bus 71 with a different bus 83 to which a multimedia (MIDI) card 51 is connected. Card 51 has an input for at least one microphone, musical instrument or other sound source
84. Card 51 has an output accommodating monaural, stereo, or other sound transducers 85. A SCSI card 86 interfaces a document scanner to bus 83.

Still further peripherals compatible with the speed selected for bus 83 are connected thereto via an I/O interface 87 which communicates with connectors for the hard disk drive HDD, the floppy disk drive FDD 11, mouse MS 10, keyboard KBD 9, the CD-ROM drive 13 and a printer such as a laser printer.

A cursory view of the notebook 6 in FIG. 3 shows that various rear connectors 60-64 are physically accessible through aperture 58 of FIG. 2C allowing still additional peripherals to be optionally connected. For example, the display connector 60
is connected to a second monitor 194 so that multiple screen viewing is available to the docking station user. Connector 59 of notebook 6 is connected through connector 45 to the RJ-11 telephone connector on the back of docking station 7 so that the user does not need to do any more than insert notebook 6 into docking station 7 (without connecting to the rear of notebook 6) to immediately obtain functionality from the circuits of notebook 6.

In FIG. 4, an alternative embodiment of docking station PCB has a comprehensive connector 89 to which the connectors 60-64 of notebook 6 connect. The connectors 60-64 are not independently accessible physically through any aperture 58 of FIG.
2C, in contrast with the system of FIG. 3. In this way, when notebook 6 is inserted into docking compartment 15, straight-through lines from connectors 60-64 through connector 89 pass respectively to display 8, to a PRINTER peripheral, to floppy disk drive FDD, to mouse MS, and to keyboard KBD. Comprehensive connector 89 not only accommodates lines from a bus to bus interface 90 to bus buffers 72, cascaded between buses 104 and 71, but also has an HDD path from notebook 6 to the internal hard disk drive HDD of docking station 7.

The docking station of FIG. 4 has the printer, FDD, MS, KBD and HDD disconnected when the notebook 6 is removed, by contrast with the docking station and notebook system of FIG. 3. However, the docking station of FIG. 4 confers a substantial economic cost advantage, especially in situations where the user does not need to use these peripherals when the notebook 6 is removed. The docking station of FIG. 3 confers substantial flexibility and functionality advantages, especially in situations in which the docking station continues to be used by a second user when the notebook user has taken the notebook elsewhere. Docking station 7 is augmented by the data and processing power available from notebook 6, when the notebook is reinserted into docking station.

Similar circuit arrangements are marked with corresponding numerals in FIGS. 3 and 4, as to docking station power supply 69, Power On/Off switch 41, power plug 40, notebook system 100, main bus 71, SCSI interface 77, video input circuit 52, LAN circuit 79, interface chip 82, multimedia card 51 and SCSI card 86.

Note in FIG. 4 that the SCSI card 77 is connected to the document SCANNER peripheral, providing advantageously high bandwidth input from the scanner to the hard disk drive HDD, floppy disk drive FDD, and microprocessor unit MPU 102. CD-ROM is connected by path 95 in FIG. 4 to the ISA or EISA bus 83 in FIG. 4. Card 97 connected to bus 83 can accommodate further peripherals or, indeed, a microprocessor board so that the docking station of FIG. 4 is independently usable by second user with the notebook 6 removed.

In either FIGS. 3 or 4, the docking station provides advantageous system expandability through i) ISA/EISA slots, ii) additional HDD space, CDROM, multimedia with monaural, stereo, quadraphonic and other sound systems, and iii) wide bandwidth PCI bus 71 local bus slots. A further area of advantage is quick, easy connections to desired non-portable equipment through i) an easier to use, bigger keyboard, ii) bigger, higher quality, CRT display iii) better mouse, printer, and so on. For example, the user merely pushes the notebook 6 into the docking station 7 quickly and easily, and all peripherals are then hooked up, without any further user hookup activity. Another area of advantage is that the docking station 7 provides a platform by which users can retrofit ISA or EISA add-in cards from a previous installation and obtain their use with the notebook 6.

In FIGS. 5, 6, and 7 (which detail the system 100 in FIGS. 3 and 4) a block diagram of a first part of a preferred embodiment computer system 100 shows in FIG. 5 a single-chip microprocessor unit MPU 102 connected to a bus 104, DRAM (dynamic random access memory) 106, FPU (floating point unit) 108, single-chip peripheral control unit (PCU) 112, single-chip peripheral processor unit PPU 110 (shown in FIG. 6) and a display controller 114 (shown in FIG. 7). The FPU 108 of FIG. 5 is suitably either implemented on a separate chip as shown, or integrated onto the same chip as MPU 102 in, for example, a 486DX chip, a 586-level microprocessor, or a superscalar or multi-processor of any type.

In FIG. 6, PPU 110 has terminals connected via an 8-bit bus 116 to a keyboard controller and scan chip KBC/SCAN 118, BIOS (basic input/output system) ROM (read only memory) 120, HDD (hard disk drive) unit 122, and field programmable logic array (FPGA) chip 124. PPU 110 has further terminals connected to a floppy disk drive (FDD) 126, a printer port EPP/ECF 128 to a printer 129, and two serial input/output ports SIO 130 and 132.

A temperature sensor 140, or heating sensor, is connected via logic 124 to the rest of the system to signal temperature levels and cooperate in the power management of the system.

KBC/SCAN 118 is connected to a computer keyboard 142 and computer mouse input device 144.

BIOS ROM 120 is addressed by addresses by signals from MSB (most significant bits) or LSB (least significant bits) 16-bit halves of bus 104 via a buffer multiplexer (MUX) 150. Also BIOS ROM is addressed via 16 bit addresses built up by successive 8-bit entries from bus 116 in two cascaded 8-bit registers 152 and 154. In this way, separate PPU 110 pins for BIOS ROM addresses are advantageously rendered unnecessary.

An audio sound system 160 is connected to PPU 110, thereby providing sound resources for the system 100.

A power switch circuit 170 responsive to a SUSPEND# (the # suffix indicating, throughout this specification, that the signal is active at a low level) line from PPU 110 controls the supply of power from a power supply 172 to system 100 via three pairs of lines from power switch 170 to supply voltages VPP and VCC to system 100. Power supply 172 is energized by an electrical battery 176 and/or an external power source 174.

A clock switch control circuit 180 (FIG. 5) supplies clock signals for system 100 via a line CLK of bus 104.

Returning to FIG. 5, 4 banks of DRAM 106 are resistively connected to MPU 102 via 13 memory address MA lines, 8 CAS (column address strobe) lines, four RAS (row address strobe) lines, and a WE (write enable) line. 32 memory data MD lines provide a path for data to and from DRAM 106 between MPU 102 and DRAM 106.

A frequency-determining quartz crystal 182 of illustratively 50 MHz (MegaHertz) is connected to MPU 102. A 32 KHz (kilohertz) output terminal from PPU 110 is connected resistively to display controller 114.

In FIG. 7, display controller 114 is connected directly to an LCD (liquid crystal display) or active matrix display of monochrome or full color construction. Display controller 114 is connected via a CRT (cathode ray tube) interface (I/F) 192 to a CRT computer monitor 194. A blanking adjustment control 196 is connected to display controller 114. A frame buffer 202 is connected to display controller 114 via address, data and control lines. Two sections A and B of display DRAM 204 and 206 are also connected to display controller 114 via their own address, data and control lines.

Additional bus master devices 210, such as LAN (local area network) and SCSI (Small Computer System Interface) are connected to bus 104 in system 100. Also, slave devices 220 connect to bus 104.

FIG. 8 is a plan view of a preferred embodiment apparatus having a multiple layer (e.g. 10-layer) printed wiring board 302 and electronic components of the computer system 100 of FIGS. 5-7. FIG. 8 shows a component side of printed wiring board
302, while a solder side of board 302 lies opposite (not shown) from the component side. Arranged at vertices of a centrally located quadrilateral 303, and interiorly disposed on the component side of board 302, are the MPU 102, PPU 110, PCU 112 and video, or display, controller 114. All these component devices 102, 110, 112 and 114 are on a high speed bus 104 (as shown in FIGS. 3 through 7), and because the quadrilateral affords an arrangement whereby these devices are located very close to each other, the high speed bus 104 is advantageously made physically small and compact both for small physical size and low electromagnetic interference due to small electrical size. Near the PCU 112 and near a corner 304 of board 302 lies card connector
306, constructed according to a selected interface standard, such as the Personal Computer Memory Card International Association (PCMCIA) standard.

At the system level, system 100 as implemented in the embodiment of FIG. 8 has a main microprocessor integrated circuit 102, a peripheral control unit (PCU) integrated circuit 112, a peripheral processor unit (PPU) integrated circuit 110, a display controller unit integrated circuit 114, and a bus 104 on the printed wiring board interconnecting each of the integrated circuits 102, 112, 110, and 114. The integrated circuits 102, 112, 110 and 114 establish corners of a quadrilateral 303
bounding the bus 104. Further provided are a plurality of external bus connectors disposed in parallel outside quadrilateral 303 and connected to bus 104. A clock chip 180, such as of the well-known AC244 type, is approximately centrally located inside quadrilateral 303 and connected via approximately equal-length lines to each of the integrated circuits 102, 112, 110 and 114 thereby minimizing clock skew.

Four long DRAM 106 SIMM (single inline memory module) socket connectors for banks 0-3 lie parallel to each other, parallel to a short side 308 of board 302, and perpendicular to the connector 306. FPU 108 is located adjacent to one of the DRAM connectors near the MPU 102. SIMM sockets for the DRAMs provide a direct path for the wiring traces on the printed wiring board 302.

Along a longer side 310 of board 302 lie LED connectors D5 and D6 and a loudspeaker connector J33. Next to the holder for battery B1 are connectors J17 for mouse 144 and J18 for keyboard 142. A power supply unit 172 located on the edge of side
310 lies near a corner 312 diagonally opposite corner 304.

A second short side 314 lies opposite side 308 of board 302. At the edge of side 314 are located two power connectors J36 and J37, a serial connector J22 and a parallel port connector J38 designated "Zippy." Looking interiorly, between side 314
and PPU 110 and parallel to short side 314 are a floppy disk drive connector J19 located closely parallel to a hard disk drive connector J21.

A second long side 316 lies opposite side 310 of board 302. At the edge of side 316 and centrally located are a 15 pin connector J11 parallel to a 20.times.2 pin header J12. A video connector J13 lies next to J12 below quadrilateral 303.

Between video controller 114 and PCU 112 lie three TMS45160 chips 113, available from Texas Instruments Incorporated, disposed parallel to each other and to side 316 and substantially parallel to the side of quadrilateral 303 defined by vertices
114 and 112. Next to video controller 114 outside quadrilateral 303 lie three bus 104 connectors J14, J15, J16 parallel to each other and to long side 316.

FPGA 124 is located above PPU 110 between PPU 110 and side 310 near power supply 172.

A DOS-compatible static 486 core in MPU 102 allows on-the-fly clock-scale and clock-stop operation to conserve battery power. The special clocking scheme allows optional clock stopping between keystrokes. Low voltage operation such as 3.3 volts or less, coupled with power management, provides the capability to achieve low system battery power consumption. Bus 104 is a high speed high bandwidth bus to improve data transfers of bandwidth-intensive I/O devices such as video. Electrical noise is minimized by this embodiment which has short conductor trace lengths and direct point-to-point clock traces. Each clock trace has a series or parallel termination to prevent undesirable reflections. An economical 74LS244 clock driver 180 is provided in the interior of quadrilateral 303. Placement of that clock driver 180 is such that the length of the clock traces therefrom to each chip 110, 102, 114 and 112 are approximately equal, advantageously minimizing clock skew.

Integrated card controller PCU 112 can be configured to support a portable peripheral bus such as PCMCIA (Personal Computer Memory Card International Association), for example. The connector 306 near corner 304 has one card insertion level in a plane on the top side of board 302 and a second card insertion level in a plane on the underside of board 302.

Single 8-bit ROM 120 support allows for integration of the system BIOS and video BIOS into the same device to reduce motherboard real estate and reduce cost. MPU 102, PPU 110 and PCU 112 are highly integrated into three 208 pin PQFP devices (see FIG. 58 later hereinbelow) which reduces board space and reduces active battery power consumption by integrating all CPU and system logic.

In other embodiments, the PPU 110 and PCU 112 are separate integrated circuit devices. In still other embodiments the MPU 102, PPU 110 and PCU 112 are integrated into only one single-chip device. However, the three chip embodiment shown, with its substantially equal pin numbers, provides remarkable economy and board layout convenience.

In the three-chip embodiment illustrated in FIGS. 5-7, the chips are manufactured using submicron process technology to illustratively provide operation up to 66 MHz and higher at 3.3 volts while keeping power consumption and heat dissipation remarkably low.

Returning to FIG. 8, physical strength and reasonable rigidity without fragility are provided by the relatively small size of board 302. Additional mounting holes near connectors for bus 104 are provided. Board 302 is firmly mounted with screws, bolts, rivets or other mounting elements in an enclosure 325 associated with or comprised by base 22 of FIG. 1. When an external connection to bus 104 is made, such as in a docking station or other environment, the mounting elements in the additional mounting holes advantageously provide substantial load-bearing support strength for improved reliability.

In FIG. 9 microprocessor unit (MPU) 102 comprises a preferred embodiment device illustrated in block diagram form. MPU 102 integrates a 486-class CPU (central processing unit) 701 which has a CPU core 702, an 8K-byte write-through 32-bit instruction/data cache 704, and a clock, phase-locked loop (PLL), and control circuit 706. CPU core 702 is described in the TI 486 Microprocessor: Reference Guide, 1993, which is hereby incorporated herein by reference. Cache 704 is two-way set associative and is organized as 1024 sets each containing 2 lines of 4 bytes each. The cache contributes to the overall performance by quickly supplying instructions and data to an internal execution pipeline.

A power management block 708 provides a dramatic reduction in current consumption when the microprocessor MPU 102 is in standby mode. Standby mode is entered either by a hardware action in unit 920 of PPU 110, described hereinbelow relative to FIG. 11, or by a software initiated action. Standby mode allows for CPU clock modulation, thus reducing power consumption. MPU power consumption can be further reduced by generating suspend mode and stopping the external clock input. The MPU 102 is suitably a static device wherein no internal data is lost when the clock input is stopped or clock-modulated by turning the clock off and on repeatedly. In one preferred embodiment, without suggesting any limitation in the broad range of embodiments, the core is a three volt, 0.8 micron integrated circuit having clock operation at 50 or 66 MHz., with clock doubling.

Core 702 has a system-management mode with an additional interrupt and a separate address space that is suitably used for system power management or software transparent emulation of I/O (input/output) peripherals. This separate address space is also accessible by the operating system or applications. The system management mode is entered using a system management interrupt which has a higher priority than any other interrupt and is maskable. While running in the separate address space, the system management interrupt routine advantageously executes without interfering with the operating system or application programs. After reception of the system management interrupt, portions of the CPU are automatically saved, system management mode is entered and program execution begins in the separate address space. System management mode memory mapping into main DRAM memory is supported.

The MPU 102 has interface logic 710 which communicates via external FPU/IF terminals to FPU 108 when the latter is present.

System configuration registers 712 are accessible via a CPU local bus 714. Bus 714 is connected to CPU 701, to a bus bridge circuit 716, and to a DRAM memory controller (MCU) 718. Registers 712 also are bidirectionally connected to the bus bridge circuit 716 via line 722.

DRAM memory controller 718 is connected to system configuration registers 712 via line 721 and receives signals via a line 724 from bus bridge 716. DRAM memory controller 718 supplies DRAM addresses and DRAM control signals to external terminals of single-chip MPU 102. DRAM memory controller 718 is connected by handshake line 727 to power management circuit 708, which circuit 708 is also connected by line 726 to bus bridge 716 and by line 728 to clock, phase lock loop and control circuit 706.

A data circuit 720 provides a data router and data buffers. DRAM memory controller 718 supplies signals to circuit 720 via line 732. Data circuit 720 also bidirectionally communicates with bus bridge 716 via line 730. Data circuit 720 reads and writes DRAM data to external terminals on data bus 734. Main bus 104 connects via terminals to MPU 102 and connects via paths 736 and 738 to data circuit 720 and bus bridge 716 respectively. Data circuit 720 includes two-level posted DRAM write buffers, an integrated four-level DRAM refresh queue, and provides for three programmable write-protection regions.

DRAM memory controller 718 supports up to 256 megabytes or more of DRAM memory with up to four or more 32-bit banks without external buffering. For example, DRAMS of 256K, 512K, 1M, 2M, 4M, 8M, and 16M asymmetric and symmetric DRAMS and up to
64M and higher DRAMS are readily supported. Shadowed RAM is supported. Additionally, the memory interface buffers can be programmed to operate at different operating voltages such as 3.3 or 5.0 volts for different types of DRAMS. The DRAM memory controller 718 is programmable to support different access times such as 60 or 80 nanoseconds (ns). For example, 60 ns. is quite advantageous at 50 and 66 MHz. clock speeds at 3.3 v. Varous refresh modes are programmably supported, such as slow, self, suspend, and CAS-before-RAS refresh. Maximum memory throughput occurs because DRAM parameters are driven off the internal high-speed 50/66 MHz. CPU clock to improve resolution, thus taking full advantage of the integration of the DRAM controller.

The bus bridge 716 acts as an integrated interface which is made compliant with whatever suitable specification is desired of bus 104. Bus bridge 716 advantageously acts, for example, as a bus master when there is a MPU 102 initiated transfer between the CPU and bus 104, and as a target for transfers initiated from bus 104. A bus-quiet mode advantageously supports power management. The bus-quiet mode is used to inhibit cycles on bus 104 when the CPU is accessing the DRAM 106 or internal cache 704. Put another way, bus quieting reduces system power consumption by toggling the data/address bus 104 only on bus transfers. Bus quieting is not only implemented on MCU 718 but also PPU 110 bus bridge 716 and XD/IDE block 934, described hereinbelow relative to FIG. 11. All signals, buses and pins are made to change state only when they need to. For example, each data bus flip-flop holds its state until the next change of state.

As thus described, MPU 102 integrates in a single chip a 486-class CPU, a DRAM controller, and a bus interface in any suitable integrated circuit package, of which one example is 208 pin PQFP (plastic quad flat pack). PPU 110 and PCU 112 also partition system functionality into respective single-chip solutions which can have the same type of package as the MPU 102, such as a plastic package. These latter two chips can even be pinned out in a preferred embodiment from the same 208 pin PQFP package type.

In FIG. 10 a preferred embodiment layout for MPU 102 has an improved topography wherein MPU 102 is realized as an integrated circuit die with a single substrate 802 with approximately 1:1 ratio of side lengths. Various circuit regions or blocks are fabricated on substrate 802 by a CMOS (complementary metal oxide semiconductor) process. Other processes such as BiCMOS (bipolar CMOS) can also be used.

The 486 CPU core 702 is located in one corner of the die to provide maximum accessibility pin-out with short conductor length to bond pads 804 on the nearby margins forming a right angle at the corner 806 of the substrate 802. Cache 704 lies closely adjacent to CPU core 702 for high speed CPU access to the cache. The memory controller 718 MCU is laid out together in an approximately rectangular block of circuitry lying along a strip parallel to cache 704, and perpendicular to microcode ROM and core 702 along substantially most of an edge of the chip 802 opposite to an edge occupied by cache 704. In this way cache 704 and MCU 718 bracket core 702.

On a side 818 opposite microcode ROM of core 702 lies bus bridge 716 laid out in a long strip parallel and stretching most of the length of side 818. Advantageously, the long length of this bus interface 820 provides physical width accessibility to the numerous terminals for connection to the wide bus 104 of system 100 of FIGS. 3-7.

In FIG. 11 PPU 110 provides a single-chip solution that has numerous on-chip blocks on chip 901.

First is a bus interface 902 to interface from external bus 104 to an on-chip bus 904. Bus interface 902 is compatible with bus 104 externally, and is at the same time also compatible with bus 904 as a fast internal bus for integration of several peripherals described hereinbelow. For example, the peripherals in various embodiments suitably provide peripheral functions compatible with the IBM-compatible "AT" computers, or compatible with Apple "Macintosh" computers or peripherals having any desired functionality and operational definition as the skilled worker establishes. Bus interface 902 has advantageously short bus 104 ownership when mastering to minimize overall system latency. Bus interface 902 provides fast DMA (direct memory access) transfers from internal I/O devices to agents (circuits) on bus 104.

Bus interface 902 performs a disconnection with retry operation for slow internal accesses to reduce the latency still futher. Illustrative bus 104 frequency is 33 MHz. at either 5 volts or 3.3 volts, although other lower or higher frequencies and voltages are also suitably established in other embodiments. In the embodiment of FIG. 11 the internal bus 904 is suitably clocked at half or a quarter of the bus 104 frequency, and higher or lower frequency relationships are also contemplated.

A bus arbiter 906 on-chip provides arbitration of bus 104 for the MPU 102 of FIG. 5, PPU 110 of FIG. 6, and two external bus masters 210 of FIG. 7. PPU 110 acts as a bus 104 bus master during DMA cycles for transfers between bus 104 and a DMA peripheral 910.

One preferred embodiment provides more peripherals that are compatible with the "PC-AT" architecture. Since the bus 904 provides an on-chip common connection to all of these on-chip peripherals, their speed and other electrical performance are enhanced. For example, two DMA controllers 910 control the DMA transfers through bus interface 902. In PPU 110 DMA controllers 910 are connected to bus 904 and separately also to both bus arbiter 906 and bus interface 902 via path 911. DMA controllers
910 also pin out externally to four pins from bond pads on chip 901. Two interrupt controllers 914 provide channels individually programmable to level-triggered or edge-triggered mode. Also in interrupt controllers 914 is an interrupt router that routes an external interrupt from bus 104 or an interrupt from PCU 112 to a software-selectable interrupt channel. In PPU 110 interrupt controllers 914 and a timer/counter 916 connect to bus 104 and also pin out externally to 9 pins and 2 pins respectively. An RTC (real time clock) circuit block 918 has an integrated low-power 32 kHz. oscillator and a 128 byte CMOS SRAM (static RAM). Examples of some features and circuitry which are useful in DMA controllers 910, interrupt controllers 914, timer-counter 916 and RTC circuit 918 are commercially available devices, such as the well-known 8237, 8259, 8254 and MC146818 devices, respectively (the 8237, 8259, 8254 devices available from Intel Corporation, and the MC146818 device available from Motorola) together with improvements as described herein. It is also contemplated that still other peripherals be provided on-chip for system purposes as desired.

A power management block 920 has a battery powered first section 920A for operation whenever the system 100 is energized, and a section 920B which is battery powered at all times. Power management block 920 provides clock control for CPU 702
even without a system management interrupt. Mixed voltage (e.g., 3.3v/5v) support is provided as a power management function.

Power management block 920 includes system activity timers named the STANDBY timer and the SUSPEND timer which monitor bus 104 activity via DEVSEL# signal, display frame buffer (e.g., VGA) activity (as performed by controller 114 and frame buffer
202 described above relative to FIG. 7), DMA requests, serial port 130 interrupts and chip selects via a COM1 signal, parallel-port 128 interrupts and chip select via a LPT1 signal, hard disk controller 122 interrupts and chip select, floppy disk controller 126 interrupts and chip select, programmable chip select signals, and other interrupts, all such functions described hereinabove relative to FIG. 6. Power management block 920 further provides for short term CPU clock speedup timer monitoring of keyboard 142 and mouse 144 interrupt requests from KBC/SCAN chip 118, as well as bus 104 bus master cycle requests, and masked system activity timer output.

CPU clock masking, or clock-modulation, is provided by power management block 920 hardware that includes a programmable register for adjusting the gate-on-to-gate-off ratio, i.e., a ratio of clock time on to clock time off.

A bidirectional system management interrupt handshaking protocol is supported by power management block 920. Also, six power management traps are provided for IDE block 122, FDD 126, serial port 130 COM1, parallel port 128 LPT1, as described hereinabove relative to FIG. 6, and for programmable chip selects.

Four-bit (16 level) backlight intensity adjustment pulse-width modulation (PWM) advantageously results from the operations of power management block 920 in response to intensity control 34 of FIG. 1.

When power management block 920 has caused substantial sections of PPU110 and the rest of system 102 to be deactivated, reactivation can be initiated by circuitry in block 920 responsive to an RTC alarm, a modem ring, a suspend/resume button, keyboard IRQ (interrupt request), mouse IRQ, ON/OFF button, a card system management interrupt CRDSMI from PCU 112, or a low-to-high transition on a battery input BATLOW.

Shadow registers in power management block 920 support saving the full system state to disk.

Bus quieting and I/O leakage current control circuitry are also included in power management block 920.

Advanced Power Management support is also provided by power management block 920.

Further in FIG. 11, a floppy disk controller block 930, digital disk controller (FDS), hard disk interface XD/IDE 934, serial interface block SIU 936, and a parallel port interface 983 are all coupled to internal bus 904 and to pins externally.

The floppy disk controller block 930 is integrated on-chip in PPU 110 to support 3.5 inch drives (720 kB (kilobyte), 1.44 MB (megabyte), and 2.88 MB) as well as 5.25 inch drives (360 kB and 1.2 MB). All buffers are integrated. Floppy disk controller block 930 has circuitry to accommodate data in several track formats: IBM System 34 format, perpendicular 500 kb/s (kilobits per second) format, and perpendicular 1-Mb/s (one megabit per second) format. A data FIFO (first-in-first-out) buffer operates during the execution phase of a read or write command in block 930. Block 930 also has a 255-step (16 bit) recalibrate command and function. This floppy disk controller block 930 can be reset by software. It has an integrated floppy data separator with no external components in this embodiment. Drive interface signals can be multiplexed to parallel port 938 pins for use with an external drive.

The interface 934 provides a complete IDE hard disk interface logic with high speed access. The IDE hard disk is isolated and can be powered off independently. Also included in interface 934 is a bus interface for XD bus 116 of FIG. 6, which supports BIOS ROM (which can be flash electrically erasable programmable read only memory, commonly referred to as "EEPROM"), provides keyboard controller KBC/SCAN connections, has two user-programmable chip selects, and can connect to audio CODEC (coder-decoder).

Further in FIG. 11 a block for miscellaneous control functions is provided as block 940.

Serial interfaces 936A and 936B each have a 16-byte FIFO for queuing and buffering the serial data to be transmitted and received, and has a selectable timing reference clock of 1.8461 MHz. or 8 MHz.

Parallel interface 938 has a 16-byte datapath FIFO buffer and provides DMA transfer. Support for fast parallel protocols such as ECP and EPP is suitably provided. More than one floppy disk drive FDD 126.0 and 126.1 are suitably accommodated by provision of a multiplexer 939 to mux the output of digital floppy disk controller 932 with parallel port 938. When a control signal PIFFDC from configuration registers 1222 of PPU 110 causes mux 939 to select the floppy disk, then external pins otherwise utilized by parallel port 938 are suitably used instead for a FDD 126.1.

Bus Quieting

The description now turns to the subject of bus quieting. Bus quieting reduces power dissipation and EMI (electromagnetic interference) and RFI (radio frequency interference) because fewer transitions from high to low, or low to high, occur on a given bus. As to power dissipation, fewer transitions mean less power dissipation because inherent capacitance of bus circuitry is charged from the power supply, or discharged, fewer times. Power dissipation is given by the general formula

where P is power, C is inherent capacitance, V is supply voltage, and f is number of transitions per second. The 0.5 C V.sup.2 factor relates to the energy stored in the inherent capacitance, and the factor f establishes how often the capacitance has energy moving in or out of it. The product of the factors represents a rate of energy dissipation which by definition is power dissipation. The bus quieting methods are primarily directed to reducing the repetition rate factor f.

FIGS. 12 and 13 show circuitry and methods respectively for implementing different improved approaches in bus quieting in a general case of interfacing two buses or lines. These circuits and methods are implemented in whole or in part anywhere in the systems of FIGS. 3-7 that the real estate overhead is justified by the power reduction achieved. For example, bus quieting circuitry is advantageously implemented in the PPU 110 in the XD/IDE I/F 934 among other blocks in PPU 110. A preferred embodiment circuit for XD/IDE 934 is illustrated in FIG. 14, for example. Also, bus quieting circuitry as taught herein is suitably provided in the main microprocessor MPU 102 in the memory controller unit MCU 718 and data router and data buffers 720, among other places. Still further bus quieting circuitry as described is suitably provided in the PCU 112 and other components of the illustrated systems. For instance, a display controller chip 114 has substantial memory traffic to frame buffer 202, and RAMs 204, 206 to which the bus quieting methods and structures as taught herein are applicable. The improved bus quieting circuits, systems and methods described herein are intended for reduced instruction set computer (RISC) and complex instruction set computer (CISC) portable computers, desktop personal computers, workstations, embedded microprocessor and microcomputer applications, battery powered applications of all types, and indeed to all circuits, systems and applications to which their advantages commend them.

In FIG. 12, an improved bus quieting circuit 7200 is implemented in an interface between a first bus 7201 and a second bus 7202. A selector, or multiplexer (mux), 7205 has a first input connected to first bus 7201, and an output connected via an output buffer 7207 (with low active output enable oen) to second bus 7202. An input buffer 7209 (with low active input enable rd en) is connected with its input connected to second bus 7202 and its output connected to bus 7201, bypassing mux 7205.

Mux 7205 has a second input 7212 tied to a predetermined level, such as zero (0 or "low"), and a third input 7214 connected to the Q output of a data latch 7220 clocked with a clock CLK of bus 7201. Latch 7220 has a data D input connected to the output of the mux 7205.

A fourth input to mux 7205 is directly connected to the mux 7205 output by lines 7216. This circuit can function similarly to the latch arrangement provided there is no need for clock synchronization and wherein the mux 7205 is preferably glitch-free on a mux 7205 switchover operation from bus 7201 input to lines 7216. In this way the mux 7205 performs both selection and latch functions.

Mux 7205 has control inputs among which is the output of a first bit latch 7225 for a bus-quieting control bit XQ1. The latch 7225 is accessible via bus 7201, and/or bus 7202 as desired, so that the quieting mode can be established on setup or disabled. The ability to software-select the quieting mode or to disable it on command confers power reduction and RFI reduction advantages with bus quieting enabled. When quieting is disabled in the context of an output buffer coupling internal circuitry or an internal bus of an integrated circuit to external pins or external circuitry, the ability to disable quieting confers internal visibility advantages for monitoring, test and debug operations.

Thus, an improved system (FIGS. 6 and 7) comprises an integrated circuit (e.g. PPU 110) having bus quieting with the mode enable/disable features herein, combined with peripherals (e.g. memory 120, sound 160, KBC 118, Hard Disk Drive HDD 122) and also with a monitoring circuit or external test circuitry (e.g. in FPGA 124) or a computer (e.g. MPU 102, bus master 210, or docking station test computer) external to the integrated circuit. The bus quieting feature is software accessible to enable or disable the bus quieting mode or modes in low-power system operation (bus-quieting on and mode type selected) and in monitoring, test and debug operations (bus-quieting turned off).

Latch 7225 has one or more bits as needed to enable no quieting (NOISY BUS of FIG. 13) or enable any selected quieting mode, as the case may be. If a single quieting mode such as Method I or Method II of FIG. 13 is implemented, one bit XQ1
suffices. If both Method I or Method II are provided as quieting options, then latch 7225 is suitably a two-bit latch.

A buffer control logic circuit 7230 has control outputs connected to output enable oen and input enable rden respectively. Among other inputs 7232 to circuit 7230 is a second quieting control bit XQ2 for tristating (floating, disabling, three-stating) at least the buffer 7207 in Method III of FIG. 13. The latch 7235 is accessible via bus 7201, and/or bus 7202 as desired, so that the Method III quieting mode can be established on set up or disabled.

In FIG. 13, suppose a particular data line of bus 7201 is valid during an interval VALID. After its strobe included in control line 7206 becomes inactive, subsequent activity on that data line of bus 7201 continues to produce transitions NOISY on bus 7202 in the absence of bus quieting. Note that NOISY as used here to describe a signal or bus, is considered as one or more logic values which are present on a second bus or signal line (e.g. XD or IDE bus) when that second bus or signal line is not involved in or necessary to an ongoing transaction on a first bus (e.g. 904) to which the second bus is in fact coupled.

Advantageously, in Method I of FIG. 13, a first step of asserting valid data and passing the data from a first line to a second line is followed by a quieting step of forcing the second line to a predetermined level until valid data for the second line is again presented.

In a circuit implementation for practicing one form of Method I of FIG. 13, the presence of a bit or bits in latch 7225 of FIG. 12 causes MUX 7205 to select a predetermined level zero on line 7212 as shown by a lower parallel line "0" in Method I of FIG. 13. In an alternative embodiment, a complementary logic value one (1) is instead provided at input 7212 or at an additional input of mux 7205. Then a second form of method I is practiced wherein bus 7202 is forced to the high level "1" in FIG.
13.

In a second method embodiment Method II of FIG. 13, a first step of asserting valid data and passing the data from a first line to a second line is followed by a quieting step of maintaining the second line at a predetermined level identical to the level of the just-presented valid data, for a predetermined or otherwise established period of time extending beyond the valid interval and/or until different valid data for the second line is later presented.

In a circuit implementation for practicing one form of Method II of FIG. 13, the presence of a bit or bits in latch 7225 of FIG. 12 causes MUX 7205 to select the input 7214, whereupon the latched value of the valid data on bus 7201 held in latch
7220 is maintained and passed on to bus 7202 via input 7214, mux 7205, and buffer 7207. Method II eliminates a transition 7310 which may occur in Method I but uses slightly more complex circuitry then Method I. Note that when valid data, or even a "noisy" level in FIG. 12, has the same logic level as a bus-quieting logic level, then no transition would occur.)

Both Method I and Method II advantageously provide outputs that can be either used on or off-chip without additional pull-up or pull-down circuitry on Bus 7202. In applications where such circuitry is already present, or its lack is of no concern, or providing it is no impediment, Method III recognizes that bus quieting can be introduced by tristating bus output buffer 7207 under control of buffer control logic 7230 and quieting control bit XQ2 in latch 7235.

Thus, in the methods, according to the preferred embodiments of the invention, as illustrated in of FIG. 13, a first step of asserting valid data and passing the data from a first line to a second line is followed by a quieting step of disconnecting or decoupling the first line from the second line for a predetermined or otherwise established period of time between data-valid intervals. In Method III, the decoupling can involve floating or disabling a coupling element that is interposed between the first and second lines. In Method II, the decoupling can involve coupling a latch instead of bus 7201 to bus 7202. In method I, the decoupling can involve coupling a predetermined logic level instead of bus 7201 to bus 7202.

It should be apparent that in some embodiments, portions of the circuitry of FIG. 12 can be omitted. For example, if method III is not practiced, latch 7235 is omitted. If only method I is practiced, the latch 7220 can be omitted. If only method II is practiced, then latch 7220 on line 7214 (or return line 7216) is retained, and the input 7212 can be omitted.

Also, slash marks as shown in FIG. 12 indicate that the circuit can be replicated for all of the data lines and applicable control lines in the busses to which quieting is relevant.

Where Method I is applicable to control lines and Method II is more advantageous for data lines, then the circuit of FIG. 12 is suitably configured so that a single one XQ1 bus-quieting control simultaneously enables Method I for the control line circuits and Method II for the data line circuits. In such type of embodiment, the circuit of FIG. 12 is not precisely replicated, but instead has the mux 7205 control circuitry designed to implement the respective methods. Also, different bus quieting methods can suitably be applied to different lines of the same bus under control of the same, or different, bus quieting bits.

As a further example, FIG. 14 shows a detailed block diagram of bus quieting circuitry and related circuitry in XD/IDE interface 934 of FIG. 11. Here, a fast-AT bus 904 internal to PPU 110 is coupled to distinct buses comprising the IDE bus to a hard disk drive external to PPU 110, and an XD bus to other external peripherals as shown in FIG. 6 herein. Attention is directed, in this regard, to copending application Ser. No. 08/363,198, and the other copending applications noted in the Background of the Invention hereinabove, which are incorporated herein by reference.

In FIG. 14 an IDE bus control state machine 7410 and an XD bus control state machine 7420 are respectively coupled to bus 904. IDE bus control state machine 7410 has inputs for bus 904 reset line RST, and bus clock line CLK (also called SYSCLK), as well as IDE power management reset line ide pmu rst and Hard Disk Drive Power control line hdd pwr. These latter two lines are respectively coupled from a reset generator and a power control block of the power management unit 920B of PPU 110. For additional detailed description of the reset generator and power control block, attention is directed to the above-referenced incorporated application Ser. No. 08/363,198, and the other copending applications noted in the Background of the Invention hereinabove. IDE bus control state machine 7410 has four output lines 7412 coupled to control A) a mux 7415 supplying an IDE I/O Read output IDEIOR# of the IDE Bus, B) correspondingly control a mux 7417 supplying an IDE I/O Write output IDEIOW# of IDE Bus, and C) correspondingly control a mux 7419 supplying IDE input/output data lines DD[15:8] of the IDE Bus via an output buffer 7421. Lines 7412 are respectively active to signify a corresponding one of four states of state machine 7410.

XD bus control state machine 7420 has inputs for ISA bus 904 lines AEN (Address Enable high for memory addressing of DMA; low for I/O cycle), AUDDAK0# and AUDDAK1# (Audio DMA Acknowledges), clock CLK, and a bus 904 line FIRST (signals First byte of ROM address) via a BALE-clocked (Bus Address Latch Enable) latch 7425. Low-active chip selects CS are provided for ROM nromcs, keyboard controller nkbccs, and programmable chip selects zero and one: npcs0, npcs1. The chip selects CS are output from a bus address decoding unit 7430 or from software accessible register bits as the skilled worker may choose to implement. The chip selects are not only supplied to state machine 7420 but also to the XD Bus itself.

XD bus control state machine 7420 has eight output lines 7432 to control a mux 7435. Mux 7435 supplies XD bus data lines XD[7:0] via an output buffer 7437. Among the eight lines 7432 is a line IDLE indicative of an Idle state of state machine
7420. Line IDLE is connected to a control input of each of 1) a mux 7441 supplying an XD Bus Read line XRD# and 2) a mux 7443 supplying an XD Bus Write line XWR#.

The important Bus Quieting bit XQ1 of FIG. 14 is connected to a control input of each of muxes 7415, 7417, 7419, 7435, 7441 and 7443. In the embodiment of FIG. 14, the XQUIET bit is active high to quiet buses IDE Bus and XD Bus when there is no access, and otherwise when low to turn bus quieting off. This bus quieting operation is described in still further detail herein after some further description of the state machines 7410 and 7420 in connection with FIGS. 15 and 16 respectively.

In FIG. 15, IDE bus control state machine 7410 is constructed in sequential logic to have four states IDE OFF, Power Up state IDE PWR UP, IDE Bus Access state IDE ACC, and an IDLE state. Since a state machine is suitably implemented in custom logic, programmable array logic (PAL) and other forms according to any chosen technique, the discussion focuses on the state transition diagram which more concisely describes the state machine.

In state machine 7410, an occurrence of active power management reset signal ide pmu rst, or inactive disk drive power control signal hddpwr#, sends the state machine 7410 to the IDE OFF state. An occurrence of a chip select for hard disk drive indicated by address 1Fx or 3Fx sends the state machine 7410 to state IDE ACC directly from any of its three other states. Such address is decoded by decoder 7430 of FIG. 14 on respective 1Fx and 3Fx decode output lines to a 2 bit latch 7445 clocked by bus address latch enable signal BALE. The 2 bit latch 7445 latch outputs are not only fed to OR-circuitry in IDE state machine 7410 but also to respective cs1Fx# and cs3Fx# lines of IDE Bus, and to inputs of a buffer control logic block 7450.

Further in FIG. 15, if neither cs1FX or cs3Fx is active and the state machine is in IDE OFF, a transition occurs from IDE OFF to IDE PWR UP upon the power management reset being or going inactive (ide pmu rst going low). Otherwise, in the absence of cs1Fx or cs3Fx active or IDE OFF transition as described, the next bus 904 clock clk rising transition will take operations to IDLE state from either IDE ACC or IDE PWR UP state. The IDLE state is also reached by assertion of a Bus 904 reset signal (fat rst) provided power management reset ide pmu rst is not active. The circuitry of IDE state machine 7410 is arranged to take one of the four lines 7412 high representing whichever one of the four states IDE OFF, IDE PWR UP, IDLE or IDE ACC is active.

In FIG. 16, XD Bus control state machine 7420 has eight states and 8 corresponding output lines 7432 for states ROMA1 (ROM address, send first byte), ROMA2 (ROM address, send second byte), ROMACC (ROM data access), Keyboard Access KBD ACC, Programmable Chip Select Access (PCS ACC), Hard Disk Drive Access (IDE ACC), Direct Memory Access Circuit Access (DMA ACC), and XD State Machine Idle state (XDIDLE). Except for immediate transition to IDLE from any state upon Bus 904 Reset signal fat rst, the transitions are made on low-to-high clock clk edges when various conditions occur as next described.

As indicated by circuitry including AND gate 7610 and NOR-gate 7675, state ROMA1 is reached whenever a ROM chip select signal romcs is active and a smpfirst output of latch 7425 (shown in FIG. 14) is active and the state is not already any of states ROMA1, ROMA2, or ROMACC. Operations move from state ROMA1 to ROMA2 after a clock cycle, and from state ROMA2 to ROMACC after another clock cycle. If operations do not begin with ROMA1 as just described, a priority of state selection determines the state according to whatever chip select is active or to resolve contention if more than one chip select is active:

______________________________________ Top priority: ROMACC if romcs is active Next: KBD ACC if kbccs is active Next: PCS ACC if either pcs0 or pcs1 is active (NAND 7630) Next: IDE ACC if either 1Fx/3Fx address active (NAND 7640) Next: DMA ACC if aen active and either AUDDAK0 or AUDDAK1 active (NAND 7650, AND 7655) Last Priority: IDLE if no chip select active, upon next clock. ______________________________________

The description now returns to FIG. 14 to discuss the bus quieting operations controlled by these state machines 7410, 7420 and the XQUIET software-accessible bus quieting control bit.

In FIG. 14, mux 7415 has three inputs respectively for a logic one, a logic zero, and a bus 904 I/O Read IOR# signal stretched by a pulse stretcher circuit 7462. Mux 7417 has three inputs respectively for a logic one, a logic zero, and a bus 904
I/O Write IOW# signal stretched by a pulse stretcher circuit 7464. Mux 7419 has two 8-bit inputs respectively for logic zeros, and a bus 904 data high-byte SD[15:8].

The mux 7415, 7417, 7419 outputs are controlled by the IDE state machine 7410 states and, further in the IDLE state specifically, by the XQUIET bit as well. In IDE ACC, mux 7415, 7417 outputs are stretched IOR#, IOW#; and mux 7419 output passes SD[15:8]. Any of the IDE ACC state output signal and the signals that produce IDE ACC can be regarded as indicative of valid data for the present purposes. In IDE OFF, the mux 7415, 7417 outputs are both zero (read and write both active) to avoid dumping current into the external hard disk drive 122, assuming it is off; and mux 7419 data output is all zeros. In IDE PWR UP, the mux 7415, 7417 outputs are both one to inactivate hard disk drive read and write; and mux 7419 output is all zeros.

In the IDLE state of the state of state machine 7410, bus quieting bit XQUIET controls the bus quieting function described above relative to FIG. 14. If XQUIET is zero (no bus quieting), the operation is just like IDE ACC state, and the operations on bus 904 drive the lines on the IDE Bus causing avoidable power dissipation.

However, if in the IDLE state of state machine 7410, XQUIET is one (bus quieting active), Method I of FIG. 13 is implemented in the following way. The one (1) inputs of mux 7415 and 7417 are selected to inactivate the read and write outputs IDEIOR# and IDEIOW# by forcing them to a high logic level (1). The zero (0) 8-bit input of mux 7419 is selected to drive the data lines DD[15:8] to zeroes on the IDE Bus. (In an alternative embodiment they are all driven high (ones) on DD[15:8] if zeroes do not produce the lower power quiescent condition for the IDE part of system 100.)

Further in FIG. 14, mux 7441 has three inputs respectively for a logic one, a bus 904 memory read MEMR# (connected also to buffer control logic 7450), and a bus 904 I/O Read IOR# signal stretched by a pulse stretcher circuit 7462. Mux 7443 has three inputs respectively for a logic one, a bus 904 memory write MEMW#, and a bus 904 I/O Write IOW# signal stretched by a pulse stretcher circuit 7464. Mux 7435 has four 8-bit inputs respectively for a bus 904 data low-byte SD[7:0], low word-address byte SA[9:2], high word-address byte SA[17:10], and an 8-zeroes input.

The mux 7441, 7443, 7435 outputs are controlled by the XD state machine 7420 states and, further in the XDIDLE state specifically, by the XQUIET bit as well. In states KBD ACC, PCS ACC, and DMA ACC, the mux 7441, 7443 outputs are stretched IOR#, IOW#; and mux 7419 output passes data low-byte SD[7:0]. In states ROMA1, ROMA2 and IDE ACC, the mux 7441, 7443 outputs are both one to inactivate XD bus read XRD# and write XWR#; and mux 7435 output is word-address low-byte, word-address high-byte, and data low-byte for these states respectively. In state ROMACC, the mux 7441, 7443 outputs are bus 904 MEMR# and MEMW# respectively; and mux 7435 output is data low-byte (in case the ROM is EEPROM and thus writable).

In the XDIDLE state of state machine 7420, the state of bus quieting bit XQUIET controls the bus quieting function described above relative to FIG. 14. If XQUIET is zero (no bus quieting), the mux 7441, 7443, 7435 operation is the same as in the ROM ACC state, and the operations on bus 904 drive the lines on the XD Bus causing avoidable power dissipation.

However, if in the XDIDLE state of state machine 7420, XQUIET is one (bus quieting active), Method I of FIG. 13 is implemented in the following way. The one (1) inputs of mux 7441 and 7443 are selected to inactivate the read and write outputs XRD# and XWR#. The zero (0) 8-bit input of mux 7435 is selected to drive the data lines XD[7:0] to zeroes on the XD Bus. (In an alternative embodiment they are all driven high (ones) on XD[7:0] if zeroes do not produce the lower power quiescent condition for the XD part of system 100.)

In another alternative embodiment, muxes 7419 and 7435 of FIG. 14 are each replaced with the circuit of FIG. 12 to operate latch 7220. In this way, data bus quieting Method II is employed for the data lines while Method I is used to quiet the read and write lines.

An address line mux 7438 is controlled by the eight state line outputs from state machine 7420 and not by the XQUIET bit. XD bus byte-address lines XA[1:0] are ordinarily fed with the corresponding 2 LSB lines SA[1:0] in all states except KBD ACC wherein XA[1] is instead fed by SA[2]. Also, for state machine 7420 states DMA ACC, IDE ACC and XDIDLE, the byte address lines XA[1:0] are forced by mux 7438 to 00 (both zeroes) to ensure aligned addresses.

Description turns now to the I/O buffers 7421, 7423 and 7437, 7439 and to the buffer control logic 7450.

In FIG. 14, buffer control logic 7450 has low active outputs IDE data output enable nddoen to output buffer 7421 and not to input buffer 7423, XD data output enable nxdoen to output buffer 7437 and not to input buffer 7439.

The buffer control logic 7450 basically sifts its inputs to determine whether a read or write on which bus (IDE or XD bus) is being selected, and then enables an output buffer 7421 or 7437 correspondingly. On reads XRD# and IDEIOR#, the output buffers 7421 and 7437 are disabled. If Method III of FIG. 13 is employed, an additional software-accessible bus quieting bit XQ2 is suitably used to disable the output buffers 7421 and 7437 during bus quieting periods when they are otherwise enabled under Methods I and II.

FIG. 9, MPU 102 includes a microprocessor, memory controller, and PCI Bridge Unit, all on a single integrated circuit chip.

Features of this preferred embodiment include:

Integrated 486 clock-doubled static core

50-MHz and 66-MHz operation at 3.3 V

Direct high speed bus interface into internal 486-CPU bus

Integrated 8K-Byte cache

Supports advanced power management software

System management mode hardware

High-priority system management interrupt (SMI)

Suspend mode (hardware and software initiated)

Integrated 50-MHz and 66-MHz memory controller

Programmable DRAM timing optimized for 60-ns access at 50 and 66 MHz

Supports 3.3 V and 5 V DRAMs

Supports up to 256M-byte DRAM in four 32-bit banks without external buffering

Supports 256K, 512K, 1M, 2M, 4M, 8M, and 16M asymmetric and symmetric DRAMs

Supports shadowed RAM

SMM Memory mapping into main memory (DRAM)

Two-level DRAM write buffers

Integrated 4-level DRAM refresh queue

Programmable write-protection regions

Advanced power management for DRAM

Suspend refresh

Self refresh

Slow refresh

CAS before RAS refresh

Integrated PCI bus interface for master/slave operation

The microprocessor unit (MPU) 102 of FIG. 9 integrates a 486 CPU 701, DRAM controller 718, and PCI interface 716 into a single chip contained in a 208-pin PQFP (plastic quad flat pack) package.

The 486 CPU core contains an 8K-byte write-through, 32-bit instruction/data cache 704. The cache 704 is two-way set associative and organized as 1024 sets each containing 2 lines of 4 bytes each. The cache contributes to the overall performance by quickly supplying instructions and data to an internal execution pipeline of CPU core 702.

MPU 102 power-management features allow a dramatic reduction in electrical current consumption when the microprocessor is in a standby mode. Standby mode is entered either by a hardware or software initiated action as described in connection with PPU 110 in FIG. 23. Standby mode allows for CPU clock modulation via a MaskClock MSKCLK input pin of MPU 102 as shown in FIG. 27, thus reducing power consumption. Once in standby mode, the MPU power consumption can be further reduced in a suspend mode, as discussed in connection with FIG. 33, by stopping the external clock input. Since the MPU 102 is a static device, no internal data is lost when the clock input is stopped.

A system-management mode (SMM) provides an additional interrupt SMI# and an address space that can be used for system power management or software transparent emulation of I/O peripherals or other purposes. SMM is entered using the system-management interrupt (SMI) which has a higher priority than any other interrupt. While running in protected SMM address space, the SMI interrupt routine can execute without interfering with the operating system or application programs. After reception of an SMI, portions of the CPU are automatically saved, SMM is entered and program execution begins at the SMM address space. The location and size of the SMM memory is programmable. Seven SMM instructions in the 486 core instruction set permit saving and restoring the total CPU state when in SMM mode.

In FIG. 9, MPU 102 integrates a high performance DRAM controller 718 that supports up to 256M bytes of DRAM memory 106 with up to four 32-bit banks without external buffering. Additionally, memory interface buffers 720 can be programmed to operate at 3.3 V or 5 V. The DRAM controller 718 is programmable to support 60 ns and 80 ns accesses. Various refresh modes are supported which include: slow, self, suspend, and CAS-before-RAS refresh.

An on-chip PCI interface 716 (bus bridge) is suitably provided compliant with the PCI 2.0 specification. The PCI interface 716 acts as a bus master when there is a CPU initiated transfer between the CPU and the high speed PCI bus 104 and as a target for PCI initiated transfers. An important feature which supports power management is a bus-quiet mode used to inhibit PCI bus cycles when the CPU is accessing the DRAM 106 or internal cache 704.

The embedded 486 core processor 702 is initialized when the RESET signal is asserted. The processor 702 is placed in real mode ("8086" mode), signal states shown in the next table are established, and the registers listed in the following table are set to their initialized values. RESET invalidates and disables the cache 704, turns off paging and returns the processor 706 clock circuit to non clock-doubled mode. When RESET is asserted, the microprocessor 102 terminates all local bus activity and all internal execution. During the time that RESET is asserted, the internal pipeline is flushed and no instruction execution or bus activity occurs.

Approximately 350 to 450 CLK2 clock cycles (additional 220+60 cycles if self-test is requested) after deassertion of RESET, the processor 702 begins executing instructions at the top of physical memory (address location FFFF FFF0h). When the first intersegment JUMP or CALL is executed, address lines A31-A20 of local bus 714 in FIG. 9 are driven low for code-segment-relative memory-access cycles. While these address lines are low, the microprocessor 102 executes instructions only in the lowest 1M byte of physical address space until system-specific initialization occurs via program execution.

The internal circuitry of 486 CPU core 702 is diagrammed and described in greater detail in TI486 Microprocessor: Reference Guide, 1993, available from Texas Instruments Incorporated and hereby incorporated herein by reference.

The clock circuitry 706 is described in U.S. Pat. No. 5,442,325, issued Aug. 15, 1995, entitled "A Voltage-Controlled Oscillator and System with Reduced Sensitivity to Power Supply Variation" and hereby incorporated herein by reference.

In FIG. 9 the PCI bus bridge 716 provides the interface between the rest of MPU 102 and the PCI bus 104. The integrated 486 core processor 701 and memory controller 718, 720 subsystems are connected to the PCI bus 104 through the PCI bridge 716. The PCI bridge 716 maps the address space of local bus 714, of the integrated 486 core processor 701, into the address space of the PCI bus 104; and provides the mechanism that allows the 486 core processor to access PCI configuration space. The PCI bridge 716 provides a low-latency path through which the 486 core processor directly accesses other PCI bus agents mapped anywhere in memory and I/O spaces. Additionally, the PCI bridge 716 provides a high-bandwidth path that allows PCI bus masters outside MPU 102 direct access to main memory. MPU 102 is capable of behaving as a bus master (initiator) or PCI Slave (target) running at 0 MHz up to 25 or 33 MHz and much higher frequencies into hundreds of Mega-Hertz according to the concepts disclosed herein.

MPU 102 implements a 256-byte configuration space, which is a physical address space for registers 712 to configure PCI agents. The configuration registers 712 are accessed via an Index/Data register pair.

For PCI bus 104 to main memory accesses, the MPU 102 is a target on the PCI bus 104. For host to peripheral component accesses, the MPU is a master on the PCI bus 104. The host can read and write both configuration and non-configuration address spaces. When the host is accessing the MPU configuration registers 712, the MPU 102 is both the master and the target. Configuration cycles initiated by MPPU 102 circuitry in bridge 716 to MPU configuration registers 712 are not forwarded to the PCI bus 104.

The FRAME, IRDY, and TRDY signals, are some PCI control signals. FRAME is asserted by the initiator (master) to indicate the beginning and end of a PCI transfer. IRDY is asserted by the initiator to indicate that the data is valid (write) or that it is ready to accept data (read). TRDY is asserted by the PCI target to indicate that the data is valid (read) or that it is ready to accept data (write).

All PCI transactions begin with the assertion of FRAME whereupon the master places address and control information on the address/data AD and C/BE command/byte enable lines. If the transaction is a read, the next cycle is used to allow the direction of the bus to turn around and be driven by the target. If the transaction is a write, the next cycle can be a data phase containing the data that is to be transferred to a target.

A data phase completes when both IRDY and TRDY are asserted. If either IRDY or TRDY are negated during the data phase, wait states are inserted by bus bridge 716, for example. FRAME is negated when the initiator has only one data transfer remaining and IRDY is asserted, as in cycles with multiple data phases such as burst cycles. Otherwise, if no burst cycle occurs, FRAME is negated when IRDY is asserted. When FRAME and IRDY are both negated (high), the data transfer is complete and the bus 104 is in an idle cycle.

When MPU 102 asserts FRAME, the other PCI agents in the system decode the address being driven onto the AD lines of bus 104. PCU 112, Display Controller 114 and devices 210 and 220 of FIGS. 5-7 decode the address on bus 104, and the PPU 110
decodes addresses not claimed by other devices. When an agent device decodes an address as being its own, it identifies itself as the target by asserting an active signal on select line DEVSEL. If no device responds within five clocks, MPU 102
terminates the cycle with a master abort. When MPU 102 is the target of another PCI master as in the case of a PPU 110 to main memory 106 transfer, MPU 102 asserts DEVSEL to claim the cycle.

Bus commands indicate to the PCI target devices the type of transaction that the master PCI device is requesting. The bus commands, such as interrupt acknowledge, special cycle, I/O read, I/O write, memory read, memory write, configuration read, configuration write, memory read multiple, memory read line, and memory write and invalidate, are supported as targets and masters according to the architecture of the preferred embodiment of the invention. It is contemplated that support for these and similar bus commands, as target and initiator will be selected appropriately to the commands and the architecture of each system embodiment.

The MPU can, but does not have to, support burst cycles as a master. The burst interface is suitably provided in the memory management unit MMU of CPU core 702. In the case of another PCI master attempting to burst data to memory, the MPU PCI bridge 716 can, in a non-burst mode, also terminate the PCI burst cycle after the first data has transferred. In burst mode, however, the burst cycle executes to completion. A latency timer is suitably used to limit the amount of time that the MPU can use the PCI bus during a burst transfer.

Turning to the subject of status and error reporting, MPU 102 has two signals, PERR and SERR, for handling errors. PERR is used to report data parity errors during all PCI transactions except a special cycle. SERR is used to report address parity errors and special cycle data parity errors. PERR is asserted when a PCI agent receiving data detects a data parity error. SERR is asserted by the PCI agent that detects an address parity error or a special cycle data parity error. In the event of an error, the appropriate status bits are set in the Status and Command register in block 712 as described in register tables later hereinbelow.

Additional MPU errors include 1) access to a non-existent device or 2) accessing a target that cannot handle the request. When MPU 102, as a master, attempts to access a nonexistent device or a device that does not respond, with DEVSEL in a predetermined time, MPU 102 executes a master abort. If the MPU is accessing a target device and the target device cannot handle the request, the target aborts. In both cases, status bits in the Status and Command register are set to indicate that a master abort (MABT bit) or a target abort occurred.

MPU 102 supports both master-initiated termination as well as target-initiated termination. All transactions are concluded when both FRAME and IRDY are negated, indicating that the bus is idle. Master-initiated termination includes 1) Cycle completion or 2) Master abort, as described above, 3) timeout termination. Cycle completion is normal completion of a PCI transaction.

Time-out termination refers to a transaction that is terminated because the latency timer expired before the transaction was able to complete.

The MPU responds to a target-initiated termination in one of the following ways: 1) Retry, 2) Abort or 3) Disconnect.

Retry refers to termination by the target that informs the initiator it currently cannot respond to a transaction and that the transaction should be retried at a later time. No data transfer takes place during this transaction.

Abort refers to termination by the target when the target determines that a fatal error has occurred or that it may never be able to respond to the transaction. The received-target-abort-status bit (TABT) in the PCI Status register is set indicating that the MPU experienced a PCI target-abort condition.

Disconnect refers to termination requested because the target is unable to respond within a latency time interval after the first data phase is transferred. By contrast, no data transfers during a retry. When the MPU 102 only transfers single data, a disconnect resembles a normal cycle completion except that STOP is asserted.

As a target, the MPU completes the transaction. No retry, disconnect, or abort is issued.

The MPU 102 supports HALT and SHUTDOWN. The halt instruction (HLT) stops program execution and prevents the processor 102 from using the local bus 714 until restarted. The CPU 702 in HALT enters a low-power suspend mode. When an external hardware interrupt is detected on the INTR input pin and the interrupts are enabled (IF bit in EFLAGS=1), SMI, NMI, or RESET forces the CPU out of the halt state. The PCI bridge 716 broadcasts the HALT as a special cycle on the PCI bus 104.

Shutdown occurs when a severe error is detected that prevents further processing. The PCI bridge does not broadcast the shutdown cycle as a PCI special cycle. Instead, the PCI bridge logic internally generates a reset to the CPU.

Interrupt acknowledge cycles are generated by the MPU 102 bridge 716 when an INTR output is asserted by PPU 110 to the MPU INTR input. During interrupt acknowledge cycles, the internal bus cycle definition signal (M/IO (pin), D/C (internal), and W/R (pin)) are driven to 000. The interrupt acknowledge cycle has two 8-bit read operations, with the addresses being driven to 4 and 0 for the first and second cycles, respectively. During an interrupt acknowledge cycle, the first byte read is ignored and the second provides the 8-bit interrupt vector. LOCK is also asserted to ensure that the two reads are executed back-to-back.

On the PCI bus, the interrupt acknowledge cycle is a single cycle, in contrast to the two back-to-back read cycles on the CPU bus 714. The cycle is an internal cycle initiated by ADS and terminated by RDY. FRAME is generated on the PCI bus to the PPU to start the Interrupt Acknowledge (INTA) cycle. The CPU bus cycle definition signals are transformed into a PCI interrupt acknowledge (INTA) command. The PPU 110 responds to FRAME and the INTA command by providing a single interrupt vector byte from its internal interrupt controller 914 of FIGS. 11, 38, 43 and 44. A second RDY is generated to the CPU based on the IRDY/TRDY handshake and the cycle completes.

In a PC-compatible address map, the address space 512K-1M (00080000h-000FFFFFh) is reserved for video memory (VRAM or DRAM), ROM, and system-expansion memory. The MPU 102 PCI bridge 716 implements a DRAM Shadow and Timing Control register in block 712 that allows Read Only, Write Only, Read/Write, or Disabled attributes to be programmed for memory blocks within this space except the address range 512k-640k (0008 0000h-0009 FFFFh). This latter address range is not included because most current PC systems are populated with 640 KB of DRAM memory which spans the address space 0000 0000h-0009 FFFFh.

The next table shows the granularity defined by the DRAM Shadow and Timing Control Register for memory in the 640K-1M space (000A 0000-000F FFFFh).

Read only, write only, read/write or disabled attributes are also advantageously assigned to a memory block in the 640K-1M space. The host PCI bridge 716 response to memory access depends on whether the access originates on the CPU primary bus
714 or secondary (PCI) bus 104. As an example, a write access originating on the host bridge primary bus 714 to a memory block for which the attribute bits are set to write only (code 01 in SRRn, SRWn bits of shadow register for that memory space) does not flow through the bridge 716 to the PCI bus 104. Instead, the memory access is directed via bus 714 to the main system memory 106 controlled by the MCU 718. A read access to this same memory block originating on bus 714 does flow through the bridge to PCI bus 104 to BIOS RAM 120 of FIG. 6, for example, and is not responded to by system DRAM 106. This logic in bridge 716 advantageously supports copying of BIOS RAM to DRAM, as described later hereinbelow.

______________________________________ MPU Granularity in 640K-1M space Address Range Usage ______________________________________ 000A 0000h - 000B FFFFh Video memory (128 Kbyte Block) 000C 0000h - 000C 3FFFh Expansion BIOS ROMs (16 Kbyte Blocks) 000C 4000h - 000C 7FFFh 000C 8000h - 000C BFFFh 000C C000h - 000C FFFFh 000D 0000h - 000D 3FFFh 000D 4000h - 000D 7FFFh 000D 8000h - 000D BFFFh 000D C000h - 000D FFFFh 000E 0000h - 000E FFFFh System BIOS ROMs (64 Kbyte Blocks) 000F
0000h - 000F FFFFh ______________________________________

Accesses from the host bridge 716 secondary bus (PCI bus 104) are responded to by the bridge 716 in a different way. It is assumed that unless a given address block is disabled, there is a PCI agent on the secondary bus (PCI bus) that will respond to an access within that block. In other words, for addresses, the only accesses originating on the host bridge secondary bus 104 that are passed through to the host bridge primary bus 714 are those to an address block that has a "disabled" attribute. Accesses from the host bridge secondary bus 104 to memory blocks that have been set to read/write, read only, or write only are responded to by the PCI agent on the secondary bus 104 and not passed on to the primary bus 704. The table below describes how the host PCI bridge 716 responds to accesses within the 640K-1M space:

______________________________________ Block Access Cycle Origin of Cycle Access Attribute Goes to Listed Bus ______________________________________ CPU Read Read Only CPU (714) Primary Bus Write Only PCI (104) Read/Write CPU Disabled PCI Write Read Only PCI Write Only CPU Read/Write CPU Disabled PCI PCI Read Read Only CPU Secondary Bus Write Only PCI Read/Write CPU Disabled PCI Write Read Only PCI Write Only CPU Read/Write CPU Disabled PCI ______________________________________

The memory controller unit (MCU 718) generates timing control signals for the DRAM array 106. The MCU 718 is integrated on the same single chip as the MPU 102 and supports 1 to 4 DRAM banks and up to 256M bytes or more without external buffers. The MCU 718 supports any combination of DRAM types: 256K, 512K, 1M, 2M, 4M, 8M, or 16M. Three types of refresh modes are supported: normal, suspend refresh, and self refresh. DRAM timing parameters are programmable to allow optimized DRAM accesses for
60 ns and 80 ns DRAMs at system speeds of 50 MHz and 66 MHz. The MCU 718 is designed to coordinate memory accesses originating from the CPU 702 with memory accesses originating from the PCI Interface bridge 716. A PCI master access to main memory 106
has higher priority than a CPU 702 access to main memory 106. The CPU 702 is put on hold until the PCI master is through bursting, unless there are higher priority refresh requests pending.

Each of the 4 DRAM banks in memory 106 supports 1 to 64M bytes in 1M byte increments. The DRAM bank size is individually programmable allowing any mix of banks without restrictions on mixing DRAM size or physical location.

Memory reads or writes to DRAM are double-word aligned 32-bit wide accesses. The MCU 718 has one RAS line per DRAM memory bank where RAS0-3 correspond directly to banks 0-3. Bank 0 contains the lowest addresses and bank 3 contains the highest addresses. The MCU 718 provides eight CAS lines. Each DRAM bank uses four CAS lines; one CAS line per byte. CAS3 and CAS7 control the high-order bytes while CAS0 and CAS4 control the low-order bytes. CAS3-0 drives DRAM banks 0 and 2. CAS7-4 drives DRAM banks 1 and 3.

The MCU 718 provides a common Write Enable (WE) line that is connected to all DRAM memory banks.

The following table shows the various DRAM technologies that are supported by the memory controller. The memory array types are selected by programming the Memory Array Type register. Each bank is individually programmable to support any of the DRAM array types.

__________________________________________________________________________ DRAMs Supported Organiza- Size tion Devices Memory per (Depth per Bits per Address Widths Array Bank Width) xBank Device Rows Columns Type (Mbits) __________________________________________________________________________ 256K .times. 1 .times. 32* 256K 9 (MA8-MA0) 9 (MA8-MA0) 2 1 256K .times. 4 .times. 8 1M 9 (MA8-MA0) 9 (MA8-MA0) 2 1 256K .times. 16 .times. 2 4M 9 (MA8-MA0) 9
(MA8-MA0) 2 1 11 (MA10-MA0) 8 (MA7-MA0) 3 1 512K .times. 8 .times. 4 4M 10 (MA9-MA0) 9 (MA8-MA0) 2 2 12 (MA11-MA0) 8 (MA7-MA0) 3 4 1M .times. 1 .times. 32* 1M 10 (MA9-MA0) 10 (MA9-MA0) 1 4 1M .times. 4 .times. 8 4M 10 (MA9-MA0) 10
(MA9-MA0) 1 4 1M .times. 8 .times. 4 8M 10 (MA9-MA0) 10 (MA9-MA0) 1 4 12 (MA11-MA0) 9 (MA8-MA0) 2 4 1M .times. 16 .times. 2 16M 10 (MA9-MA0) 10 (MA9-MA0) 1 4 12 (MA11-MA0) 9 (MA8-MA0) 2 4 2M .times. 8 .times. 4 16M 11 (MA10-MA0) 10
(MA9-MA0) 1 8 13 (MA12-MA0) 9 (MA8-MA0) 2 8 2M .times. 16 .times. 2 32M 11 (MA10-MA0) 10 (MA9-MA0) 1 8 13 (MA12-MA0) 9 (MA8-MA0) 2 8 4M .times. 1 .times. 32* 4M 11 (MA10-MA0) 11 (MA10-MA0) 0 16 4M .times. 4 .times. 8 16M 11 (MA10-MA0) 11 (MA10-MA0) 0 16 4M .times. 8 .times. 4 32M 11 (MA10-MA0) 11 (MA10-MA0) 0 16 4M .times. 16 .times. 2 64M 11 (MA10-MA0) 11 (MA10-MA0) 0 16 13 (MA12-MA0) 10 (MA9-MA0) 1 16 8M .times. 8 .times. 4 64M 13 (MA12-MA0) 10 (MA9-MA0) 1 32 16M .times. 1 .times. 32* 16M 12 (MA11-MA0) 12 (MA11-MA0) 0 64 16M .times. 4 .times. 8 64M 12 (MA11-MA0) 12 (MA11-MA0) 0 64 __________________________________________________________________________ *Due to the capacitive loading caused by higher fanout on the memory address ines, these implementations are less preferable.

DRAM Timing

The DRAM Interface timing is programmable on a per-bank basis to support several DRAM speeds. The MCU provides two parameters that are used to program DRAM timing. These parameters are programmable by setting the DTMG1-0 bits in the DRAM Shadow and Timing Control register. The first parameter is the RAS activation to DRAM access time (DTMG1). The second parameter is CAS to READY sampling time (DTMG0). The next table shows some example values for programming the DRAM timing types 0, 1, and 2. The timing type is selected for the entire DRAM array. The following table shows the number of access wait states for the different memory cycles and timing types.

______________________________________ DRAM Timing Types RAS CAS to READY System DRAM Timing DTMG Access Sampling Clock Speed Type 1 0 T Cycles (MHz) (ns) ______________________________________ 2 1 0 4 2 50 60 1 0 1 5 3 50 80 66 60 0* 0
0 6 4 50 100 66 80 ______________________________________ *Default.

______________________________________ Wait States for DRAM Memory Cycles Wait States (T Cycles) DRAM Memory Cycle Type 2 Type 1 Type 0 ______________________________________ Normal Read (Single) 5 6 8 Normal Write (Single) 4 5 6 Normal Read (Back to Back) 5/6 6/8 8/10 Normal Write (Back to Back) 4/6 5/8 6/10 Normal Read and Write (Back to Back) 5/5 6/7 8/8 Normal Write and Read (Back to Back) 4/7 5/9 6/12 Page Hit Read 3 4 6 Page Hit Write 2 3 4 Page Hit Read (Back to Back)
3/3 4/4 6/6 Page Hit Write (Back to Back) 2/2 3/3 4/4 Page Hit Read and Write (Back to Back) 3/2 4/3 6/4 Page Hit Write and Read (Back to Back) 2/3 3/4 4/6 Page Miss Read 8 10 13 Page Miss Write 7 9 11 Page Miss Read (Back to Back) 8/8 10/10
13/13 Page Miss Write (Back to Back) 7/7 9/9 11/11 Page Miss Read and Write (Back to Back) 8/7 10/9 13/11 Page Mis