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United States Patent5786984
Bonardi , ; et al.July 28, 1998
Title
Modular portable personal computer
Abstract
A modular portable personal computer includes one or more flexible bays accessible from the front surface of the computer. One or more of the flexible bays may be configured as a dual functional bay to enable the bay to interchangeably receive different modular devices, such as a modular floppy disk drive or a modular battery pack. With such a configuration, the modular floppy disk drive can be removed for portable operation and an additional battery pack installed to provide increased electrical power to the portable personal computer during portable operation. The portable personal computer is also provided with a plurality of cavities formed in a bottom surface. These cavities allow for various upgrades to be made without opening the computer housing. For example, a modular hard disk drive cavity is provided on the bottom side of the personal computer. The modular hard disk drive cavity is adapted to receive a modular hard disk drive which can be relatively easily removed and installed without opening the computer housing. In addition, a cavity may be provided which is closed by an access cover which includes one or more standard in-line memory module (SIMM) sockets to enable additional SIMMs to be added without opening the computer housing. The CPU in the modular portable personal computer can also be rather easily and quickly replaced. In particular, a cavity is formed in the bottom of the portable personal computer and carries an electrical connector that is electrically connected to the mother board. A CPU mounted on a printed circuit board (PCB) is adapted to be received in the cavity. A mating connector is provided on the PCB to enable the CPU to be connected to the motherboard. An access panel provides access to the cavity to enable the CPU to be replaced without the need to open the computer housing.
Inventors:Bonardi; Timothy A. (Buchanan, MI), Fuhs; Eric D.  (Stevensville, MI), Ojeda; Peter A.  (Mundelein, IL), Griffin; Wayne L.  (St. Joseph, MI), Hallowell; William C.  (Spring, TX), Wagner; John P.  (Round Rock, TX), Wang; Bruce  (Livonia, MI), Zappacosta; Elisa E.  (Issaquah, WA)
Assignee:Packard Bell NEC (Sacramento, CA)
Appl. No.:415229
Filed:March 24, 1995
Current U.S. Class:361/686 361/727 361/685 
Field of Search:361/679,683,684,685,686,724,725,727 364/708.1 312/223.2 345/169,905
U.S. Patent Documents
5132876July 1992Ma
5278730January 1994Kikinis
5311397May 1994Harshberger et al.
5325262June 1994Ma
5331509July 1994Kikinis
5365230November 1994Kikinis
5426564June 1995Hsu
5526226June 1996Katoh et al.
D359034June 1995Kondo
D364151November 1995Yamazaki
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National Semiconductor, "AT/LANTIC.TM. Evaluation Software Description--ATLES," pp. 1-6, Dec. 3, 1992. .
National Semiconductor, "DP83905EB-AT-AT/LANTIC.TM. Evaluation Board," pp. 1-11 plus four pages of schematics, Jan. 22, 1993. .
Cirrus Logic, "CL-PD6710/6720 Advance Data Book," 1 page, Jan. 1993. .
Maxim, "Triple-Output Power-Supply Controller for Notebook Computers," MAX783, pp. 4-241, Aug. 1993. .
John R. Quain, "Moving Up to Multimedia," PC Magazine, pp. 112-116, 120, 121, 124-128, 135, 136, 138, 142, 143, 146, 151, 152, 154 and 157, Oct. 25, 1994. .
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Power IC's Datebook, 1993 Edition, National Semiconductor, "LP2950/LP2950AC/LP2950C 5V and LP2051/LP2951AC/LP2951C Adjustable Micropower Voltage Regulators," pp. i & II and 2-95 thru 2-107. .
Crystal Semiconductor Corp., CS4231, "Parallel Interface, Multimedia Audio Codec," pp. 4-165, Nov. 1993. .
MOZART Preliminary Specification, pp. 1-3, Dec. 1993. .
Russ Uithoven, "Software Specification for the Ninja Charging Cradle (MOACC)," pp. 1-5, Version 1.1, Mar. 9, 1994. .
IBM ThinkPad, "Dock 1 User's Guide," pp. iii-xii, 1-1 thru 6-18, A-1 thru D-5 and 14 unnumbered pages. .
IBM ThinkPad 750 brochure..~
Primary Examiner: Feild; Lynn D.
Attorney, Agent or Firm:Fitch, Even, Tabin & Flannery
Parent Case Text


CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in part of U.S. Design application Ser. No. 29/027,521, filed Aug. 23, 1994, which issued as U.S. Design Pat. No. 370,006, and is related to the following U.S. patent applications, all filed on even date: External Flexible Bay, Ser. No. 08/410,603, abandoned; Flexible Multimedia System, Ser. No. 08/411,379, pending; Removable LCD and Stand Assembly, Ser. No. 08/410,634, pending; Peripheral Card Locking Device, Ser. No. 08/410,633, issue fee paid; and Active Port Replicator, Ser. No. 08/412,505, pending.
Claims

What is claimed and desired to be secured by Letters Patent of the United States is:
1. A modular personal computer system comprising:
a motherboard;
a first housing for carrying said motherboard, said first housing including one or more predetermined bays formed from one or more interior cavities open on one predetermined side and having a predetermined size to enable said interior cavities to be accessible from said predetermined side, said interior cavities sized and shaped to receive correspondingly sized and shaped modules inside said interior cavities;
a first predetermined electrical connector carried in an interior portion of each of said one or more first interior cavities, said first predetermined electrical connector electrically coupled to said motherboard;
a predetermined module adapted to be received in said one or more interior cavities, said predetermined module comprising a second housing for housing a standard peripheral device, said module sized and shaped to be received in said one or more interior cavities and a second predetermined electrical connector carried by said second housing, said second predetermined electrical connector being configured to mate with said first predetermined electrical connector when said second housing is fully inserted into said one or more cavities;
an external bay adapted to be mounted externally to said first predetermined housing;
said external bay including means for enabling said external bay to be electrically coupled to said motherboard, said external bay formed with a second cavity open on one side and sized to be substantially the same size as said first interior cavity to enable said one or more predetermined modular devices to be interchangeably installed in said first interior cavity; and
an electrical connector carried in an interior portion of said second cavity in said external bay and configured to mate with said electrical connector on said modular device when said modular device is fully inserted in said second cavity and said external bay.

2. A modular personal computer system as recited in claim 1, wherein said predetermined side is a front surface of said first housing.

3. A modular personal computer system as recited in claim 2, wherein said predetermined device is a predetermined modular floppy disk drive.

4. A modular personal computer system as recited in claim 1, wherein said predetermined electrical connector and one of said one or more predetermined bays is electrically coupled to said motherboard to enable two different types of modular devices to be electrically coupled to said motherboard.

5. A modular personal computer system as recited in claim 4, wherein one of said two predetermined different types of modular devices is a predetermined battery pack for providing portable electrical power to said personal computer.

6. A modular personal computer as recited in claim 4, wherein said one of said two different types of modular devices is a floppy disk drive.

7. A modular personal computer system as recited in claim 1, wherein said modular device is a hard disk drive.

8. A modular personal computer system as recited in claim 7, wherein said first cavity for receiving said hard disk drive is accessible from a bottom surface of said first housing.

9. A modular computer system as recited in claim 1, wherein said first housing further includes one or more third cavities in said first housing open to one or more predetermined surfaces of said first housing for removably receiving one or more predetermined electrical components; said third cavities including means electrically coupled to said motherboard, said cavity adapted to receive one or more predetermined electrical devices; and means for electrically coupling said one or more predetermined electrical components to said motherboard.

10. A modular portable computer system as recited in claim 9, wherein said predetermined electrical component is a standard in-line memory module (SIMM).

11. A modular portable computer system as recited in claim 9, wherein said predetermined electrical components include a CPU mounted on a printed circuit board that is adapted to be removably received within said third cavity.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a portable personal computer and more particularly to a modular portable personal computer having one or more flexible bays adapted to receive one or more types of modular devices, such as a floppy disk drive or a battery pack, which enables additional memory to be added and allows the central processing unit (CPU) and hard disk drive to be rather easily and quickly replaced without opening up the housing.

2. Description of the Prior Art

Various portable personal computers are known. Such portable personal computers normally include a floppy disk drive, a hard disk drive and a battery pack for portable operation. The floppy disk drive is normally secured to the housing and cannot be readily removed without substantial disassembly of the portable personal computer.

In certain applications, particularly portable applications, the floppy disk drive is known to be under utilized if the user is working solely with files on the hard disk drive. However, due to the difficulty in removing the floppy disk drive from the portable housing, the floppy disk drives are not normally removed for portable operation. Due to the space constraints within such portable personal computers, the floppy disk drive limits the size of the battery pack, thereby decreasing portable use.

Another known problem with portable personal computers is the difficulty in upgrading such computers. In particular, in order to make any type of change, such as add additional memory or replace the hard disk drive, it is often necessary to open the computer housing. Many users are reluctant to replace components within the computer housing and therefore have such upgrades done by computer technicians, which can be rather expensive.

Another problem with such portable personal computers normally is the inability to upgrade the CPU. In many known applications, the CPU is wired down on the motherboard and thus replacement of the CPU can require not only opening the housing but replacement of the entire motherboard. In some known computer systems, it is known to provide an expansion socket on the motherboard to accommodate an upgrade CPU. However, such expansion sockets require additional space, that is generally not available in such portable personal computers.

SUMMARY OF THE INVENTION

It is an object of the present invention to solve various problems of the prior art.

It is another object of the present invention to provide a portable personal computer which has the ability to selectively carry additional battery packs for portable operation.

It is yet a further object of the present invention to provide a portable personal computer with one or more modular bays, which enables modular devices, such as a modular battery pack and a modular floppy disk drive, to be quickly and easily connected and disconnected without the need to open the computer housing.

It is yet a further object of the present invention to provide a portable personal computer which enables various components of the computer to be upgraded without the need to open the computer housing.

It is yet another object of present invention to provide a portable personal computer which allows the main memory to be upgraded without the need to open the computer housing.

It is yet another object of the present invention to provide a portable personal computer which enables the hard disk drive to be replaced without the need to open the computer housing.

It is yet a further object of the present invention to provide a portable personal computer which enables the CPU to be upgraded without the need to replace the motherboard or to open the computer housing.

Briefly, the present invention relates to a modular portable personal computer which includes one or more flexible bays accessible from the front of the computer. One or more of the flexible bays may be configured as a dual functional bay to enable the bay to interchangeably receive different modular devices, such as a modular floppy disk drive or a modular battery pack. With such a configuration, the modular floppy disk drive can be removed for portable operation and an additional battery pack installed to provide increased electrical power for the portable personal computer during portable operation. The portable personal computer is also provided with a plurality of cavities formed in a bottom surface. These cavities allow for various upgrades to be made without opening the computer housing. For example, a modular hard disk drive cavity is provided on the bottom side of the personal computer. The modular hard disk drive cavity is adapted to receive a modular hard disk drive which can be relatively easily removed and installed without opening the computer housing. In addition, a cavity may be provided which is closed by an access cover which includes one or more single in-line memory module (SIMM) sockets to enable additional SIMMs to be added without opening the computer housing.

The modular portable personal computer is also configured to enable the CPU to be rather easily and quickly replaced. In particular, a cavity is formed in the bottom of the portable personal computer and carries an electrical connector that is electrically connected to the mother board. A CPU mounted on a printed circuit board (PCB) is adapted to be received in the cavity. A mating connector is provided on the PCB to enable the CPU to be connected to the motherboard. An access panel provides access to the cavity to enable the CPU to be replaced without the need to open the computer housing.

BRIEF DESCRIPTION OF THE DRAWING

These and other objects and advantages of the present invention will become readily apparent upon consideration of the following detailed description and attached drawing, wherein:

FIG. 1 is a perspective view of a flexible connectivity system in accordance with the present invention.

FIG. 2 is a perspective view of a portable personal computer in accordance with the present invention.

FIG. 3 is a perspective view of the portable personal computer shown in FIG. 2, illustrating an external flexible bay in accordance with the present invention.

FIGS. 4A-4D are schematic diagrams for the external flexible bay in accordance with the present invention illustrating a microcontroller and a portion of the control circuitry for the system.

FIG. 4E is a mapping diagram illustrating the positional relationship of FIGS. 4A-4D.

FIGS. 5A-5D are similar to FIGS. 4A-4D illustrating the connectors for the personal computer, printer and I/O devices installed in the external flexible bay.

FIG. 5E is a mapping diagram illustrating the positional relationship of FIGS. 5A-5D.

FIGS. 6A-6I represent flow charts for the microcontroller illustrated in FIG. 4D.

FIG. 7 is a perspective view of the external flexible bay in accordance with the present invention.

FIGS. 8 and 9 are perspective views of the external flexible bay illustrated in FIG. 7, in different states of assembly.

FIG. 10 is a perspective view of a modular battery pack for use with the external flexible bay and personal computer in accordance with the present invention.

FIGS. 11 and 12 are exploded perspective views illustrating the modular battery pack shown in FIG. 10 in different states of assembly.

FIG. 13 is a perspective view of a modular disk drive for use with the external flexible bay and personal computer in accordance with the present invention.

FIGS. 14 and 15 are exploded perspective views of the modular disk drive shown in FIG. 13 in different states of assembly.

FIGS. 16-40 are schematic diagrams for a main circuit board for an active port replicator in accordance with the present invention.

FIGS. 41-47 are schematic diagrams for a network interface board for the active port replicator in accordance with the present invention.

FIGS. 48-64 are schematic diagrams for a PCMCIA interface board in accordance with the present invention.

FIG. 65 is a perspective view of the active port replicator in accordance with the present invention illustrating the replicated ports.

FIGS. 66-71 are perspective views of the active port replicator in accordance with the present invention in various stages of assembly.

FIG. 72 is a perspective view of the active port replicator in accordance with the present invention illustrating the docking system for docking the active port replicator to a personal computer.

FIG. 73A is a partial plan view of a latch assembly for the active port replicator in accordance with the present invention shown with a personal computer shown in phantom just prior to being docked to the active port replicator and with the latch assembly in an unlatched position.

FIG. 73B is similar to FIG. 73A but with the personal computer docked to the active port replicator and with the latch assembly shown in a latched position.

FIGS. 74A and 74B represent a block diagram of the multimedia system in accordance with the present invention.

FIG. 74C is a schematic diagram of a WAV option card for the multimedia system in accordance with the present invention.

FIG. 74D is a schematic diagram of an amplifier circuit which forms part of the audio subsystem for the multimedia system in accordance with the present invention.

FIGS. 75-86 are electrical schematic diagrams of the multimedia system in accordance with the present invention.

FIG. 87 is a perspective view of the multimedia system in accordance with the present invention.

FIG. 88 is a perspective view of the multimedia system in accordance with the present invention, illustrating a portable personal computer close to being docked to the system.

FIG. 89 is a perspective view of the multimedia system showing a portable personal computer docked thereto but with a latch assembly in accordance with the present invention shown in an unlatched position.

FIG. 90 is a side elevational view of the multimedia system in accordance with the present invention showing a portable personal computer close to being docked thereto.

FIGS. 91A, 91B and 91C are exploded perspective drawings of the multimedia system in accordance with the present invention.

FIGS. 92-94 are perspective views of the bottom of the multimedia system in accordance with the present invention partially disassembled.

FIG. 95 is a perspective view of the power supply portion of the multimedia presentation system in accordance with the present invention.

FIG. 96 is a perspective view of the multimedia presentation system showing the bottom cover installed thereto.

FIG. 97 is a perspective view of a portable personal computer in accordance with the present invention with a removable LCD display.

FIG. 98 is a perspective view of a portable presentation system in accordance with the present invention for enabling an LCD display to be used remotely from said personal computer.

FIG. 99 is a bottom view of a stand assembly which forms a portion of the portable presentation system in accordance with the present invention.

FIG. 100 is a perspective view of the stand assembly illustrated in FIG. 99 shown with a bottom cover removed.

FIG. 101 is similar to FIG. 100 but shown with a connector assembly removed.

FIG. 102 is a perspective view of the connector assembly illustrated in FIG. 101.

FIG. 103 is a plan view of the stand assembly in accordance with the present invention shown with the LCD display removed therefrom.

FIG. 104 is similar to FIG. 103 but illustrating the LCD display latched to the stand assembly.

FIG. 105 is an exploded perspective view of an adapter assembly in accordance with the present invention.

FIG. 106 is a perspective view of the housing for the adapter assembly illustrated in FIG. 105 shown with a connector assembly removed.

FIGS. 107 and 108 show the electrical connections to the adapter assembly illustrated in FIG. 106.

FIG. 109 is a partial plan view of a latch assembly on the LCD display shown with the latch assembly in an unlatched position and with a mating bracket on a personal computer removed.

FIG. 110 is similar to FIG. 109 shown with the latch assembly in a latch assembly latched to a mating bracket.

FIG. 111 is an elevational view of the rear of the portable personal computer in accordance with the present invention illustrating the brackets that are adapted to engage the latch assemblies on the removable LCD display and adapter assembly.

FIGS. 112A and 112B are perspective views similar to FIGS. 110 and 109, respectively.

FIG. 113 is a partial exploded perspective view of the latch assembly on the adapter assembly in accordance with the present invention.

FIG. 114 is a partial perspective view of the latch assembly on the adapter assembly shown in an unlatched position.

FIG. 115 is similar to FIG. 114 but with the latch assembly in a latch assembly.

FIG. 116 is a simplified block diagram of the modular portable personal computer in accordance with the present invention.

FIG. 117 is a perspective view of the bottom of the modular personal computer in accordance with the present invention.

FIG. 118 is similar to FIG. 117 showing the modular devices removed.

FIG. 119 is a front elevational view of the modular personal computer in accordance with the present invention illustrating the modular bays.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, a flexible modular connectivity system for a portable personal computer (PC) is shown, generally identified with the reference numeral 100. As shown, the flexible modular connectivity system 100 enables a notebook size PC
102, such as the Z-NOTEFLEX PC, as manufactured by Zenith Data Systems Corporation, in Buffalo Grove, Ill., to be rather easily and quickly connected to various input/output (I/O) devices for use in a desktop application. In particular, as will be discussed in more detail below, the flexible modular connectivity system 100 includes an active port replicator 104, which replicates various ports on the PC 102 including serial, parallel and mouse ports to facilitate use of external I/O devices with the PC 102 in a desktop application and the active port replicator 104 is user-upgradeable to provide additional interfaces for the PC 102 including a PCMCIA and a network interface. In a desktop application, the notebook size PC 102 is docked to the active port replicator 104, which, in turn, may be connected to various I/O devices, such as a desktop size monitor 106 and a printer 108. Such a configuration enables the notebook size PC 102 to be utilized with a full-size monitor 106 and a printer
108 in a desktop application, while eliminating the need for disconnecting such I/O devices when the notebook size PC 102 is used in a portable application and reconnecting the devices 106 and 108 for a desk-type application.

As shown, the desktop size monitor 106 is directly connected to a video port 110, available on the active port replicator 104, with a suitable cable 112. The printer 108, in turn, may either be connected to a parallel port 114 on the active port replicator 104 or may be connected by way of an external flexible bay 116. When the printer 108 is connected by way of the external flexible bay 116, a cable 117 is used to connect the parallel port 114 on the active port replicator 104 to the external flexible bay 116. The printer 108, in turn, is connected to the external flexible bay 116 by way of another cable 118. In this application, the external flexible bay 116 acts as a pass-through device for the parallel port 114 on the active port replicator 104.

In addition to the parallel port 114 and video ports 110, the port replicator 104 may also be configured with a serial port 119 and two type PS/2 ports 120 and 121. The type PS/2 ports 120 and 121 enable an external mouse 122 to be connected to the port replicator 104 by way of a suitable cable 124 and an external keyboard (not shown) for desktop application.

As will be discussed in more detail below, the external flexible bay 116 may be used for either a modular floppy disk drive 125 (FIG. 13) or for charging a modular battery pack 127 (FIG. 10). Moreover, in order to provide optimum flexibility of the system 100, various connection configurations are possible for battery charging. For example, as shown in FIG. 1, a suitably sized AC to DC converter 126 is connected to a source of AC electrical power 128 by way of an appropriate cable 130. In this application, the AC to DC converter 126 is connected both to the active port replicator 104 and the external flexible bay 116 in order to charge the battery pack 127 (FIG. 10), disposed within the external flexible bay 116, as well as a battery pack
127 (FIG. 2) within portable PC 102. As will be discussed in more detail below, the battery pack 127 within the external flexible bay 116 is given charging priority. In particular, the AC to DC converter 126 is connected to a power port 132 on the port replicator 104 by way of a suitable cable 134 (FIG. 1). The power from the AC to DC converter 126 is passed through to the external flexible bay 116 by connecting a suitable cable 136 to an additional power port 138 on the rear of the active port replicator 104.

In an alternate configuration (not shown), the AC to DC converter 126 is connected directly to the external flexible bay 116, which, in turn, is connected to a power port (not shown) on the rear of the PC 102. Alternately, the AC to DC converter
126 can be connected directly with the PC 102 with or without the active port replicator 104 to charge the battery pack within the PC 102. Depending on the configuration used, the capacity of the AC to DC converter 126 must be sized accordingly.

The external flexible bay 116 provides for various configurations for optimum flexibility. More particularly, the external flexible bay 116 may be used as an external floppy disk drive 125 or for charging a spare battery pack 127. For example, a modular battery pack 127 (FIG. 10) may be charged by way of the external flexible bay 116. In this application the battery pack 127 is inserted within the external flexible bay 116, connected as discussed above. In an alternate configuration, the external flexible bay 116 may be used with the modular floppy disk drive 125 (FIG. 13). In this application a floppy disk drive 125, as will be discussed in more detail below, is removed from the notebook size PC 102 as shown in FIG. 2 in order to receive a spare battery pack 127 to provide additional battery capacity for the PC 102 in a portable application.

When the system 100 is configured as illustrated in FIG. 1, the external flexible bay 116 will have two modes of operation under the control of a mode select switch 137 (FIGS. 1 and 7) disposed on the external flexible bay 116. In a floppy drive mode, the external flexible bay 116 acts as an external floppy drive. In a printer mode the external flexible bay 116 merely acts as a pass-through parallel port for the printer 108. In this mode the external floppy drive 125 is disabled as will be discussed below.

The PC 102, adapted to be utilized with the flexible system 100, is illustrated in FIGS. 2 and 3. In particular, the notebook size PC 102 is configured with a flexible bay 141 and a battery pack bay 142. The battery pack bay 142 is configured to receive the modular battery pack 127, as shown. In order to provide additional battery capacity for the PC 100 in a portable application, the flexible bay 141 is adapted to receive either the modular battery pack 127 or the modular floppy disk drive
125. In particular, in order to provide additional battery capacity in a portable application, the modular floppy disk drive 125 may be removed from the flexible bay 141 and may be inserted into the external flexible bay 116. An additional modular battery pack 127 may then be disposed within the battery pack bay 141 to double the battery capacity of the PC 100 for a portable application. As will be discussed in more detail below, the modular floppy drive 125, as well as the modular battery pack
127, are dimensioned to be received within either the flexible bay 141 within the notebook size portable PC 102 or within the external flexible bay 116 to provide optimum flexibility.

EXTERNAL FLEXIBLE BAY

The schematic diagrams for the external flexible bay 116 are illustrated in FIGS. 4A-4E and 5A-5E. The software for the external flexible bay 116 is illustrated in FIGS. 6A-6I. A copy of the source code for the external flexible bay 116 is attached as Appendix A. As will be discussed in more detail below, the external flexible bay 116 is adapted to communicate with the modular battery pack 127 by way of a serial communications link. The modular battery pack 127, as well as the software control of the modular battery pack 127, is disclosed in detail in: "Intelligent Ni-MH Battery Pack with Gas Gauge and Charge Control, Revision 1.0" by Zenith Data Systems, attached as Appendix B, herein incorporated by reference.

Since the AC to DC converter 126 provides the requisite power for the external flexible bay 116, the AC to DC converter 126 is connected to the external flexible bay 116 either directly or by way of the port replicator 104 as illustrated in FIG.
1. As discussed above, the AC to DC converter 126 may be connected to a power port 132, for example, an 8-pin connector 150 on the external flexible bay 116, or alternatively, as shown in FIG. 1 or as discussed above. When the AC to DC converter 126 is connected either directly to the external flexible bay 116 or by way of the port replicator 104 and the cable 136 (FIG. 1), the positive DC voltage from the AC to DC converter 126 is available on the DCIN and CHRGIN pins on the connector 150 (FIG. 4A). The DC voltage from the AC to DC converter 126 is used to develop a power supply VCC3, for example, 3.3 Vdc, for a microcontroller 154 (FIG. 4D). In particular, the DCIN pins on the power port connector 150 are connected to a switching power supply, indicated within the dashed box 156 (FIGS. 4A and 4B). The switching power supply 156 may include resistors 158, 160 and 162; capacitors 164, 166, 168, 170, 172, 174, 176, 178; ferrite bead inductors 180, 182; a wire-wound inductor 184; a Schottky diode
186; a field-effect transistor (FET) 188; and a switching regulator IC 190, such as a Model No. 1147-5, as manufactured by Linear Technology, which includes a power drive output pin Pdrv, which drives the gate of the FET 188.

The output of the switching regulator 156 is serially connected to a linear voltage regulator 192, for example, a Model No. LD2951, by Micrel, which provides a 3.3 volt output, identified as VCC3, for use as a power supply voltage for the microcontroller 154. In order to stabilize the input and output voltages, capacitors 194 and 196 are connected between the input and output pins, IN and OUT, respectively, of the linear voltage regulator 192. Two voltage divider resistors 198 and 200
are selected to provide an output voltage at the output terminal OUT to be 3.3 volts for use by the microcontroller 154.

The external flexible bay 116 is a flexible bay and, as mentioned above, is adapted to be utilized for a modular floppy drive 125 or to charge a modular battery pack 127. When the external flexible bay 116 is used to charge the modular battery pack 127, the circuitry determines the status of the modular battery pack 127 installed in the external flexible bay 116. The modular battery pack 127 when installed in the external flexible bay 116 is given priority over any modular battery pack 127 in the notebook size PC 102. As discussed in detail in copending U.S. patent application Ser. No. 07/975,879, filed on Nov. 13, 1992, hereby incorporated by reference, the charging requirements of the modular battery pack 127 are provided by way of a charge control signal. In particular, the charge control signal controls the amount of charging current to be provided by the AC to DC converter 126 to the modular battery pack 127 as a function of the state of charge of the modular battery pack 127. Since the system 100 is capable of being utilized with a modular battery pack 127 installed within the external flexible bay 116, as well as a modular battery pack 127 installed within the portable PC 102, two charge control signals CHRGCNTRL and CHRGCNTRLI (FIG. 4A) are defined. The charge control signal CHRGCNTRL is used in conjunction with the modular battery pack 127 installed in the external flexible bay 116, while the charge control signal CHRGCNTRLI is used for the modular battery pack
127 installed within the portable PC 102.

The charge control signal CHRGCNTRL for the modular battery pack 127 installed in the external flexible bay 116 is available at a connector 210 (FIG. SD), used to connect the battery pack 127 to the external flexible bay 116. The charge control signal CHRGCNTRLI is available at a connector 212 (FIG. 4A), used to connect the portable PC 102 to the system 100. A pair of multiplexers (MUXES) 214 and 216 (FIG. 4C) are used to control which of the two charge control signals CHRGCNTRL and CHRGCNTRLI are connected to the system 100. Depending on which modular battery pack 127 has priority, the charge control signals CHRGCNTRL and CHRGCNTRLI are amplified by an amplifier 218 whose output forms a charge control output signal CHRGCNTRLO to battery charger 126, available at the connector 150 (FIG. 4A) . As discussed in detail in the above-mentioned copending application, the charge control output signal CHRGCNTRLO controls the amount of charging current supplied by the AC to DC converter 126
(i.e., the current supplied by the AC to DC converter 126 to the CHRGIN terminals on the connector 150 or 212).

The charge control signal amplifier 218 (FIG. 4C) may be configured as an operational amplifier with its inverting input tied to its output, which, in turn, is connected to the charge control output signal CHRGCNTRLO. The charge control signals CHRGCNTRL and CHRGCNTRLI from the modular battery packs 127 from the external flexible bay 116 or the PC 102, respectively, are applied to the noninverting input of the amplifier 218. In particular, the charge control signal CHRGCNTRL is dropped across a resistor 220 and applied to the non-inverting input of the operational amplifier 218 by way of a pair of voltage divider resistors 222 and 224 and the MUX 214. The charge control signal CHRGCNTRLI from the modular battery pack 127 within the PC 102 is applied to the noninverting input of the amplifier 218 by way of the MUX 216 and the voltage dividing resistors 222 and 224. Thus, depending on the states of the MUXES 214 and 216, either the charge control signal CHRGCNTRL or CHRGCNTRLI will be amplified by the amplifier 218 to provide the control signal CHRGCNTRLO to the battery charger 126.

The system 100 is further adapted to sense when the PC 102 is on. In particular, the DC current supplied by the AC to DC converter 126 is dropped across a sensing resistor 226 (FIG. 4A), connected to the DCIN pin on the connector 150 by way of a fuse 228. The voltage drop across the resistor 226 is amplified by an amplifier 230 (FIG. 4C). In particular, the junction between the resistor 226 and the fuse 228 is applied to an inverting input of the amplifier 230 by way of a resistor 232. The other side of the resistor 226 is applied to a noninverting input of the amplifier 230 by way of a resistor 234. The noninverting input of the amplifier 230 is referenced to a predetermined reference voltage by way of the voltage divider resistors 235
and 237 being connected to the output of the VCC3 of the linear regulator 192 (FIG. 4B) . The inverting input is also connected to the output by way of a resistor 239 and connected to ground by way of a resistor 243. The resistors 232, 234, 237 and 243
determine the gain of the amplifier 230 while the resistors 235 and 243 add a DC of f set.

Since the amplifiers 218 and 230 are, in essence, being used as current amplifiers, the negative power supply input -V is grounded. The positive power supply voltage +V is derived from the input voltage from the AC to DC converter 126, available at the DCIN terminal at the connector 150 by way of the resistor 226 and the fuse 228. A capacitor 241 stabilizes the voltage to the input power supply +V of the amplifiers 218 and 230.

As mentioned above, the current-sensing resistor 226 is used to determine when the PC 102 is on to ensure that the maximum composite output current (i.e. DCIN+battery charger) of the battery charger 126 is not exceeded. In particular, the DC current supplied from the AC to DC converter 126 is dropped across the resistor 226, a resistor 235 and a resistor 237 to define a voltage, proportional to the amount of DC current supplied by the AC to DC converter 126. This voltage is read by the microcontroller 154 (FIG. 4D) at port PB4 by way of a voltage divider which includes the resistors 242 and 244 (FIG. 4C). In order to ensure that the signal does not change during the A/D sample period, a low-pass filter (FIG. 4C) is connected between port PB4 and ground. The low-pass filter includes a single capacitor 248 incorporated into the voltage divider network. The microcontroller 154 may be, for example, an SGS Thompson type ST6225 microcontroller, which includes an on-board analog-to-digital converter. As such, the analog voltage signal representing the DC current being supplied by the AC to DC converter 126 may be applied directly to the microcontroller 154.

As will be discussed in more detail below, the modular battery pack 127 installed in the external flexible bay 116 is given priority over the modular battery pack 127 within the notebook size PC 102. The charge control signal CHRGCNTRL is used to read the battery charge level and set an external port PB3. Thus, when the charge level of the modular battery pack 127 within the external flexible bay 116 is low, the output signal on the external port PB3 (FIG. 4C) on the microcontroller 154 will be low, which, as will be discussed in more detail below, will connect the output power from the AC to DC converter 126 to the modular battery pack 127 installed in the external flexible bay 116. More particularly, the DC power from the AC to DC converter 126 is available at the CHARGIN pin on the input port connector 150 (FIG. 4A). This signal CHARGIN is connected to a switch 245, which may be implemented as a FET. In particular, the source terminals of the FET 245 are connected to the CHARGIN pin on the power port connector 150, while the drain terminals of the FET 245 are connected to a positive DC terminal BATT+ on the connector 210 (FIG. 5D) to connect the AC to DC converter 126 to the modular battery pack 127 within the active port replicator 104. The FET 245 is under the control of another switch 247, which may be implemented as a bipolar junction transistor (BJT). A resistor 248 is connected between the base and emitter terminals of the BJT 246 for biasing, while a resistor 250 is serially connected to the base terminal for current limiting. The base terminal of the BJT 247 is normally pulled high by way of a pull-up resistor 252.

When the output port PB3 of the microcontroller 154 is low, another switch 254, also implemented as a BJT, whose collector is connected to the base terminal of the switch 247, causes the switch 247 to close, which, in turn, provides a negative voltage at the gate terminal of the FET 245 by way of the resistors 256 and 258. A biasing resistor 260 and a current-limiting resistor 262 are connected to the BJT 254 as described above.

The switch 247 may also be used to provide a status indication of the charging status of the battery pack 127 within the external flexible bay 116. In particular, a light-emitting diode (LED) 264 may be connected to the collector terminal of the switch 247 by way of a current-limiting resistor 266. A signal DCIN from the AC to DC converter 126, which indicates that the AC to DC converter 126 is plugged in, is applied to the anode of the LED 264. Thus, as long as the switch 247 is closed, indicating that the battery pack 127 in the external flexible bay 116 is being charged, the LED 264 will be conducting, indicating the charging status.

As indicated above, the circuitry is capable of additionally charging the modular battery pack 127 within the PC 102 after the modular battery pack 127 in the external flexible bay 116 has been fully charged. In this situation, the output port PB3 from the microcontroller 154 will be high, indicating that the modular battery pack 127 within the external flexible bay 116 is fully charged. During this condition, the high on the output port PB3 on the microcontroller 154 will bias a switch 268; configured as a BJT with a biasing resistor 270 and a current-limiting resistor 272. The BJT 268 controls a switch 274, for example, a FET, which, in turn, connects the output of the AC to DC converter 126 to the modular battery pack 127 in the PC 102
by way of a power port 212. In this situation the high signal at the output port PB3 on the microcontroller 154 will cause the switch 268 to close, which, in turn, generates a negative voltage at the gate terminal of the FET 274 by way of the resistors
276 and 278.

As discussed above, when the modular battery pack 127 within the external flexible bay 116 is being charged, the CHRGCNTRL signal from the battery pack 127 in the external flexible bay 116 is connected to the current amplifier 218 by way of an analog switch 214. The analog switch 214 is under the control of the BJT 254. In particular, the control line for the analog switch 214 is coupled to the collector terminal of the BJT 254, normally pulled high by way of the pull-up resistor 252. The BJT 254 is under the control of the port PB3 of the microcontroller 154. When the modular battery pack 127 in the external flexible bay 116 is being charged, the output port PB3 will be low, which, in turn, will result in the collector terminal of the BJT 254 being high. This condition will cause the analog switch 214 to close, thus connecting the CHRGCNTRL signal from the modular battery pack 127 within the external flexible bay 116 to the system 100.

During conditions when the modular battery pack 127 within the PC 100 is being charged, the output port PB3 will be high, causing the BJT 254 to close, which grounds the collector terminal, connected to the control line of the MUX 214. Such low voltage will cause the analog switch 214 to open, thus disconnecting the CHRGCNTRL signal from the system 100. During such a condition when the battery pack 127 in the PC 100 is to be charged by the system 100, the charge control signal CHRGCNTRLI is connected to the system 100, while the signal CHRGCNTRL is disconnected from the system 100. The charge control signal CHRGCNTRLI is connected to the system by way of the analog switch 216. The analog switch 216 is under the control of a switch 280, which may be implemented as a BJT, configured with a biasing resistor 282 and a current-limiting resistor 284. The collector terminal of the BJT 280 is normally pulled high by way of pull-up resistor 286. When the switch 280 is closed, the collector terminal is pulled low, causing the analog switch 216 to open, thus disconnecting the charge control signal CHRGCNTRLI from the system 100. Since the charging of the modular battery pack 127 within the external flexible bay 116 and the battery pack 127
within the PC 102 are under the control of port PB3 of the microcontroller 154, during conditions when the modular battery pack 127 within the PC 102 is to be charged, the output of the port PB3 in the microcontroller 154 will be high. This high signal at the output port PB3 will, in turn, cause the BJT 254 to close, which, in turn, will pull the signal to the base terminal of the BJT 280 low, which, in turn, will force the input signal to the analog switch 216 to be high by way of the pull-up resistor
286, to close the analog switch 216 to connect the charge control signal CHRGCNTRLI to the system.

As mentioned above, the external flexible bay 116 is adapted to be utilized as an external floppy drive and also as a passthrough parallel port, which can be used for connection to an external printer 108. As mentioned above, the external flexible bay 116 has two modes of operation. In particular, the system 100 has a floppy drive mode and a printer mode. As will be discussed in more detail below, connections to the modular floppy drive 125 inserted within the flexible external bay 116
are disconnected anytime a printer cable is connected to the external parallel port connector 292 (FIG. 5B) on the exterior of the external flexible bay 116. In this mode, the standard floppy disk drive signals (shown at terminals 19-40 of the connector
210) are disconnected from the connector 290 (FIG. SA) within the flexible external bay 116. When a printer cable is not connected, the standard floppy disk drive signals from the PC 102 will be fed from the parallel port connector 290 (FIG. 5A) through the internal connector 210 (FIG. 5D) to enable the floppy disk drive within the external flexible bay 116 to be under the control of the PC 102.

Referring to FIGS. 5A-5D, a parallel port connector 290 is used to connect to the PC 102. The port 290 is implemented as a 25-pin connector and is connected to a plurality of bus switches 294, 296, 298 and 299; for example, Quick Switch model
24QSOP 10-bit bus switches, by way of a plurality of RF filtering circuits, shown within the dashed box 301. As indicated above, a mode-selector switch 137, for example, a signal pole, single throw switch, is provided on the exterior of the external flexible bay 116 (FIG. 4D). In particular, the switch 137 is connected to port PB2 in the microcontroller 154 by way of a pull-up resistor 303. One side of the switch 137 is connected to the pull-up resistor 303 while the other side is connected to ground. In a first position with the switch 137 open as shown, a high input is applied to the input port PB2 on the microcontroller 154. When the switch 137 is closed, the signal to the input port PB2 is pulled low in order to indicate the position of the switch 137.

The system 100 ascertains the position of the switch 137 to determine whether the mode-selector switch 300 was placed in the floppy mode or the printer mode. In particular, as mentioned above, the position of the switch 137 is monitored by an input port PB2 on the microcontroller 154. Depending on the position of the switch 137, the output ports PB0 and PB1 are used to indicate whether a floppy mode or a printer mode was selected. In particular, the output port PB1 on the microcontroller
154 goes high anytime the floppy mode was selected to generate an active low floppy signal -FLOPPY. More particularly, the output port PB1 on the microcontroller 154 is tied to a switch 304, configured as a BJT. The collector of the BJT 304 is tied high by way of a resistor 306. The -FLOPPY signal is available at the output of the collector. Thus, whenever the floppy mode is selected, the output port PB1 will go high, which closes the switch 304, which, in turn, causes the -FLOPPY signal to go low. Similarly, when the printer mode of operation is selected, the output port PB0 will go high to generate an active low -PRINTER signal. In particular, the output port PB0 is used to control a switch 308, configured as a BJT. The collector of the BJT 308 is tied high by way of a resistor 310. The -PRINTER signal is available at the collector terminal. Thus, anytime the output port PB0 goes high, the switch 308 will close, causing the collector to be tied to ground, forcing the -PRINTER signal low.

These signals, -PRINTER and -FLOPPY, are used to control the bus switches 294, 296, 298 and 299. More particularly, as shown on FIGS. 5B and 5D, the -PRINTER signal is applied to the bus switches 294 and 296 in order to connect the parallel connector 290 to the connector 292 in order to provide standard parallel port signals to the printer 108. Similar to the input side, RF filtering within the dashed box 312 is provided between the bus switches 294 and 296 and the connector 292.

The -FLOPPY signal, in turn, is used to control the bus switches 298 and 299. When the -FLOPPY signal is low, a modular floppy disk drive, installed within the external flexible bay 116 will be connected to the connector 290 by way of the bus switches 298 and 299.

As mentioned above, the modular floppy drive 125 cannot be used when a printer is being used. Thus, a selector switch 300 is used to toggle between a printer mode and a floppy mode. In order to prevent an improper configuration of the system
100, pin 24 on the 25-pin connector 292 (FIG. 5B) is monitored. Normally, when no printer cable is connected to the 25-pin connector 292, pin 24, identified as PNFI, is grounded by way of the switch 320 (FIG. 4D), anytime the mode-selector switch 300 is placed in a floppy mode of operation. In particular, the PNFO signal, available on pin 24 of the connector 290, is connected to the collector terminal of the BJT 320, by way of a resistor 321. The BJT 320, having a biasing resistor 323 connected across its base and emitter terminals, is connected to port PB1 on the microcontroller 154 by way of a current-limiting resistor 325. When a floppy mode is selected, the output port PB1 will be high, causing the BJT 320 to conduct, which, in turn, grounds the signal PNFO through a resistor 321.

A signal PNFI, tied to pin 24 of the 25-pin connector 292, is pulled high by a pull-up resistor 322. Thus, when no printer connector cable is connected to the 25-pin connector 290, the signal PNFI will be high. This signal PNFI is tied to an input port PB5 on the microcontroller 154. As mentioned above, whenever a printer cable is connected to the 25-pin connector 290, the pin 24 on the connector 292 will be connected to ground, which, in turn, will cause the signal PNFI to go low. Thus, depending on the position of the mode selector switch 300 and whether a printer cable is connected to the system 100, as will be discussed in more detail below, the bus switches 294, 296, 298 and 299 will enable either the battery pack 127 or the modular floppy disk drive 125, installed in the external flexible bay 116 to be utilized in the system 100.

The external flexible bay 116 provides status indication of the state of charge of the modular battery pack 127 installed therewithin and whether the floppy mode or printer mode was selected by the mode selector switch 137. In particular, ports PA5 and PA6 of the microcontroller 154 (FIG. 4D) are connected to status indication segments 330 and 332, respectively, of a LCD display 334 on the external flexible bay 116 (FIG. 7) by way of a connector 333 to indicate whether a floppy mode or a printer mode was selected by way of the mode selector switch 137 (FIG. 4D). In addition, ports PA0, PA1, PA2 and PA3 may be connected to a four-segment bar graph 334 (FIG. 7) on the LCD display 334 by way of the connector 333 to indicate the status of charge of the modular battery pack 127 within the external flexible bay 116.

SOFTWARE CONTROL FOR EXTERNAL FLEXIBLE BAY

As mentioned above, the external flexible bay 116 is adapted to receive either the modular battery pack 127 or the modular floppy disk drive 125. The external flexible bay 116 is also adapted to act as a pass-through parallel port for a printer
108. However, as mentioned above, external flexible bay 116 cannot be used as a pass-through parallel port for a printer 108 when a floppy disk 125 is selected for use. Thus, the mode-selector switch 137 allows either a floppy disk drive or a printer mode to be selected when both a printer 108 and floppy disk drive 127 are connected to the system. As will be discussed in more detail below, when the mode-selector switch 137 is set to the floppy disk drive mode, the printer cable, even though its connected to the connector on the external flexible bay 116, is effectively disconnected. Similarly, when a printer mode is selected, the control signals for the modular disk drive 125 are disconnected.

In an alternative configuration, wherein the battery pack 127 is installed in the external flexible bay 116, the system provides a bidirectional data link with the installed modular battery pack 127 to ascertain its charge status. The circuitry for the modular battery pack 127 is disclosed in detail in U.S. patent application Ser. No. 07/975,879, filed on Nov. 13, 1992, assigned to the same assignee as the present invention and hereby incorporated by reference. Once the charge status of the modular battery pack 127 is ascertained, the information is used to arbitrate charging between the modular battery pack 127 installed in the external flexible bay 116 and a modular battery pack 127 installed within the PC 102. The system 100 also has the capability of displaying the battery status of the modular battery pack 127 installed in the external flexible bay 116 on a four-segment LCD bar graph 334 (FIGS. 1 and 7).

The main loop of the software for the microcontroller 154 is shown in FIG. 6A. Initially, on power up, all of the various registers, for example port data and direction registers, interrupt registers, A-D data and control registers and timer registers are initialized in step 400. After the registers are initialized, the microcontroller 154 watchdog timer is reset in step 402. As indicated above, the microcontroller 154 communicates with the modular battery pack 127 installed within the external flexible bay 116 by way of a bidirectional data link. More particularly, two general purpose input/output ports PC6, PB6 and PC7, PB7 on the microcontroller 154 are used. In particular, clock and data signals BATCLK and BATDATA are connected to the PC7 and PC6 ports respectively of the microcontroller 154 by way of analog switches 403 and 405 whose control inputs are tied high to enable one port to be set as an input port and the other port set as an output port, thereby providing a bidirectional data link relative to the microcontroller 154 in the external flexible bay 116. In addition, should power be lost to the microcontroller 154, the analog switches 403 and 405 will disconnect the microcontroller 154 from the modular battery pack 127 to prevent the modular battery pack 127 from backfeeding the microcontroller 154. The BATCLK and BATDATA signals are similarly connected to a pair of general purpose ports on a microcontroller (not shown) within the modular battery pack 127, discussed in detail in Appendix B.

After the watchdog timer is reset, the system checks in step 404 to determine if any data requested from the modular battery pack 127, such as level or status information, has been received. As will be discussed in more detail below, data over the serial data link is shifted one bit at a time. Thus, in step 404, the system ascertains whether the requested data, whether it be status or level information, has been received from the battery pack. If an entire byte from the modular battery pack
127 has been received, the system proceeds to FIG. 6B and processes the data in that byte as will be discussed below. If a complete byte of data from the battery pack is not available, the system proceeds to step 406 and determines whether the mode-select switch 137 has been depressed. If so, the system proceeds to FIG. 6C to configure the external flexible bay 116 according to the particular mode selected. If the mode-select push button 137 was not depressed, the system proceeds to step
408. In this step 408, the floppy disk drive and printer cable are checked, as well as the system level are polled in a periodic basis, for example two seconds. If the poll timer has timed out, the system proceeds to FIGS. 6D and 6E to process the information. If not, the system proceeds to step 410 to determine if a battery process is pending. As mentioned above, battery data between the external flexible bay 116 and the modular battery pack 127 is sent one bit at a time. Thus, if a battery process is pending, the system proceeds to FIG. 6F to process that information. If not, the microcontroller 154 goes into a sleep mode and waits for the next interrupt in step 412.

As mentioned above, if a requested data byte, whether it be status or level information, has been received, the data byte is processed by the flow chart illustrated in FIG. 6B. When data from the modular battery pack 127 is received, a communication flag is set. After the communication flag is detected, it is cleared in step 414. After the communication flag is cleared, the system detects whether the battery present flag has been set in step 416. The battery present status is detected by communication with the battery pack 127 in the external flexible bay 116 by way of a serial data link discussed in Appendix B. If a battery pack 127 is detected in the external flexible bay 116, a flag is set in step 416 to indicate the presence of a modular battery pack 127 in the external flexible bay 116.

As mentioned above, the microcontroller 154 communicates with the modular battery pack 127 installed within the external flexible bay 116 by way of a bidirectional data link. The communication protocol over the data link includes various status and level commands. In order to correctly interpret the data received from the battery pack, the various status and level commands issued by the microcontroller 154 are stored. Thus, in step 418, the system determines if the last command was a status command. As discussed in more detail in copending application Ser. No. 07/975,879, various possible battery status states are possible.

If the last command was not a status command, the system proceeds to step 420 to determine if the last command was a level command. As discussed in more detail in Appendix B, the battery level is determined and converted to a digital value by an onboard 8-bit A to D converter and will return a value between 0 and 64 H to provide a battery level between 0 and 100%. If the command was not a level command, the system proceeds to step 422 where the data byte from the modular battery pack 127 is checked to determine if it was acknowledged. In particular, in addition to battery level as mentioned above, the modular battery pack 127 can return the following six data bytes: BPD ACK-acknowledge; BPD LOW-low battery warning byte; BPD CRIT-critical battery byte; BPD SHUT-shut down byte; BPD FAIL-battery pack failure; and BPD DEAD-battery pack dead. Thus, in step 422, the system compares the received data byte with the acknowledge data byte BPD ACK. If the data byte was acknowledged by the modular battery pack 127, the system exits and returns to the main program in FIG. 6A. If not, the battery command issued by the microcontroller 154 is cleared in step 424.

If the status command is pending as indicated in step 418, the system gets the status byte from the modular battery pack 127 and stores it in step 426. After the status byte from the modular battery pack 127 is saved, the system proceeds to step
428 and again checks whether the last command was a status command. If so, the system proceeds to step 424 and clears the command. If it is determined in step 428 that the last command was not a status command, the system assumes that the last command was a battery level command and gets the battery level in step 430. After the battery level is obtained in step 430, the system analyzes the battery level in step 432 to determine if the battery status is normal. As indicated above, the modular battery pack 127 can communicate back to the microcontroller 154 with various status bytes indicating various status states. If the battery status is normal, the system proceeds to step 434 and checks whether the battery level is less than 95% of the nominal battery capacity. If the battery level is less than 95% of the nominal battery capacity, the system proceeds to step 436 and selects the modular battery pack 127 within the external flexible bay 116 for charging. Bit 3 of the B port of the microcontroller is then pulled low in step 438 in order to direct the charging current to the battery within the external flexible bay 116 and to provide the appropriate charge control signal from the battery pack 127 to the charger 126. Subsequently, the battery command is cleared in step 424, and the system returns to the main loop.

If the level of the modular battery pack 127 within the external flexible bay is greater than 95% the system checks in step 436 to determine if the modular battery pack 127 within the external flexible bay 116 is currently being charged. If so, the system exits to the main loop. If a charge is not in progress, the system selects the modular battery pack 127 within the portable personal computer 102 for charging in step 440. Subsequently, in step 438, bit 3 of port B of the microcontroller 154
is set high in order to enable the modular battery pack 127 within the PC 102 to be charged as discussed above. After port B is set, the battery command is cleared in step 424 and the system exits to the main program.

If the battery status is found to be not normal and not failed, it is assumed that the battery pack 127 is dead and needs to be charged. Thus, in step 432, the system checks the battery flags to determine if the modular battery pack 127 within the external flexible bay 116 has either been removed or has failed in step 442. Should the modular battery pack 127 be removed or have been determined to have failed, the system proceeds to step 440 in order to charge the modular battery pack 127
within the PC 102. If it is determined in step 442 that the modular battery pack 127 has not failed, the modular battery pack 127 within the external flexible bay 116 is selected for charging in step 436 and charged as discussed above.

If, after a data byte is received in step 404, the system determines in step 420 that a level command is pending, the system then proceeds to step 444 and gets the received level. Subsequently, in step 446, the new battery level is compared with the previous level. If the level is the same, the system proceeds to step 428. If not, the new level is saved in step 448 and the flags are then set for the system on/off command to be sent to the battery pack in step 450. After the system on/off command flags are set, the LCD display registers are set up to display the battery capacity by way of the four-segment LCD display in step 452.

As mentioned above, the system is able to detect whether a modular disk drive 125 is installed and whether a printer cable has been connected to the external flexible bay 116. The system also monitors whether the mode-select switch 137 has been depressed. In particular, the mode-select push button 137 is connected to bit 2 of port B on the microcontroller 154. As discussed above, the mode-select switch 137 is normally pulled high by the pull-up resistor 303 (FIG. 4D), causing the input to bit
2 of the input/output port PB to be high. Since the switch 137 is connected to ground, anytime the mode-select switch 137 is depressed to enable either a printer or floppy disk drive to be selected, bit 2 is pulled to ground, indicating a mode selection. Thus, anytime the system determines in step 406 (FIG. 6A) that the mode-select switch 137 has been selected, the system proceeds to FIG. 6C and clears any battery pack communication flags that may be existing in step 454. Once the battery pack communication flags are cleared, the system next checks to determine whether a modular disk drive 125 has been installed in the external flexible bay 116 in step 456. In particular, pin 31 of the connector 210 (FIG. 5D) within the external flexible bay 116 is monitored. This pin 31 is normally pulled high by way of a pull-up resistor 457. Anytime a modular disk drive 125 is installed within the external flexible bay 116, pin 31 (-FDDDET) is grounded. This signal, -FDDDET, is connected to an input port bit 4 on port C of the microcontroller 154. Thus, in order to determine whether or not a modular disk drive 125 is installed in the external flexible bay 116, the microcontroller 154 merely monitors bit 4 of port C. If this bit is high, the system assumes that no modular disk drive 125 is installed. If bit 4 on port C is low, the system assumes a modular disk drive 125 is installed within the external flexible bay 116. If the system determines in step 456 that a modular disk drive 125 is not installed in the external flexible bay 116, the system proceeds to step 458 in order to update bit 1 of port B in order to cause the 10-bit bus switches to disconnect the floppy disk drive signals from the connector 210 (FIG. 5D) within the external flexible bay 116. After the output port is updated, the system proceeds to step 460 and sets a refresh icons flag. After the refresh icons flag is set in step 460, the system returns to the main program.

If the system determines in step 456 that a modular disk drive 125 is installed, the system next checks in step 462 whether the floppy mode has been selected by way of the selector switch 137. If the floppy disk drive mode has not been selected, the system proceeds to step 464 and turns off the printer icons, which may be located on the external flexible bay 116 along with floppy disk drive icons. Subsequently, in step 466, the floppy disk drive icons are turned on and the system then proceeds to step 458 where bit 1 of port B is set in order to configure the bus switches 294, 296, 298 and 299 (FIGS. 5B and 5D) for a floppy disk drive mode of operation as discussed above.

If the system determines in step 462 that the floppy disk drive mode was selected by way of the selector switch 137, the system proceeds to step 468 and turns off the floppy disk drive icons on the LCD display on the external flexible bay 116. After the floppy disk drive icons are turned off, the printer icons are turned on in step 470. After the printer icons are turned on, bit 0 of port B is pulled high in order to configure the bus switches 294, 296, 298 and 299 (FIGS. 5B and 5D) for a printer mode of operation.

As will be discussed below, the microcontroller 154 includes an onboard timer, used to poll the status of the external flexible bay 116, as well as to determine the magnitude of the current on the DCIN line to determine whether the PC 102 is on or off. This information is passed on to the battery pack via serial data link and is used by the microcontroller within the battery pack 127 as an input to the charging algorithm. The status of the above-mentioned states is polled periodically at predetermined time intervals. Every time the time interval times out, a timer process flag is set in the main loop in step 408. After the timer process flag is set, the system proceeds to FIG. 6D and clears the timer process flag in step 472. After the timer process flag is cleared, the mode selector switch 137 is debounced and its state is saved in step 474 to determine the mode of operation selected. After the state of the mode selector switch 137 is saved, the system checks in step 476 whether a modular disk drive 125 has been inserted in the external flexible bay 116 as discussed above If not, a flag is set in step 478 indicating that a modular disk drive 125 has not been installed in the external flexible bay 116 during the current time interval. After the flag is set, the system proceeds to step 480 in order to configure the bus switch 294, 296, 298 and 299 (FIGS. 5B and SD) to disconnect the modular disk drive 125 from the connector 210 (FIG. SD) within the housing of the external flexible bay 116. In addition, the floppy disk drive icon on the LCD is turned off. If a modular disk drive 125 has not been installed in the external flexible bay 116, the system defaults to a printer mode of operation in step 482 and configures the bus switch 294, 296, 298 and 299 (FIGS. 5B and SD) accordingly. In addition, in step 482, the printer icon on the LCD display available on the exterior of the external flexible bay 116 is turned on. Subsequently, in step 484, the output ports on the microcontroller 154 are updated to indicate a printer mode of operation. After the output ports on the microcontroller 154 are updated, the system proceeds to step 486 after which it services the timer in step 488.

If the system determines in the manner discussed above that a modular disk drive 125 has been installed in the external flexible bay 116, the system checks its last status in step 490 to determine if a modular disk drive 125 was installed before. If not, a no floppy disk drive flag is set in step 492 and the system checks and the system goes to step 502 as discussed below. If the modular disk drive 125 was attached before, the system proceeds to step 506 to determine if a printer 108 is attached. If a modular disk drive was previously installed as determined in step 490, the system next determines in step 506 whether a printer cable is connected. In order to determine if a printer connector is connected to the 25-pin connector 292
(FIG. 5B) on the external flexible bay 116, the system monitors pin 24 (PNF1) of that connector. Pin 24 is normally pulled high by a pull-up resistor 322 (FIG. 4D) and connected to port PB5 by way of a resistor 493 (FIG. 5B) which forms a portion of an EMI filter. Thus, normally when no printer cable is connected, bit 5 of port B is high. Once a printer cable is connected to the 25-pin connector on the external flexible bay 116, pin 24 will be pulled low, causing the input to bit 5 of port PB to be low, which indicates that a printer cable is connected. If so, a printer attached flag is set in step 498 and the system defaults to a printer mode and proceeds through steps 480-488.

If the system determines in step 506 that a printer is not connected, the system then checks in step 508 to determine whether a printer was connected during the last time interval. If not, the system proceeds to service the timer in step 488. If it is determined that a printer was previously installed, the system proceeds to step 500 and sets a flag indicating that a printer 108 is not attached to the external flexible bay 116. Subsequently, in step 502, the printer icons are turned of f and the floppy disk drive icons are turned on in step 504, indicating a floppy disk drive mode of operation. Subsequently, the output ports are set in step 484 in order to configure the bus switches 294, 296 298 and 299 for a floppy disk drive mode of operation.

If the system determines in step 490 that a modular disk drive 125 was previously attached, it then proceeds to step 506 to determine if a printer cable has been connected. If not, the system proceeds to step 508 and checks whether a printer cable was connected during the last time interval. If not, the system proceeds to step 488 to service the timer. If so, the system proceeds to step 500 and updates the status flag to indicate that a printer is no longer attached to the system. As indicated above, the status of the modular disk drive 125, the printer cable and the system status are continuously polled at periodic time intervals, for example two seconds. Thus, in step 512, a two-second counter is decremented. The system next checks in step 514 whether the predetermined time interval has expired. If not, the system exits back to the main program. If the two-second time period has expired, the two-second counter is reset in step 516. After the two-second counter is reset, the system reads the status of bit 4 of port B to determine whether the PC 102 is on as discussed above. In particular, the A to D converter onboard the microcontroller 154 is enabled in step 518. After the value is read in step 520, the A to D converter is disabled in step 522. The value received from the A to D converter, which represents the current from the AC to DC converter 126, is then checked in step 524. In particular, the value from the A to D converter is compared with a predetermined value indicative of the PC 102 being ON. If the value from the onboard A to D converter is greater than the predetermined value, the system assumes that the PC 102 is ON. If the external AC to DC converter 126 is plugged into the system, the system next checks in step 526 to determine if the PC 102 was previously ON. If SO, the system proceeds to step 528 and sets a battery process flag, and then exits to the main program.

If, in step 526, the PC 102 was not previously ON, a flag is set in step 530 indicating the same. After the system on flag is set, the system next checks in step 532 whether a modular battery pack 127 is present in the external flexible bay 116. If so, a process on/off flag is set in step 534. If not, the system proceeds to set the battery process flag in step 528.

If the system determines in step 524 that the system is off, the system then checks in step 534 whether the system was on before. If so, a system off flag is set in step 536 and the system then proceeds to step 532 to determine if a modular battery pack 127 is present.

Referring back to the main loop in FIG. 6A, the system determines in step 410 whether any battery processes are pending. If so, the system proceeds to FIG. 6F. In step 530 the system gets the latest command and then checks it to see if the command is a resend command, indicative of a communications problem. If so, the request is cleared in step 534. After the request is cleared, the command is saved in step 536 and sent to the modular battery pack 127 in step 538. Subsequently, the system returns to the main program. If the command is not a resend command, the system next checks in step 540 whether communication is in progress. As will be discussed in more detail below, byte commands are sent to the modular battery pack 127 one bit at a time. Battery status and level data bytes are returned in response to those commands. Anytime a command is being transmitted to the modular battery pack 127 or data is being transmitted back from the modular battery pack 127 within the external flexible bay 116, a communication in progress flag is set. Thus, in step 540, the system checks to determine if the communication in progress flag is set, indicating a communication between the battery pack and the microcontroller 154. If a communication is in progress, the system exits to the main program.

After the communication between the modular battery pack 127 within the external flexible bay 116 and the microcontroller 154 is complete, the communication in progress flag is cleared. Thus, after the communication progress flag is cleared, indicating that the communication is complete between the modular battery pack 127 installed in external flexible bay 116 and the microcontroller 154, the system next checks in step 542 whether the latest command is a level command. If not, the system proceeds to step 544 to determine if the latest command is a status command. If the latest command is neither a level command or a status command, the system next checks in step 546 whether the latest command is a system on command indicating that the PC 102 is ON in step 546. If the latest command is not a system on command, the system next checks in step 548 whether the latest command is a system off command. If the latest command is not a system off command, the system assumes that the command was not a valid battery command and exits back to the main program.

Requests for level, status, system on or system off commands are stored in a bit buffer, BPROCESS. Thus, if the system determines in step 542 that the latest command is a level command, the bit corresponding to a send level command is cleared in the bit buffer in step 550. Subsequently, the level command is stored in a temporary register in step 552 and then saved in step 536.

Similarly, if the system determines in step 544 that the latest command was a status command, the bit corresponding to a status command request is cleared in the bit buffer in step 554. Subsequently, the status command is stored in a temporary register in step 556 and then saved in step 536.

The system on and system off commands are treated in much the same manner. In particular, if the system determines in step 546 that the latest command is a system on command, the bit corresponding to a system on send is cleared in the bit buffer in step 558. Subsequently, the command is stored in a temporary register in step 560 and later saved in step 536 and sent to the battery pack within the external flexible bay 116 in step 538. Should the system determine in step 548 that the latest command is a system off command, the bit corresponding to a system off command is cleared in the bit buffer in step 562. Subsequently, the command is stored in a temporary register in step 564.

As will be discussed in FIGS. 6G, 6H and 6I, battery commands are sent between the microcontroller 154 and the modular battery pack 127 within the external flexible bay 116 or the PC 102 by way of the bidirectional data lines BATCLK and BATDATA. As mentioned above, commands such as status level, system on and system off are formulated as data bytes and sent serially by way of the bidirectional data link one bit at a time. Thus, the flow chart illustrated in FIG. 6G is entered once for each bit either sent or received by the microcontroller 154. The protocol for the data sent between the battery pack and the microcontroller 154 is comprised of eleven bits: a start bit; a stop bit; a parity bit; and 8 data bits. Data is received or transmitted by way of the BATDATA line whenever the BATCLK line is held low.

The system determines in step 566 from the battery process bit buffer whether or not command data is to be sent to the battery pack in the external flexible bay 116 or whether status or level information is to be received back from the battery pack. If command information is to be sent to the modular battery pack 127, the system proceeds to step 568. If no command data is being sent to the modular battery pack 127, the system assumes that data is to be received over the bidirectional data link from the modular battery pack 127 within the external flexible bay 116 or PC 102. After it is determined that the microcontroller 154 is to receive data from the modular battery pack 127, the system next checks to determine if the received bit is the parity bit. As mentioned above, the communications protocol consists of an 8-bit data byte, a start bit and a stop bit, as well as a parity bit. As mentioned above, the flow chart illustrated in FIG. 6G is entered once for each bit sent or received.

Thus, the system keeps track of the number of bits being received to determine whether the parity bit has been received in step 570. If not, the system ascertains in step 572 whether the received bit is a "1". The "1" bits are counted for the purpose of calculating the parity, which for purposes of illustration, may be odd parity. Thus, in step 572, if the system determines that the received bit is a "1", a ones counter is then incremented in step 574. After the ones counter is incremented, the received bit is rotated into a buffer in step 576. If it's determined that the received bit is not a "1" in step 572, the system proceeds directly to step 576 and does not increment the ones counter.

If the received bit is the parity bit, the system checks in step 578 whether the parity bit is a "1", indicative of odd parity. If so, the ones counter is incremented in step 580 as discussed above to calculate the parity. If not, the system proceeds to step 582 to determine if all bits have been received. As indicated above, a protocol for communication from the modular battery pack 127 either in the external flexible bay 116 or PC 102 to the microcontroller 154 consists of an 8-bit data byte, together with a start bit, stop bit and a parity bit. If all of the bits have not been received as indicated in step 582, the system resets the communication timer. In particular, the system allows a predetermined time period, for example, for the clock line BATCLK to be asserted after the bit is read. Thus, if all bits have not been received as indicated in step 582, the system proceeds to step 584 and sets, for example, a three-millisecond timer. After the three-millisecond timer is set in step 584, the system checks to see if the clock line is high in step 586. If the clock line is already high, the system exits, if not, the three-millisecond timer is decremented in step 588. Subsequently, the system checks in step 590 to see if the three-millisecond timer has timed out. If not, the system loops back to step 586 to check if the clock line is high. If the three-millisecond timer has timed out or the clock line has gone high, the system exits.

If, in step 582, the system determines that all bits have been received, the system next checks in step 592 whether there have been any communication errors. If so, the system sets a flag in step 594 indicating a communication error. Subsequently, the system sets a flag for a time-out period for requesting resending of the data byte in step 596. Since all bits were indicated as received in step 582, a flag receive byte is set in step 598 and the system proceeds to step 584 to set the clock line timer as discussed above.

If no line control or communication errors are detected in step 592, the system next checks in step 600 whether there was a parity error. If not, the system sets the received byte flag in step 598 and proceeds to step 584 as discussed above. If a parity error is detected, the system sets a parity error flag in step 602 and then proceeds to step 598 as discussed above.

If data is to be sent to the modular battery pack 127 installed within the external flexible bay 116 or PC 102, the system gets the data and stores it in a temporary register in step 604. Subsequently, since only a single bit is sent at a time, the bit is rotated into position in step 606. Subsequently, in step 608, the system determines whether the bit to be sent is a 1 or a 0. If the bit to be sent is a zero, the battery data line BATDATA is set in step 610 and the bit counter is decremented in step 612. If a 1 is to be sent, the battery data line BATDATA is pulled low in step 614, after which the bit counter is decremented in step 612.

The system next determines in step 616 whether all bits have been sent by examining the bit counter. If less than all the bits were sent, the system proceeds to step 618 and sets the timeout value for the battery clock line BATCLK and subsequently proceeds to steps 584 through 590.

If the system determines in step 616 that all bits were sent, the system next checks in step 620 whether there were any communication errors. If not, the system resets the bit counter in step 622. If there were communication errors, a line error flag is set in step 624. Subsequently, the bit counter is reset in 622, after which a send flag is reset in step 626. After the send flag is reset, the system executes steps 618 and 584-590 to control the timer for control of the battery clock line BATCLK as discussed above.

HARDWARE FOR THE EXTERNAL FLEXIBLE BAY, MODULAR BATTERY PACK AND MODULAR DISK DRIVE

The hardware for the external flexible bay 116 is shown in FIGS. 7-9. The hardware for the external battery pack 127 is shown in FIGS. 10-12. The hardware for the modular disk drive 125 is shown in FIGS. 12-15.

Referring first to FIGS. 7-9, the external flexible bay 116 may be configured with a two housing defining a base portion 652 and a cover portion 654 (FIG. 8). The circuitry illustrated in FIGS. 4A-4D and 5A-5D is carried by a printed circuit board (PCB) 656 (FIG. 9) which may be secured with suitable fasteners 658. The parallel port connectors 290 and 292 (FIGS. 5A and 5B) may be carried by a rear panel portion 660, which may be removable and connected to the PCB 656 as discussed above. The connectors 150 and 212 (FIG. 4A) may be rigidly carried by side wall portions 662 and 664 of the base portion 652 and connected as discussed above. The connector 333 (FIG. 9) may be carried by the PCB 656 and connected to the various displays on the cover portion 654, discussed above.

A pair of interior side walls 666 and 668 are formed within the base portion 652 to receive either the modular disk drive 125 or the modular battery pack 127. A pair of interior backstop 670 with a centrally disposed generally rectangular notch
672 is disposed generally perpendicular to the interior side walls 666 and 668 to define a cavity 669. The connector 210 is aligned with the interior backstops 670 and disposed within the notch 672 to ensure adequate insertion of either the modular disk drive 125 or the modular battery pack 127. As will be discussed in more detail below, the base portion 652 is formed with a recessed portion 674 at an insertion end of the cavity 669 to cooperate with covers 676 and 678 (FIGS. 10 and 15) formed on the modular battery pack 127 and modular disk drive 125, respectively, which compensate for the different widths of the modular disk drive 125 and modular battery pack 127.

The modular battery pack 127 is illustrated in FIGS. 10-12. The modular battery pack 127 includes a generally box-shaped base portion 680, whose width is sized to fit between the interior side walls 666 and 668 (FIG. 8) of the external flexible bay 116 as well as within the bays 141 and 142 on the PC 102 (FIG. 3). The base portion 680 is open on top and closed by a cover 681 (FIG. 11) by suitable means, for example by sonic welding or with an adhesive. A plurality of serially connected battery cells 682 may be disposed within the base portion 680 and connected to a PCB 684 which contains the circuitry described in the above-mentioned copending patent application. The PCB 684 is connected via a flexible cable (not shown) to a connector
685 in a rear wall portion 686 of the base portion 680 for mating with connector 210 (FIGS. 5D and 9) within the external flexible bay 116.

As mentioned above, the modular battery pack 127 includes a stop 676, rigidly secured to the base portion 680. The stop 676 cooperates with the back stops 670 and 672 within the external flexible bay 116 as well as back stops (not shown) within the PC 102 (FIG. 3) to ensure proper insertion.

The modular disk drive 125 is illustrated in FIGS. 13-15. The modular disk drive 125 includes a box-like base portion 690, open on top, and closed by a cover 692. The base portion 690 including the rigidly attached stop 678 are sized to enable the modular disk drive 125 to be inserted into the external flexible bay 116 or the bay 141 on the PC 102 (FIG. 3). A suitably sized 3.5" floppy disk drive 693, for example a Model No. MD 3661 or 3771, as manufactured by Canon, is installed within the base portion 690. Rectangular cutouts 694 may be formed in the rear wall portion 695 of the base portion 690 to receive a connector 696 (FIG. 15), connected to the floppy disk drive 693 by way of a ribbon cable 698 to enable the modular disk drive 125
to be plugged into the connector 210 (FIG. 5D) within the external flexible bay 116 or a similar connector (not shown) in the bay 141 in the PC 102 (FIG. 3).

A plurality of apertures 700 may be formed in side wall portions 702 and 704 of the base portion 690. The apertures 700 are located to be aligned with apertures 706 on the floppy disk drive 693 when installed within the base portion 690 to enable the floppy disk drive 693 to be securely installed thereto by way of suitable fasteners 708.

In order to enable the floppy disk drive 693 to be removed, the cover 692 may be formed with one or more resilient tabs 710 (FIG. 14). The resilient tabs 710 are adapted to cooperate with generally rectangular apertures 712 disposed in the side wall portions 702 and 704.

As shown, the modular disk drive 125 is described and illustrated for use with the floppy disk drive 693. In such a configuration, the stop 678 is formed with an aperture 714 for receiving a 3.5" floppy disk (not shown). Alternatively, the modular disk drive 125 could be used with a hard disk drive (not shown). In that configuration, a stop similar to the stop 676 for the modular battery pack 127 would be used which may be provided with an external LED (not shown) to indicate access to the hard disk drive.

ACTIVE PORT REPLICATOR

The active port replicator 104, in accordance with the present invention, facilitates desktop and portable operation of a portable PC 102, such as a Z-NOTE-FLEX, as manufactured by Zenith Data Systems in Buffalo Grove, Ill. In particular, the active port replicator 104 is adapted to be connected to the ports on the portable PC such that external I/O devices, such as printers, monitors, keyboards and the like can be connected thereto for desktop operation. During a portable mode of operation rather than disconnecting all of the various external I/O devices, the portable PC 102 is merely disconnected from the active port replicator 104 rather quickly and easily. When it is desired to return to desktop application, the portable PC 102 is merely reconnected to the active port replicator 104.

As mentioned above, the active port replicator replicates various ports on the portable PC 102, such as a serial port, parallel port, video port, type PS/2 port, and a power input port. An additional type PS/2 port may be provided to enable an external keyboard as well as an external mouse to be connected simultaneously. In addition, as will be discussed in more detail below, the active port replicator 104 is user upgradeable to provide a local area network (LAN) interface, such as 10Base-T ethernet interface, and a PCMCIA interface. The PCMCIA interface provides additional PCMCIA slots, for example, two type III PCMCIA slots, which can be used for adding additional memory, a fax modem, or other PCMCIA options.

The active port replicator 104 is illustrated in FIGS. 16-73. In particular, the active port replicator 104 includes a main board 740 (FIG. 68), a LAN board 742 and a PCMCIA board 744 (FIG. 67). The circuitry on the main board 740 is illustrated in FIGS. 16-40. The main board 740 is a passive board that replicates the system ports as discussed above plus provides an additional type PS/2 port. The LAN board 742, illustrated in FIGS. 41-46, provides a 10Base-T ethernet interface. The PCMCIA board 744 may provide two additional type III PCMCIA slots. The PCMCIA board 744 is illustrated in FIGS. 48-64. Finally, the physical details of the active port replicator 104 are illustrated in FIGS. 65-73.

Referring first to FIGS. 16-40, the port replicator 104 interfaces to the PC 102 by way of a 152 contact pinless connector 750 (FIGS. 16A and 7). The connector 750 is adapted to mate with a corresponding connector on the PC 102 to replicate a serial port, parallel port, video port, type PS/2 port and a power input port on the PC 102. In addition, as mentioned above, the active port replicator 104 provides an additional type PS/2 port to enable a keyboard (not shown) and a mouse 122 to be connected to the port replicator 104 simultaneously. In addition to port replication, the main board 740 also provides for battery charging and logic circuitry that provides various signals to the external flexible bay 116 which determines which of the modular battery packs 127 in the PC 102 and the external flexible bay 116 are charged.

Table 1 defines the signals attached to the 152 contacts on the connector 750 while Table 2 defines I/O address and Table 3 defines interrupt assignments. Certain signals, -I0CS16, IOCHRDY and -IOW, are filtered by way of filter circuits which include the resistors 751, 753, 755 and capacitors 757, 759 and 761 (FIG. 16B).

TABLE 1 ______________________________________ Pin Signal Direction Description ______________________________________ 1 GND -- Ground 2 GND -- Ground 3 GND -- Ground 4 LPTSTRB 0 Parallel Port Data Strobe 5 LPTD0 0 Parallel Port Data Bit
0 6 LPTD1 0 Parallel Port Data Bit 1 7 LPTD2 0 Parallel Port Data Bit 2 8 LPTD3 0 Parallel Port Data Bit 3 9 LPTD4 0 Parallel Port Data Bit 4 10 LPTD5 0 Parallel Port Data Bit 5 11 LPTD6 0 Parallel Port Data Bit 6 12 LPTD 7 0 Parallel Port Data Bit 7 13 DTR 0 Serial Port Data Terminal Ready 14 TXD 0 Serial Port Transmit Data 15 RTS 0 Serial Port Request To Send 16 DSR I Serial Port Data Set Ready 17 BC-CTL 0 Battery Pack Charge Control 18 NC-IN I Ninja Battery Charge Input 19 DCIN I Ninja DC In Voltage (+15 V) 20 DCIN I Ninja DC In Voltage (+15 V) 21 BATTGND -- Battery Ground 22 BATTGND -- Battery Ground 23 BATTGND -- Battery Ground 24 RDYLOUT O 25 DRQ7 I DMA Request line 7 26 RDYLINL I 27 AUDGND -- Audio Ground 28 PRPWRON O Port Replicator Power On control 29 ZPORT1 I Z-Port Select line 1 30 SA21 O ISA Bus Address Bit 21 31 SA20 O ISA Bus Address Bit 20 32 SA19 O ISA Bus Address Bit 19 33 SA18 O ISA Bus Address Bit 18 34 SA13 O ISA Bus Address Bit 13 35 SA12 O ISA Bus Address Bit 12 36 SA11 O ISA Bus Address Bit 11 37 SA10 O ISA Bus Address Bit 10 38 SA5 O ISA Bus Address Bit 5 39 SA4 O ISA Bus Address Bit 4 40 SA3 O ISA Bus Address Bit 3 41 SA2 O ISA Bus Address Bit 2 42 ZEROWS I ISA Bus Zero Wait State 43 AEN O ISA Bus Address Enable 44 RSTDRV O Reset Drive 45 BALE O ISA Bus Address Latch Enable 46 MEMR O ISA Bus Memory Write command 47 IOR O ISA Bus I/O Read command 48 SA1 O ISA Bus Address Bit 1 49 SD0 B ISA Bus Data Bit 0 50 SD2 B ISA Bus Data Bit 2 51 SD4 B ISA Bus Data Bit 4 52 SD6 B ISA Bus Data Bit 6 53 SD8 B ISA Bus Data Bit 8 54 SD10 B ISA Bus Data Bit 10 55 SD12 B ISA Bus Data Bit 12 56 SD14 B ISA Bus Data Bit 14 57 IRQ5 I Interrupt Request line 5 58 IRQ11 I Interrupt Request line 11 59 IRQ10 I Interrupt Request line 10 60 IRQ15 I Interrupt Request line 15 61 IRQ3 I Interrupt Request line 3 62 IRQ7 I Interrupt Request line 7 63 IRQ14 I Interrupt Request line 14 64 RDPCACT I PCMCIA Activity 65 MSDATA B Mouse Port Data line 66 TB5V O Track Ball 5 volts 67 TB5V O Track Ball 5 68 VIDRES1 O Video Resolution 1 69 DACGND -- Video DAC ground 70 GREEN O CRT Green gun 71 CRTHSYNC O CRT Horizontal Sync 72 CRTVSYNC O CRT Vertical Sync 73 VIDRES3 O Video Resolution 3 74 GND -- Ground 75 GND -- Ground 76 GND -- Ground 77 GND -- Ground 78 GND -- Ground 79 GND -- Ground 80 LPTAFD O Parallel Port Auto Feed 81 LPTERR I Parallel Port Error 82 LPTINIT O Parallel Port Initialize 83 LPTSLTI O Parallel Port Select In 84 FPNF O Parallel Port Not Floppy control 85 LPTACK I Parallel Port Acknowledge 86 LPTBUSY I Parallel Port Printer Busy 87 LPTPE I Parallel Port Printer Paper Empty 88 LPTSLCT I Parallel Port Printer Select Acknowledge
89 RI I Serial Port Ring Indicator 90 CTS I Serial Port Ciear To Send 91 RXD I Serial Port Receive Data 92 DCD I Serial Port Data Carrier Detect 93 NC-IN I Ninja Battery Charge Input 94 NC-IN I Ninja Battery Charge Input 95 DCIN I Ninja DC in Voltage (+15 V) 96 DCIN I Ninja DC In Voltage (+15 V) 97 BATTGND -- Battery Ground 98 BATTGND -- Battery Ground 99 ATCLK O ISA Bus Clock 100 RDYROUT O 101 DACK7 O DMA Acknowledge Line 7 102 RDYLINR I 103 AUDGND -- Audio Ground 104 RDPCSPK I PCMCIA PC Speaker Input 105 ZPORT0 I Z-Port Select Line 0 106 PRRDY I Port Replicator Ready (Power OK) 107 RFSH O ISA Bus Refresh 108 SA22 O ISA Bus Address Bit 22 109 SA23 O ISA Bus Address Bit 23 110 SA14 O ISA Bus Address Bit 14 111 SA15 O ISA Bus Address Bit 15 112 SA16 O ISA Bus Address Bit 16 113 SA17 O ISA Bus Address Bit 17 114 SA6 O ISA Bus Address Bit 6 115 SA7 O ISA Bus Address Bit 7 116 SA8 O ISA Bus Address Bit 8 117 SA9 O ISA Bus Address Bit 9 118 IOCS16 I ISA Bus I/O Chip Select 16 119 TC O ISA Bus Terminal Count 120 SBHE O ISA Bus System Byte High Enable 121 MEMCS16 I ISA Bus Memory Chip Select 16 122 IOCHRDY I ISA Bus I/O Channel Ready 123 MEMW O ISA Bus Memory Write Command 124 IOW O ISA Bus I/O Write Command 125 SA0 O ISA Bus Address Bit 0 126 SD1 B ISA Bus Data Bit 1 127 SD3 B ISA Bus Data Bit 3 128 SD5 B ISA Bus Data Bit 5 129 SD7 B ISA Bus Data Bit 7 130 SD9 B ISA Bus Data Bit 9 131 SD11 B ISA Bus Data Bit 11 132 SD13 B ISA Bus Data Bit 13 133 SD15 B ISA Bus Data Bit 15 134 IRQ9 I Interrupt Request Line 9 135 DACK1 O DMA Acknowledge Line 1 136 DRQ1 I DMA Request Line 1 137 IRQ4 I Interrupt Request Line 4 138 IRQ12 I Interrupt Request Line 12 139 QPTISMI I OPTI Chip System Management Interrupt 140 RDPCRI I PCMCIA Ring Indicator 141 MSCLK I Mouse Port Clock 142 KBCLK I Keyboard Port Clock 143 KBDATA B Keyboard Port Data 144 VIDRES0 O Video Resolution 0 145 RED O CRT Red Gun 146 DACGND -- Video DAC ground 147
DACGND -- Video DAC ground 148 BLUE O CRT Blue Gun 149 VIDRES2 O Video Resolution 2 150 GND -- Ground 151 GND -- Ground 152 GND -- Ground ______________________________________

TABLE 2 ______________________________________ IO Port (hex) Description ______________________________________ 300-31F LAN Module option A (default) 320-33F LAN Module option B 340-35F LAN Module option C 360-37F LAN Module option D 3E0
PCMCIA Module controller index register 3E1 PCMCIA Module controller data register ______________________________________

TABLE 3 ______________________________________ IRQ Line Description ______________________________________ 3 LAN Module Option 1/PCMCIA Module Controller 4 PCMCIA Module Controller 5 LAN Module Option 2/PCMCIA Module Controller 7 PCMCIA Module Controller 9 LAN Module Option 3 (default)/ PCMCIA Module Controller 10 PCMCIA Module Controller 11 PCMCIA Module Controller 12 PCMCIA Module Controller 14 PCMCIA Module Controller 15 LAN Module Option 4/PCMCIA Module Controller ______________________________________

Various signals from the connector 750, including the address signals SA[0:23], the data signals SD[0:15] and various control signals are provided with radio frequency interference (RFI) filters. These RFI filters include the resistors 752 to
862 (FIG. 17) and a plurality of capacitors 864-974 (FIGS. 19, 23-25).

Five (5) volt power supplies ETHVCC and PCMCVCC are generated by the network board 742 (ETHVCC) and the PCMCIA board 744 (PCMCVCC), respectively, and are ORed to the main board 740 by way of a pair of diodes 976 and 977 and coupled by way of an in-line ferrite bead inductor 975 (FIG. 20). In particular, connectors for the PCMCIA board 744 and the LAN interface card 742 are identified by the reference numerals 1000 and 1002 and illustrated in FIGS. 21 and 22, respectively. As will be noted therein, the 5 volt power supply PCMCVCC for the PCMCIA card 744 is available from terminals 13 and 47 of the connector 1000 while the 5 volt power supply for the LAN card 742 is available from terminals 54 and 56 of the connector 1002. The 5 volt power supplies PCMCVCC and ETHVCC are used to develop the five volt supply PRVCC5 for the main board. The 5 volt power supply PRVCC5 on the main board 740 is used primarily as power for the quick switches and pulling up various address, data and control lines by way of the pull-up resistors 1004-1102 as illustrated in FIGS. 26 and 27 to prevent the signals to the PCMCIA board 744 from floating. A pair of transistors 979 and 981 and biasing resistors 983 and 985 may be used as an alternative to the diodes 976
and 977 as shown in FIG. 20 to reduce spurious triggering of the supervisory IC 1104 (FIG. 28), which monitors the 5 volt supply and generates a reset to the LAN board 742 and PCMCIA board 744 at initial power up and any subsequent power failure. The power supervisory circuit is also used to disable the bus switches 1112 and 1124 when power to the PC 102 is turned off to prevent backpowering of the PC 102.

In order to prevent various external I/O devices from backpowering the main board 740, a power supervisory circuit is illustrated in FIG. 28 which monitors the 5 volt power supply PRVCC5 and, as will be discussed below, will disconnect the accessory boards 742 and 744 from the main board in the event of a loss of power in the PC 102. In particular, the 5 volt power supply voltage PRVCC5 is applied to a microprocessor supervisory IC 1104, for example, a Maxim model MAX 707, by way of input resistors 1106, 1108 and 1110 (FIG. 28). As will be discussed in more detail below, the output of the microprocessor supervisory IC 1104 includes an active high reset RESET, used as a control signal to control a plurality of bus switches 1112-1124 (FIG.
18), which, in turn, are used to disconnect the PCMCIA board 744 and LAN board 742 from the main board 740 when power to the PC 102 is unavailable. In particular, as discussed above, the 5 volt power supply voltage PRVCC5 is generated by the PCMCIA board 744 and LAN board 742. Accordingly, when the PC 102 is on, it generates a power on signal PRPWRON, which, in turn, enables the LAN card 742 and PCMCIA card 744 power supplies ETHVCC and PCMCVCC which allow the supervisory circuit to release the RESET status. When the reset signal RESET on the microprocessor supervisory IC 1104 is high, as will be discussed in more detail below, it will cause the bus switches 1112-1124 to be closed, thereby connecting the PCMCIA board 744 and the LAN board 742
to the main board 740. Conversely, should the power supply to the PC 102 be lost or unavailable, the power supply voltage PRVCC5 will be low. During such a condition, a microprocessor supervisory IC 1104 will cause the bus switches 1112-1124 (FIG. 18) to disconnect the PCMCIA board 744 and LAN board 742 from the main board 740.

The microprocessor supervisory IC 1104 (FIG. 28) is also used to develop other reset signals, such as -PORST, --PRRESET and PRRESET. In particular, the active low output signal -RESET of the microprocessor supervisory IC 1104 is applied to a NAND gate 1128 and pulled low by a pull-down resistor 1130. A power supply signal --QRSTDRV (FIG. 27) is applied to the input of the NAND gate 1128. The power supply signal --QRSTDRV will be low when the power supply voltage PRVCC5 for the main board
740 is unavailable. The output of the NAND gate 1128 generates an active high reset signal PRRESET for the network interface board 742. The active high reset signal PRRESET for the network interface board 742 is applied to pin 19 of the connector 1002.

A NAND gate 1126 is used to generate an active low system reset signal --PRRESET for the PCMCIA board 744. In particular, the active high output signal from the NAND gate 1128 is applied to an input of the NAND gate 1126. The main board power supply voltage PRVCC5 is applied to another input of the NAND gate 1126 to develop the active low reset signal --PRRESET. This reset signal --PRRESET is applied to terminal 92 of the connector 1000 (FIG. 21B) to provide a reset signal for the PCMCIA board 744.

In addition to the reset signals --PRRESET and PRRESET, a power on signal PRPWRON from the PC 102 is also used to cut off power to the LAN board 742 and the PCMCIA board 744 in the event that the power supply to the PC 102 is turned off or unavailable. In particular, referring to FIG. 16A, a power-on signal PRPWRON from the PC 102 is applied to pin 28 of the main connector 750 and is otherwise pulled low by way of a pull-down resistor 1132 (FIG. 16A). This signal PRPWRON, in turn, is applied to pin 19 of the connector 1000 for the PCMCIA board 744 and to pin 9 of the connector 1002 for the LAN board 742. The power on signal PRPWRON will be high after the power supply voltage in the PC 102 is stabilized after power up. Thus, as will be discussed in more detail below, use of the power on signal PRPWRON will prevent power from being applied to the PCMCIA board 744 and the LAN board 742 and thereby also prevents power from being supplied to the main board until the power supply voltage in the PC 102 has stabilized.

Due to the flexibility of the system 100, two pins 29 and 105 (--Zport 1 and --Zport 0) on the connector 750 (FIG. 16A) are used to identify the particular device into which the PC 102 is connected. More particularly, as will be discussed in more detail below, the connector 750 on the active port replicator 104 is adapted to be connected to a mating connector on the PC 102. These two pins, 29 and 105, enable up to four different options to be identified to the PC 102. For example, as illustrated in Table 4 below, various options are possible.

TABLE 4 ______________________________________ ZPORT 1 ZPORT 0 Blank ______________________________________ 0 0 Active 0 1 Passive 1 0 Multimedia 1 1 Not Present ______________________________________

When the active port replicator 104 is furnished with a LAN board 742 and/or a PCMCIA board 744 and connected to the PC 102, both pins 29 and 105 on the connector 750 are low. More particularly, pin 29 is pulled low by way of a pull-down resistor 1134 (FIG. 16A). Pin 105 is pulled low by way of a pull-down resistor 1622 (FIG. 54B) connected to pin 94 of the PCMCIA connector 1620 which mates with connector 1000 and/or the pull-down resistor 1446 (FIG. 45) connected to pin 57 of the LAN board connector 1444 which mates with connector 1002 (FIG. 22) to indicate the presence of a PCMCIA and/or a LAN upgrade. Thus, anytime the active port replicator 104 is connected to the PC 102 and a PCMCIA upgrade or LAN is installed in the port replicator 104, signals --Zport 0 and --Zport 1 will be active low to indicate to the PC 102 that the active port replicator 104 is connected to the rear of the PC 102. Alternately, when neither a PCMCIA nor a LAN upgrade is included in the active port replicator 104, --Zport 0 will be high, which will indicate to the PC 102 that a passive port replicator (i.e. port replicator without a PCMCIA or a LAN upgrade) is connected to the rear of the PC 102. Alternately, as will be discussed in more detail below, the PC 102 is adapted to be connected to a portable multimedia presentation system which provides full multimedia capabilities for the PC 102. When the PC 102 is connected to such a multimedia system, the signal --Zport 1 will be high, while the signal --Zport will be low. Lastly, when the PC 102 is not connected to anything (i.e. during portable operation), the signals --Zport 1 and --Zport 0 are pulled high.

As mentioned above, the active port replicator 104 duplicates the standard ports on the PC 102 and provides an additional type PS/2 port to enable both a keyboard (not shown) as well as a mouse 122 (FIG. 1) to be connected to the active port replicator 104 simultaneously. Referring to FIGS. 30-35, the replicated ports are shown. In particular, FIG. 30 illustrates a serial port 1138 configured as a 9-pin connector. Each of the signals for the serial port 1132 with the exception of pin 5
are filtered by way of a plurality of lowpass capacitors 1140-1154 connected to ground. Pin 5 is connected directly to ground. The serial port signals (ADCD, ADSR, --ARXD, ARTS, --ATXD, ACTS, ADTR and ARI) are connected to the 152-pin connector 750 by way of current-limiting resistors 1156-1170, which enables the port replicator 104 to act as a pass-through device to enable the serial port to be replicated at the serial port connector 1138 (FIG. 30).

Similarly, the two type PS/2 ports are illustrated in FIGS. 31 and 32. The PS/2 ports are implemented as 6-pin connectors 1172 and 1174. In particular, the connector 1172 is adapted to be utilized for an external keyboard, while the connector
1174 is adapted to be utilized for an external mouse. Referring first to the keyboard port 1172, pins 1, 4 and 5 are connected to the main connector 750 (FIGS. 16A-16B). In particular, pin 1, representative of keyboard data KBDATA, is connected to pin
143 on the main connector 750 by way of a current-limiting inductor 1176 and filtering capacitors 1178 and 1180. Pin 5, which represents the keyboard clock, KBCLK, is connected to pin 142 of the connector 750 by way of an inductor 1182 and filtering capacitors 1184 and 1186. The power for the keyboard port 1172 is developed by way of the 5 volt power supply TB5V, available at pins 66 and 67 of the main connector 750. In particular, pin 4 of the keyboard port connector 1172 is applied to the 5 volt power supply TB5V by way of a fuse 1188 and filtering capacitor 1189. Pin 3 of the keyboard port connector 1172 is grounded.

Similarly, data MSDATA from the mouse port connector 1174 is connected to pin 65 of the main connector 750 by way of a current-limiting inductor 1188 and filtering capacitors 1190 and 1192. Pin 5 of the mouse port connector 1175 is connected to pin 141 of the connector 750 for the mouse clock MSCLK by way of a current-limiting inductor 1194 and filtering capacitors 1196 and 1198. The power supply for the mouse port 1174 MSPWR is developed from the 5 volt power supply TB5V, available at pins 66
and 67 of the main connector. In particular, pin 4 of the mouse port connector 1174 is applied to the 5 volt power supply TB5V by way of a fuse 1200 and a filtering capacitor 1202.

As mentioned above, the active port replicator 104 also includes a parallel port which includes a 25-pin connector 1204. Each of the standard parallel port signals identified in FIG. 33 are connected to the main connector 750 to enable the port replicator 104 to replicate a standard parallel port available at the PC 102. In particular, each of the pins 1-25 of the parallel port connector 1204 is connected to the main connector 750 by way of a serially coupled current-limiting resistor
1206-1240 and a filtering capacitor 1242-1276.

FIGS. 34 and 35 illustrate a video port which includes a 15-pin connector 1278 and two audio LINE IN and LINE OUT jacks 1280 and 1282. The standard video port signals connected to the video port connector 1278 are connected to the main connector
750 by way of a plurality of resistors 1280-1294, a plurality of inductors 1291, 1293 and a plurality of filtering capacitors 1296-1303. Similarly, the LINE IN and LINE OUT audio jacks 1280 and 1282 are connected to the main connector 750 by way of a plurality of in-line, wire-wound inductors 1304-1310, as well as plurality of capacitors 1312-1330.

As illustrated in FIG. 1, the power from the AC to DC converter 126 is applied to a power port 132 by way of a cable 134. The cable 134 is plugged into a power port 132 and, in tu