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United States Patent
5770964
Suma
June 23, 1998
Title
Arrangement enabling pin contact test of a semiconductor device having clamp protection circuit, and method of testing a semiconductor device
Abstract
A clamp circuit for clamping potential of an internal node electrically connected to an external terminal has its clamping function activated and inactivated selectively in accordance with a control signal generated by a control circuit in response to a forced monitor mode activating signal. An output portion of a substrate potential generating circuit generating a prescribed internal voltage is selectively connected to the internal node in response to a control signal generated from a second control circuit in response to the forced monitor mode activating signal. In a semiconductor device having the clamp circuit for absorbing surge current, pin contact test, external monitoring of an internal potential and external application of the internal potential can be realized.
Inventors:
Suma; Katsuhiro
(Hyogo,
JP
)
Assignee:
Mitsubishi Denki Kabushiki Kaisha
(Tokyo,
JP
)
Appl. No.:
675759
Filed:
July 3, 1996
Foreign Application Priority Data
Aug 29, 1995 [JP] 7-220442
Current U.S. Class:
327/328
327/534
327/327
Field of Search:
327/534,537,546,545,309,318,319,321,327,328,407,408,411,564-566 365/226,229,201
U.S. Patent Documents
5023476
June 1991
Watanabe et al.
5119337
June 1992
Shimisu et al.
5189316
February 1993
Murakami et al.
5321653
June 1994
Suh et al.
5400290
March 1995
Suma et al.
5448199
September 1995
Park
5467026
November 1995
Arnold
5615158
March 1997
Ochoa et al.
Foreign Patent Documents
5-242698
., 1992
JP
6-194424
., 1993
JP
61-232658
., 1985
JP
Other References
Fundamentals of MOS Digital Integrated Circuits, by John P. Uyemura, 1988, Chapter 10, p. 586..~
Primary Examiner:
Tran; Toan
Attorney, Agent or Firm:
McDermott, Will & Emery
Claims
What is claimed is:
1. A semiconductor device, comprising:
first clamping means coupled between an internal node coupled to an external terminal and a first reference voltage source node, for clamping potential at said internal node at a first prescribed potential level; and
control means responsive to a test mode designating signal for generating and applying to said first clamping means, a control signal for inhibiting clamping operation of said first clamping means regardless of the voltage level at said internal node when said test mode designating signal is active.
2. The semiconductor device according to claim 1, wherein
said first clamping means includes at least one first insulated gate type field effect transistor and at least one second insulated gate type field effect transistor connected in series to each other between said internal node and said first reference voltage source node,
said at least one first insulated gate type field effect transistor receiving at a gate thereof a voltage on said first reference voltage source node, and
said at least one second insulated gate type field effect transistor receiving at a gate thereof the control signal from said control means.
3. The semiconductor device according to claim 2, wherein
said at least one first insulated gate type field effect transistor is connected to said internal node, and said at least one second insulated gate type field effect transistor is connected between said first insulated gate type field effect transistor and said first reference voltage source.
4. The semiconductor device according to claim 2, wherein
the second insulated gate type field effect transistor is connected to said internal node, and said at least one first insulated gate type field effect transistor is connected between said internal node and said at least one second insulated gate type field effect transistor.
5. The semiconductor device according to claim 2, wherein
said at least one first insulated gate type field effect transistor and said at least one second insulated gate type field effect transistor both have a first conductivity type.
6. The semiconductor device according to claim 1, wherein
said first clamping means includes one insulated gate type field effect transistor connected between said internal node and said first reference voltage source node and receiving at a gate thereof said control signal from said control means.
7. The semiconductor device according to claim 1, further comprising:
internal voltage generating means operating with the first reference voltage as one operating voltage for generating an internal voltage greater in absolute value than the voltage at said first reference voltage node;
internal voltage connecting means responsive to activation of said test mode designating signal for coupling an output portion of said internal voltage generating means to said internal node, and
said control means includes means for generating said control signal at a voltage level of the output portion of said internal voltage generating means when said test mode designating signal is active.
8. The semiconductor device according to claim 1, wherein
said first clamping means includes at least first and second insulated gate type field effect transistors connected in series between said internal node and said first reference voltage source node; and
said control means includes
first control signal generating means responsive to said test mode designating signal for generating and applying to the gate of said first insulated gate type field effect transistor, a first control signal which attains to such a voltage level that renders conductive said first insulated gate type field effect transistor when said test mode designating signal is active and attains to a voltage level generated by said first reference voltage source when said test mode designating signal is inactive, and
second control signal generating means responsive to said test mode designating signal for generating and applying to the gate of said second insulated gate type field effect transistor, a second control signal which attains to a voltage level transmitted to said internal node when said test mode designating signal is active and attains to the voltage level of said first reference voltage source node when said test mode designating signal is inactive.
9. The semiconductor device according to claim 6, wherein
said control means includes means for generating, as said control signal, a voltage at a voltage level of said first reference voltage source node when said test mode designating signal is inactive, and generating a voltage at a voltage level transmitted to said internal node when said test mode designating signal is active.
10. The semiconductor device according to claim 1, further comprising:
internal voltage generating means for generating an internal voltage greater in absolute value than the voltage of said first reference voltage source node; and
connecting means responsive to said control signal for coupling an output portion of said internal voltage generating means to said internal node.
11. The semiconductor device according to claim 2, further comprising:
internal voltage generating means for generating an internal voltage greater in absolute value than the voltage of said first reference voltage source node; and
connecting means responsive to said control signal for coupling an output portion of said internal voltage penetrating means to said internal node, wherein
said connecting means includes an n channel insulated gate type field effect transistor, and said second insulated gate type field effect transistor is an n channel insulated gate type field effect transistor;
said control means includes means responsive to said test mode designating signal for generating mutually complementary signals for application to the gate of the insulated gate type field effect transistor of said connecting means and to the gate of said second insulated gate type field effect transistor, respectively;
said second insulated gate type field effect transistor receives at the gate thereof a second reference voltage when said test mode designating signal is inactive, difference between the second reference voltage and the first reference voltage being greater than the absolute value of each threshold voltage of the insulated gate type field effect transistors, and receives at the gate a voltage at the output portion of said internal voltage generating means when said test mode designating signal is active; and
the insulated gate type field effect transistor of said connecting means receives at the gate thereof a signal at a voltage level of the output portion of said internal voltage generating means when said test mode designating signal is inactive, and receives at the gate thereof a control signal at said second reference voltage level when said test mode designating signal is active.
12. The semiconductor device according to claim 10, wherein
said first reference voltage source node supplies a ground voltage, and said internal voltage generating means generates a negative voltage lower than said ground voltage.
13. The semiconductor device according to claim 10, wherein
said first reference voltage source node supplies a power supply voltage and said internal voltage generating means generates a high voltage higher than said power supply voltage.
14. The semiconductor device according to claim 2, wherein
said first and second insulated gate type field effect transistors are p channel insulated gate type field effect transistors, and said first reference voltage source node supplies a power supply voltage.
15. The semiconductor device according to claim 1, wherein
said clamping means includes
at least one first insulated gate type field effect transistor of a first conductivity type and at least two second insulated gate type field effect transistors of the first conductivity type connected in series between said internal node and said first reference voltage source node,
said at least one first insulated gate type field effect transistor receiving at a gate thereof a voltage from said first reference voltage source node;
said control means includes
first control signal generating means for applying a first internal voltage to the gate of one of said two second insulated gate type field effect transistors when a first test mode specifying signal of said test mode designating signal is active, and applying to the gate of said one insulated gate type field effect transistor a voltage enabling formation of a channel therein when said first test mode specifying signal is inactive, and
second control signal generating means for generating a second internal voltage for application to the gate of the other one of said at least two second insulated gate type field effect transistors when a second test mode specifying signal of said test mode designating signal is active, and for generating a voltage allowing formation of a channel in said the other insulated gate type field effect transistor for application to the gate of said the other insulated gate type field effect transistor when said second test mode specifying signal is inactive; wherein
when said test mode designating signal is inactive, one of said first and second test mode specifying signals is activated and the other is kept inactive.
16. The semiconductor device according to claim 15, further comprising:
a first connection gate responsive to activation of said first test mode specifying signal for connecting said internal node to an output portion of a first internal voltage generating means generating said first internal voltage; and
a second connection gate responsive to activation of said second test mode specifying signal for coupling an output portion of a second internal voltage generating means generating said second internal voltage to said internal node.
17. The semiconductor device according to claim 1, further comprising:
second clamping means coupled between said internal node and a second reference voltage source node different from said first reference voltage source node for clamping voltage at said internal node at a second clamp level; and
second control means responsive to activation of a second test mode designating signal for generating and applying to said second clamping means a control signal which inactivates clamping function of said second clamping means.
18. The semiconductor device according to claim 17, wherein
said second clamping means includes at least one first insulated gate type field effect transistor receiving at a gate thereof a voltage of said second reference voltage source node, and at least one second insulated gate type field effect transistor in which a channel is selectively formed in response to said control signal,
said first and second insulated gate type field effect transistors being connected in series to each other between said second reference voltage source node and said internal node.
19. The semiconductor device according to claim 1, further comprising:
internal voltage generating means for generating an internal voltage greater in absolute value than the voltage supplied at said first reference voltage source node;
connection control means responsive to said test mode designating signal for coupling an output portion of said internal voltage generating means to said internal node; and
stopping means responsive to activation of said test mode designating signal for inactivating said internal voltage generating means to stop internal voltage generating operation.
20. A semiconductor device, comprising:
internal voltage generating means for generating an internal voltage of a prescribed level different from a level of an internal operating power supply voltage;
means, responsive to activation of a test mode designating signal, for stopping internal voltage generating operation of said internal voltage generating means; and
means for applying an externally applied voltage to output portion of said internal voltage generating means in response to said test mode designating signal being active.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a protection circuit for clamping potential at an internal node connected to an external terminal, and to a method of testing therefor. More specifically, the present invention relates to an arrangement and method for setting potential of an internal node exactly at a prescribed voltage level.
2. Description of the Background Art
Various semiconductor devices such as microcomputers, memory devices and gate arrays are embedded in various electric products including personal computers and work stations. Of these semiconductor devices, many are formed by MOS transistors (insulated gate type field effect transistors) which are suitable for higher degree of integration and lower power consumption. A DRAM (Dynamic Random Access Memory) is known as a memory constituted by MOS transistors. Memory capacity of the DRAM has been much increased recently, and it comes to be used as a main memory for a personal computer or a work station. Since personal computers and work stations come to have higher performance at lower cost, the DRAM is also required of higher performance at lower cost. However, various characteristics tests necessary for providing high performance and highly reliable DRAM products come to be ever complicated, which results in longer test time, which in turn results in higher product cost.
In order to cope with this problem, in logic devices such as microcomputers and gate arrays, a testability function has been long incorporated in the step of design, so as to facilitate tests. However, also in a semiconductor memory, testability design comes to be essential to solve this problem. As one such testability design, there is JEDEC (Joint Electron Device Engineering Counsel) standardized multibit test related to reduction in test time of the DRAM. In the multibit test, data is compressed so as to reduce number of accesses and to reduce test time. More specifically, to a plurality of memory cells which require a plurality of accesses in total in a normal mode, same data is written in only one access in the test mode. The data which have been written to the plurality of memory cells are read in the chip device, and a signal indicating whether or not the logics of the read data coincide with each other is output in one access cycle. Since a plurality of memory cells are tested simultaneously, test time can be significantly reduced as compared with one-by-one testing of the memory cells.
Various test modes not standardized by JEDEC have also been proposed for the DRAM. For example, there is a method realizing a high temperature operation at a room temperature, as disclosed, for example, in Japanese Patent Laying-Open No.
5-242698. In this method, the number of stages of inverters in a delay chain constituted by a plurality of cascade connected inverters for providing a delay to a specific control signal is reduced in the test mode, and a specific access path (data input/output path) related to the delay chain is short-circuited. As the number of stages of the inverters constituting the delay chain is reduced, delay time is reduced, and as the specific access path is short-circuited, time for data transfer is reduced, and hence the operation at a high temperature is equivalently realized by the operation at an ordinary temperature.
Further, there is a method of testing reliability of a semiconductor device by changing a level of a substrate bias voltage applied to a semiconductor substrate region so as to accelerate failure of the semiconductor device associated with the substrate bias voltage.
Further, a method facilitating external monitoring as to whether an internal voltage is at a prescribed voltage level or not by transmitting an internal voltage generated in the device to a specific pad in a test mode, such as disclosed in Japanese Patent Laying-Open No. 6-194424, has been proposed.
Further, in the semiconductor device, various protection circuits are also provided to ensure reliability during normal operation.
FIG. 34 shows the structure of the input protection circuit disclosed, for example, in Japanese Patent Laying-Open No. 61-232658. Referring to FIG. 34, the input protection circuit is connected between an external pin terminal 7 and an internal circuit 11. The input protection circuit includes a resistor 8, for limiting current, connected between an input node NA of internal circuitry 11 and external terminal 7, a P+/N- junction diode 9a connected in forward direction between internal node NA and a power supply node VCC, and a P-/N+ junction diode 9b connected in reverse direction between internal node NA and a ground node VSS.
Internal circuit 11 has a structure of CMOS inverter constituted by a p channel MOS transistor 11a and an n channel MOS transistor 11b, which inverts a logic of a signal applied to internal node NA for transmission to another internal circuit. Internal circuit 11 simply has a function of an input buffer.
P+/N- junction diode 9a and P-/N+ junction diode 9b have junction breakdown voltages increased, by increasing impurity concentration at portions which are connected to the internal node NA. The operation will be briefly described.
Now, forward voltage drop of junction diode 9a is represented by V9a and forward voltage drop of junction diode 9b is represented by V9b. When the voltage VA at internal node NA becomes equal to or higher than VCC+V9a, junction diode 9a is rendered conductive, preventing the voltage VA at node NA from attaining a voltage level exceeding VCC+V9a. Here, VCC also represents the voltage at power supply node VCC. By contrast, when the voltage VA at node NA becomes equal to or lower than VSS-V9b, junction diode 9b is rendered conductive, supplies current from ground node VSS to internal node NA to increase the voltage at internal node NA, so as to prevent the voltage VA at internal node NA from lowering to be VSS-V9b or lower. Provision of junction diodes 9a and 9b prevents the voltage level at internal node NA from attaining too high or too low when a noise such as surge is applied to external terminal 7, and hence, prevents dielectric breakdown of MOS transistors 11a and 11b caused by application of excessive current to the internal circuit 11. Resistor 8 has a function of preventing breakdown of PN junction caused by a large current flowing through junction diode 9a and/or 9b when excessive voltage is applied to external terminal 7. Further, resistor 8 has a function of suppressing excessive current flow, when such excessive current is generated at external terminal 7.
Since the input protection circuit such as described above is employed, the voltage VA at internal node NA is kept at a voltage level between VCC+V9a and VSS-V9b, application of abnormal voltage to internal circuit can be prevented, and hence malfunction or breakdown of internal circuit 11 caused by abnormal voltage is prevented. Thus reliability of the semiconductor device is ensured.
The semiconductor device is shipped with being sealed in a package by, for example, resin seal. In addition to wafer level tests, the semiconductor device is also subjected to final test before shipment. At this final test, all signals are input/output through an external pin terminal (lead terminal) as the semiconductor device has already been sealed in a package. If, at that time, such an input protection circuit as shown in FIG. 34 is provided and the signal is input/output through external terminal 7, desired test may not be correctly carried out.
FIG. 35 shows an example of an arrangement for internal voltage detection test. FIG. 35 shows an arrangement in which voltage level of a substrate potential VBB generated by a substrate potential generating circuit 15 is externally monitored. Substrate potential generating circuit 15 applies a bias voltage of a negative potential to a p type semiconductor substrate region (well region or semiconductor layer) in a semiconductor memory device, for example, so as to stabilize a threshold voltage of an n channel MOS transistor, to prevent formation of a parasitic MOS transistor and to prevent soft error in the semiconductor memory device. An n channel MOS transistor Q1 for connection, which is rendered conductive in response to a test mode designating signal .phi.c for electrically connecting an output portion of substrate potential generating circuit 15 to internal node NA is provided at the output portion of substrate potential generating circuit 15.
In the normal operation mode, test mode designating signal .phi.c is at a low level corresponding to the level of negative potential VBB, transistor Q1 is off, and the output portion of substrate potential generating circuit 15 is disconnected from internal node NA.
When substrate potential VBB is to be monitored, test mode designating signal .phi.c attains to the high level, and transistor Q1 turns on. The output portion of substrate potential generating circuit 15 is electrically connected to internal node NA, and negative voltage VBB from substrate potential generating circuit 15 is transmitted to internal node NA. Internal node NA is connected to external terminal 7 through resistor 8. Therefore, by externally monitoring the voltage level at external terminal 7, the voltage level of substrate potential VBB generated by substrate potential generating circuit 15 can be detected. Therefore, whether or not the substrate potential generating circuit 15 operates correctly can be identified externally.
However, there is junction diode 9b connected between internal node NA and ground node VSS. Therefore, when the absolute value of the voltage level of substrate voltage VBB transmitted to internal node NA becomes larger than the forward voltage drop V9b of junction diode 9b, junction diode 9b is rendered conductive, clamping the voltage level at internal node NA at the voltage level of -V9b. Therefore, when the absolute value of the negative voltage VBB generated by substrate potential generating circuit 15 becomes larger than the forward voltage drop of junction diode 9b, it becomes impossible to correctly measure the voltage level of the substrate voltage VBB generated by substrate potential generating circuit 15.
More specifically, if the absolute value of negative voltage VBB is larger than the forward voltage drop V9b (=Vclamp) of junction diode 9b as shown in FIG. 36, the voltage level of negative voltage VBB transmitted to internal node NA is clamped by junction diode 9b, and hence the voltage VMON monitored at external terminal 7 would not be the actual voltage level of negative voltage VBB, but rather the voltage level of clamp level Vclamp (=V9b) which is higher than the actual level by the potential .DELTA.V. Therefore, the voltage VMON externally monitored through external terminal 7 has a voltage level different from that of the negative voltage VBB actually generated by substrate potential generating circuit 15, making it impossible to detect correct potential level.
The junction diode 9b shown in FIGS. 34 and 35 is used for an IF leak test which will be described later, and hence it is not possible to remove the junction diode 9b.
FIG. 37A shows an arrangement for IF leak test (pin contact test). As shown in FIG. 37A, resistor 8 is connected to a pad 70a provided in the periphery of the semiconductor device chip. Pad 70a is electrically connected to external terminal 7
through a bonding wire 70b. In the IF leak test (pin contact test), whether or not the external terminal 7 and pad 70a are surely connected electrically is tested. More specifically, at this test, a negative voltage VEN is applied through an ampere meter 70c to external terminal 7. When the absolute value of negative voltage VEN applied to external terminal 7 becomes larger than the forward voltage drop V9b of junction diode 9b, current IA flows from ground node VSS to external terminal 7 through resistor 8, pad 70a and bonding wire 70b.
FIG. 37B shows voltage-current characteristic at the IF leak test (pin contact test). By determining whether or not the current value IM detected by ampere meter 70c is at a prescribed value or higher when the negative voltage VF of a prescribed voltage level is applied to external terminal 7, it is possible to determine whether or not external terminal 7 and pad 70a are electrically connected reliably.
In order to perform the IF leak test (pin contact test) such as described above, it is not possible to remove junction diode 9b. Therefore, as long as there is junction diode 9b in the input protection circuit, exact external monitoring of the voltage level of the substrate potential VBB generated by substrate potential generating circuit 15 such as shown in FIG. 35 is not possible after the semiconductor device is packed.
Further, in the final test of the semiconductor device, when a test voltage of a desired voltage level is applied from external terminal 7 to an internal node (for example, output portion of substrate potential generating circuit 15 of FIG. 35) different from the internal node NA so as to accelerate failure or operating margin and if the test voltage is a negative voltage, it is impossible to apply a negative voltage of which absolute value is larger than the forward voltage drop of junction diode 9b to the desired internal node, because of the clamping function of junction diode 9b shown in FIG. 34 or 35. Accordingly, internal state of the semiconductor device cannot be externally set, and hence desired characteristic test cannot be performed. The characteristic test includes, as will be described in greater detail later, a test in which pause refresh failure is accelerated by making deeper the substrate bias in the semiconductor memory device.
The above described problems caused by the clamp diode in the input protection circuit are experienced not only when the negative voltage is applied but also when a high voltage is applied.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having internal circuit protection function which allows desired test accurately even after the semiconductor device is sealed in a package.
Another object of the present invention is to provide a semiconductor device in which voltage of a desired level can be exchanged between external and internal nodes during testing, and which can protect internal circuitry from abnormal voltage/current such as external surge in normal operation mode.
A still further object of the present invention is to provide a semiconductor device having internal circuit protection function which allows external monitoring of internal potential after the device is packed in a package, application of external potential to an internal node, and pin contact test.
The semiconductor device in accordance with the present invention includes a first clamp circuit connected between an internal node coupled to an external pin terminal and a first reference voltage source for clamping the potential of the internal node at a first prescribed potential level, and a control circuit responsive to a test mode designating signal for generating a control signal for inhibiting clamping operation of the first clamp circuit and for applying the generated control signal to the first clamp circuit.
A method of testing a semiconductor device in accordance with the present invention includes the steps of applying a test mode designating signal to stop operation of an internal voltage generating circuit, and supplying an external voltage to an output portion of the internal voltage generating circuit.
In the test mode operation, the clamp circuit clamping the internal node at a prescribed potential os inactivated, and hence it becomes possible to accurately apply a voltage of a desired level externally to an internal node without any influence of the clamp level of the clamp circuit, and it becomes possible to externally monitor the voltage at the internal node through an external terminal.
When the test mode designating signal is inactivated, the clamp circuit starts its operation, clamping the internal node at a prescribed potential level. Therefore, test such as pin contact test (IF leak test) can be performed accurately.
Further, since the operation of the internal voltage generating circuit is stopped in test mode operation, it becomes possible to set the internal voltage accurately at the desired voltage level externally, and hence necessary characteristic test can be performed accurately.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 schematically shows a structure of a main portion of a semiconductor device in accordance with a first aspect of the present invention.
FIG. 2 is a diagram of signal waveforms showing the operation of the semiconductor device shown in FIG. 1.
FIG. 3 schematically shows a structure of a main portion of a semiconductor device in accordance with a second embodiment of the present invention.
FIG. 4 schematically shows a structure of a main portion of a semiconductor device in accordance with a third embodiment of the present invention.
FIG. 5 schematically shows a structure of a main portion of a semiconductor device in accordance with a fourth embodiment of the present invention.
FIG. 6 is a diagram of signal waveforms showing the operation of the semiconductor device shown in FIG. 5.
FIG. 7 schematically shows a structure of a main portion of a semiconductor device in accordance with a fifth embodiment of the present invention.
FIG. 8 schematically shows a structure of a main portion of a semiconductor device in accordance with a sixth embodiment of the present invention.
FIG. 9 schematically shows a structure of a main portion of a semiconductor device in accordance with a seventh embodiment of the present invention.
FIG. 10 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 9.
FIG. 11 shows a structure of a modification of the seventh embodiment of the present invention.
FIG. 12 schematically shows a structure of a main portion of a semiconductor device in accordance with an eighth embodiment of the present invention.
FIG. 13 shows a structure of a modification of the eighth embodiment of the present invention.
FIG. 14 schematically shows a structure of a main portion of a semiconductor device in accordance with a ninth embodiment of the present invention.
FIG. 15 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 14.
FIG. 16 schematically shows a structure of a main portion of a semiconductor device in accordance with a tenth embodiment of the present invention.
FIG. 17 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 16.
FIG. 18 schematically shows a structure of a main portion of a semiconductor device in accordance with an eleventh embodiment of the present invention.
FIG. 19 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 18.
FIG. 20 schematically shows a structure of a main portion of a semiconductor device in accordance with a twelfth embodiment of the present invention.
FIG. 21 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 20.
FIG. 22 shows a structure of a modification of the twelfth embodiment of the present invention.
FIG. 23 schematically shows a structure of a main portion of a semiconductor device in accordance with a thirteenth embodiment of the present invention.
FIG. 24 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 23.
FIG. 25 schematically shows a structure of a main portion of a semiconductor device in accordance with a fourteenth embodiment of the present invention.
FIG. 26 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 25.
FIG. 27 schematically shows a structure of a main portion of a semiconductor device in accordance with a fifteenth embodiment of the present invention.
FIG. 28 is a diagram of signal waveforms representing the operation of the semiconductor device shown in FIG. 27.
FIG. 29 schematically shows a structure of a modification of the fifteenth embodiment of the present invention.
FIG. 30 schematically shows a structure of a main portion of a semiconductor device in accordance with a sixteenth embodiment of the present invention.
FIG. 31 is a block diagram schematically showing a structure of a main portion of a semiconductor device in accordance with a seventeenth embodiment of the present invention.
FIG. 32 schematically shows a structure of an internal voltage generating circuit and of a circuit portion generating a forced monitor mode activating signal shown in FIG. 31.
FIGS. 33A to 33C are illustrations related to failure mode acceleration test.
FIG. 34 schematically shows a structure of an input portion of a conventional semiconductor device.
FIG. 35 schematically shows a structure for externally monitoring a substrate potential of a conventional semiconductor device.
FIG. 36 is an illustration showing the problem experienced in the structure of FIG. 35.
FIG. 37A shows a manner of pin contact test of a conventional semiconductor device, and FIG. 37B shows relation between applied voltage and current at the time of pin contact test.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
FIG. 1 shows a structure of a main portion of a semiconductor device in accordance with the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device includes a first clamp circuit 10 for clamping a potential at internal node NA at a prescribed potential; a first protection circuit 20 provided between internal node NA and external terminal 7; and a first control circuit 30 responsive to a test mode designating signal TEST1 for generating and applying to the first clamp circuit 10, a control signal IFG1 inhibiting clamping operation of the first clamp circuit 10.
Internal circuit 11 has similar structure as that shown in FIG. 34, which operates using power supply voltage VCC and ground voltage VSS as operational power supply voltages, performs prescribed buffer processing on a signal at internal node NA and transmits the processed signal to another internal circuit.
First clamp circuit 10 includes an n channel MOS transistor Q3 having one conduction electrode node connected to internal node NA, a gate electrode node coupled to receive ground voltage VSS and another conduction node; and an n channel MOS transistor Q4 connected between MOS transistor Q3 and the ground node (reference voltage source) VSS and receiving, at its gate, the control signal IFG1. In the following description, a voltage source and the voltage applied thereto will be denoted by the same reference characters.
The first protection circuit 20 includes resistors R1 and R2 connected in series between external pin terminal 7 and internal node NA, and an n channel MOS transistor Q2 connected between a connection node of resistors R1 and R2 and the ground node VSS. MOS transistor Q2 has, as a gate insulating film, an element isolating insulating film formed, for example, by LOCOS (Local Oxidation of Silicon), and has a large threshold voltage. The MOS transistor Q2 has its gate and one conduction node both connected to ground node VSS, and hence it has the same function as a diode. Resistor R1 has a function of limiting current to prevent a large current from flowing through MOS transistor Q2, and resistor R2 prevents large current causing malfunction such as breakdown of PN junction from flowing through MOS transistors Q3 and Q4 of the first clamp circuit 10.
The first control circuit 30 includes an inverter IV1 inverting test mode designating signal TEST1; a p channel MOS transistor Q5 connected between power supply node VCC and node B and receiving at its gate the test mode designating signal TEST1; a p channel MOS transistor Q6 connected between power supply node VCC and a node C and receiving, at its gate, an output signal from inverter IV1; an n channel MOS transistor Q7 connected between node B and a node VBB to which a negative voltage is applied, and having its gate connected to node C; and an n channel MOS transistor Q8 connected between node C and node VBB to which a negative voltage is applied, and having its gate connected to node B.
MOS transistors Q7 and Q8 have their gates and drains cross coupled, to form a flipflop. Control signal IFG1 to be applied to MOS transistor Q4 included in the first clamp circuit 10 is output from node B. Test mode designating signal TEST1
changes between ground voltage VSS and power supply voltage VCC. The first control circuit 30 has a level converting function that test mode designating signal TEST1 is inverted and low level of the output signal thereof is converted to the level of the negative voltage VBB, as will be described in greater detail later.
The semiconductor device further includes a substrate potential generating circuit 15 for applying a bias voltage VBB, which is at a prescribed negative potential level, to a substrate region; a second control circuit 40 responsive to the test mode designating signal TEST1 for generating a second control signal Gcnt1; and a first internal potential connecting circuit 60 responsive to the second control signal Gcnt1 from the second control circuit 40 for electrically connecting the output portion of substrate potential generating circuit 15 to internal node NA. The first internal potential connecting circuit 60 is formed by an n channel MOS transistor Q13 connected between internal node NA and the output portion of substrate potential generating circuit 15 and receiving at its gate the second control signal Gcnt1.
The second control circuit 40 includes an inverter IV2 for inverting test mode designating signal TEST1; a p channel MOS transistor Q9 connected between a power supply node (second reference voltage source) and a node D and receiving at its gate test mode designating signal TEST1; a p channel MOS transistor Q10 connected between power supply node VCC and a node E and receiving at its gate an output signal from inverter IV2; an n channel MOS transistor Q11 connected between node D and node VBB to which a negative voltage is applied, and having its gate connected to node E; and an n channel MOS transistor Q12 connected between node E and node VBB to which the negative voltage is applied, and having its gate connected to node D. The second control signal Gcnt1 is output from node E. The nodes VBB to which the negative voltage is applied in control circuits 30 and 40 are coupled to the output portion of substrate potential generating circuit 15. The operation of the semiconductor device shown in FIG. 1 will be described with reference to FIG. 2, which is a diagram of signal waveforms.
In the first protection circuit 20, MOS transistor Q2 has the large threshold voltage. When we represent the threshold voltage of MOS transistor Q2 as V2, MOS transistor Q2 is rendered conductive when the potential at a connection portion between resistors R1 and R2 attains to -V2 or lower, and it supplies current from ground node VSS to the connection portion of resistors R1 and R2. MOS transistor Q2 has a field insulating film as a gate insulating film, and hence it has sufficiently large threshold voltage as compared with the threshold voltages of MOS transistors Q3 and Q4 included in the first clamp circuit 10. Therefore, when a large negative surge voltage is applied to external terminal 7, the large surge current is absorbed by MOS transistor Q2, and hence application of unnecessarily large negative potential to the first clamp circuit 10 is prevented, and hence breakdown of MOS transistors Q3 and Q4 included in the first clamp circuit 10 can be prevented.
A mode for monitoring internal potential and a test mode in which a prescribed voltage is externally applied to a specific internal node will be referred to as forced monitor mode, to be distinguished from the pin contact test (IF leak test).
When the forced monitor mode is inactive, forced monitor mode activating signal TEST1 is at a low level, which is at the level of the ground voltage VSS. In the first control circuit 30, the output signal from inverter IV1 attains to the high level, which is at the level of the power supply voltage VCC, MOS transistor Q5 turns on and MOS transistor Q6 turns off. Node B is charged by MOS transistor Q5, MOS transistor Q8 comes to have larger conductance, and hence the potential at node C is lowered to a voltage level of the node VBB to which the negative voltage is applied. As the potential at node C lowers, gate potential of MOS transistor Q7 lowers, and its conductance becomes smaller. When the potential at node B further increases and reaches the level of the power supply voltage VCC, MOS transistor Q8 turns on, the potential at node C attains to the level of the negative voltage VBB, and MOS transistor Q7 turns off. Therefore, in this state, the first control signal IFG1 output from node B attains to the high level at the level of the power supply voltage VCC.
In the first clamp circuit 10, MOS transistor Q4 is receiving the first control signal IFG1 which is at the level of the power supply voltage VCC, and it is turned on to transmit the ground voltage VSS to one conduction node of MOS transistor Q3. In n channel MOS transistor, a conduction node of which potential is lower serves as a source. In this state, MOS transistor Q3 operates in a diode mode, and when the potential at node NA reaches -V3 or lower (where V3 is the threshold voltage of MOS transistor and VSS=0 V), MOS transistor Q3 is rendered conductive, current flows from ground node VSS to internal node NA, and the potential at internal node NA increases. Therefore, the lowermost potential of internal node NA is clamped at the potential level of -V3.
In the second control circuit 40, as in the first control circuit, the forced monitor mode activating signal TEST1 is at the low level, which is at the level of the ground potential VSS. Therefore, the potential at node D is at the level of the power supply voltage VCC, and the potential at node E is at the level of the negative voltage VBB. Therefore, in the first internal potential connecting circuit 60, the potential level of the second control signal Gcnt1 applied to its gate is the same as the potential at its source (output portion of substrate potential generating circuit 15), and hence the transistor is kept off and the internal node NA is electrically disconnected from the output portion of substrate potential generating circuit 15.
Therefore, in this state, the first clamp circuit 10 and the first protection circuit 20 operate as an ordinary input protection circuit, and pin contact test can be performed by first clamp circuit 10. More specifically, a negative voltage VF (VF<-V3) at a prescribed voltage level is applied to external terminal 7 so as to render MOS transistor Q3 conductive, causing current flow from ground node VSS to external terminal 7. Consequently, whether or not external terminal 7 is electrically connected to internal pad (shown in FIG. 1) can be tested. Therefore, even at the final test after the semiconductor device is packed in a package, pin contact test can be surely performed.
Sometimes, pin contact test is performed with the externally applied power supply potential VCC set at a level lower than the normally used voltage level. When substrate potential generating circuit 15 generates a negative voltage (bias voltage) VBB using the external power supply voltage VCC, it may be possible that the negative voltage VBB has smaller absolute value. Though it depends on the structure of substrate potential generating circuit 15 (which will be described later), where the substrate bias potential is to be generated by utilizing charge pump operation of a capacitor, the lowest potential reached by the negative voltage VBB never exceeds -2.multidot.VCC. The power supply voltage VCC applied to the power supply node VCC is at the level of the external power supply voltage VCC where a single power source structure is employed, and it is at the voltage level of an internal power supply voltage where an internal power supply voltage is generated by down converting the external power supply voltage, utilizing an internal down converting circuit.
In this case, the difference between the power supply voltage VCC and the negative voltage VBB becomes smaller, a gate-source voltage of the MOS transistor is not sufficiently large, so that MOS transistors Q5 and Q8 are not completely turned on and MOS transistors Q6 and Q7 are not completely turned off, in the first control circuit 30, and hence the first control signal IFG1 from node B is possibly maintained at a voltage level between the power supply voltage VCC and the negative voltage VBB. In this case, by applying a negative voltage sufficiently lower (more negative) than the negative voltage VBB to external terminal 7, it becomes possible to render MOS transistors Q3 and Q4 both conductive. When the voltage level at internal node NA is a negative potential level, the sources of MOS transistors Q3 and Q4 are nodes closer to the internal node. Therefore, by the potential at node NA, MOS transistor Q3 turns on, and if the source potential of MOS transistor Q4 is at a potential level lower by more than the threshold voltage V4 of MOS transistor Q4 than the potential level of the first control signal IFG1, MOS transistor Q4 is turned on. Therefore, as the first control signal IFG1 is higher than the negative voltage VBB, pin contact test can be performed by turning on the MOS transistors Q3 and Q4 by applying a voltage more negative than the negative voltage VBB to the external terminal 7.
The high level of the first control signal IFG1 has only to be a voltage level at which MOS transistor Q4 is kept on. If a voltage not lower than the threshold voltage Vth (=V4) is applied, MOS transistor Q4 turns on (assuming that the ground voltage VSS is 0 V), similar effect can be obtained, and hence the high level of the first control signal IFG1 need not be the power supply voltage VCC.
The operation in the forced monitor mode will be described. In the forced monitor mode, forced monitor mode activating signal TEST1 attains to the high level (the level of the power supply voltage VCC: the level of the external power supply voltage or internally down converted power supply voltage).
In the first control circuit 30, the output signal from inverter IV1 attains to the low level of the ground voltage VSS. Consequently, MOS transistor Q5 turns off and MOS transistor Q6 turns on. Node C is charged by MOS transistor Q6, MOS transistor Q7 comes to have larger conductance, node B is discharged through MOS transistor Q7 and has the potential decreased. As the potential at node B lowers, MOS transistor Q8 comes to have smaller conductance, and the speed of discharging of node C slows down. Thus the potential at node C quickly rises to the high level (the level of the power supply voltage VCC), MOS transistor Q7 turns on, and discharges the node B to the negative voltage level of the node VBB to which the negative potential is applied. Therefore, in MOS transistor Q8, the gate potential and the source potential come to be the same with each other, and thus the transistor turns off. Therefore, in this state, the first control signal IFG1 output from node B is at the low level of negative voltage VBB.
Meanwhile, in the second control circuit 40, in response to the activation (high level) of forced monitor mode activating signal TEST1, the potential at node D attains to the level of the negative voltage VBB, and the potential at node E attains to the high level of the power supply voltage VCC. Therefore, the second control signal Gcnt1 attains to the high level, MOS transistor Q13 included in the first internal potential connecting circuit 60 turns on, and the output portion of substrate potential generating circuit 50 is electrically connected to internal node NA. Consequently, the negative voltage VBB generated from substrate potential generating circuit 50 is transmitted to internal node NA. In this case, even when MOS transistor Q3
turns on by the negative voltage VBB, as the first control signal IFG1 is at the level of the negative voltage VBB, in MOS transistor Q4, the gate potential is the same as or lower than the source potential (in an n channel MOS transistor, a conduction node of lower potential serves as a source), and hence MOS transistor Q4 is kept surely off. Therefore, current path is not formed between internal node NA and ground node VSS, and negative voltage VBB generated by the substrate potential generating circuit 15, which has been transmitted to internal node NA, is transmitted to external terminal 7 with its voltage level precisely maintained. Therefore, by externally monitoring the voltage level applied to external terminal 7, whether or not substrate potential generating circuit 15 is generating the negative voltage VBB of a desired voltage level accurately can be determined, and hence whether the substrate potential generating circuit 15 is acceptable or not can be determined.
Now an example is considered in which negative voltage VBB is externally applied and transmitted to the output portion of substrate potential generating circuit 15. The nodes to which the negative potential is applied in the first control circuit 30 and the second control circuit are connected to the output portion of substrate potential generating circuit 15. Therefore, when a negative voltage is externally applied to internal node NA, the negative voltage is transmitted through the first internal potential connecting circuit 60 to substrate potential generating circuit 15, and in response, the negative voltage VBB of the node VBB to which the negative voltage is applied is set to the level of the externally applied voltage. Therefore, the potential level of the first control signal IFG1 which is at the low level attains to the level of the negative voltage externally applied, the voltage level applied to the internal node NA becomes equal to the potential level of the first control signal IFG1, so that MOS transistor Q4 is surely kept off and current path from internal node NA to the ground node VSS can be shut off. Consequently, it is possible to apply a negative voltage of a desired voltage level externally and to transmit the negative voltage through internal node NA to the output portion of substrate potential generating circuit 15, and hence it is possible to appropriately adjust the voltage level of negative voltage VBB externally. A characteristic test which is performed by externally setting the voltage level of the negative voltage VBB will be described in greater detail later.
MOS transistor Q2 included in the first protection circuit 20 has its threshold voltage set to a value sufficiently larger than the voltage level of the externally applied negative voltage. This is to prevent MOS transistor Q2 from being turned on when the negative voltage is applied (V2>.vertline.VM.vertline.: V2 represents threshold voltage of MOS transistor Q2 and VM represents negative voltage applied to external terminal 7).
In the first clamp circuit 10, MOS transistors of the same conductivity type, more specifically, n channel MOS transistors are used. In this case, MOS transistors Q3 and Q4 can be formed in the same well or the same substrate region (though element isolating film is necessary), a region for pn isolation is not necessary, and hence area occupied by the first clamp circuit can be reduced. Further, since MOS transistors included in the first protection circuit 20 are formed by n channel MOS transistors, the first clamp circuit 10 and the first protection circuit 20 can be formed together in the same well, a region for well separation is not necessary, and hence area of occupation can be reduced.
By providing the first control circuit 30 for activating/inactivating the clamping function of the first clamp circuit 10 and the second control circuit for generating a control signal for connecting the output portion of substrate potential generating circuit 15 to internal node NA separatedly from each other, it becomes possible to appropriately arrange the first and second control circuits 30 and 40 in accordance with the arrangement of the first clamp circuit 10 and the first internal potential connecting circuit 60, enabling optimal layout. Further, the first and second control circuits 30 and 40 each drive the gate capacitance of only one MOS transistor, and hence large drivability is not required. Accordingly, area of occupation can be sufficiently made smaller, and hence increase in occupation area in the circuit can be suppressed.
As described above, in accordance with the first embodiment of the present invention, the clamping function of the first clamp circuit clamping the negative voltage level of internal node NA is inactivated when the forced monitor mode is activated. Therefore, in the forced monitor mode, a voltage of a desired voltage level can be externally applied to an internal node, and the level of the internal voltage transmitted to the internal node can be accurately read externally. Further, when the forced monitor mode is inactive, the clamping function of the first clamp circuit is enabled, and hence pin contact test can be performed accurately by applying a negative voltage externally.
Second Embodiment
FIG. 3 shows a structure of a main portion of the semiconductor device in accordance with the second embodiment of the present invention. In the structure shown in FIG. 3, the control signal Gcnt1 for the first internal potential connecting circuit 60 for selectively connecting the output portion of substrate potential generating circuit 15 to the internal node NA and the control signal IFG1 for the first clamp circuit 10 are output from the same control circuit 80. The first protection circuit 20, the first clamp circuit 10 and the first internal potential connecting circuit 60 have the same structure as those shown in FIG. 1, and corresponding portions are denoted by the same reference characters.
Control circuit 80 includes an inverter IV receiving forced monitor mode activating signal TEST1; a p channel MOS transistor Q15 connected between power supply node VCC and a node F and receiving at its gate the forced monitor mode activating signal TEST1; a p channel MOS transistor Q16 connected between power supply node VCC and a node G and receiving at its gate the output signal from inverter IF; an n channel MOS transistor Q17 connected between node F and node VBB to which the negative voltage is applied, and having its gate connected to node G; and an n channel MOS transistor Q18 connected between node G and node VBB to which the negative voltage is applied and having its gate connected to node F. The first control signal IFG1 is output from node F, and the second control signal Gcnt1 is output from node G.
The circuit constituted by MOS transistors Q15 to Q18 has the same structure as the circuit portion of a level converter included in control circuits 30 and 40 shown in FIG. 1. Therefore, when the node F is at the level of the power supply voltage VCC, node G is at the level of the negative voltage VBB, and if node G is at the level of the power supply voltage VCC, the node F is at the level of the negative voltage VBB. As is apparent from the diagram of waveforms shown in FIG. 2, control signals IFG1 and Gcnt1 are complementary to each other. Therefore, by generating mutually complementary control signals IFG1 and Gcnt1 by using one control circuit 80 in accordance with the forced monitor mode activating signal TEST1, the operation of internal potential connecting circuit 60 and of clamp circuit 10 can be similarly controlled as in the first embodiment.
In the structure of the second embodiment shown in FIG. 3, similar effects as in the first embodiment shown in FIG. 1 can be obtained, and in addition, the following effects can be obtained. The first and second control signals IFG1 and Gcnt1
can be generated by one control circuit 80, and hence area occupied by the control circuit can be reduced, and the area occupied by the circuits for activating/inactivating the clamping function can be reduced.
Further, since MOS transistor Q13 included in the first internal potential connecting circuit 60 is arranged near the control circuit 80 and the first clamp circuit 10, the distance between MOS transistor Q13 and internal node NA can be reduced, voltage drop (increase) caused by line resistance between MOS transistor Q13 and internal node NA can be reduced, hence the negative voltage VBB at a received voltage level can be transmitted to internal node NA, and the voltage at a desired voltage level can be accurately supplied to the output portion of substrate potential generating circuit 15 (not shown) in FIG. 3 from internal node NA. Further, since the distance between internal node NA and the first internal potential connecting circuit 60
is small, there is small line capacitance, and hence MOS transistor Q13 even with small current supplying power can sufficiently charge (discharge) the internal node NA to the level of the substrate bias voltage (negative voltage) VBB generated by the substrate potential generating circuit 15, and hence the size of the transistor (channel width or the ratio between channel width and the channel length) can be reduced. Accordingly, gate capacitance of MOS transistor Q13 becomes smaller, and what is required for the control circuit 80 is only to transmit mutually complementary control signals to the gates of MOS transistors Q4 and Q13 through a short line. The gate capacitances to be driven are sufficiently small, and hence large driving power is not required for the control circuit 80. In other words, the size of MOS transistors Q15 to Q18 (channel width or ratio between channel width and channel length) constituting the control circuit 80 can be reduced, and hence area occupied by control circuit 80 can be made smaller.
As described above, according to the second embodiment of the present invention, the operation of the first internal potential connecting circuit and of the first clamp circuit are controlled by generating complementary control signals by one control circuit, the area occupied by the control circuit can be reduced.
Third Embodiment
FIG. 4 shows a structure of a main portion of a semiconductor device in accordance with the third embodiment of the present invention. In the structure of the semiconductor device shown in FIG. 4, the structure of the first clamp circuit 10
differs from that of the first and second embodiments above. The first control signal IFG1 is output from control circuit 30 or 80 shown in FIG. 4. First internal potential connecting circuit 60 for electrically connecting the output portion (denoted by VBB) of the substrate potential generating circuit in response to the second control signal Gcnt1 is provided at internal node NA. The second control signal Gcnt1 may be generated from a second control circuit provided separatedly from control circuit 30 shown in FIG. 4, or it may be generated from the control circuit 80.
The first protection circuit 20 and the internal circuit 11 have the same structures as in the first and second embodiments above.
In the first clamp circuit 10, MOS transistor Q4 receiving at its gate the second control signal IFG1 has one conduction node connected to internal node NA. MOS transistor Q3 is connected between MOS transistor Q4 and ground node VSS. MOS transistor Q3 has its gate connected to ground node VSS.
In the forced monitor mode (in which forced monitor mode activating signal TEST1 is active), when the negative voltage VBB is applied to internal node NA, MOS transistor Q4 is immediately turned off. Therefore, it is possible to maintain the potential level at internal node NA stable at high speed. If MOS transistor Q3 is connected to internal node NA and internal node NA attains to the negative voltage VBB, the negative voltage VBB is transmitted through MOS transistor Q3 to MOS transistor Q4. When the potential at the drain (node connected to MOS transistor Q3) of MOS transistor Q4 attains to the level of the negative voltage VBB, MOS transistor Q4 is turned off. Therefore, in such a structure, there is a difference between the time point at which the voltage at the drain (conduction node connected to MOS transistor Q3) of MOS transistor Q4 reaches the negative voltage VBB by the leakage current of MOS transistor Q3 and the time point at which the prescribed negative voltage VBB is transmitted to internal node NA, which means that a relatively long period of time is necessary until the voltage level of the internal node NA is held at a desired voltage level. Therefore, the voltage at internal node NA cannot be stabilized quickly at the prescribed voltage level quickly. Therefore, if it is necessary to stabilize the voltage at internal node NA at high speed, stabilization at high speed can be accomplished by connecting MOS transistor Q4 receiving at its gate the first control signal IFG1 to internal node NA as shown in FIG. 4.
Except this point, the structure is the same as that described in the first and second embodiments, and similar effects can be obtained.
As described above, according to the third embodiment, the voltage level at the internal node NA can be stabilized at a desired voltage level at high speed.
Fourth Embodiment
FIG. 5 shows a structure of a main portion of a semiconductor device in accordance with the fourth embodiment of the present invention.
In the semiconductor device shown in FIG. 5, the first clamp circuit 10 includes an n channel MOS transistor Q3 having one conduction terminal connected to internal node NA and its gate connected to ground node VSS; and a p channel MOS transistor Q5 connected between MOS transistor Q3 and ground node VSS. To the gate of p channel MOS transistor Q5, complementary control signal /IFG1 applied from node C of control signal generating circuit 30 is applied. Control signal /IFG1 is complementary to the control signal IFG1 shown in the first to third embodiments above.
In the forced monitor mode, control signal /IFG1 attains to the high level, which is at the level of the power supply voltage VCC, and in other operation modes, the signal /IFG1 attains to the level of the negative voltage VBB. Other structures are the same as those of the first or second embodiments above, and corresponding portions are denoted by the same reference characters.
As shown in FIG. 6, when the forced monitor mode is inactive, the signal /IFG1 attains to the level of the negative voltage VBB. When the negative voltage VBB is applied to node NA, MOS transistor Q5 is turned off only when the potential at one conduction node (conduction node connected to transistor Q3) of MOS transistor Q5 becomes lower than the negative voltage VBB. Therefore, as long as a negative voltage shallower than (having smaller absolute value than) the negative voltage VBB is applied to node NA, MOS transistor Q5 is kept off. Therefore, by applying a negative voltage within this range to internal node NA through external terminal 7, pin contact test can be performed, and voltage level at internal node NA can be clamped in normal operation mode.
When the forced monitor mode is activated, signal /IFG1 attains to the high level of the level of power supply voltage VCC as shown in FIG. 6, cutting current path between MOS transistor Q3 and ground node VSS. In this state, MOS transistor Q5
turns on when the potential of one conduction node (node connected to transistor Q3) becomes higher than the level of the power supply voltage VCC applied to its gate. MOS transistor Q3 receives at its gate the ground voltage VSS, and prevents transmission of a higher voltage than voltage VSS level to MOS transistor Q5. Therefore, when the forced monitor mode is activated, MOS transistor Q5 is surely maintained off, and current path between internal node NA and ground node VSS is surely cut off. When the forced monitor mode is inactive, the signal /IFG1 is at the level of the negative voltage VBB, MOS transistor Q5 is on, and MOS transistor Q3 operates in the diode mode, surely clamping the voltage level at internal node NA at a prescribed potential level. Therefore, in the fourth embodiment also, the pin contact test and forced monitor mode for the negative potential can both be implemented.
The control signal Gcnt1 for the first internal potential connecting circuit 60 changes in same phase with the signal /IFG1, and hence it may be generated from node C of the first control signal generating circuit 30, or it may be generated from a separate control signal generating circuit.
As described above, in accordance with the fourth embodiment, even when the first clamp circuit is formed by n and p channel MOS transistors, the similar effects as in the first or second embodiment can be obtained.
The substrate region of the p channel MOS transistor Q5 is connected to internal node NA through MOS transistor Q3. When MOS transistor Q3 is conductive, there is a voltage drop (voltage increase) in MOS transistor Q3, and hence pn junction between impurity region and the substrate region of MOS transistor Q5 will never be biased in forward direction. However, the substrate region of MOS transistor Q5 may be connected to receive power supply voltage VCC.
Fifth Embodiment
FIG. 7 shows a structure of a main portion of a semiconductor device in accordance with a fifth embodiment of the present invention. In FIG. 7, the substrate potential generating circuit and the internal potential connecting circuit are not shown only for simplification of the figure. The semiconductor device shown in FIG. 7 has the same structure as the semiconductor device shown in FIG. 5 except that in the first clamp circuit 10, positions of MOS transistors Q5 and Q3 are exchanged. In FIG. 7, portions corresponding to the structure of FIG. 5 are denoted by the same reference characters and description thereof is not repeated.
When the forced monitor mode is inactive, the control signal /IFG1 is at the level of the negative voltage VBB. In this state, in the first clamp circuit 10, generally the potential at node NA is higher than the gate potential of MOS transistor Q5, a channel is formed in MOS transistor Q5, and the potential at internal node NA is transmitted to MOS transistor Q3. When the voltage level at internal node NA reaches the level of the negative voltage VBB, the gate and source potentials of MOS transistor Q5 become equal to each other, and MOS transistor Q5 turns off. When pin contact test is to be performed, by applying a voltage between negative voltage VBB and -V3, a current path is formed between internal node NA and ground node VSS, and hence desired pin contact test can be performed. Here, V3 represents the threshold voltage of MOS transistor Q3. In the normal operation mode also, the potential at internal node NA is transmitted to MOS transistor Q3 as long as it is more negative than the potential level of negative voltage VBB, and hence desired clamping function can be realized.
When the forced monitor mode is active, control signal /IGF1 attains to the high level, which corresponds to the level of power supply voltage VCC. As long as the internal node NA is lower than the power supply voltage VCC level, MOS transistor Q5 is kept off, as its gate potential is higher than the source potential. Therefore, when a negative voltage is externally applied to internal node NA or the output portion of a substrate potential generating circuit, not shown, is connected to internal node NA through the internal potential connecting circuit, MOS transistor Q5 is surely off, and hence there is not a leak current to MOS transistor Q3. Therefore, the potential level at internal node NA can be set to a desired voltage level quickly, and hence the start point of test can be made earlier.
As described above, according to the fifth embodiment of the present invention, a p channel MOS transistor is connected to internal node NA and a control signal is applied to its gate, so that when the potential at the internal node attains to the negative potential level of a desired voltage, the p channel MOS transistor Q5 is surely turned off, and hence the voltage level at internal node NA can be stabilized at the prescribed voltage level quickly. As in the first to fourth embodiments, both pin contact test and forced monitor mode can be implemented.
Sixth Embodiment
FIG. 8 shows a structure of a main portion of a semiconductor device in accordance with the sixth embodiment of the present invention. The structure shown in FIG. 8 is the same as that of the embodiment shown in FIG. 5 except that the control signal generating circuit 80 generates the first control signal /IFG1 as well as the second control signal (connection control signal) Gcnt1. The first internal potential connecting circuit 60 includes an n channel MOS transistor Q13. The p channel MOS transistor Q5 included in first clamp circuit 10 and n channel MOS transistor Q13 in the first internal potential connecting circuit 60 are turned on/off complementarily. Therefore, by applying signals /IFG1 and Gcnt1 changing in the same phase to the gates of MOS transistors Q5 and Q13, these MOS transistors Q5 and Q13 can be turned on/off complementarily.
In the structure of the sixth embodiment shown in FIG. 8, two control signals are generated by one control signal generating circuit 80, and area occupied by the circuit can be reduced. Further, since operations of first clamp circuit 10 and first internal potential connecting circuit 60 are both controlled by one control signal generating circuit, activation/inactivation of these circuits can be surely performed complementarily, and therefore it becomes unnecessary to adjust timings for activating/inactivating these circuits.
In the sixth embodiment, it is possible to reduce the length of internal interconnection between internal node NA and the first internal potential connecting circuit 60, and accordingly, as in the second embodiment above, the size (channel width) of MOS transistor Q13 can be made smaller. Control signal generating circuit 80 have only to drive a small gate capacitance, and hence size of components (channel width, ratio of channel width and channel length) can be reduced, and hence scale of the control signal generating circuit 80 can be reduced. Therefore, area of occupation can be made smaller.
In the structure shown in FIG. 8, the positions of MOS transistors Q3 and Q5 may be exchanged.
Seventh Embodiment
FIG. 9 shows a structure of a main portion of a semiconductor device in accordance with the seventh embodiment of the present invention. In FIG. 9, the internal potential connecting circuit and the substrate potential generating circuit are not explicitly shown, for the simplicity of the figure. The first protection circuit 20 and the internal circuit 11 have the same structures as those described in the embodiments above. The first clamp circuit 10 for clamping the potential (negative potential) at internal node NA at a prescribed potential level includes an n channel MOS transistor Q18 coupled to internal node NA and receiving at its gate the control signal /IFG1, and an n channel MOS transistor Q19 connected between MOS transistor Q18 and the ground node VSS and receiving at its gate the control signal IFG1.
The control signals /IFG1 and IFG1 for controlling activation/inactivation of clamping operation of the first clamp circuit 10 are output from a control circuit 90. Control circuit 90 includes an inverter IV1 receiving the forced monitor mode activating signal TEST1; a p channel MOS transistor Q4 connected between power supply node VCC and internal node B and receiving at its gate the signal TEST1; a p channel MOS transistor Q6 connected between power supply node VCC and node C and receiving at its gate an output signal from inverter IV1; an n channel MOS transistor Q7 connected between node B and node VBB to which the negative voltage is applied, and having its gate connected to node C; and an n channel MOS transistor Q8 connected between node C and node VBB to which the negative voltage is applied and having its gate connected to node B. Control signal IFG1 is output from node B. Transistors Q5 to Q8 have level converting function, and control signal IFG1 changes between power supply voltage VCC and negative voltage VBB.
Control circuit 90 further includes an inverter IV4 receiving forced monitor mode activating signal TEST1; a p channel MOS transistor Q14 connected between power supply node VCC and node F and receiving at its gate the signal TEST1; an n channel MOS transistor Q16 connected between node F and ground node VSS and having its gate connected to node G; and an n channel MOS transistor Q17 connected between node G and ground VSS and having its gate connected to node F. Control signal /IFG1 is output from node G. Control signal /IFG1, therefore, changes between power supply voltage VCC and ground voltage VSS. The operation of the circuit shown in FIG. 9 will be described with reference to FIG. 10, which is a diagram of signal waveforms.
When the forced monitor mode is inactive, forced monitor mode activating signal TEST1 is at the low level, and output signals from inverters IV1 and IV4 are at the high level which corresponds to the level of the power supply voltage VCC. In this state, MOS transistor Q5 is on and MOS transistor Q6 is off. When the potential at node B increases and the gate-source voltage of MOS transistor Q8 exceeds the threshold voltage thereof, MOS transistor Q8 is rendered conductive, and potential at node C is discharged to node VBB to which negative voltage is applied, and hence the potential at node C lowers. As the potential at node C lowers, conductance of MOS transistor Q7 becomes smaller, thus making smaller the current flowing from node B to node VBB. By repetition of this operation, node C attains to the level of the negative voltage VBB, and node B attains to the level of the power supply voltage VCC. In this state, MOS transistor Q7 turns off and MOS transistor Q8 turns on. The control signal IFG1 output from node B is set to a high level corresponding to the level of the power supply voltage VCC. In the level converting portion constituted by MOS transistors Q14 to Q17, MOS transistors Q14 and Q17 turned on while MOS transistors Q15
and Q16 turned off, and node G attains to the level of the ground voltage VSS. Thus, the control signal /IFG1 applied to the gate of MOS transistor Q18 attains to the level of the ground voltage VSS.
In the first clamp circuit 10, MOS transistor Q19 receives at its gate the control signal IFG1 at the level of the power supply voltage VCC and turns on, and transmits the ground voltage VSS to one conduction node (node to which MOS transistors Q18 and Q19 are connected) of MOS transistor Q18. Therefore, both the gate and the source of MOS transistor Q18 attain to the level of the ground voltage VSS, so that MOS transistor Q18 operates in the diode mode and clamps the negative potential level at node NA at the voltage level of -V18. Here, V18 represents the threshold voltage of MOS transistor Q18. Therefore, by applying a negative voltage VF to external terminal 7 in this state, pin contact test checking whether the external terminal 7 is surely electrically contacted with a pad (not shown) can be performed. When the forced monitor mode is inactive, the internal potential connecting circuit (not shown) is kept non-conductive, and the output portion of substrate potential generating circuit and internal node NA are electrically disconnected.
When the forced monitor mode is active, forced monitor mode activating signal TEST1 attains to a high level, and output signals from inverters IV1 and IV4 attain to the low level, which corresponds to the level of the ground voltage VSS. In this state, MOS transistors Q6, Q7, Q15 and Q16, turn on, and MOS transistors Q5, Q8, Q14 and Q17 turn off. The control signal IFG1 output from node B attains to the level of the negative voltage VBB, and control signal /IFG1 output from node G attains to the level of the power supply voltage VCC. In the first clamp circuit 10, MOS transistor Q18 turns on by the control signal /IFG1 which is at the level of the power supply voltage VCC, and electrically connects internal node NA to MOS transistor Q19. MOS transistor Q19 is receiving at gate the control signal IFG1 at the level of the negative voltage VBB. Therefore, even when the potential at internal node NA attains to the level of the negative potential VBB, MOS transistor Q19 is still kept off. This is because the source of MOS transistor Q19 is the conduction node connected to internal node NA, and hence the source potential is the same as the gate potential.
In this state, an internal potential connecting circuit, not shown, is rendered conductive in response to the output Gcnt1 of the common or separate control circuit, connecting electrically the output portion of substrate potential generating circuit to internal node NA. Therefore, even when the negative voltage VBB from substrate potential generating circuit is transmitted to internal node NA, MOS transistor Q19 is kept off, and hence the level of the negative voltage VBB transmitted to the internal node NA can be surely determined through external terminal 7. By contrast, when a negative voltage is applied to external terminal 7, MOS transistor Q19 is kept off unless the potential at internal node NA, that is, the externally applied voltage becomes lower by the absolute value of the threshold voltage of MOS transistor Q19 than the negative voltage VBB, and hence the potential at internal node NA can be correctly transmitted to the output portion of the substrate potential generating circuit through the internal potential connecting circuit, not shown. When the potential at the output portion of the substrate potential generating circuit changes, the voltage level applied to the node VBB to which the negative voltage is applied of control circuit 90 changes accordingly. Therefore, in response, the potential level of control signal IFG1 changes, and hence control signal IFG1 is kept equal to the voltage level applied to the internal node NA. Therefore, MOS transistor Q19 can be surely turned off, and voltage of a desired level can be applied to the output portion of the substrate potential generating circuit through internal node NA and internal potential connecting circuit, from external terminal 7.
In the first clamp circuit 10, when the forced monitor mode is inactive, control signal IFG1 is at the level of the power supply voltage VCC, MOS transistor Q19 turns on, and one conduction node of MOS transistor Q18 is electrically connected to the ground node VSS. When the forced monitor mode is activated, control signal /IFG1 attains to the high level which corresponds to the level of the power supply voltage VCC, MOS transistor Q18 turns on, and one conduction node of MOS transistor Q19 is connected to internal node NA. Therefore, connection node between MOS transistors Q18 and Q19 is always electrically connected to the internal node NA or the ground node VSS, and it is never set to a floating state. Therefore, when the forced monitor mode is activated, the connection node of MOS transistors Q18 and Q19 changes at high speed in accordance with the change in potential at the internal node NA, and in response, internal node NA can change its potential level at high speed, following the voltage level applied from the external terminal 7 or from the substrate potential generating circuit.
[Modification]
FIG. 11 shows a structure of a modification of the seventh embodiment in accordance with the present invention. In the structure shown in FIG. 11, MOS transistor Q18 included in the first clamp circuit 10 receives at its gate the forced monitor mode activating signal TEST1 as control signal /IFG1. Except this point, the structure of FIG. 11 is the same as that shown in FIG. 9. In the structure shown in FIG. 9, the control signals IFG1 and /IFG1 can be changed at the same timing, in accordance with the change in the forced monitor mode activating signal TEST1 (since the control signal generating portion has the same structure). When the forced monitor mode activating signal TEST1 is generated internally (based on timing conditions of a plurality of external signals, for example), the signal TEST1 changes between the levels of power supply voltage VCC and the ground voltage VSS. Therefore, control signal /IFG1 of a necessary voltage level can be generated. Therefore, transistors Q14
to Q17 and inverter IV4 shown in FIG. 9 can be eliminated, and hence area occupied by the control portion can be reduced.
As described above, in accordance with the seventh embodiment of the present invention, in the first clamp circuit, MOS transistors of which on/off states controlled by a control signal are connected in series, there is no node which is electrically floating in the first clamp circuit, and hence it becomes unnecessary to change/discharge the floating node. Therefore, the internal node can be set to a necessary voltage level at high speed.
Eighth Embodiment
FIG. 12 shows a structure of a main portion of a semiconductor device in accordance with the eighth embodiment of the present invention. In the structure shown in FIG. 12 also, the internal potential connecting circuit for connecting the output portion of substrate potential generating circuit to the internal node NA is not explicitly shown.
The structure shown in FIG. 12 is the same as the structure shown in FIG. 9 except the structure of the first clamp circuit 10, and corresponding portions are denoted by the same reference characters. In the first clamp circuit 10 shown in FIG.
12, n channel MOS transistor Q19 receiving at its gate the control signal IFG1 is connected to internal node NA, and n channel MOS transistor Q18 receiving at its gate the control signal /IFG1 is connected between MOS transistor Q19 and the ground node VSS. MOS transistor Q18 which functions as a clamp element when the forced monitor mode is inactive, is connected to internal node NA through MOS transistor Q19. When the forced monitor mode is active, MOS transistor Q19 is turned off while receiving at its gate the control signal IFG1 at the level of the negative voltage VBB, and prevents leak current from internal node NA to MOS transistor Q18. Therefore, there is no node which is at a floating state associated with the internal node NA, and hence it becomes unnecessary to charge/discharge the internal node which is at the floating state. Therefore, the internal node NA can be set to the level of a prescribed voltage (voltage applied to external terminal 7 or negative voltage transmitted from substrate potential generating circuit (not shown)) at high speed, and hence when the forced monitor mode is activated, the forced monitor mode operation can be executed at high speed.
When the forced monitor mode is inactive, control signal IFG1 is at the level of the power supply voltage VCC, MOS transistor Q19 turns on and electrically connects MOS transistor Q18 which functions as a clamp element to internal node NA. Therefore, pin contact test can be performed by MOS transistor Q18 without any difficulty.
[Modification]
FIG. 13 shows a structure of a modification of the eighth embodiment of the present invention. In the structure shown in FIG. 13, the forced monitor mode activating signal TEST1 is applied to the gate of MOS transistor Q18 included in the first clamp circuit 10 as control signal /IFG1. Except for this point, the structure of FIG. 13 is the same as that shown in FIG. 12. Control circuit 90a includes MOS transistors Q5 to Q8, and outputs control signal IFG1 of which level is converted, in response to forced monitor mode activating signal TEST1. In control circuit 90a, as compared with control circuit 90 shown in FIG. 12, MOS transistors Q14 to Q17 become unnecessary, and hence area of occupation can be reduced.
The operation of the circuit shown in FIG. 13 is the same as that of the circuit shown in FIG. 12. When the forced monitor mode activating signal TEST1 is active, even when the voltage level is lower than the level of the power supply voltage VCC, so long as it is higher than the voltage level at which MOS transistor Q18 turns on (that is, a voltage level higher than the threshold voltage of MOS transistor Q18), MOS transistor Q18 turns on, electrically connecting MOS transistor Q19 to ground node VSS, and hence it is possible to prevent any node from being set to the floating state. Therefore, even in such a structure in that the forced monitor mode activating signal TEST1 is directly applied externally, the MOS transistor Q18 can be correctly set to the on/off state in accordance with the operation mode (provided that low level is set to the level of the ground voltage VSS), and necessary function can be correctly implemented.
As described above, in accordance with the eighth embodiment of the present invention, the MOS transistor cutting off the current path in the forced monitor mode is adapted to be connected to the internal node. Therefore, a path through which leak current flows between internal node NA and a floating node or a ground node can be completely cut off, and hence the voltage at the internal node NA can be set to the prescribed voltage level at high speed.
Ninth Embodiment
FIG. 14 shows a structure of a main portion of a semiconductor device in accordance with the ninth embodiment of the present invention. In the structure shown in FIG. 14, first clamp circuit 10 is formed by one n channel MOS transistor Q20
connected between internal node NA and the ground node VSS and receiving at its gate the control signal IFG1. Control circuit 95 includes an inverter IV1 receiving forced monitor mode activating signal TEST1; a p channel MOS transistor Q5a connected between the ground node VSS and the node B and receiving at its gate the forced monitor mode activating signal TEST1; a p channel MOS transistor Q6a connected between the ground node VSS and node C and receiving at its gate an output signal from inverter IV1; an n channel MOS transistor Q7 connected between node B and node VBB to which the negative voltage is applied and having its gate connected to node C; and an n channel MOS transistor Q8 connected between node C and node VBB to which the negative voltage is applied, and having its gate connected to node B.
Control signal IFG1 is output from node B. MOS transistors Q5a and Q6a have the absolute value of the threshold voltage made sufficiently small. Internal circuit 11 and first protection circuit 20 have the same structures as those described with reference to the embodiments above. The operation of the semiconductor device shown in FIG. 14 will be described with reference to FIG. 15, which is a diagram of waveforms.
When the forced monitor mode is inactive, forced monitor mode activating signal TEST1 is at a low level, which corresponds to the level of the ground voltage VSS, and the output signal from inverter IV1 attains to the level of the power supply voltage VCC. MOS transistor Q6a is completely turned off. MOS transistor Q5a is set to a weak on state, and supplies current from ground node VSS to node B. In accordance with the potential at node B, MOS transistor Q8 turns on, and discharges the potential at node C to the voltage level of node VBB to which the negative voltage is applied. When the potential at node C lowers, MOS transistor Q7 changes to the off state responsively, and when the potential at node C finally reaches the level of the negative voltage VBB, MOS transistor Q7 is completely turned off. It requires much time until node B fully reaches the ground voltage VSS by the influence of the threshold voltage of MOS transistor Q5a. The absolute value of the threshold voltage of MOS transistor Q5 is sufficiently made small, and the potential at node B is set approximately at the level of the ground voltage VSS. Accordingly, control signal IFG1 from node B attains to the low level (which is substantially the level of the ground voltage VSS), and MOS transistor Q20 included in the first clamp circuit 10 operates in a diode mode, realizing a prescribed clamping function. Here, if the control signal IFG1 does not fully reach the level of the ground voltage VSS, the gate potential of MOS transistor Q20 becomes a little higher than the level of the ground voltage VSS. However, provided that the absolute value of the threshold voltage of MOS transistor Q5a is made sufficient smaller than the threshold voltage of MOS transistor Q20, necessary clamping function can be realized without any difficulty. If MOS transistors Q20 and Q5a have approximately the same threshold voltage in absolute value, the clamp level of node NA can be set approximately at the level of the ground voltage.
At this time, the first internal potential connecting circuit is rendered non-conductive by forced monitor mode activating signal TEST1, through a path, not shown. Therefore, by applying a desired negative voltage to external terminal 7, it is possible to cause a current to flow through the first clamp circuit 10 (transistor Q20) from internal node NA to the ground node VSS, and hence pin contact test can be performed correctly. Further, when the internal node NA changes to a negative voltage in normal operation mode, MOS transistor Q20 is rendered conductive, and clamps the negative voltage at a prescribed voltage level (-V20+.vertline.VQ5a.vertline.), where V20 represents threshold voltage of MOS transistor Q20, and VQ5a represents the threshold voltage of MOS transistor Q5a.
When the forced monitor mode is activated, forced monitor mode activating signal TEST1 attains to a high level, and the output signal of inverter IV1 attains to the low level, which corresponds to the level of the ground voltage VSS. In this state, conversely, MOS transistor Q5a turns off and MOS transistor Q6a turns on. The voltage at node C increases to the level of the absolute value of the threshold voltage of MOS transistor Q6a, and MOS transistor Q7 is turned on. When the potential at node B lowers to the level of the negative voltage VBB, the gate potential and source potential of MOS transistor Q8 become equal to each other, and hence the transistor is completely turned off. Thus lowering of the potential at node C is prevented, MOS transistor Q7 is kept on, and control signal IFG1 output from node B is surely set to the level of the negative voltage VBB. As a result, in the first clamp circuit 10, MOS transistor Q20 is kept off even when the negative voltage VBB is transmitted to internal node NA from external terminal 7 or from the first internal potential connecting circuit. This enables transmission of a negative voltage from external terminal 7 to the output portion of the substrate voltage generating circuit, and external monitoring of the voltage level at the output portion of the substrate voltage generating circuit.
When a voltage VF which is deeper (more negative) than the negative voltage VBB is to be applied to external terminal 7, the deep negative voltage VF is transmitted to the output portion of the substrate potential generating circuit through the first internal potential connecting circuit connected to internal node NA. Therefore, in this case, the voltage level attains to deeper negative voltage VF than at the node VBB, to which the negative voltage is applied, of control circuit 95, and accordingly, control signal IGF1 attains to the level of the negative voltage VF. Therefore, in the first clamp circuit 10, even when MOS transistor Q20 once turns on in response to the deep negative voltage VF which has been transmitted to internal node NA, it is quickly turned off, leakage at MOS transistor Q20 can be prevented, and the potential at internal node NA is stably kept at the level of the voltage of VF which is externally applied.
In this manner, both external monitoring of the internal voltage level and external setting of the internal voltage become possible.
According to the ninth embodiment, the first clamp circuit 10 is formed only by one MOS transistor, and hence compared with the structures of the first to eighth embodiments, the area occupied by the clamp circuit can be reduced. Therefore, a clamp circuit in which activation/inactivation of clamping function is controlled can be implemented by occupying an area comparable to that occupied by a conventional one diode-connected clamp element.
Tenth Embodiment
FIG. 16 shows a structure of a main portion of a semiconductor device in accordance with the tenth embodiment of the present invention. Control circuit 95 generating control signal IFG1 includes a first control signal generating circuit 95a responsive to forced monitor mode activating signal TEST1 for outputting complementary signals GATE and ZGATE at the levels of power supply voltage VCC and negative voltage VBB, respectively; and a second control signal generating circuit 95b for outputting control signal IFG1 changing between the levels of ground voltage VSS and negative voltage VBB in accordance with the complementary signals GATE and ZGATE from the first control signal generating circuit 95a. The first clamp circuit 10
includes an n channel MOS transistor Q20 connected between internal node NA and ground node VSS and receiving at its gate the control signal IFG1. Except the structure of control circuit 95, the structure shown in FIG. 16 is the same as that shown in FIG. 14, and corresponding portions are denoted by the same reference characters.
The first control signal generating circuit 95a includes an inverter IV1 receiving the forced monitor mode activating signal TEST1; a p channel MOS transistor Q5 connected between power supply node VCC and node B and receiving at its gate the forced monitor mode activating signal TEST1; a p channel MOS transistor Q6 connected between supply voltage node VCC and node C and receiving at its gate an output signal from inverter IV1; an n channel MOS transistor Q7 connected between node B and node VBB to which the negative voltage is applied and having its gate connected to node C; and an n channel MOS transistor Q8 connected between node C and node VBB to which the negative voltage is applied and having its gate connected to node B. The absolute value of threshold voltages of MOS transistors Q5 and Q6 need not be made smaller. The signal GATE is output from node C, and the signal ZGATE is output from node B.
The second control signal generating circuit 95b includes a p channel MOS transistor Q21 connected between ground node VSS and a node N and receiving at its gate the signal ZGATE; a p channel MOS transistor Q22 connected between ground node VSS and a node N and receiving at its gate the signal GATE; an n channel MOS transistor Q23 connected between node M and node VBB to which the negative voltage is applied and having its gate connected to node N; and an n channel MOS transistor Q24 connected between node N and node VBB to which the negative voltage is applied and having its gate connected to node M. Control signal IFG1 is output from node N.
The operation of the control circuit shown in FIG. 16 will be described with reference to FIG. 17, which is a diagram of waveforms. When the forced monitor mode is inactive, the signal TEST1 is at the low level, which corresponds to the level of the ground voltage VSS, and the output signal from inverter IV1 attains to the high level, which corresponds to the level of the power supply voltage VCC. In this state, MOS transistor Q5 turns on and MOS transistor Q6 turns off. When the potential at node B increases and a potential difference between the potential at node B and the potential at node VBB to which the negative voltage is applied exceeds the threshold voltage of MOS transistor Q8, MOS transistor Q8 turns on, lowering the potential at node C. As the potential at node C lowers, MOS transistor Q7 comes to have smaller conductance, and when the potential difference between node C and node VBB to which the negative voltage is applied becomes smaller than the threshold voltage of MOS transistors Q7, MOS transistor Q7 turns off. Thus the potential at node B is set to the level of the power supply voltage VCC, and the potential at node C is set to the level of the negative voltage VBB.
In the second control signal generating circuit 95b, by the signal ZGATE at the level of the power supply voltage VCC, MOS transistor Q21 is turned off. Meanwhile, since the signal GATE is at the level of the negative voltage VBB, MOS transistor Q22 is surely set to the on state, increasing the potential at node N to the level of the ground voltage VSS. As the potential at node N increases, MOS transistor Q23 turns on when the gate-source potential becomes higher than its threshold voltage, and lowers the potential at node N. As the potential at node N lowers, MOS transistor Q24 comes to have smaller conductance, and when the potential difference between node N and node VBB to which the negative voltage is applied becomes smaller than the threshold voltage of MOS transistor Q24, MOS transistor Q24 turns off. Finally, MOS transistor Q24 is turned off, MOS transistor Q23 is turned on, and control signal IFG1 attains to the level of the ground voltage VSS. In this state, in the first clamp circuit 10, the gate and source potentials of MOS transistor Q22 are both at the level of the ground voltage VSS, and hence the transistor Q22 operates in the diode mode.
In order for the MOS transistor Q22 to be turned on, it is necessary to set the threshold voltage V22 of MOS transistor Q22 such that the absolute values .vertline.V22.vertline. is not larger than the absolute value .vertline.VBB.vertline. of the negative voltage of VBB. As long as this condition is satisfied, MOS transistors Q21 and Q22 can be set to the on/off state in accordance with signal TEST1 and the control signal IFG1 at the level of the ground voltage can be surely generated, even when the difference between negative voltage VBB and the ground voltage VSS is small. When the control signal IFG1 is at the level of the ground voltage, the first internal potential connecting circuit is rendered non-conductive, by a control signal through a path, not shown, and the output portion of the substrate potential generating circuit and internal node NA are electrically disconnected. Therefore, pin contact test can be surely carried out.
When the forced monitor mode is activated, signal TEST1 is set to the high level (which is not always at the level of the power supply voltage VCC). In this state, the output signal from inverter IV1 attains to the low level, which corresponds to the level of the ground voltage VSS. MOS transistor Q5 turns off and MOS transistor Q6 turns on. Node C is charged by MOS transistor Q6, so that its potential rises, and MOS transistor Q7 turns on, lowering the potential at node B. Consequently, finally, MOS transistor Q8 turns off, MOS transistor Q7 turns on, node B attains to the level of the negative voltage VBB and node C attains to the level of the power supply voltage VCC.
In the second control signal generating circuit 95b, by the signal ZGATE at the level of the negative voltage VBB, MOS transistor Q21 is turned on, and by the signal GATE at the level of the power supply voltage VCC, MOS transistor Q22 is turned off. As a result, node N attains to the level of the ground voltage VSS, and MOS transistor Q24 turns on when its gate-source potential becomes larger than its threshold voltage, lowering the node N to the level of the negative voltage VBB. As the potential at node N lowers, MOS transistor Q21 is turned off. Therefore, control signal IFG1 output from node N attains to the level of the negative voltage VBB. At this time, the first internal potential connecting circuit turns on through a separate path (not shown), so that the output portion of the substrate potential generating circuit is connected to internal node NA. Therefore, when the potential at internal node NA is at the level of the negative voltage VBB, the gate and source potentials of MOS transistor Q20 are equal to each other, and hence the transistor Q20 is kept off. Therefore, voltage can be applied from external terminal 7, and the voltage level of the negative voltage VBB from the internal voltage generating circuit can be externally monitored.
For the MOS transistors Q21 and Q22 to be turned on, the absolute value of the threshold voltages of these transistors must be smaller than the absolute value of the negative voltage VBB. As long as this condition is satisfied, MOS transistors Q21 and Q22 can be surely switched on/off, even when the difference between the ground voltage VSS and the negative voltage VBB is small.
In the forced monitor mode, when a negative voltage VF which is deeper or more negative than the negative voltage VBB is applied, MOS transistor Q20 is rendered conductive at the time point of application of this voltage. However, the voltage transmitted to internal node NA is transmitted to the output portion of the substrate potential generating circuit through the first internal potential connecting circuit, and the voltage level of negative voltage VBB lowers to the level of the externally applied voltage VF in response (the driving power for applying the voltage VF externally is sufficiently larger than the current drivability of the substrate potential generating circuit). Therefore, the voltage level of control signal IFG1
also lowers to the level of the negative voltage VF, MOS transistor Q20 can be surely turned off, and leak current path between internal node NA and the ground node VSS can be cut. Therefore, internal node NA can be accurately set to the level of the externally applied voltage VF.
In the structure shown in FIG. 16 also, the first clamp circuit 10 is formed only by one MOS transistor, and hence area of occupation can be reduced. Further, control circuit 95 is constituted by two stages of level converting circuits, and therefore even when the difference between the negative voltage VBB and the ground voltage VSS and/or the difference between the power supply voltage VCC and the ground voltage is small, MOS transistors Q21 and Q22 included in the second control signal generating circuit can be surely switched on/off, and hence control signal IFG1 can be surely changed to the levels of ground voltage VSS and negative voltage VBB. Further, what is required for the MOS transistors Q21 and Q22 is simply to have the absolute value of the threshold voltage made smaller than the absolute value of negative voltage VBB. Making the absolute value of the threshold voltage sufficiently small does not require any additional manufacturing step (the step of ion implantation for compensation of threshold voltage), and therefore a control signal having necessary voltage level can be generated easily.
Eleventh Embodiment
FIG. 18 shows a structure of a main portion of a semiconductor device in accordance with the eleventh embodiment of the present invention. In a semiconductor memory device, a boosted voltage VPP which is higher than the power supply voltage is utilized. The boosted voltage VPP is used, for example, to set the voltage level of a word line driving signal transmitted to a selected word line to be higher than the power supply voltage VCC in a dynamic random access memory. Further, the boosted voltage may be applied to a control gate or a source region of a memory cell during erasing operation or programming of a non-volatile semiconductor memory device.
Referring to FIG. 18, the semiconductor device includes a second protection circuit 120 arranged between external terminal 7 and internal node NA for absorbing a high voltage applied to external terminal 7; a second clamp circuit 110 connected between internal node NA and power supply voltage node (reference voltage source) VCC for clamping the high potential at internal node NA at a prescribed potential level; and a third control circuit 130 responsive to a second forced monitor mode activating signal TEST2 for inactivating the clamping function of the second clamp circuit 110. The third control circuit 130 generates signal IFG2 for controlling activation/inactivation of the clamping function, and in addition, a connection control signal Gcnt2. The semiconductor device further includes a second connection control circuit 160 responsive to the connection control signal Gcnt2 for electrically connecting internal node NA to a boosted node VPP. The boosted node VPP represents a node to which the boosted voltage generated by an internal boosted voltage generating circuit, not shown, is transmitted. This may be an output portion of the boosted voltage generating circuit.
The second protection circuit 120 includes two resistors R3 and R4 connected in series between external terminal 7 and internal node NA, and a p channel MOS transistor Q20 having one conduction node connected to a connection portion between resistors R3 and R4 and its gate and the other conduction node connected to power supply node VCC. MOS transistor Q25 has a field insulating film as a gate insulating film, and has a small negative threshold voltage (threshold voltage of which absolute value is large). When a high voltage is applied to external terminal 7, MOS transistor Q25 is rendered conductive to absorb the high voltage, preventing application of a high voltage which cannot be absorbed by the clamp circuit to the internal circuit. Resistor R3 prevents a large current from flowing to MOS transistor Q25, and resistors R3 and R4 prevent a large current from flowing to the second clamp circuit 110.
The second clamp circuit 110 includes a p channel MOS transistor Q35 connected to internal node NA, and a p channel MOS transistor Q34 connected between MOS transistor Q35 and power supply node VCC. MOS transistor Q35 has its gate connected to power supply node VCC, and MOS transistor Q34 is connected to receive at its gate the control signal IFG2. Substrate regions of MOS transistors Q34 and Q35 are connected to power supply node VCC. When the voltage at internal node NA exceeds power supply voltage VCC, it is discharged through the substrate region, so as to absorb noise at high speed.
The third control circuit 130 includes an inverter IV2 receiving the second forced monitor mode activating signal TEST2; a p channel MOS transistor Q30 connected between ground node VSS and a node I and receiving at its gate the signal TEST2; an n channel MOS transistor Q31 connected between the ground VSS and an internal node J and receiving at its gate an output signal from inverter IV4; a p channel MOS transistor Q32 connected between node I and boosted node VPP and having its gate connected to node J; and a p channel MOS transistor Q33 connected between node J and boosted node VPP and having its gate connected to node I. Control signal IFG2 is output from node J, and control signal Gcnt2 is output from node I. Control circuit 130 has a function of converting and outputting the binary control signal TEST2 to a signal changing between the boosted voltage VPP and the ground voltage VSS.
The second internal potential connecting circuit 160 includes a p channel MOS transistor Q36 connected between boosted node VPP and internal node NA and receiving at its gate the control signal Gcnt2. Substrate region of MOS transistor Q36 is connected to the boosted node VPP. The second internal potential connecting circuit 160 may be formed by using an n channel MOS transistor. However, in that case, in order to transmit the boosted voltage VPP to the internal node NA, it becomes necessary to further boost the control signal Gcnt2. Use of a p channel MOS transistor eliminates a circuit structure for boosting the control signal, and hence circuit structure can be simplified. The structure of the internal circuit 11 is the same as that shown in FIG. 1. The operation of the semiconductor device shown in FIG. 8 will be described with reference to FIG. 19, which is a diagram of signal waveforms.
When the forced monitor mode is inactive, forced monitor mode activating signal TEST2 is at the low level, and in control circuit 130, the output signal from inverter IV4 attains to the high level which corresponds to the level of the power supply voltage VCC. Consequently, MOS transistor Q30 turns off, MOS transistor Q31 turns on, and the potential at node J lowers. MOS transistor Q32 comes to have larger conductance as the potential at node J lowers, and it supplies current from boosted node VPP to node I to raise the potential at node I. As the potential at node I increases, MOS transistor Q33 comes to have smaller conductance. Finally, MOS transistor Q33 turns off, MOS transistor Q32 turns on, the potential at node J reaches the level of the ground voltage VSS, and the potential at node I attains to the level of the boosted voltage VPP.
In the first clamp circuit 110, MOS transistor Q34 turns on, receiving the control signal IFG2 at the level of the ground voltage VSS at its gate, and transmits the power supply voltage VCC to MOS transistor Q35. Consequently, MOS transistor Q35
operates in the diode mode, and functions as a clamp element. When the voltage at node NA becomes higher than VCC+Vthp, MOS transistor Q35 is rendered conductive, electrically connecting node NA to power supply node VCC, so that the voltage level at internal node NA lowers. Here, Vthp represents the absolute value of the threshold voltage of MOS transistor Q35.
Meanwhile, in the second internal potential connecting circuit 160, the control signal Gcnt 2 at the level of the boosted voltage VPP is being applied to the gate of MOS transistor Q36, and MOS transistor Q36 is kept off unless the potential at node NA becomes higher than the boosted voltage VPP. If MOS transistors Q36 and Q35 have the same threshold voltage, MOS transistor Q36 turns on when the potential at node NA attains to VPP+Vthp, while MOS transistor Q35 turns on when the potential at internal node NA attains to VCC+Vthp or higher. Therefore, if the current drivability of MOS transistor Q35 is set larger than that of MOS transistor Q36, even when the potential at internal node NA is abruptly increased because of noise, the potential level at internal node NA can be lowered by the second clamp circuit 110, and hence MOS transistor Q36 in the second internal potential connecting circuit 160 can be surely maintained off. Therefore, in this state, it is possible to apply a high voltage VPP from external terminal 7 and externally determine whether a current flows through the first clamp circuit 110, and hence pin contact test can be performed by using a high voltage. The high voltage VPP have only to satisfy the relation VPP>VP>VCC.
When the forced monitor mode is activated, forced monitor mode activating signal TEST2 is set to the high level. The high level of the forced monitor mode activating signal TEST2 have only to be a level not lower than the threshold voltage Vth of MOS transistors Q30 and Q31, and it need not be at the level of the power supply voltage VCC. However, it is necessary that the signal TEST2 changes exceeding the input logic threshold value of inverter IV4.
In this state, the output signal from inverter IV4 is at the level of the ground voltage VSS, MOS transistor Q31 is off and MOS transistor Q30 is on. Therefore, node I is discharged to the level of the ground voltage by MOS transistor Q30, and when the potential at node I becomes higher than the boosted voltage VPP at the boosted node VPP by the threshold value (that is, lower by the absolute value of the threshold voltage), MOS transistor Q33 turns on, raising the potential at node J. As the potential at node J rises, MOS transistor Q32 comes to have lower