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United States Patent5751592
Takai , ; et al.May 12, 1998
Title
Apparatus and method of supporting functional design of logic circuit and apparatus and method of verifying functional design of logic circuit
Abstract
By means of tables, characters, and the like displayed on the screen of a CRT monitor, a functional diagram editor element can generate, on the screen of the CRT monitor, a functional diagram for representing the operation of a logic circuit. A functional diagram check element detects the presence or absence of a contradiction in the generated functional diagram. Furthermore, a functional simulation element can perform the functional verification of the functional diagram free from contradiction. A hardware-description-language conversion element can generate a hardware description language from the functional diagram in which the circuit operation has undergone error correction. A logic synthesis element can generate netlist information from said hardware description language.
Inventors:Takai; Yuji (Osaka, JP), Nakatani; Kazue  (Kyoto, JP), Matsumoto; Michihiro  (Osaka, JP)
Assignee:Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Appl. No.:579154
Filed:December 27, 1995
Foreign Application Priority Data
May 06, 1993 [JP] 5-105311
Jul 21, 1993 [JP] 5-180337
Nov 09, 1993 [JP] 5-279302
Current U.S. Class:716/5 716/18 
Current International Class:G06F 17/50 (20060101)
Field of Search:364/488-491 395/500
U.S. Patent Documents
4510572April 1985Reece et al.
4566064January 1986Whitaker
4695968September 1987Sullivan, II et al.
4855726August 1989Nishio
4891773January 1990Ooe et al.
4916627April 1990Hathaway
4922432May 1990Kobayashi et al.
5005136April 1991Van Berkel et al.
5051938September 1991Hyduke
5202841April 1993Tani
5212650May 1993Hooper et al.
5222029June 1993Hooper et al.
5224055June 1993Grundy et al.
5243538September 1993Okuzawa et al.
5287289February 1994Kageyama et al.
Foreign Patent Documents
1-309185Dec., 1989JP
Other References
de Lange et al., "A Hierarchical Constraint Graph Generation and Compaction System For Symbolic Layout", IEEE, pp. 532-535, 1989. .
Feng et al., "Single Multiple-Values PLA's and the Design of Fast Multiple-Valued Arithmetic Operation Units for Systolic MV-DTW Processor," IEEE, 1991, pp.2216-2219. .
Choon B. Kim "Multiple Mixed-Level HDL Generation From Schematics For Asic Design" IEEE pp. 8-2.1-2.4, Aug. 1991. .
XJ Wang "Behavioral VHD1 Code Generation For Synchronous FSM's " IEEE pp. 529-532, Feb. 1992. .
Nikkei Electronics, No. 565, SPeeDChART-VHDL, Oct. 12, 1992, p. 239..~
Primary Examiner: Teska; Kevin J.
Assistant Examiner: Roberts; A. S.
Attorney, Agent or Firm:McDermott, Will & Emery
Parent Case Text


This is a continuation application of application Ser. No. 08/238,745 filed May 5, 1994, now abandoned.
Claims

We claim:
1. A functional design verification apparatus for verifying the functional design of a logic circuit, comprising:
an encode means for accepting an n-bit input signal (n.gtoreq.2) in which each bit is represented by one of logic signals 0, 1, X, and Z and encoding each bit of said input signal to an encoded bit consisting of a 0-drive bit which indicates whether or not the logic value of said bit can be 0 and a 1-drive bit which indicates whether or not the logic value of said bit can be 1 so as to generate an encoded input signal consisting of a 0-drive word composed of n 0-drive bits and a 1-drive word composed of n 1-drive bits; and
a ZX conversion means for accepting said encoded input signal and converting that encoded bit of the n encoded bits in said encoded input signal, which corresponds to the logic signal Z, to the encoded bit which corresponds to the logic signal X so as to generate a converted signal;
an output signal evaluation means for accepting said converted signal and obtaining, based on the 0-drive word and 1-drive word of said converted signal, the 0-drive word and 1-drive word which correspond to the result of a logic operation to be subjected to functional simulation so as to generate the encoded output signal consisting of the obtained 0-drive word and 1-drive word; and
a decode means for accepting said encoded output signal and restoring a combination of the m-th (1.ltoreq.m.ltoreq.n) 0-drive bit in the 0-drive word of said encoded output signal and the mth 1-drive bit in the 1-drive word of the encoded output signal to representation by one of the logic signals 0, 1, X, and Z so as to generate an n-bit output signal.
2. A functional design support apparatus according to claim 1, wherein said ZX conversion means has:
a logical OR evaluation means for accepting the encoded input signal from said encode means, performing the logical OR operation between the 0-drive word and 1-drive word of said encoded input signal, and outputting the result of the operation as an intermediate result;
a bit inversion means for accepting said intermediate result, performs the logical NOT operation with respect to said intermediate result, and outputting the result of the operation as a ZX conversion mask; and
a ZX-conversion-mask processing means for accepting said encoded input signal and said ZX conversion mask, performing the logical OR operation between the 0-drive word of said encoded input signal and said ZX conversion mask, outputting the result of the operation as the 0-drive word of the converted signal, performing the logical OR operation between the 1-drive word of said encoded input signal and said ZX conversion mask, and outputting the result of the operation as the 1-drive word of the converted signal.
3. A functional design verification apparatus according to claim 1, wherein:
when a logical operation to be performed is a conjunction operation, said output signal evaluation means performs a disjunction operation of 0-drive words and a conjunction operation of 1-drive words of values of a signal to be input.
4. A functional design verification apparatus according to claim 1, wherein when a logical operation to be performed is a disjunction operation, said output signal evaluation means performs a conjunction operation of 0-drive words and a disjunction operation of 1-drive words of values of a signal to be input.
5. A functional design verification apparatus according to claim 1, wherein when a logical operation to be performed is a NOT operation, said output signal evaluation means exchanges 0-drive words and 1-drive words of values of a signal to be input.
6. A functional design verification apparatus according to claim 1, wherein said output signal evaluation means performs to disjunction operation of 0-drive words and a conjunction operation of 1-drive words of values of a signal to be input when a logical operation to be performed is a conjunction operation;
said output signal evaluation means performs a conjunction operation of 0-drive words and a disjunction operation of 1-drive words of values of a signal to be input when a logical operation to be performed is a disjunction operation; and
said output signal evaluation means exchanges 0-drive words and 1-drive words of values of a signal to be input when a logical operation to be performed is a NOT operation.
Description
BACKGROUND OF THE INVENTION

The present invention relates to an apparatus and method of supporting and verifying, in designing a logic circuit, the functional design of the logic circuit by means of a functional diagram in which the operation of the logic circuit is represented by symbols, tables, characters, and the like and to an apparatus and method of verifying the functional design of a logic circuit.

In general, logic design plays a major part in designing a logic circuit. The logic design has conventionally been achieved by means of a logic design support apparatus through such a procedure as shown in FIG. 58: First, a logic design drawing is created by laying out symbols representing logic elements on the screen of a display unit and connecting the symbols by lines. Then, the logic design support apparatus generates netlist information from the resulting logic design drawing.

FIG. 58 is a block diagram showing the structure of the logic design support apparatus.

In the drawing, a reference numeral 501 designates an input unit, 502 designates a CRT monitor for displaying a logic design drawing described by a logic-design-drawing editor unit 505, 503 designates a processor of the logic, design support apparatus, and 504 designates a logic-design-drawing-information storage unit for storing logic-design-drawing information on logic elements representing the logic of a logic circuit and on the interconnection thereof.

The logic-design-drawing editor element 505 has functions of: describing the logic design drawing on the screen of the CRT monitor 502; storing, in the logic-design-drawing-information storage unit 504, the logic-design-drawing information on the described logic design drawing; and reading the logic-design-drawing information from the logic-design-drawing-information storage unit 504.

A logic-design-drawing check element 506 reads the logic-design-drawing information from the logic-design-drawing-information storage unit 504 and detects the presence or absence of a contradiction in the logic design drawing indicated by the logic-design-drawing information.

A logic simulation element 507 reads the logic-design-drawing-information which has undergone the detection by the logic-design-drawing check element 506 and hence is free from contradiction, and executes logic simulation with respect to the logic design drawing, thereby verifying the logic of the logic circuit.

A net list conversion element 508 reads, from the logic-design-drawing-information storage unit 504, the logic-design-drawing information which has undergone the logic verification by the logic simulation element 507 and generates netlist information from the logic design drawing.

A reference numeral 509 designates the netlist information generated by the netlist conversion element 508.

As the logic circuit has become more complicated and larger in scale, however, there arises a need for design which is higher in level than the logic design. In view of the foregoing circumstances, there has recently been practiced a method in which the operations of a circuit is described in a hardware description language by means of a text editor and the netlist information is generated from the hardware description language through logical synthesis.

In addition to the method mentioned above, there is also known a method in which a part of the operation of a logic circuit is graphically designed by means of a tool such as: SPeeDCHART-VHDL (Nikkei Electronics, No. 565, Oct. 12, p.239 (1992)), whereby a state transition diagram representing the operation of the control part of a logic circuit is inputted so that the operation is verified in the state transition diagram and that a hardware description language representing the operation is automatically generated; or a design system for ASIC supported by a calculator which is disclosed in Japanese Laid-Open Patent Publication No. 1-309185, whereby the data flow in a logic circuit is represented using a flow chart so that the function thereof is verified in the flow chart and that a netlist is automatically generated from the flow chart.

In the above logic design support apparatus, the logic of the logic circuit is represented by laying out the symbols representing its logic elements and connecting the symbols by lines, while functional design should be accomplished based on a higher-level concept of data transfer to the state transition diagram and to storage elements. Consequently, with the above logic design support apparatus, the functional design cannot be achieved satisfactorily by simply replacing the logic elements by the storage elements, so that it is difficult to apply the above logic design support apparatus to the functional design.

Moreover, in the case of designing using a hardware description language, a logic-circuit designer who is familiar with a circuit diagram may find a difficulty in using a user interface whereby the operation of a logic circuit is described in a language, resulting in much labor and time required for the operation.

In the case of designing using the state transition diagram or flow chart, only a part of the operation of the logic circuit can be designed, so that the other parts of the operation should eventually be designed using a hardware description language.

For example, the state transition diagram can describe only the control operation of the logic circuit. The flow chart representing the data-flow can also describe only the control operation. To describe the whole operation of the logic circuit, however, it is required to describe the data processing operation, control operation, and combinational logic, so that the conventional design in graphic representation is not satisfactory.

SUMMARY OF THE INVENTION

The present invention has been achieved in view of the foregoing. An object of the present invention is to provide an apparatus having a user-friendly interface, wherein all the operations of a logic circuit can be inputted by means of symbols, tables, characters, and the like without using any hardware description language, functional verification can be performed by means of the symbols, tables, characters, and the like, and a hardware description language can be generated from the symbols, tables, characters, and the like.

To achieve the above object, a first functional design support apparatus of the present invention comprises: a display unit for displaying graphic elements such as symbols, tables, and characters; a storage unit for storing functional diagram information on a functional diagram in which the operational function of the logic circuit is represented by said graphic elements; a functional diagram editor means having a function of describing, by means of the graphic elements, a functional diagram on the screen of said display unit, a function of storing, in said storage unit, the functional diagram information on the described functional diagram, and a function of reading the functional diagram information from set storage unit; a functional diagram check means for reading, from said storage unit, the functional diagram information on the functional-diagram described by said functional diagram editor means and detecting the presence or absence of a contradiction in said functional diagram;. a functional simulation means for reading, from said storage unit, the functional diagram information on the functional diagram which has been detected for a contradiction by said functional diagram check means and performing functional verification with respect to said functional diagram; a hardware-description-language conversion means for reading, from said storage unit, the functional diagram information on the functional diagram which has undergone the functional verification performed by said functional simulation means and generating a hardware description language from said functional diagram; and a logic synthesis means for accepting the hardware description language generated by said functional- description-language conversion means and generating netlist information.

With the above structure, a functional diagram for representing the operation of the logic circuit can be generated, by the functional diagram editor means, on the screen of the display unit using graphic elements such as symbols, tables, and characters. Thus, it becomes possible to carry out the functional design of the logic circuit without using the hardware description language. It is also possible to automatically generate the hardware description language from the above functional diagram and to further obtain the netlist information from the generated hardware description language. Hence, the above apparatus provides the following effects:

(1) It saves the designer of a logic circuit the labor of mastering the hardware description language, which is not used therein.

(2) It enables the accumulation and extensive use of design resources, for the hardware description language is not used therein.

(3) It provides a more visible image of the designed circuit to the designer, for the functional design of the logic circuit is carried out by means of graphic images such as symbols, tables, and characters.

(4) It reduces the period of time required for designing a logic circuit.

(5) It can expect the standardization of techniques for designing a logic circuit.

In the above first functional design support apparatus, it is preferred that Preferably, in the above first functional design support apparatus 1, said display unit has a multi-window consisting of first, second, third, and fourth windows, and said functional diagram editor means has: a state-transition-diagram editor means for describing, in the first window of said display unit, a control part of the logic circuit in the form of a state transition diagram; a data path editor means for describing, in the second window of said display unit, a data path part of the logic circuit in the form of a data path diagram which shows the layout of functional elements and the interconnection thereof; a truth table editor means for describing, in the third window of said display unit, a combinational circuit part of the logic circuit in the form of a truth table; and a logical expression editor means for describing, in the forth window of said display unit, that combinational circuit of the combinational circuit part of the logic circuit, which is difficult to represent on a truth table, in the form of a logical expression table.

With the above structure, it is possible to simultaneously describe a plurality of functional diagrams of the state transition diagram, data path diagram, truth table, and logical expression table in the multi-window of the display unit. Hence, the apparatus provides the following effects:

(1) It can expect the widespread and expanded use of the functional design using the state transition diagram, data path diagram, truth table, and logical expression table.

(2) It can efficiently describe the operations of the logic circuit in accordance with its function, because it uses the state transition diagram, data path diagram, and truth table or logical expression table in describing the operations with respect to the control part, data path part, and combinational circuit part of the logic circuit, respectively.

(3) In the case of designing a large-scale logic circuit, the above apparatus divides the logic circuit into several parts so that the individual parts are described in a plurality of windows, for it can simultaneously describe, in the multi-window of the display unit, the plurality of functional diagrams of the state transition diagram, data path diagram, truth table, and logical expression table. Accordingly, design efficiency is improved and the designed circuit becomes more visible.

Preferably, in the above first functional design support apparatus, the above functional diagram check means has: a check means having a function of reading the functional diagram information from said storage unit and judging, based on check rules, whether or not a contradiction exists in the functional diagram indicated by said functional diagram information and a function of generating check result information; a check result screen display means for displaying the check result information on the screen of said display unit; and an error-report-file generation means for generating, from the check result information, an error report file which was obtained by organizing check results. With the above structure, the connection, definition, and reference in the functional diagram can easily be recognized, so that a mistake at an early stage can easily be detected.

A second functional design support apparatus of the present invention is composed of the first functional design support apparatus which further comprises: a language based function simulator for accepting the hardware description language generated by said hardware-description-language conversion means and performing functional simulation in the hardware description language, wherein said hardware-description-language conversion means has: a conversion means for simulation for converting the functional diagram information to a hardware description language for simulation which is suitable for said language based function simulator; and a conversion means for logic synthesis for converting the functional diagram information to a hardware description language for logic synthesis which is suitable for said logic synthesis means and which ensures that the operation of the logic circuit after the logic synthesis is identical with a functional simulation result in said hardware description language for simulation, which is implemented by said language based function simulator.

With the above structure, in the functional design using the functional diagram information, a hardware description language for logic synthesis which is suitable for the logic synthesis means or a hardware description language for functional simulation which is suitable for the language based function simulator is generated from the functional diagram information, so that it becomes possible to obtain a circuit which ensures the same operation in logic synthesis and functional simulation.

Preferably, in the above second functional design support apparatus, said conversion means for logic synthesis has: a conversion means for converting the functional diagram information to a hardware description language suitable for said logic synthesis means, which implements, after logic synthesis, a conditional transfer in a data path diagram indicated by said functional diagram information as a selector without priority; a conversion means for converting the functional diagram information to a hardware description language suitable for said logic synthesis means, which implements, after the logic synthesis, the conditional transfer in the data path diagram indicated by said functional diagram information as a selector with priority; a conversion means for converting the functional diagram information to a hardware description language suitable for said logic synthesis means, which implements, after the logic synthesis, the conditional transfer in the data path diagram indicated by said functional diagram information as a tri-state without priority; and a conversion means for converting the functional diagram information to a hardware description language suitable for said logic synthesis means which implements, after the logic synthesis, the conditional transfer in the data path diagram indicated by said functional diagram information as a tri-state with priority.

With the above structure, in the functional design using the functional diagram information, a hardware description language for logic synthesis suitable for the circuit structure to be implemented after logic synthesis is generated from the functional diagram information, so that a logic circuit of desired structure can be obtained after logic synthesis.

Preferably, in the above second functional design support apparatus, said logic synthesis means has: a first logic synthesis means suitable for the state transition diagram; a second logic synthesis means suitable for the data path diagram; and a third logic synthesis means suitable for random logic, and said conversion means for logic synthesis has: a state-transition-diagram conversion means for converting information on the state transition diagram, which is included by the functional diagram information, to a hardware description language suitable for said first logic synthesis means; a data-path-diagram conversion means for converting information on the data path diagram, which is included by the functional diagram information, to a hardware description language suitable for said second logic synthesis means; a truth table conversion means for converting information on a truth table, which is included by the functional diagram information, to a hardware description language suitable for said second logic synthesis means; and a logical expression conversion means for converting information on a logical expression table, which is included by the functional diagram information, to a hardware description language suitable for said third logic synthesis means.

With the above structure, in the functional design using the functional diagram information, the control part of the circuit is converted to a hardware description language suitable for a logic synthesis means for the state transition diagram, the data path part of the circuit is converted to a hardware description language suitable for a logic synthesis means for the data path, and the random logic of the circuit is converted to a hardware description language suitable for a logic synthesis means for the random logic, so that an optimum logic circuit can be obtained after logic synthesis.

Preferably, in the above second functional design support apparatus, said conversion means for logic synthesis has: a first conversion means for converting data-path-diagram information on each facility such as a register or a terminal in the data path diagram, which is included by the functional diagram information, to a hardware description language suitable for said logic synthesis means, which implements, after logic synthesis, a conditional transfer in each facility as a selector without priority; a second conversion means for converting said data-path-diagram information on each facility to a hardware description language suitable for said logic synthesis means, which implements, after the logic synthesis, the conditional transfer in each facility as a selector with priority; a third conversion means for converting said data path diagram information on each facility to a hardware description language suitable for said logic synthesis means, which implements, after the logic synthesis, the conditional transfer in each facility as a tri-state without priority; and a fourth conversion means for converting said data-path-diagram information on each facility to a hardware description language suitable for said logic synthesis means, which implements, after the logic synthesis, the conditional transfer in each facility as a tri-state with priority, and said logic synthesis conversion means reads the functional diagram information from said storage unit and operates, in each facility in the data path diagram, said first conversion means, said second conversion means, said third conversion means, or said fourth conversion means in consideration of the desired circuit model structure to be obtained after the logic synthesis.

With the above structure, it becomes possible in the functional design using the functional design information to generate, from the functional diagram information, a hardware description language for logic synthesis which is suitable for the circuit structure to be implemented after logic synthesis, so that a logic circuit in which each facility has a desired circuit structure can be obtained after logic synthesis.

A third functional design support apparatus of the present invention is composed of the above first functional design support apparatus, wherein said functional simulation means has: a function simulator means for executing forward step simulation, in which the operational function of the logic circuit is simulated for a specified period of simulation time t based on the state value at a simulation time T so as to obtain the state value at a simulation time (T+t); an input display means for accepting test data used in the simulation executed by said function simulator means and displaying a functional simulation result which is implemented by said function simulator means; and a control means for controlling the transfer of said test data from said input display means to said function simulator means and the transfer of said functional simulation result from said function simulator means to said input display means.

With the above structure, it becomes possible to execute functional simulation for a limited period of time. Moreover, every time functional simulation is executed, test data can be inputted and the simulation result can be displayed. Hence, the operational functions can be verified halfway through the simulation so that an error in test data can be detected at an early stage.

A fourth functional design support apparatus is composed of the above third functional design support apparatus, wherein said function simulator means further has a function of executing backward simulation for obtaining the state value at a simulation time (T-nxt) (n is an integer equal to or more than 1).

With the above structure, it becomes possible to return the simulation time to the past. Consequently, it becomes possible to restart the functional simulation so that, even if the inputted data contains an error or if the inputted data is to be changed, it is not required to restart the functional simulation from the time 0. Hence, the period required for verifying the operational functions of the logic circuit can be reduced, resulting in increased verification efficiency.

Preferably, in the above third or fourth functional design support apparatus, said input display means has a hardware-description-language input display means for accepting said test data in the hardware description language in which the operational function of the logic circuit is described in a statement and displaying said functional simulation result in said hardware description language, and said control means has a hardware-description-language input display control means for controlling said hardware-description-language input display means.

With the above structure, it becomes possible to, e.g., input test data and display the functional simulation result in the hardware description language for the circuit to be subjected to the functional simulation, which is displayed in the multi-window of the display unit. Consequently, the functional operation of the circuit can be verified easily in the hardware description language.

A fifth functional design support apparatus of the present invention is composed of the above third functional design support apparatus of the present invention, wherein said input display means has a functional diagram input display means for accepting, as said test data, a pattern in the functional diagram in which the operational function of the logic circuit is represented by means of graphic elements such as symbols, tables, and characters and displaying said functional simulation result in said functional diagram, and said control means has a functional diagram input display control means for controlling said functional diagram input display means.

With the above structure, it becomes possible to, e.g., input a pattern and display the functional simulation result in the functional diagram of the circuit to be subjected to functional simulation, which is displayed in the multi-window of the display unit. Consequently, it becomes possible to easily recognize the state values of the circuit models operating in parallel, so that the operational function of the logic circuit operating in parallel can be verified more easily and more efficiently. Moreover, in a debugging operation, the cause of an error can be tracked down spatially in the functional diagram, so that debug efficiency can be increased.

Preferably, in the above fifth functional design support apparatus, said functional diagram input display means has a data-path-diagram input display means for accepting, as said test data, a pattern in data-path-diagram representation in which the operational function of the logic circuit is represented in the data path diagram and displaying said functional simulation result in said data-path-diagram representation, and said functional diagram input display control means has a data-path-diagram input display control means for controlling said data-path-diagram input display means.

Moreover, in the above fifth functional design support apparatus, said functional diagram input display means has a state-transition-diagram input display means for accepting, as said test data, a pattern in state-transition-diagram representation in which the operational function of the logic circuit is represented in the state transition diagram and displaying said functional simulation result in said state-transition-diagram representation, and said functional diagram input display control means has a state-transition-diagram input display control means for controlling said state-transition-diagram input display means.

Furthermore, in the above fifth functional design support apparatus, said functional diagram input display means has a logical expression input display means for accepting, as said test data, a pattern in logical expression representation in which the operational function of the logic circuit is represented in a logical expression and displaying said functional simulation result in said logical expression representation, and said functional diagram input display control means has a logical expression input display control means for controlling said logical expression input display means.

Furthermore, in the above fifth functional design support apparatus, said functional diagram input display means has a truth table input display means for accepting, as said test data, a pattern in truth table representation in which the operational function of the logic circuit is represented in a truth table and displaying said functional simulation result in said truth table representation, and said functional diagram input display control means has a truth table input display control means for controlling said truth table input display means.

With the above structure, it becomes possible to, e.g., input a pattern and display the functional simulation result in the data path diagram, state transition diagram, logical expression representation, truth table representation of the circuit to be subjected to functional simulation, which are displayed in the multi-window of the display unit. Consequently, the operational functions of the logic circuit operating in parallel can be verified more easily and more efficiently. Moreover, since the cause of an error can be tracked down spatially in the individual diagrams in a debugging operation, debug efficiency can also be increased.

Preferably, in the above third or fourth functional design support apparatus, said input display means has a control panel display means for displaying a control panel which controls the execution of functional simulation by said function simulator means and the inputting of said test data, and said control means has a control panel display control means for controlling said control panel display means.

With the above structure, it becomes possible to, e.g., control the execution of functional simulation and the inputting of test data on the control panel displayed in the multi-window of the display unit. Consequently, functional simulation can be performed interactively, so that the operational function of the logic circuit can be verified with improved efficiency.

Preferably, in the above third or fourth functional design support apparatus, said function simulator means has a state value storage table for holding a state value transition history at all the simulation times for each circuit model constituting the logic circuit. With the above structure, it becomes possible in the functional simulation process not only to perform time forward functional simulation but also to switch halfway to time backward functional simulation, thereby rapidly returning to a past time, so that the operational function of the logic circuit can be verified with increased efficiency.

Preferably, in the above third or fourth functional design support apparatus, said function simulator means has: an event list composed of a list of events for storing information on changes in the state value; an event processing means for fetching an event from said event list, selecting a process to be performed depending on the type of said fetched event, and updating the state value; and an evaluation means for evaluating an element which may undergo a new change in the state value due to the updating of the state value by said event processing means and, if a change occurs in the state value, storing information on the change in an event so that the event is added to said event list, and said event processing means has: a processing means for fetching an event from said event list; a processing means for judging the type of the event fetched by said processing means; a processing means for updating the state value; a processing means for updating the state value of a clock signal; and a processing means for updating an input data signal of a register.

With the above structure, in the case where a clock signal and an input signal change at the same time in a storage element such as a register or RAM which operates in synchronization with the rise edge or fall edge of the clock signal, if there is a time difference between an event process with respect to the change in the clock signal and an event process with respect to the change in the input signal, the same functional simulation result can be obtained. Hence, the same operation can be ensured in functional simulation. A sixth functional design support apparatus of the present invention is composed of the above third or fourth functional design support apparatus, wherein said input display means has: an encode means for accepting an n-bit input signal (n.ltoreq.2) in which each bit is represented by one of logic signals 0, 1, X, and Z and encoding each bit of said input signal to an encoded bit consisting of a 0-drive bit which indicates whether or not the logic value of said bit can be 0 and a 1-drive bit which indicates whether or not the logic value of said bit can be 1 so as, to generate an encoded input signal consisting of a 0-drive word composed of n 0-drive bits and a 1-drive word composed of n 1-drive bits; and a decode means for accepting an encoded output signal consisting of the 0-drive word composed of n 0-drive bits and the 1-drive word composed of n 1-drive bits and restoring a combination of the m-th (1 .ltoreq.m.ltoreq.n) 0-drive bit in the 0-drive word of said encoded output signal and the m-th 1-drive bit in the 1-drive word of the encoded output signal to representation by one of the logic signals 0, 1, X, and Z so as to generate an n-bit output signal, and said function simulator means has: a ZX conversion means for accepting said encoded input signal and converting that encoded bit of the n encoded bits in said encoded input signal, which corresponds to the logic signal Z, to the encoded bit which corresponds to the logic signal X so as to generate a converted signal; and an output signal evaluation means for accepting said converted signal and obtaining, based on the 0-drive word and 1-drive word of said converted signal, the 0-drive word and 1-drive word which correspond to the result of a logic operation to be subjected to functional simulation so as to generate said encoded output signal.

A functional design verification apparatus for verifying the functional design of a logic circuit comprises: an encode means for accepting an n-bit input signal (n.ltoreq.2) in which each bit is represented by one of logic signals 0, 1, X, and Z and encoding each bit of said input signal to an encoded bit consisting of a 0-drive bit which indicates whether or not the logic value of said bit can be 0 and a 1-drive bit which indicates whether or not the logic value of said bit can be 1 so as to generate an encoded input signal consisting of a Q-drive word composed of n 0-drive bits and a 1-drive word composed of n 1-drive bits; and a ZX conversion means for accepting said encoded input signal and converting that encoded bit of the n encoded bits in said encoded input signal, which corresponds to the logic signal Z, to the encoded bit which corresponds to the logic signal X so as to generate a converted signal; an output signal evaluation means for accepting said converted signal and obtaining, based on the 0-drive word and 1-drive word of said converted signal, the 0-drive word and 1-drive word which correspond to the result of a logic operation to be subjected to functional simulation so as to generate the encoded output signal consisting of the obtained 0-drive word and 1-drive word; and a decode means for accepting said encoded output signal and restoring a combination of the m-th (1 .ltoreq.m.ltoreq.n) 0-drive bit in the 0-drive word of said encoded output signal and the m-th 1-drive bit in the 1-drive word of the encoded output signal to representation by one of the logic signals 0, 1, X, and Z so as to generate an n-bit output signal.

With the above structure, it becomes possible for the encode means to encode each bit of the multi-bit input signal, represented by one of the four values of the logic signals 0, 1, X, and Z, by the two bits of the 0-drive bit which indicates whether or not the logic value becomes 0 and the 1-drive bit which indicates whether or not the logic value becomes 1. Moreover, in the encoded input signal, the ZX conversion means converts the encoded bit corresponding to the logic signal Z to the encoded bit corresponding to the logic signal X. Based on the 0-drive word and 1-drive word of the converted signal, the output signal evaluation means obtains the 0-drive word and 1-drive word which correspond to the result of the logic operation to be subjected to functional simulation, so as to generate the encoded output signal. In this case, since the two drive words are composed of the binary logic signals 0 and 1, it is possible to simultaneously obtain all the bits in the encoded output signal corresponding to the result of the logic operation to be subjected to functional simulation. Each drive bit in the 0-drive word and 1-drive word of the encoded output signal thus obtained is restored by the decode means to representation by one of the four values of the logic signals 0, 1, X, and Z, thereby generating the output signal.

As described above, since the multi-bit input signal represented by the four values can be encoded to the binary encoded input signal composed of the 0-drive word and 1-drive word, multiple digits can be processed at the same time by treating the logic signal represented by the four values as the binary signal. Consequently, it is unnecessary to obtain the result of an operation for each bit, so that the logic operation between multi-bit logic signals represented by the four values can be performed at a higher speed.

Preferably, in the above sixth functional design support apparatus, said ZX conversion means has: a logical OR evaluation means for accepting the encoded input signal from said encode means, performing the logical OR operation between the 0-drive word and 1-drive word of said encoded input signal, and outputting the result of the operation as an intermediate result; a bit inversion means for accepting said intermediate result, performing the logical NOT operation with respect to said intermediate result, and outputting the result of the operation as a ZX conversion mask; and a ZX-conversion-mask processing means for accepting said encoded input signal and said ZX conversion mask, performing the logical OR operation between the 0-drive word of said encoded input signal and said ZX conversion mask, outputting the result of the operation as the 0-drive word of the converted signal, performing the logical OR operation between the 1-drive word of said encoded input signal and said ZX conversion mask, and outputting the result of the operation as the 1-drive word of the converted signal.

In the above functional design support apparatus, said ZX conversion means has: a logical OR evaluation means for accepting the encoded input signal from said encode means, performing the logical OR operation between the 0-drive word and 1-drive word of said encoded input signal, and outputting the result of the operation as an intermediate result; a bit inversion means for accepting said intermediate result, performs the logical NOT operation with respect to said intermediate result, and outputting the result of the operation as a ZX conversion mask; and a ZX-conversion-mask processing means for accepting said encoded input signal and said ZX conversion mask, performing the logical OR operation between the 0-drive word of said encoded input signal and said ZX conversion mask, outputting the result of the operation as the 0-drive word of the converted signal, performing the logical OR operation between the 1-drive word of said encoded input signal and said ZX conversion mask, and outputting the result of the operation as the 1-drive word of the converted signal.

With the above structure, each bit in the intermediate result outputted from the logical OR evaluation means is inverted by the bit inversion means, resulting in the ZX conversion mask. The ZX conversion mask processing means accepts the encoded input signal and ZX conversion mask, performs the logical OR operation between the 0-drive word of the encoded input signal and the ZX conversion mask, and performs the logical OR operation between the 1-drive word of the encoded input signal and the ZX conversion mask. Consequently, the former logical OR is outputted as the 0-drive word of the converted signal, while the latter logical OR is outputted as the 1-drive word of the converted signal. Hence, it becomes possible to easily execute the ZX conversion whereby the encoded bit corresponding to the logical signal Z in the encoded input signal to the encoded bit corresponding to the logical signal X.

Preferably, the above third or fourth functional design support apparatus further comprises a test vector generation means for generating, based on said functional simulation result, a test vector which describes the content of the test data. With the above structure, it becomes possible to generate a test pattern for the language based function simulator from the result of the functional simulation that has been performed interactively using the test data inputted in order to interactively debug the logic circuit. Therefore, it becomes possible to interactively generate the test data and correct it, while debugging the logic circuit and verifying the operational function thereof, so that the test vector for the language based function simulator can be generated and corrected interactively. As a result, it becomes possible to automatically generate a highly reliable test vector, while it becomes unnecessary to newly generate a test vector for the language based functional simulator, so that the design of the logic circuit can be verified in a reduced period of time with increased efficiency.

Preferably, in the above third or fourth functional design support apparatus, said control means is divided into a function-simulator control part for controlling said function simulator means and an input display control part for controlling said input display means. With the above structure, since the control means is divided into the input display control part for controlling the input display means and the function simulator control part for controlling the function simulator means, if the function of the input display means is to be changed or added to, it is sufficient to change only the input display control part without changing the function simulator control part. Conversely, if the function of the functional simulator means is to be changed or added to, it is sufficient to change only the function simulator control part. Consequently, the apparatus can easily satisfy the user's requirements, so that it becomes possible to realize an environment in which the operational function of a logic circuit can be verified efficiently.

Preferably, in the above third functional design support apparatus, said function simulator means further has a function of executing forward jump simulation, in which the operational function of the logic circuit is simulated for a period of simulation time (mxt) (m is an integer equal to or more than 2) based on the state value at the simulation time T so as to obtain the state value at a simulation time (T+mxt), and said control means has: a forward step control means for controlling the execution of said forward step simulation; a forward jump control means for controlling the execution of said forward jump simulation; a pattern setting control means for setting said test data to said function simulator means; and a result fetch control means for fetching said functional simulation result from said function simulator means.

In the above functional design support apparatus, said function simulator means further has a function of executing forward jump simulation by simulating, based on the state value at the simulation time T, the operational function of the logic circuit for a period of simulation time (mxt) (m is an integer equal to or more than 2) so as to obtain the state value at a simulation time (T+mxt), and said control means has: a forward step control means for controlling the execution of said forward step simulation; a forward jump control means for controlling the execution of said forward jump simulation; a pattern setting control means for setting said test data to said function simulator means; and a result fetch control means for fetching said functional simulation result from said function simulator means.

With the above structure, it becomes possible to select, if required, from the various types of functional simulations and execute the selected one. Moreover, since it becomes possible during executing the functional simulation to input test data including the test pattern, periodic pattern, and memory pattern and fetch the existing functional simulation result, the operational functions of the logic circuit can be verified with increased efficiency.

Preferably, in the above third or fourth functional design support apparatus, said input display means has a table input display means for accepting, as said test data, a pattern in tabular form and displaying said functional simulation result in tabular form, and said control means has a table input display control means for controlling said table input display means.

With the above structure, it becomes possible to, e.g., input the pattern in tabular form and display the functional simulation result in the window of the display unit. Consequently, the user can easily recognize the state values of the individual circuit models operating in parallel not in a sequence of characters but on a table, so that the operational functions of the logic circuit can be verified more easily than in the case where they are verified using only characters, resulting in increased verification efficiency.

Preferably, in the above third or fourth functional design support apparatus, said input display means has a waveform input display means for accepting, as said test data, a waveform pattern and displaying said functional simulation result in waveform, and said control means has a waveform input display control means for controlling said waveform input display means.

With the above structure, it becomes possible to, e.g., input the pattern in the form of a wave and display the functional simulation result in the window of the display unit. Consequently, the operational functions of the logic circuit can be verified more easily than in the case where they are verified using only characters, resulting in increased verification efficiency.

Preferably, in the above third or fourth functional design support apparatus, said input display means has a memory pattern input display means for accepting, as said test data, the memory pattern of a memory in the logic circuit and displaying the memory pattern as said functional simulation result, and said control means has a memory pattern input display control means for controlling said memory pattern input display means.

With the above structure, it becomes possible to input the memory pattern with ease using, e.g., a cursor mode function, copy function, count function, and change function. It is also possible to display the memory pattern every time functional simulation is executed . Consequently, the operational function of the logic circuit provided with a memory can easily be verified in a reduced period of time with increased efficiency.

Preferably, in the above third or fourth functional design support apparatus, said input display means has a pattern history input display means for displaying, in tabular form, the past test data used in the simulation previously executed by said function simulator means and accepting, as new test data, the test data selected from said past test data, and said control means has a pattern history input display control means for controlling said pattern history input display means.

With the above structure, it becomes possible to, e.g., display the previously inputted test data in the window of the display unit and, by selecting from the test data displayed, reuse the previously inputted test data. Consequently, in the case of restarting functional simulation, it becomes unnecessary to manually input test data from the beginning. By simply selecting the test data displayed by the pattern history input display means, the test data is automatically transferred to the function simulator means, so that functional simulation can be executed. If the selected test data contains an error, it can be eliminated by selectively correcting the faulty data, while leaving the other displayed test data as it is. If the logic circuit is changed, the test data can similarly be reused by simply storing the result of the previous functional simulation in a file and loading it. Hence, the operational functions of the logic circuit can be verified in a reduced period of time with increased efficiency.

A functional design verification method of verifying the functional design of a logic circuit comprises: a test data input step of inputting test data; a forward simulation step of simulating, based on said inputted test data, the operational function of the logic circuit for a specified period of simulation time; and a result display step of displaying a functional simulation result obtained through the execution of said forward simulation step.

With the above structure, functional simulation can be executed in a limited period of time. Moreover, every time functional simulation is executed, test data can be inputted and the functional simulation result can be displayed. Consequently, the operational functions of the logic circuit can be verified halfway through the simulation, so that an error in the test data can be detected at an early stage.

A second functional design verification method of verifying the functional design of a logic circuit of the present invention, wherein the state values of the logic circuit at all the simulation times antecedent to the current simulation time are preliminarily stored, comprises: a backward simulation step of returning the simulation time to a past simulation time so as to obtain, as a functional simulation result, the state value of the logic circuit at said past simulation time; and a result display step of displaying said functional simulation result obtained through the execution of said backward simulation step.

Moreover, in the above second functional design verification method, said backward simulation step is for obtaining the state value of the logic circuit at the preceding simulation time by returning the simulation time to the preceding simulation time.

With the above structure, it becomes possible to recognize the state values at the past simulation time. Consequently, if the logic circuit or test data contains an error, a trace back operation can easily be performed in order to tack down its cause, resulting in increased debug efficiency.

A third functional design verification method of verifying the functional design of a logic circuit of the present invention, wherein a state value storage table which can hold all the state values of the logic circuit at all the simulation times is preliminarily provided, comprises: a test data input step of inputting test data; a test data set step of setting, as the state value of the logic circuit at a simulation time T, said inputted test data to said state value storage table; a state value read step of reading, from said state value storage table, the state value of the logic circuit at the simulation time T, which has been held in the state value storage table; a forward simulation step of simulating, based on said read state value, the operational function of the logic circuit for a specified period of simulation time t; a result write step of writing, as the state value of the logic circuit at a simulation time (T+t), a forward simulation result obtained through the execution of said forward simulation step in said state value storage table; a first result display step of displaying said forward simulation result as the state value of the logic circuit at the simulation time (T+t) written in said state value storage table; a step of newly setting, after the execution of said first result display step, the simulation time (T+t) as a simulation time T and repeatedly executing the sequence of said state value read step, forward simulation step, result write step, and first result display step so as to set, to said state value storage table, the state values of the logic circuit at all the simulation times antecedent to the simulation time TO; a backward simulation step of updating the current simulation time in said state value storage table from the simulation time TO to a simulation time (TO-nxt) (n is an integer equal to or more than 1) so as to obtain, as a backward simulation result, the state value of the logic circuit at the simulation time (TO-nxt), which has been held in said state value storage table; and a second result display step of displaying said backward simulation result obtained through the execution of said backward simulation.

With the above structure, the state values at all the simulation times antecedent to the current simulation time can be set on the state value storage table by repeatedly executing functional simulation. With the use of the state value storage table, the simulation time can be returned to the past with ease, so that it is not required to restart the functional simulation from the time 0 even if the inputted test data contains an error or if the inputted test data is to be changed. Consequently, the operational functions of the logic circuit can be verified in a reduced period of time with increased efficiency.

Preferably, in the above first functional design verification method, said test data in said test data input step is a pattern in a functional diagram in which the operational function of the logic circuit is represented by graphic elements such as symbols, tables, and characters and said result display step is for displaying said functional simulation result in said functional diagram.

In the above second functional design verification method, said result display step is for displaying said functional simulation result in a functional diagram in which the operational function of the logic circuit is represented by graphic elements such as symbols, tables, and characters.

In the above third functional design verification said test data in said test data input step is a pattern in a functional diagram in which the operational function of the logic circuit is represented by graphic elements such as symbols, tables, and characters; said first result display step is for displaying said forward simulation result in said functional diagram; and said second result display step is for displaying said backward simulation result in said functional diagram.

With the above structure, it becomes possible to, e.g., input a pattern and display the functional simulation result in the functional diagram of the circuit to be subjected to functional simulation, which is displayed in the multi-window of the display unit. As a result, the state values of the individual circuit models operating in parallel can easily be recognized, so that the operational functions of the logic circuit operating in parallel can be verified more easily and efficiently. Moreover, since it is possible in a debugging operation to spatially track down the cause of an error in the functional diagram, debug efficiency can be increased. A seventh functional design support apparatus of the present invention is composed of the above first functional design support apparatus which further comprises: a design-constraint-information input means having a function of accepting design constraint information from the outside, a function of reading, from said storage unit, the functional diagram information on the functional diagram described by said functional diagram editor means, and a function of setting the design constraint information in said functional diagram; a design-constraint-information check means for reading, from said storage unit, the functional diagram information on the functional diagram in which the design constraint information was set by said design-constraint-information input means and detecting the presence or absence of a contradiction in said design constraint information; a design-constraint-description-language conversion means for reading, from said storage unit, the functional diagram information on the functional diagram in which the design constraint information was set by said design-constraint-information input means, analyzing said design constraint information in the functional diagram, and generating a design constraint description language; and a language based function simulator for accepting the hardware description language generated by said hardware-description-language conversion means and the design constraint description language generated by said design-constraint-description-language conversion means and performing functional simulation in the hardware description language, wherein said functional simulation means accepts, from said storage unit, the functional diagram information on the functional diagram in which the design constraint information was set by said design-constraint-information input means and performs, based on said design constraint information, delay simulation in the functional diagram, thereby performing a timing verification, and said logic synthesis means accepts the hardware description language generated by said hardware-description-language conversion means and the design constraint description language generated by said design-constraint-description-language conversion means and generates netlist information.

A functional design support method of supporting the functional design of a logic circuit of the present invention comprises: a step of generating a functional diagram by means of graphic elements such as symbols, tables, and characters; a step of detecting the presence or absence of a contradiction in the functional diagram; a step of correcting the functional diagram by means of said graphic elements; a step of accepting design constraint information and setting said design constraint information in the functional diagram; a step of judging whether or not an error exists in the design constraint information; a step of correcting the design constraint information in the functional diagram; a step of performing the functional verification and timing verification of the logic circuit based on the functional diagram and design constraint information; and a step of generating a hardware description language and a design constraint description language from the functional diagram and design constraint information.

With the above structure, it becomes possible to set, in the functional diagram in which the operations of the logic circuit are represented, the design constraint information including the timing constraint information, fan-out, fan-in, and delay constraint information. Consequently, the above method provides the following effects:

(1) Design efficiency is increased because the user can clearly recognize the manner in which the design constraints are set for the logic circuit.

(2) The user can obtain the netlist information reflecting the design constraints without using a design constraint description language, for the hardware description language and design constraint description language can be generated automatically. Hence, a circuit having a desired function can be logically synthesized in a relatively short period of time, so that the period required for designing a logic circuit can be reduced.

(3) It becomes possible to perform delay simulation and timing verification in the functional diagram, so that highly precise functional simulation can be performed in the functional diagram.

Preferably, in the above seventh functional design support apparatus, said design-constraint-information input means has a function of accepting a periodic waveform for a clock input pin of the logic circuit and a function of setting the periodic waveform to the clock input pin in the functional diagram; and said design-constraint-description-language conversion means generates the design constraint description language for setting, to said logic synthesis means, timing constraint information, including setup time and hold time of a register, for the periodic waveform set in the functional diagram by said design-constraint-information input means.

With the above structure, it becomes possible to set, to the logic synthesis means, constraints on the logic circuit such as the set-up time and hold-time of its register as the design constraints, so that a circuit approximate to a desired circuit can be obtained at a higher level of the design process.

Preferably, in the above seventh functional design support apparatus, said design-constraint-information input means has a function of accepting a fan-out for an external input pin of the logic circuit and a fan-in for an external output pin of the logic circuit and a function of setting the fan-out to the external input pin in the functional diagram and the fan-in to the external output pin in the functional diagram, and said design-constraint-description-language conversion means generates the design constraint description language for setting, to said logic synthesis means, information on the fan-out and fan-in set in the functional diagram by said design-constraint-information input means.

With the above structure, it becomes possible to set, to the logic synthesis means, the fan-out for the external input pin of the logic circuit and the fan-in for the external output pin of the logic circuit as the design constraints, so that a circuit approximate to a desired circuit can be obtained at a higher level of the design process.

Preferably, in the above seventh functional design support apparatus, said design constraint information input means has a function of accepting delay values for a terminal serving as a component of the logic circuit incapable of storing the state value, for a register serving as a component of the logic circuit capable of storing the state value, and for an external pin of the logic circuit, a function of setting the delay value to the terminal in the functional diagram, a function of setting the delay value to the register in the functional diagram, and a function of setting the delay value to the external pin in the functional diagram, said functional simulation means performs said delay simulation based on the delay values set to the terminal, register, and external pin in the functional diagram by said design-constraint-information input means, and said design-constraint-description-language conversion means generates the design constraint description language for setting, to said logic synthesis means, delay information based on the delay values set in the functional diagram by said design-constraint-information input means.

With the above structure, it becomes possible to set the delay time to the components of the logic circuit and set the delay time to the logic synthesis means as the design constraint. It also becomes possible to perform delay functional simulation in the functional diagram using the functional simulation means. Consequently, a circuit approximate to a desired circuit can be obtained, so that more detailed simulation can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the overall structure of a functional design support apparatus according to a first embodiment of the present invention;

FIG. 2 is a flow chart showing a functional design support method using the above functional design support apparatus;

FIG. 3 is a block diagram showing an example of the structure of a functional diagram editor element according to the first embodiment;

FIG. 4 is a view showing a specific example of a state transition diagram described by a state transition editor element according to the first embodiment;

FIG. 5 is a view showing a specific example of a data path diagram described by a data path editor element according to the first embodiment;

FIG. 6 is a view showing a specific example of a truth table described by a truth table editor element according to the first embodiment;

FIG. 7 is a view showing a specific example of a logical expression table described by a logical expression editor unit according to the first embodiment;

FIG. 8 is a block diagram showing an example of the structure of a functional diagram check element according to the first embodiment;

FIG. 9(a) is a view showing an example of a state transition diagram window;

FIGS. 9(b) and 9(c) are views showing an example of a data-path-diagram window;

FIG. 9(d) is a view showing an example of a truth table window;

FIG. 10 is a block diagram showing an example of the structure of a check element of the above functional diagram check element;

FIG. 11 is a view showing a specific example of check result information;

FIG. 12 is a block diagram showing an example of the structure of a hardware-description-language conversion element according to the first embodiment;

FIG. 13 is a block diagram showing an example of the structure of a hardware-description-language conversion element for logic synthesis in the above hardware-description-language conversion element according to the first embodiment;

FIG. 14(a) is a view showing an example of the state transition diagram to be converted by a state-transition-diagram conversion element according to the first embodiment;

FIG. 14(b) is a view showing a hardware description language obtained by converting the state transition diagram of FIG. 14(a);

FIG. 15(a) is a view showing an example of the data path diagram to be converted by a data path conversion element according to the first embodiment;

FIG. 15(b) is a view showing a hardware description language obtained by converting the data path diagram of FIG. 15(a);

FIG. 16(a) is a view showing an example of the truth table to be converted by a truth table conversion element according to the first embodiment;

FIG. 16(b) shows the truth table hardware description language obtained by converting the truth table of FIG. 16(a);

FIG. 17(a) s a view snowing an example of the logical expression table to be converted by a logical expression conversion element according to the first embodiment;

FIG. 17(b) is a view showing a hardware description language obtained by converting the logical expression table of FIG. 17(a);

FIG. 18 is a block diagram showing an example of the structure of the data-path-diagram conversion element according to the first embodiment;

FIG. 19 is a view showing an example of the data path diagram to be converted by the data-path-diagram conversion element of FIG. 18;

FIG. 20(a) is a view showing a hardware description language obtained through the conversion of the data path diagram of FIG. 19 by the data-path-diagram conversion element of FIG. 18;

FIG. 20(b) is a circuit diagram of a circuit obtained by logically synthesizing the hardware description language of FIG. 20(a);

FIG. 21(a) is a hardware description language obtained through the conversion of the data path diagram of FIG. 19 by the data-path-diagram conversion element of FIG. 18;

FIG. 21(b) is a circuit diagram of a circuit obtained by logically synthesizing the hardware description language of FIG. 21(a);

FIG. 22 is a block diagram showing another example of the structure of the data-path-diagram conversion element according to the first embodiment;

FIG. 23 is a view showing an example of the data path diagram to be converted by the data-path-diagram conversion element of FIG. 22;

FIG. 24(a) is a view showing a hardware description language obtained by converting a register RegA in the data path diagram of FIG. 23;

FIG. 24(b) is a view showing a hardware description language obtained by converting a register RegB in the data path diagram of FIG. 23;

FIG. 25 is a circuit diagram of a circuit obtained by logically synthesizing the hardware description language of FIG. 24(a) and the hardware description language of FIG. 24(b);

FIG. 26 is a block diagram showing an example of the structure of a functional simulation element according to the first embodiment;

FIG. 27 is a block diagram showing the structure of a function simulator element according to the first embodiment;

FIG. 28 is a view showing a state value storage table of the above function simulator element;

FIG. 29 is a view showing changes in state values resulting from the functional simulation operation of the above function simulator element;

FIG. 30(a) is a view showing a logic circuit to be subjected to forward simulation performed by a state value update element of the above function simulator element;

FIG. 30(b) is a timing chart showing data for the above forward simulation and the simulation result;

FIG. 31 is a block diagram showing the structure of an event processing element of the above function simulator element;

FIG. 32 is a block diagram showing the structure of an evaluation element of the above function simulator element;

FIG. 33 is a view showing the correspondence of an input and an output when an encoder according to the first embodiment performs encoding;

FIG. 34 is a view showing a specific example of the encoding of a logic signal;

FIG. 35 is a block diagram showing the structure of a ZX conversion element of the above evaluation element;

FIG. 36 is a view diagrammatically showing a specific example of the operation of the above evaluation element;

FIG. 37 is a view showing a specific example of the above ZX conversion element;

FIG. 38 is a block diagram showing the structures of a control unit and of an input display element according to the first embodiment;

FIG. 39 is a view showing a table displayed by a tabular input display element according to the first embodiment;

FIG. 40 is a view showing changes in simulation time due to the functional simulation control operation by a function simulator control element according to the first embodiment;

FIG. 41(a) is a view showing a control panel displayed by a control panel display element according to the first embodiment;

FIG. 41(b) is a view showing a jump execute control panel displayed by pushing a jump execute button in the above control panel;

FIGS. 42(a) and 42(b) are data path diagrams showing a logic circuit to be subjected to functional simulation;

FIG. 42(c) is a view showing a pattern in tabular form inputted to and displayed by a table input display element according to the first embodiment;

FIG. 43(a) is a waveform chart showing a waveform pattern inputted to the above waveform input display element;

FIG. 43(b) is a waveform chart showing a waveform pattern displayed by the above waveform input display element;

FIG. 44 is a view showing a memory pattern inputted to and displayed by a memory pattern input display element according to the first embodiment;

FIG. 45 is a view showing test data used in past functional simulation which is inputted to and displayed by a pattern history input display element according to the first embodiment;

FIG. 46(a) is a view showing a pattern in the form of a functional diagram inputted to a functional diagram input display element according to the first embodiment;

FIG. 46(b) is a view showing a pattern in the form of a functional diagram displayed by the above functional diagram input display element;

FIG. 47 is a block diagram showing the structures of a functional diagram input display control element and the structure of the functional diagram input display element according to the first embodiment;

FIG. 48(a) is view showing a pattern inputted to and displayed by a state-transition-diagram input display element according to the first embodiment;

FIG. 48(b) is a view showing a pattern inputted to and displayed by a logical expression input display element according to the first embodiment;

FIG. 48(c) is a view showing a pattern inputted to and displayed by a truth table input display element according to the first embodiment;

FIG. 49 is a flow chart showing a functional design verification method using a functional design support apparatus provided with the above function simulator element;

FIG. 50 is a flow chart showing a detailed process of forward simulation in the functional design verification method of FIG. 49;

FIG. 51 is a flow chart showing a detailed process of backward simulation in the functional design verification method of FIG. 49;

FIG. 52 is a block diagram showing another example of the structure of the functional simulation element according to the first embodiment;

FIG. 53 is a block diagram showing the overall structure of the functional design support apparatus according to a second embodiment of the present invention;

FIG. 54(a) is a view showing a periodic waveform set in the functional diagram by a design-constraint-information input element according to the second embodiment;

FIG. 54(b) is a view showing a design constraint description language corresponding to the periodic waveform of FIG. 54(a), which is implemented by a design-constraint description-language conversion element according to the second embodiment;

FIG. 55(a) is a view showing fan-out and fan-in set in the functional diagram by the above design-constraint-information input element;

FIG. 55(b) is a view showing a design constraint description language corresponding to the fan-out and fan-in of FIG. 55(a), which is implemented by the above design-constraint-description-language conversion element;

FIG. 56(a) is a view showing a delay value set in the functional diagram by the above design-constraint- information input element;

FIG. 56(b) is a view showing a design constraint description language corresponding to the delay value of FIG. 56(a), which is implemented by the above design-constraint-description-language conversion element;

FIG. 57 is a flow chart showing the functional design support method using the functional design support apparatus according to the second embodiment; and

FIG. 58 is a block diagram showing the structure of a conventional logic design support apparatus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Example 1

Referring now to the drawings, a functional design support apparatus according to a first embodiment of the present invention will be described above. (Overall Structure of Functional Design Support Apparatus)

FIG. 1 is a block diagram showing the overall structure of the functional design support apparatus according to the first embodiment.

In the drawing, a reference numeral 1 designates an input unit for accepting data from the outside.

A reference numeral 2 designates a CRT monitor for displaying information.

A reference numeral 3 designates a processor of the functional design support apparatus comprising a functional-diagram-information storage unit 4, a functional diagram editor element 5, a functional diagram check element 6, a functional simulation element 7, and a functional description-language conversion element 8.

The functional-diagram-information storage unit 4 stores functional diagram information on a functional diagram in which the operation of a logic circuit is represented by symbols, tables, characters, and the like.

The functional diagram editor element 5 has functions of: describing the functional diagram by means of symbols, tables, characters, and the like on the screen of the CRT monitor 2; storing, in the functional diagram-information storage unit 4, functional diagram information on the described functional diagram; and reading the functional diagram information from the functional diagram-information storage unit 4.

The functional diagram check element 6 reads the functional diagram information from the functional-diagram-information storage unit 4 and detects the presence or absence of a contradiction in the functional diagram indicated by the functional diagram information. The functional diagram information read here includes information on the functional diagram described by the functional diagram editor element 5, information on the functional diagram described in other element, and the like.

The functional simulation element 7 reads, from the functional diagram-information storage unit 4, functional diagram information free from contradiction, as a result of the detection by the functional diagram check element 6 and the correction by the functional diagram editor element 5, and executes functional simulation with respect to the functional diagram, thereby verifying the function of the logic circuit.

A hardware-description-language conversion element 8 reads functional diagram information on the functional diagram which has undergone the functional verification by the functional simulation element 7 and generates a hardware description language from the functional diagram.

A reference numeral 9 designates the hardware description language generated by the hardware-description-language conversion element 8.

A reference numeral 10 designates a language based function simulator which accepts the hardware description language 9 and a test vector so as to perform functional simulation at a high speed in the hardware description language.

A reference numeral 11 designates the test vector to be inputted to the language based function simulator 10.

A reference numeral 12 designates a logic synthesizer which accepts the hardware description language 9 and generates netlist information.

A reference numeral 13 designates the netlist information generated by the logic synthesizer 12.

FIG. 2 is a flow chart showing a functional design support method using the functional design support apparatus thus constituted.

First, as shown in Step SA1 of the flow chart, the functional diagram editor element 5 generates a functional diagram using symbols, tables, characters, and the like.

Next, in Step SA2, the functional diagram check element 6 accepts the functional diagram generated in Step SA1 and detects the presence or absence of a contradiction in the functional diagram.

Next, in Step SA3, it is determined whether or not a contradiction exists in the functional diagram. If there is no contradiction, the process goes on to Step SA4. On the other hand, if there is any contradiction, the process goes on to Step SA9 where the functional diagram is corrected using symbols, tables, characters, and the like, thereby returning to Step SA2.

In Step SA4, the functional simulation element 7 executes functional simulation in the functional diagram, so as to verify the function of the logic circuit.

Next, in Step SA5, it is determined whether or not an error exists in the operation of the logic circuit. If there is no error, the process goes on to Step SA6. On the other hand, if there is any error, the process goes on to Step SA9 where the functional diagram is corrected using symbols, tables, characters, and the like, thereby returning to Step SA2.

In the case where the functional diagram contains any contradiction or where the circuit operation represented by the functional diagram contains any error, above Steps SA2 to SA5 and Step SA9 are repeatedly performed.

If the functional diagram contains no more contradiction and if the circuit operation represented by the functional diagram contains no more error, the hardware-description-language conversion element 8 generates the hardware description language
9 from the functional diagram in Step SA6.

Subsequently, in Step SA7, the language based function simulator 10 accepts the hardware description language 9 generated in Step SA6 as well as the test vector 11 and performs functional simulation in the hardware description language.

Next, in Step SA8, the logic synthesizer 12 accepts the hardware description language 9 and generates the netlist information 13.

Thus, with the functional design support apparatus of the present embodiment, the functional design of a logic circuit can be implemented by generating a functional diagram in which the operation of the logic circuit is represented by symbols, tables, characters, and the like, without using a hardware description language. The hardware description language can be generated automatically from the functional diagram. Moreover, with the logic synthesizer, it is also possible to obtain netlist information from the hardware description language generated.

The present embodiment can be implemented both on a dedicated hardware and on a calculator having a CPU and a memory.

(Functional Diagram Editor Element)

Below, the functional diagram editor element 5 of the functional design support apparatus according to the first embodiment will be described in detail.

FIG. 3 is a block diagram showing an example of the structure of the functional diagram editor element 5. In the drawing, a functional diagram-information storage unit 4 stores functional diagram information on a functional diagram in which the operation of a logic circuit is represented by symbols, tables, characters, and the like, similarly to the corresponding unit shown in FIG. 1.

It is possible to design the logic circuit so that it is constituted by: a control part for controlling the operation; a data path part for showing data flow; and a combinational circuit part. The functional diagram editor element 5 comprises: a state-transition-diagram editor element 5a provided corresponding to the control part of the logic circuit; a data path editor element 5b provided corresponding to the data path part of the logic circuit; and a combinatorial logic editor element 5c provided corresponding to the combinational circuit part of the logic circuit. The combinatorial logic editor element 5c has a truth table editor element 5d and a logical expression editor element 5e.

The state-transition-diagram editor element 5a describes, in the multi-window of the CRT monitor 2, the control part of the logic circuit in the form of a state transition diagram. The state-transition-diagram editor element Sa also has a function of storing, in the functional diagram-information storage unit 4, the functional diagram in the form of a described state transition diagram and a function of accepting, from the functional diagram-information storage unit 4, the functional diagram in the form of a state transition diagram.

The data path editor element 5b describes, in the multi-window of the CRT monitor 2, the data path part of the logic circuit in the form of a data path diagram which shows the layout of functional elements and the interconnection thereof. The data path editor element 5b also has a function of storing, in the functional diagram-information storage unit 4, the functional diagram in the form of a described data path diagram and a function of accepting, from the functional diagram-information storage unit 4, the functional diagram in the form of a data path diagram.

The truth table editor element 5d describes, in the multi-window of the CRT monitor 2, the combinational circuit part of the logic circuit in the form of a truth table. The truth table editor element 5d also has a function of storing, in the functional diagram-information storage unit 4, the functional diagram in the form of a described truth table and a function of accepting, from the functional-diagram-information storage unit 4, the functional diagram in the form of a truth table.

The logical expression editor unit 5e describes, in the multi-window of the CRT monitor 2, that one of the combinational circuits of the logic circuit which is difficult to describe in a truth table in the form of a logical expression table. The logical expression editor element 5e also has a function of storing, in the functional diagram-information storage unit 4, the functional diagram in the form of a described logical expression table and a function of accepting, from the functional diagram-information storage unit 4, the functional diagram in the form of a logical expression table.

A reference numeral 2a designates, among windows constituting the multi-window of the CRT monitor 2, a state-transition-diagram window for displaying the state transition diagram to be edited by the state-transition-diagram editor element 5a.

A reference numeral 2b designates, among the windows constituting the multi-window of the CRT monitor 2, a data-path-diagram window for displaying the data path diagram to be edited by the data path editor element 5b.

A reference numeral 2c designates, among the windows constituting the multi-window of the CRT monitor 2, a truth table window for displaying the truth table to be edited by the truth table editor element 5d

A reference numeral 2d designates, among the windows constituting the multi-window of the CRT monitor 2, a logical expression window for displaying the logical expression table to be edited by the logical expression editor element 5e.

As described above, with the functional design support apparatus of the present embodiment, it is possible to simultaneously describe the state transition diagram, data path diagram, truth table, and logical expression table in the multi-window of the CRT monitor 2 by means of the state-transition-diagram editor element 5a, data path editor element 5b, truth table editor element 5d, and logical expression editor element 5e.

Here, the functional diagrams described by the individual editor units will be explained with reference to FIGS. 4, 5, 6, and 7.

FIG. 4 is a specific example of the state transition diagram described by the state-transition-diagram editor element 5a. In the drawing, a reference numeral 300 designates a state transition clock signal specification which specifies a clock signal for controlling the state transition, 301 designates a reset signal specification which describes a signal for forcibly returning the state under transition to the initial state and specifies the initial state by an arrow. Reference numerals 302,
303, and 304 show the states under transition. The arrows from the states show the destinations of the states after transition. The state 302 is the initial state prior to transition specified by the reset signal specification 301. Reference numerals
305 and 306 designate arrows for unconditional transition which indicates unconditional transition to the next state in synchronization with the clock signal specified by the state transition clock signal 300. A reference numeral 307 designates a condition label for conditional state transition. When the signal value of the condition label is 1, "START" of the state 302 changes to "ST1" of the state 303 in synchronization with the clock signal specified by the state transition clock signal specification. A reference numeral 308 designates an else label which is added to the arrow showing the destination of the state after transfer when the unconditional state transition did not occur and the conditional state transition did not occur, either.

FIG. 5 shows a specific example of the data path diagram described by the data path editor element 5b. In the drawing, reference numerals 310 and 311 designate input pins to which signal values are inputted from the outside. A reference numeral
312 designates an output pin for outputting the signal values to the outside. Reference numerals 313 and 314 designate terminals. A reference numeral 315 designates a register for storing the signal value in synchronization with the rise of the clock signal CLK and resetting the stored signal value to 0 when the reset signal RST is 1. Reference numerals 316, 317, and 318 designate arrows indicating the destinations of the signal values after unconditional propagation, which suggests the unconditional propagation of the signal values. Reference numerals 319 and 320 designate condition labels added to the conditional- propagation-destination arrow. When the signal value of the condition label is 1, the conditional-propagation-destination arrow suggests the propagation of the signal value. The other constituents of the data path diagram include: logical calculators for performing logical operations such as AND and OR operations; numeric calculators for performing arithmetic operations such as addition and subtraction; comparators; memories such as a RAM and ROM; page-to-page connectors for connecting a signal spreading over a plurality of data path diagrams; and submodules.

The logical calculators include: a logical NOT calculator; a logical AND calculator; a logical OR calculator; a logical EXCLUSIVE-OR calculator; a logical NAND calculator; a logical NOR calculator; and a logical EXCLUSIVE-NOR calculator. The arithmetic calculators include: an increment calculator; a decrement calculator; an adder without carry; a subtracter without borrow; an adder with carry; a subtracter with borrow; a multiplier; a divider; and a shift calculator. The comparators include: a magnitude comparator for comparing the magnitudes of the state values of signals; a match comparator for determining whether or not the state values of signals match; and a mismatch comparator for determining whether or not the state values of signals mismatch.

FIG. 6 shows a specific example of the truth table described by the truth table editor element 5d. In the drawing, reference numerals 330 and 331 designate reference signal names for describing signal names which are referred to by the truth table, 332 and 333 designate labels the signal values of which are determined by the conditions on the truth table, 334, 335, and 337 designate conditional-value fields in which values serving as conditions are described. It is possible to describe a plurality of conditions in each of the conditional-value fields. In this case, the conditions correspond to the logical OR of all the conditional values described in the conditional-value field. Reference numerals 338 and 339 designate logical AND conditional fields for performing the logical AND operation between the conditional values in the conditional field. The example shows the case where the condition of activating the label a is: sell = 1 and sel2 [1:0] =0 or 1. The condition of activating the label b is: sell = 1 and sel2 [1:0] is 2 or 3. It is possible to describe the name of the state transition diagram as the reference signal name. In this case, the state name described in the state transition diagram is described in the conditional-value field. It is possible to describe a plurality of reference signal names and labels on the truth table.

FIG. 7 shows a specific example of the logical expression table described by the logical expression editor element 5e. In the drawing, reference numerals 340 and 341 designate conditional-expression fields for describing a label name and a conditional expression in which the condition of activating the label is represented in a logical expression. Reference numerals 342 and 343 designate label names, and 344 and 345 designate conditional expressions which represent the conditions of activating the corresponding labels. The logical symbols "&," ".vertline.," "==," and "()" represent logical AND, logical OR, comparison, and parentheses, respectively. The logic symbols which can be used in the diagram are not limited thereto. Any symbol can be used therein provided that it represents a logical operation.

The truth table or logical expression table defines the condition of activating the condition label for the conditional state transition in the state transition diagram, the condition of activating the condition label added to the conditional propagation destination arrow in the data path diagram, and the like.

(Functional Diagram Check Element)

Below, the functional diagram check element 6 of the functional design support apparatus according to the first embodiment will be described in detail.

FIG. 8 is a block diagram showing an example of the structure of the functional diagram check element 6. In the drawing, a functional diagram-information storage unit 4 stores information on a functional diagram in which the operation of the logic circuit is represented by symbols, table, characters, and the like, similarly to the corresponding unit shown in FIG. 1.

The functional diagram check element 6 comprises a check element 20, a check result screen display element 22, and an error-report-file generation element 23.

The check element 20 reads functional diagram information from the functional diagram-information storage unit 4 and determines, based on check rules, whether or not the functional diagram indicated by the functional diagram information contains an error, thereby generating check result information 21.

The check result screen display element 22 displays, on the screen of the CRT monitor 2, information on the connection, definition, reference and the like of each circuit component, so that it reflects the check result information 21. This enables the cross probing of an error point and the circuit component associated with the error.

The error-report-file generation element 23 generates an error report file 24 based on the check result information 21.

The functional diagram information is implemented on the screen of the CRT monitor 2 by a plurality of windows constituting the multi-window, which are: the state-transition-diagram window representing the control part of the logic circuit; the data-path-diagram window representing the data path part of the logic circuit; and the truth table window or logical expression window representing the combinational circuit portion of the logic circuit. The names used in common in the plurality of windows are considered to designate the same components.

FIGS. 9(a), 9(b), 9(c), and 9(d) show the plurality of windows displayed on the screen of the CRT monitor 2: FIG. 9(a) shows an example of the state-transition-diagram window; FIGS. 9(b) and 9(c) show examples of the data-path-diagram window; and FIG. 9(d) shows an example of the truth table window. As shown in the drawings, the condition label Labell referred to in the state-transition-diagram window (St Machine) of FIG. 9(a) and in the data-path-diagram window (RT1) of FIG. 9(b) is defined by the truth table window (TABLE) of FIG. 9(d) by using RegA in the data-path-diagram window (RT1) of FIG. 9(b). Consequently, it becomes necessary to perform an error check over the plurality of windows in addition to the conventional error check on the connection and the like in a single window.

FIG. 10 is a block diagram showing an example of the structure of the check element 20 in the functional diagram check element 6. The check element 20 of this example is constituted so that an error check can be performed over the plurality of windows in checking the functional diagram.

Check result information 21 of FIG. 10 is the same as the one shown in FIG. 8.

In the functional diagram-information storage unit 4, there is stored: state-transition-diagram information corresponding to the state-transition-diagram window 346; data-path-diagram information corresponding to the data-path-diagram window 347; truth table information corresponding to the truth table window 348; and logical expression information corresponding to the logical expression window 349, each serving as the functional diagram information.

The check element 20 comprises: a first check element 20a for detecting a name error; a second check element 20b for detecting an undefined name; a third check element 20c for detecting duplicate names; a fourth check element 20d for detecting the disconnection between components; a fifth check element 20e for detecting an error in bit width; and a sixth check element 20f for detecting an error in the setting of the condition label. The first check element 20a detects the presence or absence of a description error in the definition of bit width which follows the name and the presence or absence of an error in which a reserved word is used in the name. The detection is performed with respect to all the windows by using the state transition diagram information, data-path-diagram information, truth table information, and logical expression information. If an error is detected, the first check element 20a outputs the check result information 21 indicating an error.

The second check element 20b examines whether or not the condition label referred to in the state-transition-diagram window 346 or data-path-diagram window 347 is defined in the truth table window 348 or logical expression window 349 by using the state-transition-diagram information, data-path-diagram information, truth table information, and logical expression information. If the condition label is not defined yet, it outputs the check result information 21 indicating the undefined condition label.

The third check element 20c examines whether or not the same name is used to define components of different types. The examination is performed with respect to all the windows by using the state-transition-diagram information, data-path-diagram information, truth table information, and logical expression information. If duplicate names are detected, the third check element elements 20c outputs the check result information 21 indicating the duplicate names.

The fourth check element 20d detects the presence or absence of any state containing no transition arrow in the state-transition-diagram window 346, the presence or absence of any functional element with no transfer arrow in the data-path-diagram window 347, and the presence or absence of any label which has not been referred to either in the truth table window 348 or in the logical expression window 349. The detection is performed with respect to each window using the state-transition-diagram information, data-path-diagram information, truth table information, and logical expression information. If the above state, functional element, or label is present, the fourth check element 20d outputs the check result information 21 indicating their presence.

The fifth check element 20e examines whether or not a transfer arrow exists between functional elements having different bit widths in the data-path-diagram window 347 or, if the bits of the functional elements defined in the data-path-diagram window 347 are partly selected and referred to in the truth table window 348 or logical expression window 349, the fifth check element 20e examines whether or not the width of the selected bit is in the range of the original bit width when it was defined. The examination is conducted using the data-path-diagram information, truth table information, and logical expression information. If there is any error in bit width, the fifth check element 20e outputs the check result information 21
indicating the bit-width error.

The sixth check element 20f examines whether or not the condition labels are set to all the transition arrows indicating the states having a plurality of transition destinations in the state-transition-diagram window 346 or whether or not the condition labels are set to all the transfer arrows of the functional element having a plurality of transfer starting functional elements in the data-path-diagram window 347. The examination is conducted using the state-transition-diagram information and data-path-diagram information. If there is any arrow to which the condition label is not set, the sixth check element 20f outputs the check result information 21 indicating the arrow to which the condition label is not set.

If the specific content of the functional diagram information read from the functional diagram-information storage unit 4 into the check element 20 corresponds to the window shown in FIG. 10, static errors contained in the functional diagram include: the undefined error in which the condition label Label5 referred to in the data-path-diagram window 347 is not defined in the truth table window 348 and in the logical expression window 349; the bit-width error in which the 4-bit register RegB is connected to the input of the 8-bit adder Add in the data-path-diagram window 347; and the condition label setting error in which, among all the transition arrows from the state St2 in the state-transition-diagram window 346, there is one to which the condition label is not set. These errors are outputted as the check result information 21, which is displayed by the check result screen display element 22 on the screen of the CRT monitor 2.

FIG. 11 shows the above check result information 21 displayed on the screen. In the drawing, a reference numeral 350 designates state transition information, 351 designates functional element connection information, and 352 designates definition and reference information for the condition label.

The state transition information 350 indicates the name of the transition destination state for each state in the state-transition-diagram window 346. The functional element connection information 351 indicates the name of the transfer starting element and the name of the transfer destination element for each functional element in the data-path-diagram window 347. If the functional element is a storage element, the name of the activation signal is also shown. The definition and reference information 352 for the condition label indicates for each condition label defined either in the truth table window 348 or in the logical expression window 349, the name of the window in which it was defined and the name of the window in which it is referred to. The check result information 21 is added to the information on the connection, definition, and reference of each circuit component.

If the label error is specified on the screen of FIG. 11 displaying the check result information, the state St2 associated with the label error in the state-transition-diagram window 346 and the transition arrow from the state St2 with no transition condition label to the state St4 are highlighted. If the bit-width error is specified on the screen of FIG. 11 displaying the check result information, the functional elements RegB and Add1 associated with the bit-width error in the data-path-diagram window 347 and the transfer arrow therebetween are highlighted. If the condition label undefined error is specified on the screen of FIG. 11 displaying the check result information, the condition label5 associated with the condition label undefined error in the data-path-diagram window 347 is highlighted. In this manner, an error point can easily be located.

In addition to the above display method using a high light, there are other methods of displaying the error point such as the blinking display method or the changing-color display method. Any display method can be used provided that it shows the error point clearly.

As described above, since the functional design support apparatus of the present embodiment is provided with the check element 20, the connection, definition, and references in the functional diagram can easily be recognized based on the check result displayed on the screen in the functional design using the functional diagram information. Consequently, it becomes possible to find out design mistakes with ease due to the check result displayed on the screen, cross-probing display of the error point, and outputted report file. (Functional Description Language Conversion Element) Below, the hardware-description-language conversion element 8 of the functional design support apparatus according to the first embodiment will be described in detail.

In general, the range covered by the description in the hardware description language for logic synthesis is narrower than the range covered by the description in the hardware description language for language-based functional simulation, so that the functional description language generated for the language based function simulator cannot be inputted to the logic synthesizer. Conversely, the hardware description language generated for the logic synthesizer can be inputted to the language based function simulator. In this case, however, the speed at which functional simulation is executed is lower than in the case where the hardware description language generated for the language based function simulator is used instead. When the same hardware description language is inputted to the logic synthesizer and to the language based function simulator, the meaning of the operation in the logic synthesizer is different from the meaning of the operation in the language based function simulator, so that the operations of the circuits in the logic synthesizer and in the language based function simulator are different. Consequently, functional verification cannot be performed effectively.

FIG. 12 is a block diagram showing an example of the structure of the hardware-description-language conversion element 8, which will solve all the problems mentioned above.

A functional diagram-information storage unit 4, hardware description language 9, language based function simulator 10, and logic synthesizer 12 shown in FIG. 12 are the same as those shown in FIG. 1.

The hardware-description-language conversion element 8 comprises a conversion element for logic synthesis 30 and a conversion element for simulation 31.

The conversion element for logic synthesis 30 reads the functional diagram information from the functional diagram-information storage unit 4 and generates, from the functional diagram information, a hardware description language for logic synthesis 32 which is suitable for the logic synthesizer 12. The conversion element for logic synthesis 30 also has a function of generating a hardware description language for logic synthesis 32A which is suitable for another logic synthesizer 12A and a function of generating a hardware description language for logic synthesis 32B which is suitable for still another logic synthesizer 12B.

The simulation conversion element 31 reads the functional diagram information from the functional-diagram-information storage unit 4 and generates, from the functional diagram information, a hardware description language for simulation 33 which is suitable for the language based function simulator 10. Moreover, the conversion element for simulation 31 has a function of generating a hardware description language for simulation 33A which is appropriate for another language based function simulator 10A and a function of generating a hardware description language for simulation 33B which is suitable for still another language based function simulator 10B.

Thus, with the functional design support apparatus of the present embodiment, the functional diagram information can be converted, by the conversion element for logic synthesis 30, to the hardware description language for logic synthesis which is suitable for the logic synthesizer. At the same time, the functional diagram information can also be converted, by the conversion element for simulation 31, to the hardware description language for language based functional simulation which is suitable for the language based function simulator. Consequently, the circuits which operate in the same manner both in the logic synthesizer and in the language based function simulator can be obtained without considering the operations of the hardware description languages, so that the above problems can be solved at the same time.

FIG. 13 is a block diagram showing an example of the structure of the conversion element for logic synthesis 30 in the hardware-description-language conversion element 8.

A functional diagram-information storage unit 4, conversion element for logic synthesis 30, hardware description language f or logic synthesis 32, and logic synthesizer 12 are the same as those show