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United States Patent5619508
Davis , ; et al.April 8, 1997
Title
Dual port interface for a computer-based multifunction personal communication system
Abstract
A personal communications system enables the operator to simultaneously transmit voice and data communication to a remote site. The personal communications system is equipped with two telephone line interfaces to allow connection between two remote sites. The connection between the first remote site and the local site may operate in a voice over data communications mode to simultaneously send compressed voice and data. The connection between the local site and a second site is a voice only connection allowing the first remote site to talk to the second remote site without breaking the data communication connection between the first site and the local site. The second remote site amy be a public telephone network. The communication between the first remote site and the second remote site through the local site may also be a data communication connection, or it may also be a voice over data communication connection.
Inventors:Davis; Jeffrey P. (Ham Lake, MN), Sharma; Raghu  (North Oaks, MN)
Assignee:Multi-Tech Systems, Inc. (Mounds View, MN)
Appl. No.:409017
Filed:March 23, 1995
Current U.S. Class:370/495 370/496 379/93.08 
Field of Search:370/81,80,110.1,76,79 379/101,109,108,93,96
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Primary Examiner: Chin; Wellington
Attorney, Agent or Firm:Schwegman, Lundberg, Woessner & Kluth, P.A.
Parent Case Text


This patent application is a divisional of U.S. patent application Ser. No. 08/161,915 filed Dec. 3, 1993, now U.S. Pat. No. 5,453,986 which is a Continuation-In-Part of U.S. patent application Ser. No. 08/142,801 filed Oct. 25, 1993 now U.S. Pat. No. 5,453,986, issued on Sep. 26, 1995, entitled "RINGDOWN AND RINGBACK SIGNALLING FOR A COMPUTER-BASED MULTIFUNCTION PERSONAL COMMUNICATIONS SYSTEM", the complete application of which is hereby incorporated by reference, which application is also a Continuation-In-Part of U.S. patent application Ser. No. 08/002,467 filed Jan. 8, 1993 now U.S. Pat. No. 5,452,289 issued on Sep. 19, 1995 entitled "COMPUTER-BASED MULTIFUNCTION PERSONAL COMMUNICATIONS SYSTEM", the complete application of which, including the microfiche appendix, is also hereby incorporated by reference.
Claims

We claim:
1. A communication apparatus, comprising:
data interface connected a personal computer;
first telephone line interface means for connection to a first telephone line;
second telephone line interface means for connection to a second telephone line;
telephone device means for receiving local voice signals from a local user and for conveying remote voice signals from a remote user to the local user;
full-duplex conversion means connected to the telephone device means for converting the local voice signals into outgoing digital voice data and for converting incoming digital voice data into the remote voice signals;
voice compression means connected to the full-duplex conversion means for compressing the outgoing digital voice data into compressed outgoing digital voice data and for decompressing compressed incoming digital voice data into the incoming digital voice data;
main control means connected to the voice compression means, the data interface, the first telephone line interface means and the second telephone line interface means, for
receiving the compressed outgoing digital voice data from the voice compression means,
receiving outgoing computer digital data from the personal computer through the data interface,
multiplexing and transmitting compressed outgoing digital voice data with the outgoing computer digital data to the first telephone line interface means for transmission on the first telephone line,
receiving and demultiplexing compressed incoming digital voice data and incoming computer digital data from the first telephone line interface means from the first telephone line, and
passing the remote voice signals to the second telephone line interface means for transmission on the second telephone line.

2. The apparatus according to claim 1 wherein the main control means is further operable for detecting silent periods in the outgoing digital voice data and for producing in response thereto a silence flag and wherein the main control means is further operable for transmitting outgoing conventional digital data when the silence flag indicates the absence of voice information and wherein the main control means is further operable for multiplexing and transmitting both the compressed outgoing digital voice data and the outgoing computer digital data when the silence flag indicates the presence of voice information.

3. The apparatus according to claim 1 wherein the first telephone line includes a cellular telephone link and wherein the main control means is further operable for periodically transmitting a cellular supervisory packet on the first telephone line and for maintaining the cellular telephone link over the telephone line if the receipt of the cellular supervisory packet is acknowledged within a predetermined period of time and for dropping the link over the telephone line if the cellular supervisory packet is not acknowledged within a predetermined period of time.

4. The apparatus according to claim 1 wherein the voice compression means is further operable for compressing the outgoing digital voice data into compressed outgoing digital voice data by performing the steps of:
a.) removing any DC bias in the outgoing digital voice signal to produce a pre-emphasized outgoing digital voice signal;
b.) pre-emphasizing the normalized outgoing digital voice signal to produce a pre-emphasized outgoing digital voice signal;
c.) dividing the pre-emphasized outgoing digital voice signal into segments to produce a current speech segment and a past speech segment;
d.) predicting the pitch of the current speech segment to form a pitch prediction;
e.) calculating the gain of the pitch of the current speech segment to form a prediction gain;
f.) reconstructing the past speech segment from a compressed past segment to produce a reconstructed past segment;
g.) finding the innovation in the current speech segment by comparing the pitch prediction to the reconstructed past segment to produce an error signal;
h.) determining the maximum amplitude in the current speech segment;
i.) quantizing the error signal using a code book generated from a representative set of speakers and environments to produce a minimum mean squared error matching the form of an index into the code book; and
j.) recording the pitch prediction, the prediction gain, the maximum amplitude and the index into the code book in a packet as the compressed outgoing digital voice data.

5. The apparatus according to claim 1 wherein the main control means is further operable for passing the outgoing computer digital data along with the remote voice signals to the second telephone line interface means for transmission on the second telephone line.
Description
FIELD OF THE INVENTION

The present invention relates to communications systems and in particular to computer assisted digital communications having a voice over data communications ability which allows feed-through communications to a third party.

BACKGROUND OF THE INVENTION

A wide variety of communications alternatives are currently available to telecommunications users. For example, facsimile transmission of printed matter is available through what is commonly referred to as a stand-alone fax machine. Alternatively, fax-modem communication systems are currently available for personal computer users which combine the operation of a facsimile machine with the word processor of a computer to transmit documents held on computer disk. Modem communication over telephone lines in combination with a personal computer is also known in the art where file transfers can be accomplished from one computer to another. Also, simultaneous voice and modem data transmitted over the same telephone line has been accomplished in several ways.

There is a need in the art, however, for a personal communications system which combines a wide variety of communication functions into an integrated hardware-software product such that the user can conveniently choose a mode of communication and have that communication automatically invoked from a menu driven selection system.

There is a further need in the art for a personal communications system which provides a voice over data communications mode between a first and second party, while allowing a voice communications mode between a second and third party thereby allowing a voice connection between the first and third parties.

SUMMARY OF THE INVENTION

The present disclosure describes a complex computer assisted communications system. The subject of the present invention is a personal communications system which includes components of software and hardware operating in conjunction with a personal computer. The user interface control software operates on a personal computer, preferably within the Microsoft Windows.RTM. environment. The software control system communicates with hardware components linked to the software through the personal computer serial communications port. The hardware components include telephone communication equipment, digital signal processors, and hardware to enable both fax and data communication with a hardware components at a remote site connected through a standard telephone line. The functions of the hardware components are controlled by control software operating within the hardware component and from the software components operating within the personal computer.

Communications between the software components running on the personal computer and the local hardware components over the serial communications link is by a special packet protocol for digital data communications. This bi-directional communications protocol allows uninterrupted bidirectional full-duplex transfer of both control information and data communication.

The major functions of the present system are a telephone function, a voice mail function, a fax manager function, a multi-media mail function, a show and tell function, a terminal function and an address book function. The telephone function allows the present system to operate, from the users perspective, as a conventional telephone using either hands-free, headset or handset operation. The telephone function is more sophisticated than a standard telephone in that the present system converts the voice into a digital signal which can be processed with echo cancellation, compressed, stored as digital data for later retrieval and transmitted as digital voice data concurrent with the transfer of digital information data.

The voice over data (show and tell) component of the present system enables the operator to simultaneously transmit voice and data communication to a remote site. This voice over data function dynamically allocates data bandwidth over the telephone line depending on the demands of the voice grade digitized signal. With the present system, the user may enter voice over data mode from a data transfer mode by lifting the handset of the telephone connected to the modem. The off-hook condition is sensed and software sends a supervisory packet to the remote site to invoke voice-over-data mode. The Remote telephone will simulate a ring to alert the remote user, and the local telephone will simulate a ringback to inform the caller that the remote unit is responding.

The computer assisted communications system of the present invention includes a dual telephone line interface to allow voice over data communication through a first telephone line interface and voice communication through a second telephone line interface. In the preferred embodiment of the present invention, the first party establishes voice over data communication with the second party. The first party can then initiate a voice connection through the second telephone line interface of the second party to communicate in voice mode to a third party. In an alternate embodiment, the first party can initiate a data connection through the second telephone line interface of the second party to communicate in data mode to a third party.

These features of the hardware component of the present system along with the features of the software component of the present system running on a PC provides a user with a complete range of telecommunications functions of a modern office, be it a stationary or mobile.

DESCRIPTION OF THE DRAWINGS

In the drawings, where like numerals describe like components throughout the several views,

FIG. 1 shows the telecommunications environment within which the present invention may operate in several of the possible modes of communication;

FIG. 2 is the main menu icon for the software components operating on the personal computer;

FIG. 3 is a block diagram of the hardware components of the present system;

FIG. 4 is a key for viewing the detailed electrical schematic diagrams of FIGS. 5A-10C to facilitate understanding of the interconnect between the drawings;

FIGS. 5A-5C, 6A-6C, 7A-7C, 8A-8B, 9A-9C and 10A-C are detailed electrical schematic diagrams of the circuitry of the hardware components of the present system;

FIG. 11 is a signal flow diagram of the speech compression algorithm;

FIG. 12 is a detailed function flow diagram of the speech compression algorithm;

FIG. 13 is a detailed function flow diagram of the speech decompression algorithm;

FIG. 14 is a detailed function flow diagram of the echo cancellation algorithm;

FIG. 15 is a detailed function flow diagram of the voice/data multiplexing function;

FIG. 16 is a perspective view of the components of a digital computer compatible with the present invention;

FIG. 17 is a block diagram of the software structure compatible with the present invention;

FIG. 18 is a block diagram of the hardware components of the system including a dual telephone line interface;

FIG. 19 is a diagram of the telecommunications environment within which the dual telephone interface communication device may serve as an interface between other parties; and

FIG. 20 is a block diagram of the hardware components of the system including dual data pumps and dual telephone line interfaces; and

FIG. 21 is a diagram of the telecommunications environment within which the dual telephone interface and dual data pump communication devices are daisy-chained to provide data or voice conferencing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The specification for the multiple inventions described herein includes the present description, the drawings and a microfiche appendix. In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present inventions is defined by the appended claims.

FIG. 1 shows a typical arrangement for the use of the present system. Personal computer 10 is running the software components of the present system while the hardware components 20 include the data communication equipment and telephone headset. Hardware components 20 communicate over a standard telephone line 30 to one of a variety of remote sites. One of the remote sites may be equipped with the present system including hardware components 20a and software components running on personal computer 10a. In one alternative use, the local hardware components 20 may be communicating over standard telephone line 30 to facsimile machine 60. In another alternative use, the present system may be communicating over a standard telephone line 30
to another personal computer 80 through a remote modem 70. In another alternative use, the present system may be communicating over a standard telephone line 30 to a standard telephone 90. Those skilled in the art will readily recognize the wide variety of communication interconnections possible with the present system by reading and understanding the following detailed description.

The ornamental features of the hardware components 20 of FIG. 1 are claimed as part of Design patent application Ser. No. 29/001368, filed Nov. 12, 1992 entitled "Telephone/Modem case for a Computer-Based Multifunction Personal Communications System" assigned to the same assignee of the present inventions and hereby incorporated by reference.

General Overview

The present inventions are embodied in a commercial product by the assignee, MultiTech Systems, Inc. The software component operating on a personal computer is sold under the commercial trademark of MultiExpressPCS.TM. personal communications software while the hardware component of the present system is sold under the commercial name of MultiModemPCS.TM., Intelligent Personal Communications System Modem. In the preferred embodiment, the software component runs under Microsoft.RTM. Windows.RTM. however those skilled in the art will readily recognize that the present system is easily adaptable to run under any single or multi-user, single or multi-window operating system.

The present system is a multifunction communication system which includes hardware and software components. The system allows the user to connect to remote locations equipped with a similar system or with modems, facsimile machines or standard telephones over a single analog telephone line. The software component of the present system includes a number of modules which are described in more detail below.

FIG. 2 is an example of the Windows.RTM.-based main menu icon of the present system operating on a personal computer. The functions listed with the icons used to invoke those functions are shown in the preferred embodiment. Those skilled in the art will readily recognize that a wide variety of selection techniques may be used to invoke the various functions of the present system. The icon of FIG. 2 is part of Design patent application Ser. No. 29/001397, filed Nov. 12, 1992 entitled "Icons for a Computer-Based Multifunction Personal Communications System" assigned to the same assignee of the present inventions and hereby incorporated by reference.

The telephone module allows the system to operate as a conventional or sophisticated telephone system. The system converts voice into a digital signal so that it can be transmitted or stored with other digital data, like computer information. The telephone function supports PBX and Centrex features such a call waiting, call forwarding, caller ID and three-way calling. This module also allows the user to mute, hold or record a conversation. The telephone module enables the handset, headset or hands-free speaker telephone operation of the hardware component. It includes on-screen push button dialing, speed-dial of stored numbers and digital recording of two-way conversations.

The voice mail portion of the present system allows this system to operate as a telephone answering machine by storing voice messages as digitized voice files along with a time/date voice stamp. The digitized voice files can be saved and sent to one or more destinations immediately or at a later time using a queue scheduler. The user can also listen to, forward or edit the voice messages which have been received with a powerful digital voice editing component of the present system. This module also creates queues for outgoing messages to be sent at preselected times and allows the users to create outgoing messages with the voice editor.

The fax manager portion of the present system is a queue for incoming and outgoing facsimile pages. In the preferred embodiment of the present system, this function is tied into the Windows "print" command once the present system has been installed. This feature allows the user to create faxes from any Windows.RTM.-based document that uses the "print" command. The fax manager function of the present system allows the user to view queued faxes which are to be sent or which have been received. This module creates queues for outgoing faxes to be sent at preselected times and logs incoming faxes with time/date stamps.

The multi-media mail function of the present system is a utility which allows the user to compose documents that include text, graphics and voice messages using the message composer function of the present system, described more fully below. The multi-media mail utility of the present system allows the user to schedule messages for transmittal and queues up the messages that have been received so that can be viewed at a later time.

The show and tell function of the present system allows the user to establish a data over voice (DOV) communications session. When the user is transmitting data to a remote location similarly equipped, the user is able to talk to the person over the telephone line while concurrently transferring the data. This voice over data function is accomplished in the hardware components of the present system. It digitizes the voice and transmits it in a dynamically changing allocation of voice data and digital data multiplexed in the same transmission. The allocation at a given moment is selected depending on the amount of voice digital information required to be transferred. Quiet voice intervals allocate greater space to the digital data transmission.

The terminal function of the present system allows the user to establish a data communications session with another computer which is equipped with a modem but which is not equipped with the present system. This feature of the present system is a Windows.RTM.-based data communications program that reduces the need for issuing "AT" commands by providing menu driven and "pop-up" window alternatives.

The address book function of the present system is a database that is accessible from all the other functions of the present system. This database is created by the user inputting destination addresses and telephone numbers for data communication, voice mail, facsimile transmission, modem communication and the like. The address book function of the present system may be utilized to broadcast communications to a wide variety of recipients. Multiple linked databases have separate address books for different groups and different destinations may be created by the users. The address book function includes a textual search capability which allows fast and efficient location of specific addresses as described more fully below.

Hardware Components

FIG. 3 is a block diagram of the hardware components of the present system corresponding to reference number 20 of FIG. 1. These components form the link between the user, the personal computer running the software component of the present system and the telephone line interface. As will be more fully described below, the interface to the hardware components of the present system is via a serial communications port connected to the personal computer. The interface protocol is well ordered and defined such that other software systems or programs running on the personal computer may be designed and implemented which would be capable of controlling the hardware components shown in FIG. 3 by using the control and communications protocol defined below.

In the preferred embodiment of the present system three alternate telephone interfaces are available: the telephone handset 301, a telephone headset 302, and a hands-free microphone 303 and speaker 304. Regardless of the telephone interface, the three alternative interfaces connect to the digital telephone coder-decoder (CODEC) circuit 305.

The digital telephone CODEC circuit 305 interfaces with the voice control digital signal processor (DSP) circuit 306 which includes a voice control DSP and CODEC. This circuit does digital to analog (D/A) conversion, analog to digital (A/D) conversion, coding/decoding, gain control and is the interface between the voice control DSP circuit 306 and the telephone interface. The CODEC of the voice control circuit 306 transfers digitized voice information in a compressed format to multiplexor circuit 310 to analog telephone line interface 309.

The CODEC of the voice control circuit 306 is actually an integral component of a voice control digital signal processor integrated circuit, as described more fully below. The voice control DSP of circuit 306 controls the digital telephone CODEC circuit 305, performs voice compression and echo cancellation.

Multiplexor (MUX) circuit 310 selects between the voice control DSP circuit 306 and the data pump DSP circuit 311 for transmission of information on the telephone line through telephone line interface circuit 309.

The data pump circuit 311 also includes a digital signal processor (DSP) and a CODEC for communicating over the telephone line interface 309 through MUX circuit 310. The data pump DSP and CODEC of circuit 311 performs functions such as modulation, demodulation and echo cancellation to communicate over the telephone line interface 309 using a plurality of telecommunications standards including FAX and modem protocols.

The main controller circuit 313 controls the DSP data pump circuit 311 and the voice control DSP circuit 306 through serial input/output and clock timer control (SIO/CTC) circuits 312 and dual port RAM circuit 308 respectively. The main controller circuit 313 communicates with the voice control DSP 306 through dual port RAM circuit 308. In this fashion digital voice data can be read and written simultaneously to the memory portions of circuit 308 for high speed communication between the user (through interfaces 301, 302 or 303/304) and the personal computer connected to serial interface circuit 315 and the remote telephone connection connected through the telephone line attached to line interface circuit 309.

As described more fully below, the main controller circuit 313 includes, in the preferred embodiment, a microprocessor which controls the functions and operation of all of the hardware components shown in FIG. 3. The main controller is connected to RAM circuit 316 and an programmable and electrically erasable read only memory (PEROM) circuit 317. The PEROM circuit 317 includes non-volatile memory in which the executable control programs for the voice control DSP circuits 306 and the main controller circuits 313 operate.

The RS232 serial interface circuit 315 communicates to the serial port of the personal computer which is running the software components of the present system. The RS232 serial interface circuit 315 is connected to a serial input/output circuit
314 with main controller circuit 313. SIO circuit 314 is in the preferred embodiment, a part of SIO/CTC circuit 312.

Functional Operation of the Hardware Components

Referring once again to FIG. 3, the multiple and selectable functions described in conjunction with FIG. 2 are all implemented in the hardware components of FIG. 3. Each of these functions will be discussed in turn.

The telephone function 115 is implemented by the user either selecting a telephone number to be dialed from the address book 127 or manually selecting the number through the telephone menu on the personal computer. The telephone number to be dialed is downloaded from the personal computer over the serial interface and received by main controller 313. Main controller 313 causes the data pump DSP circuit 311 to seize the telephone line and transmit the DTMF tones to dial a number. Main controller 313 configures digital telephone CODEC circuit 305 to enable either the handset 301 operation, the microphone 303 and speaker 304 operation or the headset 302 operation. A telephone connection is established through the telephone line interface circuit 309 and communication is enabled. The user's analog voice is transmitted in an analog fashion to the digital telephone CODEC 305 where it is digitized. The digitized voice patterns are passed to the voice control circuit 306 where echo cancellation is accomplished, the digital voice signals are reconstructed into analog signals and passed through multiplexor circuit 310 to the telephone line interface circuit 309 for analog transmission over the telephone line. The incoming analog voice from the telephone connection through telephone connection circuit 309 is passed to the integral CODEC of the voice control circuit 306 where it is digitized. The digitized incoming voice is then passed to digital telephone CODEC circuit
305 where it is reconverted to an analog signal for transmission to the selected telephone interface (either the handset 301, the microphone/speaker 303/304 or the headset 302). Voice Control DSP circuit 306 is programmed to perform echo cancellation to avoid feedback and echoes between transmitted and received signals, as is more fully described below.

In the voice mail function mode of the present system, voice messages may be stored for later transmission or the present system may operate as an answering machine receiving incoming messages. For storing digitized voice, the telephone interface is used to send the analog speech patterns to the digital telephone CODEC circuit 305. Circuit 305 digitizes the voice patterns and passes them to voice control circuit 306 where the digitized voice patterns are digitally compressed. The digitized and compressed voice patterns are passed through dual port ram circuit 308 to the main controller circuit 313 where they are transferred through the serial interface to the personal computer using a packet protocol defined below. The voice patterns are then stored on the disk of the personal computer for later use in multi-media mail, for voice mail, as a pre-recorded answering machine message or for later predetermined transmission to other sites.

For the present system to operate as an answering machine, the hardware components of FIG. 3 are placed in answer mode. An incoming telephone ring is detected through the telephone line interface circuit 309 and the main controller circuit 313
is alerted which passes the information off to the personal computer through the RS232 serial interface circuit 315. The telephone line interface circuit 309 seizes the telephone line to make the telephone connection. A pre-recorded message may be sent by the personal computer as compressed and digitized speech through the RS232 interface to the main controller circuit 313. The compressed and digitized speech from the personal computer is passed from main controller circuit 313 through dual port ram circuit 308 to the voice control DSP circuit 306 where it is uncompressed and converted to analog voice patterns. These analog voice patterns are passed through multiplexor circuit 310 to the telephone line interface 309 for transmission to the caller. Such a message may invite the caller to leave a voice message at the sound of a tone. The incoming voice messages are received through telephone line interface 309 and passed to voice control circuit 306. The analog voice patterns are digitized by the integral CODEC of voice control circuit 306 and the digitized voice patterns are compressed by the voice control DSP of the voice control circuit 306. The digitized and compressed speech patterns are passed through dual port ram circuit 308 to the main controller circuit 313 where they are transferred using packet protocol described below through the RS232 serial interface 315 to the personal computer for storage and later retrieval. In this fashion the hardware components of FIG. 3 operate as a transmit and receive voice mail system for implementing the voice mail function 117 of the present system.

The hardware components of FIG. 3 may also operate to facilitate the fax manager function 119 of FIG. 2. In fax receive mode, an incoming telephone call will be detected by a ring detect circuit of the telephone line interface 309 which will alert the main controller circuit 313 to the incoming call. Main controller circuit 313 will cause line interface circuit 309 to seize the telephone line to receive the call. Main controller circuit 313 will also concurrently alert the operating programs on the personal computer through the RS232 interface using the packet protocol described below. Once the telephone line interface seizes the telephone line, a fax carrier tone is transmitted and a return tone and handshake is received from the telephone line and detected by the data pump circuit 311. The reciprocal transmit and receipt of the fax tones indicates the imminent receipt of a facsimile transmission and the main controller circuit 313 configures the hardware components of FIG. 3
for the receipt of that information. The necessary handshaking with the remote facsimile machine is accomplished through the data pump 311 under control of the main controller circuit 313. The incoming data packets of digital facsimile data are received over the telephone line interface and passed through data pump circuit 311 to main controller circuit 313 which forwards the information on a packet basis (using the packet protocol described more fully below) through the serial interface circuit 315 to the personal computer for storage on disk. Those skilled in the art will readily recognize that the FAX data could be transferred from the telephone line to the personal computer using the same path as the packet transfer except using the normal AT stream mode. Thus the incoming facsimile is automatically received and stored on the personal computer through the hardware components of FIG. 3.

A facsimile transmission is also facilitated by the hardware components of FIG. 3. The transmission of a facsimile may be immediate or queued for later transmission at a predetermined or preselected time. Control packet information to configure the hardware components to send a facsimile are sent over the RS232 serial interface between the personal computer and the hardware components of FIG. 3 and are received by main controller circuit 313. The data pump circuit 311 then dials the recipient's telephone number using DTMF tones or pulse dialing over the telephone line interface circuit 309. Once an appropriate connection is established with the remote facsimile machine, standard facsimile handshaking is accomplished by the data pump circuit 311. Once the facsimile connection is established, the digital facsimile picture information is received through the data packet protocol transfer over serial line interface circuit 315, passed through main controller circuit 313 and data pump circuit 311 onto the telephone line through telephone line interface circuit 309 for receipt by the remote facsimile machine.

The operation of the multi-media mail function 121 of FIG. 2 is also facilitated by the hardware components of FIG. 3. A multimedia transmission consists of a combination of picture information, digital data and digitized voice information. For example, the type of multimedia information transferred to a remote site using the hardware components of FIG. 3 could be the multimedia format of the MicroSoft.RTM. Multimedia Wave.RTM. format with the aid of an Intelligent Serial Interface (ISI) card added to the personal computer. The multimedia may also be the type of multimedia information assembled by the software component of the present system which is described more fully below.

The multimedia package of information including text, graphics and voice messages (collectively called the multimedia document) may be transmitted or received through the hardware components shown in FIG. 3. For example, the transmission of a multimedia document through the hardware components of FIG. 3 is accomplished by transferring the multimedia digital information using the packet protocol described below over the RS232 serial interface between the personal computer and the serial line interface circuit 315. The packets are then transferred through main controller circuit 313 through the data pump circuit 311 on to the telephone line for receipt at a remote site through telephone line interface circuit 309. In a similar fashion, the multimedia documents received over the telephone line from the remote site are received at the telephone line interface circuit 309, passed through the data pump circuit 311 for receipt and forwarding by the main controller circuit 313 over the serial line interface circuit 315.

The show and tell function 123 of the present system allows the user to establish a data over voice communication session. In this mode of operation, full duplex data transmission may be accomplished simultaneously with the voice communication between both sites. This mode of operation assumes a like configured remote site. The hardware components of the present system also include a means for sending voice/data over cellular links. The protocol used for transmitting multiplexed voice and data include a supervisory packet described more fully below to keep the link established through the cellular link. This supervisory packet is an acknowledgement that the link is still up. The supervisory packet may also contain link information to be used for adjusting various link parameters when needed. This supervisory packet is sent every second when data is not being sent and if the packet is not acknowledged after a specified number of attempts, the protocol would then give an indication that the cellular link is down and then allow the modem to take action. The action could be for example; change speeds, retrain, or hang up. The use of supervisory packets is a novel method of maintaining inherently intermittent cellular links when transmitting multiplexed voice and data.

The voice portion of the voice over data transmission of the show and tell function is accomplished by receiving the user's voice through the telephone interface 301, 302 or 303 and the voice information is digitized by the digital telephone circuit 305. The digitized voice information is passed to the voice control circuit 306 where the digitized voice information is compressed using a voice compression algorithm described more fully below. The digitized and compressed voice information is passed through dual port RAM circuit 308 to the main controller circuit 313. During quiet periods of the speech, a quiet flag is passed from voice control circuit 306 to the main controller 313 through a packet transfer protocol described below by a dual port RAM circuit 308.

Simultaneous with the digitizing compression and packetizing of the voice information is the receipt of the packetized digital information from the personal computer over interface line circuit 315 by main controller circuit 313. Main controller circuit 313 in the show and tell function of the present system must efficiently and effectively combine the digitized voice information with the digital information for transmission over the telephone line via telephone line interface circuit 309. As described above and as described more fully below, main controller circuit 313 dynamically changes the amount of voice information and digital information transmitted at any given period of time depending upon the quiet times during the voice transmissions. For example, during a quiet moment where there is no speech information being transmitted, main controller circuit 313 ensures that a higher volume of digital data information be transmitted over the telephone line interface in lieu of digitized voice information.

Also, as described more fully below, the packets of digital data transmitted over the telephone line interface with the transmission packet protocol described below, requires 100 percent accuracy in the transmission of the digital data, but a lesser standard of accuracy for the transmission and receipt of the digitized voice information. Since digital information must be transmitted with 100 percent accuracy, a corrupted packet of digital information received at the remote site must be retransmitted. A retransmission signal is communicated back to the local site and the packet of digital information which was corrupted during transmission is retransmitted. If the packet transmitted contained voice data, however, the remote site uses the packets whether they were corrupted or not as long as the packet header was intact. If the header is corrupted, the packet is discarded. Thus, the voice information may be corrupted without requesting retransmission since it is understood that the voice information must be transmitted on a real time basis and the corruption of any digital information of the voice signal is not critical. In contrast to this the transmission of digital data is critical and retransmission of corrupted data packets is requested by the remote site.

The transmission of the digital data follows the CCITT V.42 standard, as is well known in the industry and as described in the CCITT Blue Book, volume VIII entitled Data Communication over the Telephone Network, 1989. The CCITT V.42 standard is hereby incorporated by reference. The voice data packet information also follows the CCITT V.42 standard, but uses a different header format so the receiving site recognizes the difference between a data packet and a voice packet. The voice packet is distinguished from a data packet by using undefined bits in the header (80 hex) of the V.42 standard. The packet protocol for voice over data transmission during the show and tell function of the present system is described more fully below.

Since the voice over data communication with the remote site is full-duplex, incoming data packets and incoming voice packets are received by the hardware components of FIG. 3. The incoming data packets and voice packets are received through the telephone line interface circuit 309 and passed to the main controller circuit 313 via data pump DSP circuit 311. The incoming data packets are passed by the main controller circuit 313 to the serial interface circuit 315 to be passed to the personal computer. The incoming voice packets are passed by the main controller circuit 313 to the dual port RAM circuit 308 for receipt by the voice control DSP circuit 306. The voice packets are decoded and the compressed digital information therein is uncompressed by the voice control DSP of circuit 306. The uncompressed digital voice information is passed to digital telephone CODEC circuit 305 where it is reconverted to an analog signal and retransmitted through the telephone line interface circuits. In this fashion full-duplex voice and data transmission and reception is accomplished through the hardware components of FIG. 3 during the show and tell functional operation of the present system.

Terminal operation 125 of the present system is also supported by the hardware components of FIG. 3. Terminal operation means that the local personal computer simply operates as a "dumb" terminal including file transfer capabilities. Thus no local processing takes place other than the handshaking protocol required for the operation of a dumb terminal. In terminal mode operation, the remote site is assumed to be a modem connected to a personal computer but the remote site is not necessarily a site which is configured according to the present system. In terminal mode of operation, the command and data information from personal computer is transferred over the RS232 serial interface circuit 315, forwarded by main controller circuit 313 to the data pump circuit 311 where the data is placed on the telephone line via telephone line interface circuit 309.

In a reciprocal fashion, data is received from the telephone line over telephone line interface circuit 309 and simply forwarded by the data pump circuit 311, the main controller circuit 313 over the serial line interface circuit 315 to the personal computer.

As described above, and more fully below, the address book function of the present system is primarily a support function for providing telephone numbers and addresses for the other various functions of the present system.

Detailed Electrical Schematic Diagrams

The detailed electrical schematic diagrams comprise FIGS. 5A-C, 6A-C, 7A-C, 8A-B, 9A-C and 10A-C. FIG. 4 shows a key on how the schematic diagrams may be conveniently arranged to view the passing of signals on the electrical lines between the diagrams. The electrical connections between the electrical schematic diagrams are through the designators listed next to each wire. For example, on the right side of FIG. 5A, address lines A0-A19 are attached to an address bus for which the individual electrical lines may appear on other pages as A0-A19 or may collectively be connected to other schematic diagrams through the designator "A" in the circle connected to the collective bus. In a like fashion, other electrical lines designated with symbols such as RNGL on the lower left-hand side of FIG. 5A may connect to other schematic diagrams using the same signal designator RNGL.

Beginning with the electrical schematic diagram of FIG. 7C, the telephone line connection in the preferred embodiment is through connector J2 which is a standard six-pin modular RJ-11 jack. In the schematic diagram of FIG. 7C, only the tip and ring connections of the first telephone circuit of the RJ-11 modular connector are used. Ferrite beads FB3 and FB4 are placed on the tip and ring wires of the telephone line connections to remove any high frequency or RF noise on the incoming telephone line. The incoming telephone line is also overvoltage protected through SIDACTOR R4. The incoming telephone line may be full wave rectified by the full wave bridge comprised of diodes CR27, CR28, CR29 and CR31. Switch S4 switches between direct connection and full wave rectified connection depending upon whether the line is a non-powered leased line or a standard telephone line. Since a leased line is a "dead" line with no voltage, the full-wave rectification is not needed.

Also connected across the incoming telephone line is a ring detect circuit. Optical isolator U32 (part model number CNY17) senses the ring voltage threshold when it exceeds the breakdown voltages on zener diodes CR1 and CR2. A filtering circuit shown in the upper right corner of FIG. 7C creates a long RC delay to sense the constant presence of an AC ring voltage and buffers that signal to be a binary signal out of operational amplifier U25 (part model number TLO82). Thus, the RNGL and J1RING signals are binary signals for use in the remaining portions of the electrical schematic diagrams to indicate a presence of a ring voltage on the telephone line.

The present system is also capable of sensing the caller ID information which is transmitted on the telephone line between rings. Between the rings, optically isolated relays U30, U31 on FIG. 7C and optically isolated relay U33 on FIG. 7B all operate in the period between the rings so that the FSK modulated caller ID information is connected to the CODEC and data pump DSP in FIGS. 8A and 8B, as described more fully below.

Referring now to FIG. 7B, more of the telephone line filtering circuitry is shown. Some of the telephone line buffering circuitry such as inductor L1 and resistor R1 are optional and are connected for various telephone line standards used around the word to meet local requirements. For example, Switzerland requires a 22 millihenry inductor and 1K resistor in series the line. For all other countries, the 1K resistor is replaced with a 0 ohm resistor.

Relay U29 shown in FIG. 7B is used to accomplish pulse dialing by opening and shorting the tip and ring wires. Optical relay X2 is engaged during pulse dialing so that the tip and ring are shorted directly. Transistors Q2 and Q3 along with the associated discrete resistors comprise a holding circuit to provide a current path or current loop on the telephone line to grab the line.

FIG. 7A shows the telephone interface connections between the hardware components of the present system and the handset, headset and microphone.

The connections T1 and T2 for the telephone line from FIG. 7B are connected to transformer TR1 shown in the electrical schematic diagram of FIG. 8B. Only the AC components of the signal pass through transformer TR1. The connection of signals attached to the secondary of TR1 is shown for both transmitting and receiving information over the telephone line.

Incoming signals are buffered by operational amplifiers U27A and U27B. The first stage of buffering using operational amplifier U27B is used for echo suppression so that the transmitted information being placed on the telephone line is not fed back into the receive portion of the present system. The second stage of the input buffering through operational amplifier U27A is configured for a moderate amount of gain before driving the signal into CODEC U35.

CODEC chip U35 on FIG. 8B, interface chip U34 on FIG. 8A and digital signal processor (DSP) chip U37 on FIG. 8A comprise a data pump chip set manufactured and sold by AT&T Microelectronics. A detailed description of the operation of these three chips in direct connection and cooperation with one another is described in the publication entitled "AT&T V.32bis/V.32/FAX High-Speed Data Pump Chip Set Data Book" published by AT&T Microelectronics, December 1991, which is hereby incorporated by reference. This AT&T data pump chip set comprises the core of an integrated, two-wire full duplex modem which is capable of operation over standard telephone lines or leased lines. The data pump chip set conforms to the telecommunications specifications in CCITT recommendations V.32bis, V.32, V.22bis, V.22, V.23, V.21 and is compatible with the Bell 212A and 103 modems. Speeds of 14,400, 9600, 4800, 2400, 1200, 600 and 300 bits per second are supported. This data pump chip set consists of a ROM-coded DSP16A digital signal processor U37, and interface chip U34 and an AT&T T7525 linear CODEC U35. The AT&T V.32 data pump chip set is available from AT&T Microelectronics.

The chip set U34, U35 and U37 on FIGS. 8A and 8B perform all A/D, D/A, modulation, demodulation and echo cancellation of all signals placed on or taken from the telephone line. The CODEC U35 performs DTMF tone generation and detection, signal analysis of call progress tones, etc. The transmission of information on the telephone line from CODEC U35 is through buffer U28A, through CMOS switch U36 and through line buffer U25. The CMOS switch U36 is used to switch between the data pump chip set CODEC of circuit 310 (shown in FIG. 3) and the voice control CODEC of circuit 306 (also shown in FIG. 3). The signal lines AOUTN and AOUTP correspond to signals received from the voice control CODEC of circuit 306. CODEC U35 is part of circuit 311 of FIG. 3.

The main controller of controller circuit 313 and the support circuits 312, 314, 316, 317 and 308 are shown in FIGS. 5A-5C. In the preferred embodiment of the present system, the main controller is a Z80180 eight-bit microprocessor chip. In the preferred implementation, microcontroller chip U17 is a Z80180 microprocessor, part number Z84CO1 by Zilog, Inc. of Campbell, Calif. (also available from Hitachi Semiconductor as part number HD64180Z). The Zilog Z80180 eight-bit microprocessor operates at 12 MHz internal clock speed by means of an external crystal XTAL, which in the preferred embodiment, is a 24.576 MHz crystal. The crystal circuit includes capacitors C4 and C5 which are 20 pf capacitors and resistor R28 which is a 33 ohm resistor. The crystal and support circuitry is connected according to manufacturer's specifications found in the Zilog Intelligent Peripheral Controllers Data Book published by Zilog, Inc. The product description for the Z84CO1 Z80180 CPU from the Z84C01 Z80 CPU Product Specification pgs. 43-73 of the Zilog 1991 Intelligent Peripheral Controllers databook is hereby incorporated by reference.

The Z80180 microprocessor in microcontroller chip U17 is intimately connected to a serial/parallel I/O counter timer chip U15 which is, in the preferred embodiment, a Zilog 84C90 CMOS Z80 KIO serial/parallel/counter/timer integrated circuit available from Zilog, Inc. This multi-function I/O chip U15 combines the functions of a parallel input/output port, a serial input/output port, bus control circuitry, and a clock timer circuit in one chip. The Zilog Z84C90 product specification describes the detailed internal operations of this circuit in the Zilog Intelligent Peripheral Controllers 1991 Handbook available from Zilog, Inc. Z84C90 CMOS Z80KIO Product specification pgs. 205-224 of the Zilog 1991 Intelligent Peripheral Controllers databook is hereby incorporated by reference.

Data and address buses A and B shown in FIG. 5A connect the Z80180 microprocessor in microcontroller U17 with the Z80 KIO circuit U15 and a gate array circuit U19, and to other portions of the electrical schematic diagrams. The gate array U19
includes miscellaneous latch and buffer circuits for the present system which normally would be found in discrete SSI or MSI integrated circuits. By combining a wide variety of miscellaneous support circuits into a single gate array, a much reduced design complexity and manufacturing cost is achieved. A detailed description of the internal operations of gate array U19 is described more fully below in conjunction with schematic diagrams of FIGS. 10A-10C.

The memory chips which operate in conjunction with the Z80 microprocessor in microcontroller chip U17 are shown in FIG. 5C. The connections A, B correspond to the connections to the address and data buses, respectively, found on FIG. 5A. Memory chips U16 and U13 are read-only memory (ROM) chips which are electrically alterable in place. These programmable ROMs, typically referred to as flash PROMs or Programmable Erasable Read Only Memories (PEROMs) hold the program code and operating parameters for the present system in a non-volatile memory. Upon power-up, the programs and operating parameters are transferred to the voice control DSP RAM U12, shown in FIG. 9B.

In the preferred embodiment, RAM chip U14 is a pseudostatic RAM which is essentially a dynamic RAM with a built-in refresh. Those skilled in the art will readily recognize that a wide variety memory chips may be used and substituted for pseudo-static RAM U14 and flash PROMs U16 and U13.

Referring once again to FIG. 3, the main controller circuit 313 communicates with the voice control DSP of circuit 306 through dual port RAM circuit 308. The digital telephone CODEC circuit 305, the voice control DSP and CODEC circuit 306, the DSP RAM 307 and the dual port RAM 308 are all shown in detailed electrical schematic diagrams of FIGS. 9A-9C.

Referring to FIG. 9A, the DSP RAM chips U6 and U7 are shown with associated support chips. Support chips U1 and U2 are in the preferred embodiment part 74HCT244 which are TTL-level latches used to capture data from the data bus and hold it for the DSP RAM chips U6 and U7. Circuits U3 and U4 are also latch circuits for also latching address information to control DSP RAM chips U6 and U7. Once again, the address bus A and data bus B shown in FIG. 9A are multi-wire connections which, for the clarity of the drawing, are shown as a thick bus wire representing a grouping of individual wires.

Also in FIG. 9A, the DSP RAMs U6 and U7 are connected to the voice control DSP and CODEC chip U8 as shown split between FIGS. 9A and 9B. DSP/CODEC chip U8 is, in the preferred embodiment, part number WE.RTM. DSP16C, digital signal processor and CODEC chip manufactured and sold by AT&T Microelectronics. This is a 16-bit programmable DSP with a voice band sigma-delta CODEC on one chip. Although the CODEC portion of this chip is capable of analog-to-digital and digital-to-analog signal acquisition and conversion system, the actual D/A and A/D functions for the telephone interface occur in digital telephone CODEC chip U12 (corresponding to digital telephone CODEC circuit 305 of FIG. 3). Chip U8 includes circuitry for sampling, data conversion, anti-aliasing filtering and anti-imaging filtering. The programmable control of DSP/CODEC chip U8 allows it to receive digitized voice from the telephone interface (through digital telephone CODEC chip U12) and store it in a digitized form in the dual port RAM chip U11. The digitized voice can then be passed to the main controller circuit 313 where the digitized voice may be transmitted to the personal computer over the RS232 circuit 315. In a similar fashion, digitized voice stored by the main controller circuit 313 in the dual port RAM U11 may be transferred through voice control DSP chip U8, converted to analog signals by telephone CODEC U12 and passed to the user. Digital telephone CODEC chip U12 includes a direct telephone handset interface on the chip.

The connections to DSP/CODEC chip U8 are shown split across FIGS. 9A and 9B. Address/data decode chips U9 and U10 on FIG. 9A serve to decode address and data information from the combined address/data bus for the dual port RAM chip U11 of FIG.
9B. The interconnection of the DSP/CODEC chip U8 shown on FIGS. 9A and 9B is described more fully in the WE.RTM. DSP16C Digital Signal Processor/CODEC Data Sheet published May, 1991 by AT&T Microelectronics, which is hereby incorporated by reference.

The Digital Telephone CODEC chip U12 is also shown in FIG. 9B which, in the preferred embodiment, is part number T7540 Digital Telephone CODEC manufactured and sold by AT&T Microelectronics. A more detailed description of this telephone CODEC chip U12 is described in the T7540 Digital Telephone CODEC Data Sheet and Addendum published July, 1991 by AT&T Microelectronics, which is hereby incorporated by reference.

Support circuits shown on FIG. 9C are used to facilitate communication between CODEC chip U12, DSP/CODEC chip U8 and dual port RAM U11. For example, an 8 kHz clock is used to synchronize the operation of CODEC U12 and DSP/CODEC U8.

The operation of the dual port RAM U11 is controlled both by DSP U8 and main controller chip U17. The dual port operation allows writing into one address while reading from another address in the same chip. Both processors can access the exact same memory locations with the use of a contention protocol such that when one is reading the other cannot be writing. In the preferred embodiment, dual port RAM chip U11 is part number CYZC131 available from Cyprus Semiconductor. This chip includes built in contention control so that if two processors try to access the same memory location at the same time, the first one making the request gets control of the address location and the other processor must wait. In the preferred embodiment, a circular buffer is arranged in dual port RAM chip U11 comprising 24 bytes. By using a circular buffer configuration with pointers into the buffer area, both processors will not have a contention problem.

The DSP RAM chips U6 and U7 are connected to the DSP chip U8 and also connected through the data and address buses to the Zilog microcontroller U17. In this configuration, the main controller can download the control programs for DSP U8 into DSP RAMs U6 and U7. In this fashion, DSP control can be changed by the main controller or the operating programs on the personal computer, described more fully below. The control programs stored in DSP chips U6 and U7 originate in the flash PEROM chips U16
and U17. The power-up control routine operating on controller chip U17 downloads the DSP control routines into DSP RAM chips U6 and U7.

The interface between the main controller circuit 313 and the personal computer is through SIO circuit 314 and RS232 serial interface 315. These interfaces are described more fully in conjunction with the detailed electrical schematic diagrams of FIGS. 6A-6C. RS232 connection J1 is shown on FIG. 6A with the associated control circuit and interface circuitry used to generate and receive the appropriate RS232 standard signals for a serial communications interface with a personal computer. FIG.
6B is a detailed electrical schematic diagram showing the generation of various voltages for powering the hardware components of the electrical schematic diagrams of hardware components 20. The power for the present hardware components is received on connector J5 and controlled by power switch S34. From this circuitry of FIG. 6B, plus and minus 12 volts, plus five volts and minus five volts are derived for operating the various RAM chips, controller chips and support circuitry of the present system. FIG. 6C shows the interconnection of the status LED's found on the front display of the box 20.

Finally, the "glue logic" used to support various functions in the hardware components 20 are described in conjunction with the detailed electrical schematic diagrams of FIGS. 10A-10C. The connections between FIGS. 10A and 10C and the previous schematic diagrams is made via the labels for each of the lines. For example, the LED status lights are controlled and held active by direct addressing and data control of latches GA1 and GA2. For a more detailed description of the connection of the glue logic of FIGS. 10A-10C, the gate array U19 is shown connected in FIGS. 5A and 5B.

Packet Protocol Between the PC and the Hardware Component

A special packet protocol is used for communication between the hardware components 20 and the personal computer (PC) 10. The protocol is used for transferring different types of information between the two devices such as the transfer of DATA, VOICE, and QUALIFIED information. The protocol also uses the BREAK as defined in CCITT X.28 as a means to maintain protocol synchronization. A description of this BREAK sequence is also described in the Statutory Invention Registration entitled "ESCAPE METHODS FOR MODEM COMMUNICATIONS", to Timothy D. Gunn filed Jan. 8, 1993, which is hereby incorporated by reference.

The protocol has two modes of operation. One mode is packet mode and the other is stream mode. The protocol allows mixing of different types of information into the data stream without having to physically switch modes of operation. The hardware component 20 will identify the packet received from the computer 10 and perform the appropriate action according to the specifications of the protocol. If it is a data packet, then the controller 313 of hardware component 20 would send it to the data pump circuit 311. If the packet is a voice packet, then the controller 313 of hardware component 20 would distribute that information to the Voice DSP 306. This packet transfer mechanism also works in the reverse, where the controller 313 of hardware component 20 would give different information to the computer 10 without having to switch into different modes. The packet protocol also allows commands to be sent to either the main controller 313 directly or to the Voice DSP 306 for controlling different options without having to enter a command state.

Packet mode is made up of 8 bit asynchronous data and is identified by a beginning synchronization character (01 hex) followed by an ID/LI character and then followed by the information to be sent. In addition to the ID/LI character codes defined below, those skilled in the art will readily recognize that other ID/LI character codes could be defined to allow for additional types of packets such as video data, or alternate voice compression algorithm packets such as Codebook Excited Linear Predictive Coding (CELP) algorithm, GSM, RPE, VSELP, etc.

Stream mode is used when large amounts of one type of packet (VOICE, DATA, or QUALIFIED) is being sent. The transmitter tells the receiver to enter stream mode by a unique command. Thereafter, the transmitter tells the receiver to terminate stream mode by using the BREAK command followed by an "AT" type command. The command used to terminate the stream mode can be a command to enter another type of stream mode or it can be a command to enter back into packet mode.

Currently there are 3 types of packets used: DATA, VOICE, and QUALIFIED. Table 1 shows the common packet parameters used for all three packet types. Table 2 shows the three basic types of packets with the sub-types listed.

TABLE 1 ______________________________________ Packet Parameters ______________________________________ 1. Asynchronous transfer 2. 8 bits, no parity 3. Maximum packet length of 128 bytes IDentifier byte = 1 InFormation = 127 4. SPEED variable from 9600 to 57600 default to 19200 ______________________________________

TABLE 2 ______________________________________ Packet Types ______________________________________ 1. Data 2. Voice 3. Qualified: a. COMMAND b. RESPONSE c. STATUS d. FLOW CONTROL e. BREAK f. ACK g. NAK h. STREAM ______________________________________

A Data Packet is shown in Table 1 and is used for normal data transfer between the controller 313 of hardware component 20 and the computer 10 for such things as text, file transfers, binary data and any other type of information presently being sent through modems. All packet transfers begin with a synch character 01 hex (synchronization byte). The Data Packet begins with an ID byte which specifies the packet type and packet length. Table 3 describes the Data Packet byte structure and Table
4 describes the bit structure of the ID byte of the Data Packet. Table 5 is an example of a Data Packet with a byte length of 6. The value of the LI field is the actual length of the data field to follow, not counting the ID byte.

TABLE 3 ______________________________________ Data Packet Byte Structure ______________________________________ ##STR1## ##STR2## ______________________________________

TABLE 4 ______________________________________ ID Byte of Data Packet ______________________________________ ##STR3## ##STR4## ______________________________________

TABLE 5 ______________________________________ Data Packet Example ______________________________________ LI (length indicator) = 6 ##STR5## ______________________________________

The Voice Packet is used to transfer compressed VOICE messages between the controller 313 of hardware component 20 and the computer 10. The Voice Packet is similar to the Data Packet except for its length which is, in the preferred embodiment, currently fixed at 23 bytes of data. Once again, all packets begin with a synchronization character chosen in the preferred embodiment to be 01 hex (01H). The ID byte of the Voice Packet is completely a zero byte: all bits are set to zero. Table 6
shows the ID byte of the Voice Packet and Table 7 shows the Voice Packet byte structure.

TABLE 6 ______________________________________ ID Byte of Voice Packet ______________________________________ ##STR6## ______________________________________

TABLE 7 ______________________________________ Voice Packet Byte Structure ______________________________________ ##STR7## ##STR8## ______________________________________

The Qualified Packet is used to transfer commands and other non-data/voice related information between the controller 313 of hardware component 20 and the computer 10. The various species or types of the Qualified Packets are described below and are listed above in Table 2. Once again, all packets start with a synchronization character chosen in the preferred embodiment to be 01 hex (01H). A Qualified Packet starts with two bytes where the first byte is the ID byte and the second byte is the QUALIFIER type identifier. Table 8 shows the ID byte for the Qualified Packet, Table 9 shows the byte structure of the Qualified Packet and Tables 10-12 list the Qualifier Type byte bit maps for the three types of Qualified Packets.

TABLE 8 ______________________________________ ID Byte of Qualified Packet ______________________________________ ##STR9## ______________________________________

The Length Identifier of the ID byte equals the amount of data which follows including the QUALIFIER byte (QUAL byte+DATA). If LI=1, then the Qualifier Packet contains the Q byte only.

TABLE 9 ______________________________________ Qualifier Packet Byte Structure ______________________________________ ##STR10## ______________________________________

The bit maps of the Qualifier Byte (QUAL BYTE) of the Qualified Packet are shown in Tables 10-12. The bit map follows the pattern whereby if the QUAL byte=0, then the command is a break. Also, bit 1 of the QUAL byte designates ack/nak, bit 2
designates flow control and bit 6 designates stream mode command. Table 10 describes the Qualifier Byte of Qualified Packet, Group 1 which are immediate commands. Table 11 describes the Qualifier Byte of Qualified Packet, Group 2 which are stream mode commands in that the command is to stay in the designated mode until a BREAK+INIT command string is sent. Table 12 describes the Qualifier Byte of Qualified Packet, Group 3 which are information or status commands.

TABLE 10 ______________________________________ Qualifier Byte of Qualified Packet: Group 1 7 6 5 4 3 2 1 0 x x x x x x x x ______________________________________ 0 0 0 0 0 0 0 0 = break 0 0 0 0 0 0 1 0 = ACK 0 0 0 0 0 0 1 1 = NAK 0 0 0 0
0 1 0 0 = xoff or stop sending data 0 0 0 0 0 1 0 1 = xon or resume sending data 0 0 0 0 1 0 0 0 = cancel fax ______________________________________

TABLE 11 ______________________________________ Qualifier Byte of Qualified Packet: Group 2 7 6 5 4 3 2 1 0 x x x x x x x x ______________________________________ 0 1 0 0 0 0 0 1 = stream command mode 0 1 0 0 0 0 1 0 = stream-data 0 1 0 0
0 0 1 1 = stream voice 0 1 0 0 0 1 0 0 = stream video 0 1 0 0 0 1 0 1 = stream A 0 1 0 0 0 1 1 0 = stream B 0 1 0 0 0 1 1 1 = stream C ______________________________________

The Qualifier Packet indicating stream mode and BREAK attention is used when a large of amount of information is sent (voice, data . . . ) to allow the highest throughput possible. This command is mainly intended for use in DATA mode but can be used in any one of the possible modes. To change from one mode to another, a break-init sequence would be given. A break "AT . . . <cr>" type command would cause a change in state and set the serial rate from the "AT" command.

TABLE 12 ______________________________________ Qualifier Byte of Qualified Packet: Group 3 7 6 5 4 3 2 1 0 x x x x x x x x ______________________________________ 1 0 0 0 0 0 0 0 = commands 1 0 0 0 0 0 0 1 = responses 1 0 0 0 0 0 1 0 = status ______________________________________

Cellular Supervisory Packet

In order to determine the status of the cellular link, a supervisory packet shown in Table 13 is used. Both sides of the cellular link will send the cellular supervisory packet every 3 seconds. Upon receiving the cellular supervisory packet, the receiving side will acknowledge it using the ACK field of the cellular supervisory packet. If the sender does not receive an acknowledgement within one second, it will repeat sending the cellular supervisory packet up to 12 times. After 12 attempts of sending the cellular supervisory packet without an acknowledgement, the sender will disconnect the line. Upon receiving an acknowledgement, the sender will restart its 3 second timer. Those skilled in the art will readily recognize that the timer values and wait times selected here may be varied without departing from the spirit or scope of the present invention.

TABLE 13 ______________________________________ Cellular Supervisory Packet Byte Structure ______________________________________ ##STR11## ______________________________________

Speech Compression

The Speech Compression algorithm described above for use in the voice mail function, the multimedia mail function and the show and tell function of the present system is all accomplished via the voice control circuit 306. Referring once again to FIG. 3, the user is talking either through the handset, the headset or the microphone/speaker telephone interface. The analog voice signals are received and digitized by the telephone CODEC circuit 305. The digitized voice information is passed from the digital telephone CODEC circuit 305 to the voice control circuits 306. The digital signal processor (DSP) of the voice control circuit 306 is programmed to do the voice compression algorithm. The source code programmed into the voice control DSP is attached in the microfiche appendix. The DSP of the voice control circuit 306 compresses the speech and places the compressed digital representations of the speech into special packets described more fully below. As a result of the voice compression algorithm, the compressed voice information is passed to the dual port ram circuit 308 for either forwarding and storage on the disk of the personal computer via the RS232 serial interface or for multiplexing with conventional modem data to be transmitted over the telephone line via the telephone line interface circuit 309 in the voice-over-data mode of operation Show and Tell function 123).

Speech Compression Algorithm

To multiplex high-fidelity speech with digital data and transmit both over the over the telephone line, a high available bandwidth would normally be required. In the present invention, the analog voice information is digitized into 8-bit PCM data at an 8 kHz sampling rate producing a serial bit stream of 64,000 bps serial data rate. This rate cannot be transmitted over the telephone line. With the Speech Compression algorithm described below, the 64 kbs digital voice data is compressed into a 9200 bps encoding bit stream using a fixed-point (non-floating point) DSP such that the compressed speech can be transmitted over the telephone line using a 9600 baud modem transmission. This is an approximately 7 to one compression ratio. This is accomplished in an efficient manner such that enough machine cycles remain during real time speech compression to allow real time acoustic and line echo cancellation in the same fixed-point DSP.

Even at 9200 bps serial data rate for voice data transmission, this bit rate leaves little room for concurrent conventional data transmission. A silence detection function is used to detect quiet intervals in the speech signal and substitute conventional data packets in lieu of voice data packets to effectively time multiplex the voice and data transmission. The allocation of time for conventional data transmission is constantly changing depending upon how much silence is on the voice channel.

The voice compression algorithm of the present system relies on a model of human speech which shows that human speech contains redundancy inherent in the voice patterns. Only the incremental innovations (changes) need to be transmitted. The algorithm operates on 160 digitized speech samples (20 milliseconds), divides the speech samples into time segments of 5 milliseconds each, and uses predictive coding on each segment. With this algorithm, the current segment is predicted as best as possible based on the past recreated segments and a difference signal is determined. The difference value is compared to the stored difference values in a lookup table or code book, and the address of the closest value is sent to the remote site along with the predicted gain and pitch values for each segment. In this fashion, four 5 ms speech segments can be reduced to a packet of 23 bytes or 184 bits (46 bits per sample segment). By transmitting 184 bits every 20 milliseconds, an effective serial data transmission rate of 9200 bps is accomplished.

To produce this compression, the present system includes a unique Vector Quantization (VQ) speech compression algorithm designed to provide maximum fidelity with minimum compute power and bandwidth. The VQ algorithm has two major components. The first section reduces the dynamic range of the input speech signal by removing short term and long term redundancies. This reduction is done in the waveform domain, with the synthesized part used as the reference for determining the incremental "new" content. The second section maps the residual signal into a code book optimized for preserving the general spectral shape of the speech signal.

FIG. 11 is a high level signal flow block diagram of the speech compression algorithm used in the present system to compress the digitized voice for transmission over the telephone line in the voice over data mode of operation or for storage and use on the personal computer. The transmitter and receiver components are implemented using the programmable voice control DSP/CODEC circuit 306 shown in FIG. 3.

The DC removal stage 1101 receives the digitized speech signal and removes the D.C. bias by calculating the long-term average and subtracting it from each sample. This ensures that the digital samples of the speech are centered about a zero mean value. The pre-emphasis stage 1103 whitens the spectral content of the speech signal by balancing the extra energy in the low band with the reduced energy in the high band.

The system finds the innovation in the current speech segment by subtracting 1109 the prediction from reconstructed past samples synthesized from synthesis stage 1107. This process requires the synthesis of the past speech samples locally (analysis by synthesis). The synthesis block 1107 at the transmitter performs the same function as the synthesis block 1113 at the receiver. When the reconstructed previous segment of speech is subtracted from the present segment (before prediction), a difference term is produced in the form of an error signal. This residual error is used to find the best match in the code book 1105. The code book 1105 quantizes the error signal using a code book generated from a representative set of speakers and environments. A minimum mean squared error match is determined in 5 ms segments. In addition, the code book is designed to provide a quantization error with spectral rolloff (higher quantization error for low frequencies and lower quantization error for higher frequencies). Thus, the quantization noise spectrum in the reconstructed signal will always tend to be smaller than the underlying speech signal.

The channel corresponds to the telephone line in which the compressed speech bits are multiplexed with data bits using a packet format described below. The voice bits are sent in 100 ms packets of 5 frames each, each frame corresponding to 20 ms of speech in 160 samples. Each frame of 20 ms is further divided into 4 sub-blocks or segments of 5 ms each. In each sub-block of the data consists of 7 bits for the long term predictor, 3 bits for the long term predictor gain, 4 bits for the sub-block gain, and 32 bits for each code book entry for a total 46 bits each 5 ms. The 32 bits for code book entries consists of four 8-bit table entries in a 256 long code book of 1.25 ms duration. In the code book block, each 1.25 ms of speech is looked up in a 256 word code book for the best match. The 8-bit table entry is transmitted rather than the actual samples. The code book entries are pre-computed from representative speech segments. (See the DSP Source Code in the microfiche appendix.)

On the receiving end 1200, the synthesis block 1113 at the receiver performs the same function as the synthesis block 1107 at the transmitter. The synthesis block 1113 reconstructs the original signal from the voice data packets by using the gain and pitch values and code book address corresponding to the error signal most closely matched in the code book. The code book at the receiver is similar to the code book 1105 in the transmitter. Thus the synthesis block recreates the original pre-emphasized signal. The de-emphasis stage 1115 inverts the pre-emphasis operation by restoring the balance of original speech signal.

The complete speech compression algorithm is summarized as follows:

a) Remove any D.C. bias in the speech signal.

b) Pre-emphasize the signal.

c) Find the innovation in the current speech segment by subtracting the prediction from reconstructed past samples. This step requires the synthesis of the past speech samples locally (analysis by synthesis) such that the residual error is fed back into the system.

d) Quantize the error signal using a code book generated from a representative set of speakers and environments. A minimum mean squared error match is determined in 5 ms segments. In addition, the code book is designed to provide a quantization error with spectral rolloff (higher quantization error for low frequencies and lower quantization error for higher frequencies). Thus, the quantization noise spectrum in the reconstructed signal will always tend to be smaller than the underlying speech signal.

e) At the transmitter and the receiver, reconstruct the speech from the quantized error signal fed into the inverse of the function in step c above. Use this signal for analysis by synthesis and for the output to the reconstruction stage below.

f) Use a de-emphasis filter to reconstruct the output.

The major advantages of this approach over other low-bit-rate algorithms are that there is no need for any complicated calculation of reflection coefficients (no matrix inverse or lattice filter computations). Also, the quantization noise in the output speech is hidden under the speech signal and there are no pitch tracking artifacts: the speech sounds "natural", with only minor increases of background hiss at lower bit-rates. The computational load is reduced significantly compared to a VSELP algorithm and variations of the same algorithm provide bit rates of 8, 9.2 and 16 Kbit/s. The total delay through the analysis section is less than 20 milliseconds in the preferred embodiment. The present algorithm is accomplished completely in the waveform domain and there is no spectral information being computed and there is no filter computations needed.

Detailed Description of the Speech Compression Algorithm

The speech compression algorithm is described in greater detail with reference to FIGS. 11 through 13, and with reference to the block diagram of the hardware components of the present system shown at FIG. 3. Also, reference is made to the detailed schematic diagrams in FIGS. 9A-9C. The voice compression algorithm operates within the programmed control of the voice control DSP circuit 306. In operation, the speech or analog voice signal is received through the telephone interface 301,
302 or 303 and is digitized by the digital telephone CODEC circuit 305. The CODEC for circuit 305 is a companding .mu.-law CODEC. The analog voice signal from the telephone interface is band-limited to about 3,500 Hz and sampled at 8 kHz by digital telephone CODEC 305. Each sample is encoded into 8-bit PCM data producing a serial 64 kb/s signal. The digitized samples are passed to the voice control DSP/CODEC of circuit 306. There, the 8-bit .mu.-law PCM data is converted to 13-bit linear PCM data. The 13-bit representation is necessary to accurately represent the linear version of the logarithmic 8-bit .mu.-law PCM data. With linear PCM data, simpler mathematics may be performed on the PCM data.

The voice control DSP/CODEC of circuit 306 correspond to the single integrated circuit U8 shown in FIGS. 9A and 9B as a WE.RTM. DSP16C Digital Signal Processor/CODEC from AT&T Microelectronics which is a combined digital signal processor and a linear CODEC in a single chip as described above. The digital telephone CODEC of circuit 305 corresponds to integrated circuit U12 shown in FIG. 9(b) as a T7540 companding .mu.-law CODEC.

The sampled and digitized PCM voice signals from the telephone .mu.-law CODEC U12 shown in FIG. 9B are passed to the voice control DSP/CODEC U8 via direct data lines clocked and synchronized to an 8 KHz clocking frequency. The digital samples are loaded into the voice control DSP/CODEC U8 one at a time through the serial input and stored into an internal queue held in RAM and converted to linear PCM data. As the samples are loaded into the end of the queue in the RAM of the voice control DSP U8, the samples at the head of the queue are operated upon by the voice compression algorithm. The voice compression algorithm then produces a greatly compressed representation of the speech signals in a digital packet form. The compressed speech signal packets are then passed to the dual port RAM circuit 308 shown in FIG. 3 for use by the main controller circuit 313 for either transferring in the voice-over-data mode of operation or for transfer to the personal computer for storage as compressed voice for functions such as telephone answering machine message data, for use in the multi-media documents and the like.

In the voice-over-data mode of operation, voice control DSP/CODEC circuit 306 of FIG. 3 will be receiving digital voice PCM data from the digital telephone CODEC circuit 305, compressing it and transferring it to dual port RAM circuit 308 for multiplexing and transfer over the telephone line. This is the transmit mode of operation of the voice control DSP/CODEC circuit 306 corresponding to transmitter block 1100 of FIG. 11 and corresponding to the compression algorithm of FIG. 12.

Concurrent with this transmit operation, the voice control DSP/CODEC circuit 306 is receiving compressed voice data packets from dual port RAM circuit 308, uncompressing the voice data and transferring the uncompressed and reconstructed digital PCM voice data to the digital telephone CODEC 305 for digital to analog conversion and eventual transfer to the user through the telephone interface 301, 302, 304. This is the receive mode of operation of the voice control DSP/CODEC circuit 306
corresponding to receiver block 1200 of FIG. 11 and corresponding to the decompression algorithm of FIG. 13. Thus the voice-control DSP/CODEC circuit 306 is processing the voice data in both directions in a full-duplex fashion.

The voice control DSP/CODEC circuit 306 operates at a clock frequency of approximately 24.576 MHz while processing data at sampling rates of approximately 8 KHz in both directions. The voice compression/decompression algorithms and packetization of the voice data is accomplished in a quick and efficient fashion to ensure that all processing is done in real-time without loss of voice information. This is accomplished in an efficient manner such that enough machine cycles remain in the voice control DSP circuit 306 during real time speech compression to allow real time acoustic and line echo cancellation in the same fixed-point DSP.

In programmed operation, the availability of an eight-bit sample of PCM voice data from the .mu.-law digital telephone CODEC circuit 305 causes an interrupt in the voice control DSP/CODEC circuit 306 where the sample is loaded into internal registers for processing. Once loaded into an internal register it is transferred to a RAM address which holds a queue of samples. The queued PCM digital voice samples are converted from 8-bit .mu.-law data to a 13-bit linear data format using table lookup for the conversion. Those skilled in the art will readily recognize that the digital telephone CODEC circuit 305 could also be a linear CODEC.

Referring to FIG. 11, the digital samples are shown as speech entering the transmitter block 1100. The transmitter block, of course, is the mode of operation of the voice-control DSP/CODEC circuit 306 operating to receive local digitized voice information, compress it and packetize it for transfer to the main controller circuit 313 for transmission on the telephone line. The telephone line connected to telephone line interface 309 of FIG. 3 corresponds to the channel 1111 of FIG. 11.

A frame rate for the voice compression algorithm is 20 milliseconds of speech for each compression. This correlates to 160 samples to process per frame. When 160 samples are accumulated in the queue of the internal DSP RAM, the compression of that sample frame is begun.

The voice-control DSP/CODEC circuit 306 is programmed to first remove the DC component 1101 of the incoming speech. The DC removal is an adaptive function to establish a center base line on the voice signal by digitally adjusting the values of the PCM data. The formula for removal of the DC bias or drift is as follows: ##EQU1##

The removal of the DC is for the 20 millisecond frame of voice which amounts to 160 samples. The selection of .alpha. is based on empirical observation to provide the best result.

Referring to FIG. 12, the voice compression algorithm in a control flow diagram is shown which will assist in the understanding of the block diagram of FIG. 11. The analysis and compression begin at block 1201 where the 13-bit linear PCM speech samples are accumulated until 160 samples representing 20 milliseconds of voice or one frame of voice is passed to the DC removal portion of code operating within the programmed voice control DSP/CODEC circuit 306. The DC removal portion of the code described above approximates the base line of the frame of voice by using an adaptive DC removal technique.

A silence detection algorithm 1205 is also included in the programmed code of the DSP/CODEC 306. The silence detection function is a summation of the square of each sample of the voice signal over the frame. If the power of the voice frame falls below a preselected threshold, this would indicate a silent frame. The detection of a silence frame of speech is important for later multiplexing of the V-data and C-data described below. During silent portions of the speech, the main controller circuit 313 will transfer conventional digital data (C-data) over the telep