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United States Patent5581781
Gregory , ; et al.December 3, 1996
Title
Synthesizer for generating a logic network using a hardware independent description
Abstract
A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed. The logic circuit generator, using the structure and the edge conditions, creates a logic network that generates the signals specified in the user description.
Inventors:Gregory; Brent L. (Sunnyvale, CA), Segal; Russell B.  (Mountain View, CA)
Assignee:Synopsys, Inc. (Mountain View, CA)
Appl. No.:482163
Filed:June 7, 1995
Current U.S. Class:716/18 
Current International Class:G06F 17/50 (20060101)
Field of Search:364/489,490 395/800
U.S. Patent Documents
4882690November 1989Shinsa
4896272January 1990Kurosawa
5029102July 1991Drumm
Other References
VHDL-The Language by Roger Lipsett et al., IEEE Design & Test, Apr. 1986 pp. 28-41. .
VHDL-The Designer Environment by Alfred S-Gilman, IEEE Design & Test, Apr. 1986, pp. 42-47..~
Primary Examiner: Coleman; Eric
Attorney, Agent or Firm:Skjerven, Morrill, MacPherson, Franklin & Friel
Parent Case Text


This application is a continuation of application Ser. No. 07/632,439, filed Dec. 21, 1990 now abandoned.
Claims

We claim:
1. A logic network synthesizer comprising:
a graph generator wherein in response to a user description specifying only operational characteristics of a logic network, said graph generator generates a structure having a plurality of nodes interconnected by edges;
a condition generator connected to said graph generator wherein said condition generator generates edge conditions for selected edges in said structure;
an assignment condition generator connected to said condition generator wherein said assignment condition generator generates a set of assignment conditions for each variable assigned a value in said structure; and
a hardware generator connected to said assignment condition generator where said hardware generator generates a logic network using said assignment conditions.

2. The logic network synthesizer of claim 1 wherein said structure is a control flow graph.

3. The logic network synthesizer of claim 2 wherein said condition generator generates an activation condition for each edge in said control flow graph.

4. The logic network synthesizer of claim 1 wherein said selected edges include each input edge into a join node and further wherein said condition generator generates a mux condition for each input edge to a join node.

5. The logic network synthesizer of claim 1 wherein said assignment condition generator further comprises:
an asynchronous assignment condition generator.

6. The logic network synthesizer of claim 5 wherein said asynchronous assignment condition generator generates a set of asynchronous assignment conditions for hardware functions including an asynchronous load function and an asynchronous data function.

7. The logic network synthesizer of claim 5 wherein said asynchronous assignment condition generator generates a set of asynchronous assignment conditions for hardware description functions including an asynchronous high impedance function.

8. The logic network synthesizer of claim 5 wherein said asynchronous assignment condition generator generates a set of asynchronous assignment conditions for hardware description functions including a don't care function.

9. The logic network synthesizer of claim 1 wherein said assignment condition generator further comprises:
a synchronous assignment condition generator.

10. The logic network synthesizer of claim 9 wherein said synchronous assignment condition generator generates a set of synchronous assignment conditions for each variable synchronously assigned a value in said structure.

11. The logic network synthesizer of claim 9 wherein said synchronous assignment condition generator generates a set of synchronous assignment conditions for hardware description functions including a synchronous load function and a synchronous data function.

12. The logic network synthesizer of claim 9 wherein said synchronous assignment condition generator generates a set of synchronous assignment conditions for hardware description functions including a synchronous high impedance function.

13. The logic network synthesizer of claim 9 wherein said synchronous assignment condition generator generates a set of synchronous assignment conditions for hardware description functions including a don't care function.

14. The logic network synthesizer of claim 9 wherein said hardware generator generates a level sensitive latch in response to predetermined assignment conditions from said assignment condition generator.

15. The logic network synthesizer of claim 9 wherein said hardware generator generates a three-state driver in response to predetermined assignment conditions from said assignment condition generator.

16. The logic network synthesizer of claim 9 wherein said hardware generator generates an edge-triggered flip-flop in response to predetermined assignment conditions from said assignment condition generator.

17. The logic network synthesizer of claim 9 wherein said hardware generator generates an edge-triggered flip-flop with a clear-direct terminal in response to predetermined assignment conditions from said assignment condition generator.

18. The logic network synthesizer of claim 9 wherein said hardware generator generates an edge-triggered flip-flop with a set-direct terminal in response to predetermined assignment conditions from said assignment condition generator.

19. The logic network synthesizer of claim 9 wherein said hardware generator generates an edge-triggered flip-flop with a set-direct terminal and a clear-direct terminal in response to predetermined assignment conditions from said assignment condition generator.

20. The logic network synthesizer of claim 9 wherein said hardware generator generates an edge-triggered flip-flop with a set-direct terminal and a clear-direct terminal in response to predetermined assignment conditions from said assignment condition generator.

21. The logic network synthesizer of claim 9 wherein said hardware generator generates an edge-triggered flip-flop and a three-state driver in response to predetermined assignment conditions from said assignment condition generator.

22. The logic network synthesizer of claim 9 wherein said hardware generator generates a level sensitive latch and a three-state driver in response to predetermined assignment conditions from said assignment condition generator.

23. The logic network synthesizer of claim 9 wherein said hardware generator generates a feedback multiplexer in response to predetermined assignment conditions from said assignment condition generator.
Description
CROSS REFERENCE TO MICROFICHE APPENDIX

Appendix A, which is a part of the present disclosure, is a microfiche appendix consisting of 3 sheets of microfiche having a total of 205 frames. Microfiche Appendix A is a listing of computer programs and related data for one embodiment of the logic synthesizer of this invention, which is described more completely below.

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to methods and systems used to convert a hardware language description to a logic circuit and in particular to a method and system for synthesizing a logic circuit from a user description with conditional assignments of values to logic variables and no hardware specific descriptions.

2. Prior Art

The automated design of application specific integrated circuits as well as the programming of either programmable logic devices or programmable gate arrays requires specification of a logic circuit by the user. Historically, a user was required typically to supply either a logic schematic diagram for use in the automated design process or a set of boolean equations that specified the function of the logic network. The automated logic design system used this information to produce a user specific circuit.

However, many designers had neither a specific schematic diagram nor general boolean logic equations to describe the desired logic operations of the circuit. Hardware description language (HDL) was developed to assist such designers. A hardware description language provided the designer with a means for describing the operation of the desired logic circuit that was at least one level of abstraction removed from a schematic diagram or a set of boolean logic equations. Also, HDL is a more compact representation of-a circuit than the net lists that were historically used to represent circuits. Another significant advantage of HDL is that the HDL circuit description is technology independent. In a net list, logic gates from a particular vender's library are used. With a HDL description, the description is not at the logic gate level.

Ideally, HDL would permit the user to describe only the desired operation of the logic circuit, i.e., the signals generated by the logic circuit. The automated logic design system would then translate the described operation into a logic circuit that was subsequently used in the automated logic design process.

Unfortunately, hardware description language generally permitted only an operational description of simple circuit elements. For many circuit elements, such as high impedance drivers, level sensitive latches and edge sensitive flip-flops, the designer was required first to specify the specific circuit element and then the desired connection of that element using the HDL. Thus, while HDL purportedly allowed a higher level of abstraction in the specification of the logic circuit, HDL descriptions still required detailed logic knowledge for most practical circuits.

Thus, only designers that have knowledge of both the use and operation of logic elements and the desired operational features of the logic circuit can use successfully HDL. An automated logic design system with a logic circuit element independent HDL that required only knowledge of the desired operational features of the logic circuit would greatly enhance the productivity and versatility obtained with automated logic design systems, because such a system could be used by designers with limited logic knowledge. The advantages of automated logic design would be available to a far greater number of users. In spite of the general recognition of this dilemma, a system with a logic circuit element independent HDL is currently unavailable.

SUMMARY OF THE INVENTION

According to the principles of this invention, a method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements.

In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and other information in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed. The logic circuit generator, using the structure and the edge conditions, creates a logic network that generates the signals specified in the user description.

The user description is a sequence of statements that specify how the desired digital hardware operates. Specifically, the user description describes values assigned to logic variables and the conditions under which those values are assigned wherein each logic variable assigned a value represents a signal. Specification of any specific logic element, such as a flip-flop, or any connections between logic elements to generate the desired signals are not required in the user description.

Consequently, the synthesizer of this invention creates the logic network not as in the prior art systems where the choice of logic components was stated at least partially explicitly, but rather where the choice of logic components is implied by the signals and structure specified by the user. Such descriptions are easier to produce, understand, and maintain than the typical prior art description so that the user realizes significant savings in the cost of designing digital hardware.

In one embodiment, the preprocessor includes a control flow graph generating means for creating the structure having nodes and edges. The control flow graph generator creates a control flow graph, which consists of nodes and edges, and in particular split nodes, join nodes, and operation nodes. The control flow graph may include edges that go from one node in the graph to any other subsequent node in the graph. The ability to jump from one node to any subsequent node in the graph represents a significant enhancement in the capability of the control flow graph to represent a wide variety of user descriptions.

The preprocessor also includes an edge condition generating means for determining edge conditions for an edge in the control flow graph. The edge condition generator within the preprocessor generates the condition under which a node in the control flow graph is reached. Specifically, for each edge in the control flow graph, the conditions that must be satisfied to reach that edge in the graph are determined and assigned to the edge. The condition generated is an "activation condition" in one embodiment and a "mux condition" in another embodiment.

The logic circuit generator, using the edge activation conditions, or alternatively the mux conditions, and information associated with the nodes of the control flow graph converts the control flow graph into a logic network. In one embodiment, an assignment condition generator in the logic circuit generator first determines a set of assignment conditions for each variable assigned a value in the control flow graph, i.e., each signal specified by the user. The assignment conditions for a set of hardware description functions, are subsequently used by a hardware generator to create the a logic network that generates the signals represented by the logic variables in the control flow graph.

Hence, according to the principles of this invention, the hardware generator creates a logic circuit for each variable that is assigned a value in the user description, i.e., each signal specified by the user, and interconnects the logic circuits to form the logic network that generates the specified signals under the conditions specified by the user.

In one embodiment, the assignment condition generator determines an assignment condition for each function in a set of functions for each variable that is assigned a value in the user description. Herein, a function is a means to differentiate between the hardware elements that are required in the logic network that is synthesized. Specifically, the set of functions are hardware description functions that in combination with the assignment conditions, which are the values of the hardware description functions, define the logic elements that comprise the logic network.

In one embodiment the set of hardware description functions includes a group of asynchronous functions and a group of synchronous functions. If the assignment conditions for the group of synchronous functions are all zero, the asynchronous functions and assignment conditions are used by the hardware generator to create logic circuits that include logic nodes such as AND and OR gates and invertors as well as complex logic elements such as three-state drivers and level sensitive latches.

Similarly, if the assignment conditions for the group of asynchronous functions are all zero, the synchronous functions and assignment conditions are used by the hardware generator to create logic circuits that include logic nodes such as AND and OR gates and invertors as well as complex logic elements such as three-state drivers and edge-triggered flip-flops. When the assignment conditions include non-zero assignment conditions for both the synchronous and asynchronous functions, the hardware generator creates logic circuits that may include logic nodes such as AND and OR gates and invertors as well as complex logic elements such as three-state drivers, and edge-triggered flip-flops. Also, in this case, the edge-triggered flip-flops may include a clear-direct terminal and a set-direct terminal.

Hence, the hardware generator synthesizes a logic network based upon the information provided by the assignment condition generator. However, the hardware generator preferably boolean minimizes the assignment conditions prior to creation of the logic circuit. In addition, the hardware description functions may include a "don't care" function (don't care function) such that when the user assigns a value of don't care to a variable, an assignment condition is generated for the don't care function. The hardware generator uses the don't care function assignment condition to boolean minimize the logic circuit that is created.

In one embodiment, the hardware description functions include an asynchronous load function, an asynchronous data function, an asynchronous high impedance function, a synchronous load function, a synchronous data function, a synchronous high impedance function, and a "don't care" function. The asynchronous load function tells the condition under which a variable has been asynchronously assigned any value. The asynchronous data function tells the condition under which a variable has been asynchronously assigned the value one. The "don't care" function tells the condition under which a variable has been assigned a value of "don't care" by the user. Assigning the value don't care to a variable means that the variable may be assigned either a logic one or logic zero value. Thus, the "don't care" function tells the condition where the value of a variable is not important. The asynchronous high-impedance function tells the condition under which a variable has been asynchronously assigned the value of a high impedance state. Thus, the asynchronous high impedance function tells the conditions where the value of a variable is high impedance.

The synchronous load function tells the condition under which a variable has been assigned any value on a clock edge. The synchronous data function tells the condition under which a variable has been assigned the value one on a clock edge. The synchronous high-impedance function tells the condition under which a variable has been synchronously assigned the value of a high impedance state. Thus, the synchronous high impedance function tells the conditions where the value of a variable is high impedance.

In this embodiment, the value of the synchronous data function is only important when the synchronous load function is TRUE. Thus, the synchronous data function is preferably boolean minimized with the NOT of the value of the synchronous load function as a don't care condition by the hardware generator. Also, in this embodiment, the values of asynchronous data, don't care and asynchronous high impedance functions are only important when the asynchronous load function is TRUE. Thus, asynchronous data, don't care, and asynchronous high impedance functions are preferably boolean minimized with the NOT of the value of the asynchronous load function as a don't care condition by the hardware generator.

The hardware generator creates the logic elements necessary to generate the signal represented by each assignment condition. Thus, in the following description of the operation of the hardware generator, the steps necessary to create logic elements for a set of assignment conditions are not repeated. When an assignment condition simply is described as driving a particular logic element or line, an earlier description was provided on the hardware necessary to generate that assignment condition.

For a variable where the assignment conditions for the synchronous functions are all zero, the assignment condition for the asynchronous load function is a logic one, and the assignment condition for the asynchronous data function is non-zero, the logic nodes necessary to generate the asynchronous data function assignment condition are interconnected to form the logic circuit for the variable by the hardware generator.

For a variable where the assignment conditions for the synchronous functions are all zero, the assignment condition for the asynchronous load function is not a constant, and the assignment condition for the asynchronous data function is non-zero, the hardware generator creates a level sensitive latch. The asynchronous data function assignment condition (constructed as described above) drives the input terminal of the level sensitive latch and the asynchronous load function assignment condition drives the gate terminal of the latch. The signal on the output line of the latch is the value of the variable.

For a variable where the assignment conditions for the synchronous functions are all zero, the assignment condition for the asynchronous high impedance function and the asynchronous load function are not constants, and the assignment condition for the asynchronous data function is non-zero, the hardware generator creates two level sensitive latches and a three-state driver. The asynchronous data function assignment condition drives the input terminal of a first level sensitive latch and the asynchronous load function assignment condition drives the gate terminal of the latch. The signal on the output line of the first latch drives the input line of the three-state driver, sometimes referred to as a three-state element. The asynchronous high impedance assignment condition drives the input line of a second level sensitive latch and the asynchronous load function assignment condition drives the gate terminal of the latch. The signal on the output line of the second latch drives an invertor which in turn drives the data enable line of the three-state driver.

For a variable where the assignment conditions for the synchronous functions are all zero, the assignment condition for the asynchronous high impedance function is not a constant, the asynchronous load function is a logical one, and the assignment condition for the asynchronous data function is non-zero, the hardware generator creates only a logic circuit that generates the asynchronous data function assignment condition and a three-state driver. The asynchronous data function assignment condition drives the input line of the three-state driver. The asynchronous high impedance assignment condition drives an invertor which in turn drives the data enable line of the three-state driver.

For a variable where the assignment conditions for the asynchronous functions are all zero, the assignment condition for the synchronous load function is a logic one, and the assignment condition for the synchronous data function is non-zero, an edge sensitive flip-flop is created by the hardware generator. The synchronous data function assignment condition drives the input line of the flip-flop. The clock associated with the synchronous functions drives the clock terminal of the flip-flop. The signal on the output line of the flip-flop is the value of the variable.

For a variable where the assignment conditions for the asynchronous functions are all zero, the assignment condition for the synchronous load function is not a constant, and the assignment condition for the synchronous data function is non-zero, a two-to-one multiplexer and an edge sensitive flip-flop are created by the hardware generator. The synchronous data function assignment condition drives a first input terminal of the two-to-one feedback multiplexer. The synchronous load function assignment condition drives the data input select line of the multiplexer. The signal on the output line of the multiplexer drives the input line of an edge-triggered flip-flop. The clock associated with the synchronous functions drives the clock terminal of the flip-flop. The signal on the output line of the flip-flop is fedback to a second input terminal of the multiplexer. The value of the variable is the signal on the output line of the flip-flop.

For a variable where the assignment conditions for the asynchronous functions are all zero, the assignment condition for the synchronous high impedance function is not a constant, the synchronous load function is a logic one, and the assignment condition for the synchronous data function is non-zero, the hardware generator creates two edge triggered flip-flops and a three-state driver. The synchronous data function assignment condition drives the input terminal of the first edge-triggered flip-flop. The signal on the output line of the first flip-flop drives the input line of the three-state driver. The synchronous high impedance assignment condition drives the input line of a second edge-triggered flip-flop. The signal on the output line of the second flip-flop drives an invertor which in turn drives the data enable line of the three-state driver. The clock associated with the synchronous functions drives the clock terminal of the first flip-flop and the second flip-flop.

For a variable where the assignment conditions for the asynchronous functions are all zero, the assignment condition for the synchronous high impedance function is not a constant, the synchronous load function is not a constant, and the assignment condition for the synchronous data function is non-zero, the logic circuit created by the hardware generator is the same as when the synchronous load assignment condition is a logic one, except two feedback multiplexers are added to the circuit. One feedback multiplexer is inserted in the input line to the first flip-flop, as was previously described, and the other feedback multiplexer is similarly inserted in the input line of the second flip-flop.

For a variable where the assignment condition for the asynchronous load function is non-zero, the asynchronous data function assignment condition is zero, and the assignment conditions for the synchronous load function and the assignment condition for the synchronous data function are non-zero, a edge-triggered flip-flop is created by the hardware generator. The flip-flop has a clear-direct terminal that is driven by the assignment condition of the asynchronous load function assignment condition.

For a variable where the assignment conditions for the asynchronous load function, synchronous load function, and synchronous data function are non-zero, and the assignment condition for the asynchronous data function is a logic one, a edge-triggered flip-flop is again created by the hardware generator. The flip-flop has a set-direct terminal that is driven by the assignment condition of the asynchronous load function assignment condition.

For a variable where the assignment condition for the asynchronous load function is non-zero, the asynchronous data function assignment condition is not a constant, and the assignment conditions for the synchronous load function and the assignment condition for the synchronous data function are non-zero, a edge-triggered flip-flop is also created by the hardware generator. The flip-flop has a set-direct terminal and a clear-direct terminal. Logic is created by the hardware generator such that the asynchronous assignment conditions drive the set-direct and clear-direct terminals so that the appropriate signal is applied to the output line of the flip-flop.

When the asynchronous load function assignment condition is non-zero and the synchronous functions' assignment conditions are non-zero, the assignment conditions for the synchronous functions are boolean minimized by the hardware generator with the asynchronous load function assignment condition as a don't care condition. Thus, the hardware generator is a logic circuit generating means that creates a specific logic element for predetermined assignment conditions.

According to the principles of this invention, a method is provided for synthesizing a logic circuit from a user description that includes only operational characteristics of the logic circuit, e.g., signals and the circumstances under which those signals are generated. The method includes the steps of (i) generating a structure having nodes interconnected by edges where in the structure, variables representing signals are assigned values in the nodes and the edges are assigned conditions under which the edge is reached; and (ii) generating a logic network using the structure and edge conditions.

In one embodiment, the structure generating step includes (i) generating a control flow graph having nodes and edges wherein a variable is assigned a value in a node and the edges define the paths between nodes; and (ii) generating an edge condition for edges in the control flow graph where an edge condition is the condition under which a variable in the node associated with that edge is assigned a value.

The logic network generating step also may include (i) generating a set of assignment conditions for each variable assigned a value in the flow control graph; and (ii) generating a logic circuit for each set of assignment conditions where the interconnected logic circuits form the logic network. As explained, above the assignment conditions, in one embodiment are the values of a set of hardware description functions. In this method, the hardware description functions, the hardware created for the various predetermined assignment conditions, and the boolean optimizations, as described above and incorporated herein by reference, are utilized in the logic network generating step.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG, 1 is a block diagram of the hardware description language synthesizer 120 of this invention.

FIG. 2 is a more detailed block diagram of the hardware description language synthesizer 120 of this invention showing preprocessor 122 and logic circuit generator 124.

FIG. 3A is a more detailed block diagram of preprocessor 122 of this invention showing graph generator 132 and condition generator 133.

FIG. 3B is a more detailed block diagram of logic circuit generator 124 of this invention showing assignment condition generator 124A and hardware generator 124B.

FIG. 4 is an example of a control flow graph that is generated by graph generator 132 of this invention.

FIGS. 5A and 5B, illustrate an operation node and an edge from an operation node used by the assignment condition generator 124 in logic circuit generator 124.

FIG. 6A is a control flow graph generated by graph generator 133 of this invention for user description 110 in Table 2.

FIG. 6B is a control flow graph generated by graph in Table 5.

FIG. 7A is a control flow graph that is generated by graph generator 133 of this invention for the user description in Table 3.

FIG. 7B is a control flow graph generated by graph generator 133 of this invention for the user the description in Table 6.

FIG. 8A is a logic circuit created by one embodiment of logic circuit generator 124 for the user description in Table 8.

FIG. 8B is a logic circuit created by a preferred embodiment of logic circuit generator 124 of this invention for the user description in Table 8.

FIG. 8C is the logic circuit generated by logic circuit generator 124 of this invention for the user description in Table 10.

FIG. 8D is a logic circuit created by logic circuit generator 124 of this invention for the user description in Table 12.

FIG. 9A is a logic circuit created by one embodiment of logic circuit generator 124 for the user description in Table 14.

FIG. 9B is a logic circuit created by a preferred embodiment of logic circuit generator 124 of this invention for the user description in Table 14.

FIG. 10A is a logic circuit created by one embodiment of logic circuit generator 124 for the user description in Table 16.

FIG. 10B is a logic circuit created by a preferred embodiment of logic circuit generator 124 of this invention for the user description in Table 16.

FIG. 11 is a logic circuit generated by logic circuit generator 124 of this invention for the user description in Table 19.

FIG. 12 is a logic circuit generated by logic circuit generator 124 of this invention for the user description in Table 22.

FIG. 13 is a logic circuit generated by logic circuit generator 124 of this invention for the user description in Table 24.

FIG. 14A is a logic circuit created by one embodiment of logic circuit generator 124 for the user description in Table 26.

FIG. 14B is a logic circuit created by a preferred embodiment of logic circuit generator 124 of this invention fore,he user description in Table 26.

FIG. 15 is a logic circuit generated by logic circuit generator 124 of this invention for the user description in Table 28.

FIG. 16 is a logic circuit created by logic circuit generator 124 of this invention for the user description in Table 30.

FIG. 17 is a logic circuit generated by logic circuit generator 124 of this invention for the user description in Table 32.

FIG. 18 is a control flow graph created by graph generator 133 of this invention for the user description in Table 34.

FIG. 19A is a control flow graph created by graph generator 133 of this invention for the user description in Table 36.

FIG. 19B is a block diagram of a multiplexer associated with one embodiment of the logic circuit generator 124 of this invention.

FIG. 20 is a block diagram of a selector associated with one embodiment of the logic circuit generator 124 of this invention.

FIG. 21A is a control flow graph as created by graph generator 133 of this invention for the user description in Table 37.

FIG. 21B illustrates use of selectors according to the principles of this invention to generate the value of the variable Q is defined in Table 37.

FIG. 22A is a control flow graph created by graph generator 133 of this invention for the user description in Table 40.

FIG. 22B illustrates the selector for the control flow graph of FIG. 22A and the high impedance hardware description function of this invention.

FIG. 23 is a control flow graph as created by graph generator 133 of this invention for the user example in Table 42.

FIG. 24 is a control flow graph as created by graph generator 133 of this invention for the user description in Table 44.

FIG. 25 illustrates the control flow graph created by graph generator 133 of this invention for the user description in Table 46.

FIG. 26 illustrates a logic circuit created by logic circuit generator 124 for the user description in Table 46.

FIGS. 27A, 27B and 27C are block diagrams of one embodiment of the method of this invention.

DETAILED DESCRIPTION

According to the principles of this invention, a method and system are provided for generating a logic network, sometimes referred to as a logic circuit, using a hardware independent description means, sometimes called a hardware description language. Unlike the prior art methods that required at least a detailed knowledge of the characteristics and operations of complex logic elements such as high impedance drivers, level sensitive latches and edge sensitive flip-flops, only a knowledge of the desired operation of the resulting logic network is required to generate the logic network according to the principles of this invention.

Thus, the system and method of this invention allow a user with minimal knowledge of specific logic elements to generate a logic network that may be subsequently mapped and optimized using any automated logic design system. The system and method of this invention are operable in a computer system that includes a data input device, such as a keyboard, a processing unit, and an output display device. In one embodiment, the user provides a description 110 (FIG. 1) of the operation of the logic network using hardware description means 115. Description 110 is a sequence of statements that specify how the desired digital hardware operates, i.e., the signals generated by the hardware. Specifically, description 110 describes values assigned to logic variables and the circumstances under which those values are assigned, i.e., description 110 specifies the signals and the circumstances under which those signals are produced. Specification of any specific logic element, such as a flip-flop, or any connections between logic elements so as to create the desired signals are not required in user description 110. Typically, the user provides description 110 using the computer system data input device.

With hardware description means 115, the user expresses the operations, i.e., production of signals, by the logic circuit in description 110. For example, to express a high impedance state for a variable, hardware description means 115 instructs the user to set the variable equal to the character "Z". Similarly, if the user does not care about the logic state of a variable, hardware description means 115 instructs the user to set the variable equal to the character "X". Hardware description means 115 requires no specific knowledge about the operation or structure of any logic circuit element. Rather, hardware description means 115, as described more completely below, requires only a knowledge of the desired circuit's operation and a general knowledge of the use of HDL. Herein, a variable represents a signal desired by the user in the logic circuit.

Hardware description language synthesizer 120, in response to description 110, converts hardware independent description 110 into a logic network 130. Synthesizer 120 is loaded in computer system 116 using techniques known to those skilled in the art. Synthesizer 120 independently determines the logic elements required and the interconnections of the logic elements based upon the operational characteristics specified in description 110. The user does not include any hardware specific limitations in description 110.

Consequently, HDL synthesizer 120, sometimes referred to as logic network synthesizer 120, creates logic network 130, not as in the prior art systems where the choice of logic components for the synthesis was stated at least partially explicitly, but rather where the choice of logic components is implied by the signals and circumstances specified in description 110. Such descriptions are easier to produce, understand, and maintain than the typical prior art description so that the user realizes significant savings in the cost of designing digital hardware. Synthesizer 120 generates logic network 130 on computer system 116 output display device 135.

In one embodiment, the computer programs presented in Microfiche Appendix A were used in a workstation such as the SUN-4 computer system available from Sun Microsystems of Palo Alto, Calif. The computer programs were processed using the UNIX operating system SUN OS 4.0.3, the compiler, and linker provided with the SUN-4 computer system. The particular computer language and the computer system used are not an essential aspect of this invention. In view of this disclosure, those skilled in the art can implement the invention using a different computer language and/or a different computer system.

In one embodiment, synthesizer 120 (FIG. 1) includes a preprocessor 122 and a logic circuit generator 124 (FIG. 2). Preprocessor 122 receives the signal information specified in description 110. Preprocessor 122 first parses description 110. Preprocessor 122 converts the parsed description into a specific structure, a control flow graph, described more completely below, which consists of nodes and edges.

Subsequently, preprocessor 122 determines edge conditions for each edge in the control flow graph. The edge conditions and the information at the nodes of the control flow graph, i.e., the signals specified in user description 110 and the circumstances under which the signals are generated, are input information for logic circuit generator 124. Using only this information, logic circuit generator 124 automatically creates logic network 130. Logic network 130 is specified typically as a net list. Alternatively, the net list may be converted to a schematic logic diagram. The important aspect is that description 110, which included only operational results in the form of signal levels and the conditions under which those signal levels are generated, is converted to the specific logic network 130 wherein all the logic elements, including complex logic elements such as high impedance drivers, level sensitive latches, and edge sensitive flip-flops, are specified along with the interconnection of the logic elements so that the user is provided with functional logic network 130 that may be implemented in an integrated circuit or other such devices by the user.

More specifically, description 110 (FIG. 1) includes two general types of statements, directive statements and flow control statements. A directive statement assigns a specified value to a particular variable, i.e., a signal is set at a specified level. For example, the statement

assigns the value of the variable "p" to the variable x. The value of the variable "p" may either have been previously defined or be an input signal. A directive statement is any statement that contains arithmetic operators (+, -, *, /), boolean operations, (e.g. AND, OR, XOR, NOT), or any operation that combines or manipulates data values. Herein, variable "p" or a similar notation is a shorthand expression for the right hand side of a directive statement and as such may represent either a single variable or a more general set of operations that manipulate data values.

A flow control statement, as the name suggests, controls the processing of statements in the set of statements that constitute description 110. For example, in the C programming language flow control statements include "IF," "WHILE," "SWITCH," "RETURN," "BREAK," "FOR," and "GOTO." In this embodiment, hardware description means 115 includes "IF" and "GOTO" flow control statements. As is known to those skilled in the art, other flow control statements may be expressed in terms of only these two flow control statements.

Herein, the characterization of statements as "directive" and "flow control" statements is for ease of description only. Similarly, the specific operations performed by such statements are illustrative only. The important aspect of the invention is that preprocessor 122 (FIG. 2) operates on two different types of statements from description 110 that are used in the specification of the operation of the user defined logic network in description 110. Therefore, the particular names assigned to these statements and the nature of the statements are illustrative only of the principles of this invention and are not intended to limit the invention to the particular names and embodiments described herein.

In this embodiment, preprocessor 122 (FIG. 2) includes parsing means 131, graph generator means 132 and edge condition generator means 133 (FIG. 3). Parsing statements is well-known to those skilled in the art. For example see, A. Aho, R. Sethi, and J. Ullman, Compilers: Principles, Techniques and Tools, Addison-Wesley, Reading, Mass. (1986). In one embodiment, a lexical analysis is first performed using a tool entitled "lex" which is a UNIX tool described in the book of A. Aho et al., which is incorporated herein by reference. After the lexical analysis, parsing is performed using a tool entitled "yacc" which is another UNIX tool described in the book of A. Aho et al., which is also incorporated herein by reference.

After parsing means 131 of preprocessor 122 parses a statement in description 110, the parsed statements are stored in a parse tree and symbol table (also described in Aho et al. (1986)). Parsing means 131 is not an essential aspect of this invention. Any parsing means may be used to generate the parse tree and symbol table. One embodiment of the parse tree and symbol table suitable for use with this invention is described in Aho et al. (1986), which is incorporated herein by reference. Hence, parsing means 131 processes user description 110 and generates a parse tree and symbol table having a format such as that given in Aho et al. (1986).

Using the parse tree and symbol table, graph generating means 132 constructs a control flow graph, as described more completely below. A graph is a collection of vertices, sometimes referred to herein as nodes, and edges. Vertices are objects that can have a name and other properties. An edge is a connection between two vertices. In general, as described below, nodes are classified as operation nodes, split nodes, and join nodes. Edges in a control flow graph represent the flow of control between directive statements. In a control flow graph, a directive statement is represented by an operation node that has a single edge entering and a single edge leaving the node. Within the operation node is an assignment that corresponds to an operation specified by the user in a directive statement in description 110.

A flow control statement results in a more complex structure in the control flow graph than the directive statement. Typically, in the control flow graph, a split node associated with a flow control statement has one or more edges leaving the node. However, the precise representation depends upon the flow control statement. For example, in this embodiment, a GOTO statement may result in only an edge connecting two nodes. The important aspect is that a flow control node defines the condition or conditions whereby subsequent nodes in the control flow graph are accessed.

An example of a simple control flow graph is illustrated in FIG. 4. A data structure representing control flow graph 250 is created by graph generator means 132, typically in random access memory (RAM) of computer 116 (FIG. 1), for the of statements in user description 110 (TABLE 1).

TABLE 1 ______________________________________ A Portion of a Typical User Description 110 ______________________________________ 301 if ( C ) 302 E := P 303 if ( D ) 304 goto done 305 else 306 A := 1 307 endif 308 else 309 B := 0 310
endif 311 F := A + B 312 done: ______________________________________

In this embodiment, when the argument of the "if" statement in TABLE 1 is true, the sequence of statements immediately following the "if" statement are processed. When the "else" statement is encountered, processing passes to the corresponding "endif" statement. Conversely, if the argument of the "if" statement is false, the sequence of statements following the "else" statement for that "if" statement are processed. Again, processing passes to the corresponding "endif" statement. In a control flow graph, the node at which the two branches of an "if" statement converge, i.e., the node corresponding to the "endif" statement, is a "join" node. In general, a join node is any node were two or paths in the control flow graph converge, but, as explained below, a join node may have only a single input edge in some cases.

Control flow graph 250 has nine nodes 201, 203, 205, 208, 210, 212, 214, 217 and 219 and twelve edges 200, 202, 204, 206, 207, 209, 211, 213, 215, 216, 218 and 220. Edge 200 is the source for control flow graph 250. Split node 201 represents flow control statement 301 of TABLE 1. Edge 202 connects node 201 to node 203. Node 203 represents directive statement 302 (TABLE 1) and is referred to as a directive node or an operation node. Edge 202 is traversed only if condition "C" is true. (Herein, variables within a flow control statement are referred to as conditions and not variables.) In FIG. 4, the letter(s) or the arithmetic statement that is adjacent to an edge represents the condition that must be satisfied to traverse that edge. A bar over a letter is used to represent the "not" logic state of the condition represented by the letter. Similarly, two letters written side by side represent the logic "AND" function of the two conditions while two letters connected by a plus sign represents the logic "OR" function of the two conditions. This notation is used consistently to represent a condition associated with an edge of a control flow graph.

Edge 213, which is traversed when the condition "C" is not true, connects node 201 to node 214. Node 214 represents directive statement 509 (TABLE 1). Edge 204 connects node 203 to node 205. Split node 205 represents flow control statement 303
(TABLE 1). Edge 204 is traversed only if condition "C" is true. Edge 206 connects node 205 to join node 219. Edge 206 represents flow control statement 304 (TABLE 1) and is traversed only if both condition "C" and condition "D" are true.

Edge 207 connects split node 205 to operation node 208. Node 208 represents directive statement 306 (TABLE 1). Edge 207 is traversed when condition "C" is true and condition "D" is not true. Edge 209 connects node 208 and join node 210. The condition for traversal of edge 209 is the same as edge 207. Notice that join node 210 only has edge 209 into the node because the GOTO statement directed flow out of the "then" branch of the if statement. Edge 211 connects node 210 to join node 212
and edge 211 has the same condition for traversal of the edge as edge 209.

Edge 215 connects node 214 to join node 212. Edge 215 is traversed when condition "C" is not true. Edge 216 connects join node 212 to operation node 217. Node 217 represents directive statement 311 (TABLE 1). There are two paths to node 217. Node 217 is reached either if condition "C" is not true, or condition "C" is true and condition "D" is not true. Similarly, edge 218 that connects nodes 217 and 219 is reached either if condition "C" is not true, or condition "C" is true and condition "D" is not true. Node 219 is a join node that represents statement 312 (TABLE 1). Edge 220 from join node 219 is the sink for control flow graph 250.

There are several aspects of control flow graph 250 that are important. The condition for an edge leading into a directive node, e.g., node 203, and the condition from the directive node are the same. Hence, as described below, only the condition on the edge exiting a directive node is used. Also, in graph 250, each directive node contains only an assignment for a single variable, but in a more general case, one directive node may correspond to one or more directive statements.

Graph generator 132 (FIG. 3) only creates control flow graph 250 (FIG. 4). The conditions associated with an edge of graph 250 are provided here to assist in associating statements 301 through 311 of TABLE 1 with graph 250, but, as described more completely below, these conditions are an important aspect of the invention.

While control flow graph 250 is a rather simple example, graph 250 illustrates one of the important features of this invention. Graph 250 does not consist of only series and parallel paths. Typically, in prior art control flow graphs, only series parallel paths were permitted, i.e, the only permitted flow control statements were "if" statements or statements that could be represented in terms of "if" statements. In such prior art control flow graphs, the two branches of the "if" statement generated parallel paths while nodes and edges connecting the join node of one "if" statement to the head node of another "if" statement formed a series path. Within one side of a parallel path, multiple buried "if" statements were permitted, but a path from one of the "if" statements to outside the "if" statement was not available.

Thus, such prior art control flow graphs could not be used to represent an edge such as edge 206, that represents the "GOTO" flow control statement. The embodiment of processor 122 that allows the more general control flow graph 250 is a significant advance. Elimination of the parallel series restriction permits generation of more complex and useful control flow graphs, as described more completely below.

Condition generator 133 (FIG. 3) within preprocessor 122 generates the condition under which a node in the control flow graph is reached. Specifically, in one embodiment, for each edge in the control flow graph exiting from a directive node, the conditions that must be satisfied to reach that edge in the graph are determined and assigned to the edge. The condition generated is an "activation condition" in one embodiment and a "mux condition" in another embodiment. The determination of these conditions by condition generator 133 is described more completely below. In FIG. 4, for example, the activation condition for edge 218 of control flow graph 250 is "(not C)+(C,(not D))". Herein, a "+" represents the logic OR function and a "*" represents the logic AND function. In FIG. 4, the activation condition is given next to each edge.

In another embodiment, a "mux condition" is determined for the edges in the control flow graph by condition generator 133 (FIG. 3). The mux condition, as illustrated more completely below, has several advantages over activation conditions.

Condition generator 133 determines a mux condition for each edge 211, 215 feeding into join node 212 and for each edge 206, 218 feeding into join node 219. The mux condition for an edge is the boolean minimization of the activation condition for that edge with a don't care condition. The don't care condition is the NOT of the activation condition of the edge leaving the join node. (For a more general discussion of don't care conditions, see for example, R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangioranni, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Hingham, Massachusetts (1984), which is incorporated herein by reference.)

For example, the mux condition for edge 211 into join node 212, is activation condition "C AND (not D)" minimized with the don't care condition, i.e, the NOT of activation condition "(not C) OR (C AND (not D))" for edge 215 leaving join node 210, which is:

Boolean minimization of the mux condition for edge 213 results in the mux condition "C". (Herein, parenthesis are used as an aid in understanding the logic operations within the condition. Thus, "(not C)" and "not C" are the same value.) Note the mux condition is simpler than the activation condition for edge 211.

The mux condition for an edge is true only when the join node was reached via that edge. The mux condition for an edge may have any value if the join node is not reached. The freedom of the mux condition for an edge to take on any value when the join node is not reached distinguishes mux conditions from activation conditions. The activation condition for an edge is always false when the join node is not reached via that edge. Hence, the mux condition for an edge is simpler than the activation condition because a mux condition is not required to be false when the join node is not reached. The generation of the edge conditions in the control flow graph completes the operation of condition generator 133 and consequently the operation of preprocessor 122.

Logic circuit generator 124 (FIG. 2) converts the edge conditions (activation or mux conditions) and the nodes of the control flow graph into assignment conditions, as described more completely below, which are in turn used to generate a logic circuit that performs the operations that were specified by the user in description 110, i.e., the circuit generates the signals specified by the user.

Prior to considering the operation of logic circuit generator 124 in more detail, the specific hardware description means used with synthesizer 120 of this invention is described. Hardware description means 115 (FIG. 1) provides a means for expressing the possible logic function signals and the condition under which those logic function signals are obtained. In this embodiment, hardware description means 115 includes specifying logic variables which have a logic value of zero, one, "X" or "Z." A value of "X" for a variable means the user does not care about the logical value of that variable. A value of "Z" means the signal represented by the variable is in a high impedance state. Also, the user may specify logic input variables, i.e., logic input signals.

In addition to specification of values for variables, the user may specify the conditions under which a variable takes on a particular value. For example, in this embodiment, the user may specify either a predetermined condition that must be satisfied, or a clock edge condition. Thus, the user needs to know only the timing relationship between the signals or other conditions upon which generation of the signals depend. No knowledge concerning the operation of specific logic devices, such as latches or flip-flops, is required. Hence, unlike the prior art systems described above, which required specification of operation and connections for complex logic elements, synthesizer 120 of this invention generates logic network 130 from an operational description only and does not require specification of any hardware details in user description 110.

Logic circuit generator 124 (FIG. 3), using the edge activation conditions, or alternatively the mux conditions, and information associated with the nodes of the control flow graph converts the control flow graph into a logic circuit. In one embodiment, logic circuit generator 124 first determines assignment conditions, as described more completely below, for each variable assigned a value in the control flow graph. The assignment conditions in conjunction with a set of hardware description functions, also described more completely below, are subsequently used to generate logic network 130 (FIG. 1) which provides the signals represented by the logic variables in the control flow graph.

More specifically, assignment condition generator 124A (FIG. 3B) uses the conditions from condition generator 133 and the control flow graph from graph generator 132 to generate an assignment condition matrix. Each row of the matrix is a set of assignment conditions for a variable that is assigned a value in user description 110.

Hardware generator 124B generates a logic circuit for each row of the assignment condition matrix. In one embodiment, hardware generator 124B first boolean minimizes the set of assignment conditions and then generates the logic circuit for the optimized set of assignment conditions. Thus, logic network 130 includes one or more logic circuits. The logic circuits are interconnected as required by the assignment conditions to form logic network 130.

Logic circuit generator 124 uses a set of hardware description functions that represent specific operations that are implemented with specific hardware. Thus, rather than requiring the user (i) to understand the operation of hardware and (ii) to provide a specific description of that hardware in description 110, logic circuit generator 124, in this embodiment, determines an assignment condition for each variable and each of the functions in the set of hardware description functions. An "assignment condition" is the condition under which the hardware description function is true for a particular variable.

Herein, the notation "F()" represents hardware description function "F" and the notation "F(v)" represents the assignment condition for the hardware description function "F" and variable "v". In one embodiment, the hardware description functions (HDFs) are characterized as either synchronous or asynchronous functions. Synchronous HDFs apply to assignments made to variables only on clock edges. Asynchronous HDFs apply to all other assignments made to variables. In this embodiment, six different HDFs are used.

Asynchronous load function AL() tells the condition under which a variable has been asynchronously assigned any value. Asynchronous data function AD( ) tells the condition under which a variable has been asynchronously assigned the value one. Herein, logic one, one, and "1" are used interchangeably to represent the logic state "TRUE". Similarly, logic zero, zero, and "0" are used interchangeably to represent the logic state "FALSE".

Don't care function DC() tells the condition under which a variable has been assigned the value "X". Assigning the value "X" to a variable means that the variable may assigned either a logic one or logic zero value. Thus, function DC() tells the condition where the value of a variable, i.e., the signal level is not important.

High-impedance function Z() tells the condition under which a variable has been assigned the value "Z". Assigning the value "Z" to a variable means that the variable is to take on a high impedance value. Thus, function Z() tells the conditions where the value of a variable is high impedance. In another embodiment, high-impedance function Z() is replaced by an asynchronous high impedance function AZ() and synchronous high impedance function SZ().

In this embodiment, the values of functions AD(), and Z() are only important when function AL() is TRUE. Thus, functions AD(), and Z() are preferably boolean minimized with "not function AL()" as a don't care condition, as described more completely below.

Synchronous load function SL() tells the condition under which a variable has been assigned any value on a clock edge. Synchronous data function SD( ) tells the condition under which a variable has been assigned the value one on a clock edge. In this embodiment, the value of function SD() is only important when function SL() is TRUE. Thus, function SD() is preferably boolean minimized with "not function SL()" as a don't care condition, as described more completely below.

The specific names of the hardware description functions are not important. Rather, the important aspect is to define a set of functions that represent all variable types that the user may specify, and the conditions under which a particular variable type takes on a particular value. In other embodiments, additional functions may be defined, or alternatively, subsets of the functions described above may be used.

Herein, a positive clock edge is associated with synchronous functions SL() and SD(). However, the use of a positive clock edge for the synchronous functions is illustrative only of the principles of this invention and is not intended to limit the invention to only such a clock edge. As is known to those skilled in the art, a wide variety of clock edges are used in combinational logic networks. Synchronous functions SL() and SD() in logic circuit generator 124 are applicable, in general, for any of the wide variety of clock edges. In view of this disclosure, the use of another clock edge will be apparent to those skilled in the art.

The generation of assignment conditions using the edge conditions (either "mux conditions" or "activation conditions") and the nodes of the control flow graph corresponding to the directive statements is described more completely below in terms of specific examples. Each hardware description function is a boolean expression that may have a logic zero, a logic one, or some combination of logic values from a circuit.

In this embodiment, logic circuit generator 124, in particular, assignment condition generator 124A, creates an assignment condition matrix that is subsequently used in the generation of logic network 130 by hardware generator 124B. Each column of the matrix represents one hardware description function. Thus, in this embodiment, the matrix has six columns. Each row of the assignment condition matrix represents one of the variables that are assigned a value in description 110 (FIG. 2), i.e., a signal that is specified by the user. The entries in a row are the assignment conditions for that variable and are used to generate logic circuit elements that generate the output signal for that variable. Hence, logic circuit elements are generated for each row of the assignment condition matrix. The logic circuit elements for each row and related rows are interconnected as necessary by hardware generator 124B.

The function of the assignment condition matrix is more clearly illustrated by first considering the method used by logic circuit generator 124 to determine the assignment conditions for each of the hardware description functions and then considering the interpretation of the possible permutations and combinations of assignment conditions within a row of the matrix. The generation of assignment conditions using activation conditions is considered first and then the generation of assignment conditions using mux conditions is described.

For high impedance function Z(), assignment condition Z(v) is the logical OR function of all the activation conditions under which variable v is assigned high impedance value "Z". If variable v is never assigned value "Z", assignment condition Z(v) is zero For example, consider a node 251 (FIG. 5A) in the control flow graph which specifies Q :="Z" and activation condition "1" for edge 252 leaving node 251. Since for the purposes of this example this is the only node in the control flow graph that assigns the high impedance state to the variable Q, the logic OR function of the activation conditions is just "1" so assignment condition Z(Q) is "1".

For don't care function DC(), assignment condition DC(v) is also the logic OR function of all the activation conditions that result in variable v being assigned don't care value "X". If variable v is never assigned value "X", assignment condition DC(v) is zero. For this example, there is only one node 255 (FIG. 5B) in the control flow graph which specifies Q :="X" and the activation condition for edge 256 exiting that node is "1". Thus, the logic OR function of all the activation conditions is "1" so that assignment condition DC(Q) is "1".

For asynchronous load function AL(), the assignment condition for a variable is the logic OR function of the activation conditions for all edges exiting from directive nodes in the control flow graph where that variable is asynchronously assigned a value.

Consider the following user instructions (TABLE 2), which are illustrated in FIG. 6A as a control flow graph 300-A.

TABLE 2 ______________________________________ An Example of User Description 110 ______________________________________ if ( COND ) Q := 0 else endif. ______________________________________

The activation condition for edge 304-A from directive node 303-A is "COND". Since this is the only node in which variable Q is assigned a value, assignment condition AL(Q) for function AL() is also "COND."

The operation of asynchronous data function AD() is more complex than the operation of asynchronous load function AL(). A logic variable Q may asynchronously take on a logic zero value, e.g., Q :=0, a logic one value, e.g., Q :=1, or an unknown logic value, e.g., Q :=B, where B is another user defined logic variable, input variable, or a logic expression.

In general, assignment condition AD(v) for variable v is the logic OR function of all conditions under which variable v was assigned a logic one value. Notice that in contrast to the definition of assignment condition AL(v), the assignment condition AD(v) is not limited to just activation conditions. When the variable is simply assigned the constant logic one value, the activation condition is the condition used in evaluation of the logical OR function. When variable v is assigned a constant logic zero value, the condition used in evaluation of the logic OR function is a logic zero. When variable v is assigned a specific but unknown logic value, the condition used in the logic OR function is equal to the logic AND function of the activation condition where variable v was assigned that value with the unknown value assigned to variable v. Hence, the conditions used in evaluation of the logic OR function may be more complex than just the activation condition. To demonstrate the generation of rows in the assignment condition matrix for asynchronous functions AL() and AD( ), consider the following user instructions (TABLE 3), which are illustrated in FIG. 7A as control flow graph 330-A.

TABLE 3 ______________________________________ An Example of User Description 110 ______________________________________ if ( COND1 ) P := 1 else P := 0 endif if ( COND2 ) Q := B else endif. ______________________________________

The activation condition of edge 313-A from node 312-A where variable P is assigned the value "1" is "CONDI". The activation condition of edge 317-A from node 312-A where variable P is assigned the value "0" is "not COND1". Thus, using the above rules for the assignment conditions, assignment condition AL(P) for function AL() is the logic OR function of all the activation conditions from all the directive nodes where variable P is assigned a value, i.e. nodes 312-A and 316-A. The logic OR function is:

Therefore, assignment condition AL(P) for function AL() is "1." The assignment condition AD(P) for function AD() is the logic OR function of the conditions under which variable P is asynchronously assigned the value of "1", i.e., node 312-A. Thus, assignment condition AD(P) for function AD() is "COND1". Therefore, the row in the assignment condition matrix for variable P is as shown in TABLE 4 below.

Again, the same rules are used to determine assignment conditions AL(Q) and AD(Q). The activation condition for edge 322-A from node 321-A where variable Q is asynchronously assigned a value is "COND2". Thus, variable Q is asynchronously loaded if activation condition "COND2" is true. Since in this example, node 321-A is the only directive node where variable Q is assigned a value, assignment condition AL(Q) for asynchronous load function AL() is "COND2". Therefore, the entry in the assignment condition matrix in row Q and column AL() is "COND2".

At node 321-A, variable Q is driven to a logic one value only if variable B has the value "1". Thus, the two step process is used to determine the assignment condition for function A(Q). The condition under which variable Q is assigned a logic one value is the logical AND of the value of variable B (i.e., the value assigned to variable Q) and COND2 (the activation condition for the assignment), i.e., the condition is "B*COND2". The assignment condition AD(Q) is the logic OR function of all conditions under which variable Q was assigned a logic one value. Since there is only one condition, assignment condition AD(Q) is "B*COND2".

TABLE 4 ______________________________________ Vari- Assignment Conditions able AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ P 1 COND1 0 0 0 0 Q COND2 COND2*B 0 0 0 0 ______________________________________

The assignment conditions for synchronous load function SL() and synchronous function SD() are analogous to the asynchronous functions described above. For synchronous load function SL(), assignment condition SL(v) is the logical OR function of the activation conditions for all edges exiting from nodes of the control flow graph (i) where variable v is assigned a value and (ii) where the activation condition includes a clock edge. In the assignment conditions for the synchronous functions, the variable representing the clock edge (see "pos.sub.-- e" below) is replaced with a logic one.

Consider the following user instructions, which are illustrated in FIG. 6B as control flow graph 300-S.

TABLE 5 ______________________________________ An Example of User Description 110 ______________________________________ if ( positive.sub.-- edge(CLOCK) ) Q := 0 else endif. ______________________________________

The activation condition for edge 304-S from node 303-S is "positive.sub.-- edge(CLOCK)." (In the Figures and herein, "positive.sub.-- edge(CLOCK)" is also represented by "pos.sub.-- e".) Since this is the only node in which variable Q is assigned a value where the activation condition contains a clock edge, the assignment condition is for function SL(Q) is "1".

The operation of synchronous data function SD() is more complex than the operation of synchronous load function SL(). On a clock edge, a logic variable Q may synchronously take on a logic zero value, e.g., Q :=0, a logic one value, e.g., Q :=1, or an unknown logic value, e.g., Q :=B, where B is another user defined logic variable, input variable, or a logic expression.

Assignment condition SD(v) for variable v is the logic OR function of all conditions under which variable v was assigned a logic one value and the activation condition includes a clock edge. Notice that in contrast to the definition of assignment condition SL(v), assignment condition SD(v) is not limited to just the logic OR function of activation conditions. When variable v is simply assigned the constant logic one value on a clock edge, the activation condition is the condition used in evaluation of the logical OR function. When variable v is assigned a constant logic zero value on a clock edge, the condition used in evaluation of the logic OR function is a logic zero. When variable v is assigned a specified but unknown logic value on a clock edge, the condition used in the logic OR function is equal to the logical AND function of the activation conditions where variable v was assigned with the unknown value assigned to variable v. Hence, the conditions used in evaluation of the logic OR function may be more complex than just the activation condition.

To demonstrate the generation of rows in the assignment condition matrix for synchronous functions SL() and SD() consider the following user instructions (TABLE 6), which are illustrated in FIG. 7B as control flow graph 330-S.

TABLE 6 ______________________________________ An Example of User Description 110 ______________________________________ if ( positive.sub.-- edge(CLOCK) ) if (COND1) B := 1 else B := 0 endif if (COND2) Q := B else endif. else endif. ______________________________________

The activation condition of edge 313-S from node 312-S where variable B is assigned the value "1" is "COND1*positive.sub.-- edge(CLOCK)". The activation condition of edge 317-S from node 316-S where variable B is assigned the value "0" is "(not COND1)*positive.sub.-- edge(CLOCK)."

Thus, using the above rules for the assignment conditions, assignment condition SL(B) for function SL() is the logic OR function of all the activation conditions from all the directive nodes where variable P is assigned a value on a clock edge, i.e. node 312-S and 316-S. The logic OR function is just "COND1*positive.sub.-- edge(CLOCK))+((not COND1)*positive.sub.-- edge (CLOCK))" but by definition for a synchronous function "positive.sub.-- edge(CLOCK)" equals "1" because a synchronous function takes on a non-zero value only under this condition. Therefore, assignment condition SL(B) for function SL() is "(not COND1)+COND1", which is "1". Assignment condition SD(B) for function SD() is the logic OR function of the conditions under which variable B is synchronously assigned the value of "1", i.e., node 312-S Thus, assignment condition SD(B) for function SD() is "COND1", the activation condition for edge 313-S. Therefore, the row in the assignment condition matrix for variable B is as shown in TABLE 7 below.

Again, the same rules are used to determine the assignment conditions for variable Q and synchronous functions SL() and SD(). The activation condition for edge 322-S from node 321-S where variable Q is synchronously assigned a value is "COND2 * positive.sub.-- edge(CLOCK)". Thus, variable Q is synchronously loaded on a clock edge. Since in this example, node 321-S is the only directive node where variable Q is assigned a value on a clock edge, assignment condition SL(Q) for asynchronous load functions SL( ) is "COND2" because, as described above, "positive.sub.-- edge(CLOCK)" is replaced with a logic one. Therefore, the entry in the assignment condition matrix in row Q and columns SL() is "COND2".

At node 321-S, variable Q is driven to a logic one value on the clock edge only if variable B has the value "1". Thus, the two step process is used to determine the assignment condition SD(Q) for function SD(). The condition where variable Q is assigned a logic one value is the logical AND of the value assigned to variable B and the activation condition "COND2*pos.sub.-- e" for that assignment, i.e., the activation condition for edge 322-S so that the condition is "B*(COND2*pos.sub.-- e)". Assignment condition SD(Q) is the logical OR function of all conditions under which variable Q takes on a logic one value on a clock edge with the clock edge replaced by a logic one. Since there is only one such condition in control flow graph 330-S, assignment condition SD(Q) is "B*COND2".

TABLE 7 ______________________________________ Vari- Assignment Conditions able AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ B 0 0 1 COND1 0 0 Q 0 0 COND2 COND2*B 0 0 ______________________________________

The previous examples were simple examples that demonstrated generation of entries in the assignment condition matrix by assignment condition generator 124A. The next step is generation of a logic circuit for each row of the assignment condition matrix. Specifically, the following examples demonstrate the possible combinations within a row of the assignment condition matrix and the hardware that is generated for that row by logic circuit generator 124 (FIG. 2). Each example illustrates a set of predetermined assignment conditions that are used by hardware generator 124B to create specific logic elements. Hence, whenever hardware generator 124B encounters the predetermined assignment conditions, the logic elements described are created.

With respect to function AL(), consider a variable Q and the assignment condition matrix row given in TABLE 9 for variable Q. TABLE 9 is associated with the following user description (TABLE 8):

TABLE 8 ______________________________________ An Example of User Description 110 ______________________________________ If( COND ) Q := D else endif ______________________________________

"COND" is a condition.

TABLE 9 ______________________________________ Vari- Assignment Conditions able AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q COND COND*D 0 0 0 0 ______________________________________

For asynchronous load function AL(), variable Q must retain the assigned value until a subsequent assignment occurs. The operation of the asynchronous load function AL() is just the operation of a flow through latch where the assignment condition AD(Q) is the signal on the latch data input line and the value of the variable Q is the signal on the latch output line. The flow through latch is gated with assignment condition AL(Q). Thus, if assignment condition AL(Q) is "1", the input signal is transferred directly to the output line of the latch. If assignment condition AL(Q) has an unknown value, the input signal is transferred to the output line only when the assignment condition is true, i.e., takes on a logic one value.

Logic circuit 350 (FIG. 8A) generates the signals specified by user description 110 as defined in TABLE 8 above. Specifically, AND gate 340 has a first input signal that is the value assigned to variable D and a second input signal that is activation condition "COND." Output signal "D*COND" of AND gate 340 is activation condition AD(Q) and is the signal on data input line 342-D of latch 342. Activation condition "COND" is also the signal on gate terminal 342-G of latch 342. The signal on the output line of latch 342 is the value of variable Q. While circuit 350 provides the operation specified by the user description, circuit 350 may be improved.

Latch 342 does not use the value on data input line 342-D whenever the signal on gate terminal 342-G is zero. Thus, the logic circuit created by hardware generator 124B to generate assignment condition AD(Q) for the data input line 342-D is, in one embodiment, boolean minimized with "not assignment condition AL(Q)" as a don't care condition. When assignment condition AD(Q), which is "COND *D" is boolean minimized with a don't care of "not COND," the function "D" is the result Circuit 350-1
(FIG. 8B) is an improved result because fewer logic elements are required to produce the results specified by the user description in TABLE 8. Hence, circuit 350-1 is created by hardware generator 124B for the row in TABLE 9.

Thus, in more general terms, for a row in the assignment condition matrix for a variable v with assignment conditions AL(v) and AD(v), the logic circuit generated for these assignment conditions by hardware generator 124B is the boolean minimization of assignment condition AD(v) with the don't care condition of "not assignment condition AL(v)." If the value of boolean minimized assignment condition AD(v) is a boolean constant, the logic circuit is further simplified from that described above.

Consider the following user description (TABLE 10).

TABLE 10 ______________________________________ An Example of User Description 110 ______________________________________ if(COND) Q := 1 else endif ______________________________________

The row of the assignment condition matrix for variable Q is given in TABLE 11.

TABLE 11 ______________________________________ Vari- Assignment Conditions able AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q COND COND*1 0 0 0 0 ______________________________________

Boolean minimization of assignment condition AD(Q), ie., "COND * 1" with the don't care condition of "not assignment condition AL(Q)", i.e. "not COND" gives an assignment condition AD(Q) of "1". The logic circuit generated to produce the signal represented by the value of variable Q (TABLE 11) is a wire 339 (FIG. 8C).

If the value of assignment condition AL(v) for variable v is a boolean constant, the generated logic circuit is simplified in comparison to that described above for FIG. 8B. If the value of assignment condition AL(V) is 0, no hardware is generated because variable v was never asynchronously assigned a value. If the value of assignment condition AL(v) is "1", the value of variable v is simply assignment condition AD(v) so that again a latch is not needed. Therefore, hardware is built to generate assignment condition AD(v). Consider the following user description (TABLE 12).

TABLE 12 ______________________________________ An Example of User Description 110 ______________________________________ if(COND) Q := D else Q := E endif ______________________________________

The row of the assignment condition matrix for variable Q is given in TABLE 13.

TABLE 13 ______________________________________ Variable Assignment Conditions ______________________________________ AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) Q 1 D*COND + 0 0 0 0 E*COND ______________________________________

Since the value of variable Q is simply assignment condition AD(Q), a logic circuit 351 consisting of the logic nodes required to generate the signal represented by assignment condition AD(Q) is built as shown in FIG. 8D. AND gate 340-1, in response to signals "D" and "COND," feeds OR gate 341 a first input signal "D * COND." Similarly, AND gate 340-2, in response to signals "E" and "not COND," feeds OR gate 341 a second input signal "E * (not COND)." Hence, the output signal Q of OR gate
341 is just activation condition AD(Q).

With respect to function Z(v), again consider variable Q and the assignment condition matrix row given in TABLE 15 for variable Q. TABLE 15 is associated with the following user description (TABLE 14):

TABLE 14 ______________________________________ An Example of User Description 110 ______________________________________ If ( COND ) Q := "Z" else Q := b + c endif ______________________________________

Thus, characters b and c represent logic variables and string "COND" is a condition.

TABLE 15 ______________________________________ Vari- able Assignment Conditions ______________________________________ AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) Q 1 (b+c)*COND 0 0 0 COND ______________________________________

In general for a row of the assignment condition matrix for variable v where assignment condition Z(v) is not zero and asynchronous load assignment condition AL(v) is one, a three-state driver is generated by logic circuit generator 124. The data input line of the three-state driver is connected to assignment condition AD(v), the enable input line of the three-state driver is connect to the inverse of assignment condition Z(v). The value of variable v is the signal on the three-state driver's output line.

In one embodiment, logic circuit 352 (FIG. 9A) is generated by logic circuit generator 124 for the row of the assignment condition matrix shown in TABLE 15. Since the value of assignment condition AL(Q) is "1", the value of variable Q is simply assignment condition AD(v) so that hardware is built to generate assignment condition AD(v). Specifically, OR gate 341, in response to input signals b and c, generates an output signal "b+c" which is a first input signal to AND gate 340. Output signal "not COND" from invertor 346 is a second input signal to AND gate 340. Thus, the output signal from AND gate 340 is assignment condition AD(Q). Further, since assignment condition Z(Q) is not zero, and asynchronous load assignment condition AL(Q) is one, a three-state driver 343 is generated by logic circuit generator 124. The data input line of the three-state driver 343 is connected to assignment condition AD(Q), which is the output signal of AND gate 340. Output signal "not COND" from invertor
346 also drives the enable input line of the three-state driver 343.

Thus, circuit 352 corresponds to the user description in TABLE 14 which was used to generate the row of the assignment condition matrix in TABLE 15. However, circuit 352 may be improved. A three-state hardware element does not use the value on its data input line whenever the signal on its enable input line is zero. Thus, the hardware generated to produce the signal on the data input line of three-state element 343, i.e., assignment condition AD(Q), is boolean minimized with assignment condition Z(Q) as a don't care condition by hardware generator 124B. Thus, when assignment condition AD(Q), i.e., "(not COND) * (b+c)" is boolean minimized with a don't care of assignment condition Z(Q), i.e., "COND", function, "b+c" is the result. Circuit 352-1 (FIG. 9B) is the improved result that is preferably created by hardware generator 124B.

Thus, in one embodiment, when a row of the assignment condition matrix for variable v has assignment condition Z(v) and assignment condition AD(v) that are not zero, assignment condition AD(v) is boolean minimized with assignment condition Z(v) as a don't care condition. A logic circuit is created by hardware generator 124B to generate the function that results from the boolean minimization, i.e, a new assignment condition AD(v)', and the signal generated by that circuit drives the data input line of a three-state element. The "not" of assignment condition Z(v) drives the enable input line of the three-state element and the signal on the output line of the three state element is the value of variable v. Since in this embodiment function Z() is asynchronously driven, function Z() is in fact an asynchronous high impedance function AZ().

As explained above, when a row of the assignment condition matrix for variable v has a non-constant asynchronous data assignment condition AD(v) and a non-constant asynchronous load assignment condition AL(v), logic circuit generator 124 creates a latch with asynchronous data assignment condition AD(v) on the latch data input line and asynchronous load assignment condition AL(v) on the latch gate line. When a row of the assignment condition matrix for variable v has nonconstant values for asynchronous data assignment condition AD(v), asynchronous load assignment condition AL(v) and high impedance assignment condition Z(v), two latches are required. The first latch is configured the same as when assignment condition Z(v) has a logic zero value. The output of the first latch drives the data input line of a three-state element. The data input line of the second latch is driven by assignment condition Z(v) and the gate input line of the second latch is driven by assignment condition AL(v). The output line of the second latch drives an inverter which in turn drives the date enable line of the three state element. To illustrate this example more completely, consider the user description in TABLE 16.

TABLE 16 ______________________________________ An Example of a User Description 110 ______________________________________ if(COND.sub.-- 1) if(COND) Q := "Z" else Q := b + c endif else endif ______________________________________

The row of the assignment condition matrix for variable Q is presented in TABLE 17.

TABLE 17 __________________________________________________________________________ Variable Assignment Conditions __________________________________________________________________________ AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) Q COND.sub.--
1 COND.sub.-- 1* 0 0 0 COND.sub.-- 1* COND* COND (b+c) __________________________________________________________________________

In one embodiment, logic circuit 353 (FIG. 10A) is created by logic circuit generator 124 for the row of the assignment condition matrix shown in TABLE 15. Specifically, logic circuit 353 has the value of assignment condition AD(Q) connected to the input line of latch 342-1. The gate line of latch 342-1 is driven by the value of assignment condition AL(Q). The input line of three-state driver 343 is driven by the output signal of latch 342-1. The data enable line of three-state driver 343 is driven by the inverted output signal of latch 342-2. The input line of latch 342-2 is connected to the value of assignment condition Z(Q). The gate line of latch 342-2 is connected to the value of assignment condition AL(Q), i.e, "COND.sub.-- 1." Again, logic circuit 353 is a literal representation of the user description in TABLE 16.

However, as explained above, for a row of assignment condition matrix for variable Q with assignment conditions AL(Q) and AD(Q), the logic circuit generated for these assignment conditions is preferably the boolean minimization of assignment condition AD(Q) with the don't care condition of "not assignment condition AL(Q)." Also as explained above, when a row of the assignment condition matrix for variable Q where assignment condition Z(Q) and assignment condition AD(Q) are not zero, assignment condition AD(Q) is boolean minimized with assignment condition Z(Q) as a don't care condition.

Thus, assignment condition AD(Q) (TABLE 17) is boolean minimized with "(not assignment condition AL(Q)+assignment condition Z(Q)" as a don't care condition. Specifically, the don't care condition "(not COND.sub.-- 1)+(COND.sub.-- 1*COND)" is used to generate assignment condition AD(Q)', i.e., "b+c".

As described above, the data input line of second latch 342-2 is driven by assignment condition Z(Q) and gate input line 342-G of latch 342-2 is driven by assignment condition AL(Q) and preferably assignment condition Z(Q) is boolean minimized with the not of assignment condition AL(Q) as a don't care condition. The minimization gives an assignment condition Z(Q)' of "COND". Hence, after minimization the row for variable Q in the assignment condition matrix is as shown in TABLE 18.

TABLE 18 ______________________________________ Variable Assignment conditions ______________________________________ AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) Q COND.sub.-- 1 b + c 0 0 0 COND ______________________________________

Logic circuit 353-1 (FIG. 10B) is created by logic circuit generator 124 for the row of the assignment condition matrix shown in TABLE 18. Specifically, logic circuit 353-1 has the value of assignment condition AD(Q) (TABLE 18) connected to the input line of latch 342-1. The gate line of latch 342-1 is driven by the value of assignment condition AL(Q) (TABLE 18). The input line of three-state driver 343 is driven by the output signal of latch 342-1. The data enable line of three-state driver
343 is driven by the inverted output signal of latch 342-2. The input line of latch 342-2 is connected to the value of assignment condition Z(Q) (TABLE 18). The gate line of latch 342-2 is connected to the value of assignment condition AL(Q), i.e, "COND.sub.-- 1."

Comparison of FIGS. 10A and 10B shows that the boolean minimization has eliminated three logic nodes from circuit 353. Hence, as previously described, assignment conditions Z(v) and AD(v) for variable v are preferably boolean minimized with the not of assignment condition AL(v) whenever assignment condition AL(v) is other than a logic one. Assignment condition AD(v) is also boolean minimized with assignment condition Z(v) as a don't care condition.

With respect to function DC(v), again consider variable Q and the assignment condition matrix row given in TABLE 20 for variable Q. TABLE 20 is associated with the user description in TABLE 19.

TABLE 19 ______________________________________ An Example of User Description 110 ______________________________________ If ( COND ) Q := "X" else Q := b + c endif ______________________________________

Characters b and c represent logic variables and string "COND" is a condition.

TABLE 20 ______________________________________ Variable Assignment conditions ______________________________________ AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) Q 1 (b+c)* 0 0 COND 0 COND ______________________________________

In this case, the hardware generated for variable Q is assignment condition AD(Q) optimized with assignment condition DC(Q) as a "don't care." Specifically, in one embodiment, a Karnaugh map, such as the one shown in TABLE 21, is used for the optimization.

TABLE 21 ______________________________________ A Simple Karnaugh Opitmization for Don't Care ______________________________________ ##STR1## ______________________________________

The Karnaugh map shows that the optimization is just "b+C". Hence, as shown in FIG. 11, the hardware generated is simply OR gate 341 with input signals b and c and output signal Q.

Other combinations of assignment conditions in a row of the assignment condition matrix for variable v where assignment conditions AL(v), AD(v), Z(v), and DC(v) are all non-zero and not a constant are possible. However, the hardware generated by logic circuit generator 124 follows directly from the above description. Assignment condition Z(v) is boolean minimized with the not of assignment condition AL(v) as a don't care condition to obtain assignment condition Z(v)'. Assignment condition AD(v) is boolean minimized with the logic OR function of (i) the not of assignment condition AL(v) as a don't care condition, (ii) assignment condition Z(v)' as a don't care condition and (iii) assignment condition DC(v) to yield assignment condition AD(v)'. The resulting row of the assignment condition matrix for variable v includes assignment conditions AL(v), AD(v)', DC(v) and Z(v)'. Logic circuit generator 124 generates a logic network for this resulting row as described above.

The other possible entries in a row of the assignment condition matrix include one of the synchronous hardware description functions. In general, for a row in the assignment condition matrix where assignment condition SL(v) is a logic one, assignment condition AL(v) is a logic zero, and assignment condition SD(v) is non-zero, a D-type flip-flop is built for variable v by hardware generator 124B. Assignment condition SD(v) is applied to the input line of the flip-flop and the clock edge is applied to the clock input terminal. The signal on the flip-flop output line is the value of the variable v.

With respect to function SD(), again consider variable Q and the assignment condition matrix row given in TABLE 23 for variable Q for the user description in

TABLE 22 ______________________________________ An Example of User Description 110 ______________________________________ If ( positive.sub.-- edge(CLOCK) ) Q := b + c else endif ______________________________________

Thus, characters b and c represent logic variables. As described above, the condition "positive.sub.-- edge(CLOCK)" requires a synchronous function.

TABLE 23 ______________________________________ Variable Assignment Conditions ______________________________________ AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) Q 0 0 1 b+c 0 0 ______________________________________

When assignment condition AL(Q) is a logic zero and assignment condition SL(Q) is a logic one, the hardware generated for variable Q (TABLE 23) is a D-type flip-flop 344 (FIG. 12) and an OR gate 341. Signals b and c drive OR gate 341 which in turn drives the input line of D-type flip-flop 344. Clock terminal 344-CL of flip-flop 344 is driven by the clock signal, in this embodiment a positive clock edge, associated with the synchronous functions. The conditions in TABLE 23 are the simplest synchronous conditions. Other possible conditions are when either the asynchronous load assignment condition is non-zero or synchronous load assignment condition is not a logic one.

With respect to function SL(), consider a variable Q and the assignment condition matrix row given in TABLE 25 for variable Q for the user description in TABLE 24:

TABLE 24 ______________________________________ An Example of User Description 110 ______________________________________ If ( positive.sub.-- edge(CLOCK)) If ( COND ) Q := b + c else endif else endif ______________________________________

Characters b and c represent logic variables and string "COND" is a condition.

TABLE 25 ______________________________________ Assignment Conditions Variable AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q 0 0 COND (b + c)* 0 0 COND ______________________________________

As described above, the logic circuit created to generate the value of variable Q with assignment condition SL(Q) is a D-type flip-flop 344 (FIG. 13). However, when assignment condition SL(Q) is not a constant, a multiplexer is added to the logic circuit. For variable Q, a feedback multiplexer 345 is added because in this case, signal b+c, i.e., the output signal of OR gate 341, is not passed to flip-flop 344 on the positive clock edge unless condition "COND" is true. Thus, signal b+c drives a first input terminal of multiplexer 345. The second input terminal of multiplexer 345 is tied to the D-type flip-flop 344 output line. The signal selection terminal of multiplexer 345 is driven by signal "COND". Multiplexer is configured so that signal b+c is selected when signal "COND" is true. When signal "COND" is false, output signal Q is gated through flip-flop 344 by a positive clock edge. Thus, when assignment condition SL(Q) is not a constant, the multiplexer is controlled by assignment condition SL(Q) so that only when assignment condition SL(Q) is true on a clock edge the value on the flip-flop output line is assignment condition SD(Q). For all other clock edges, the value on the flip-flop output line stays at the value of variable Q.

As explained above, when a row of the assignment condition matrix for variable v has a logic one synchronous load assignment condition SL(v), logic circuit generator 124 creates a flip-flop with synchronous data assignment condition SD(v) on the flip-flop data input line and the clock edge on the flip-flop clock terminal. When a row of the assignment condition matrix for variable v has a logic one value for synchronous load assignment condition SL(v) and high impedance assignment condition Z(v) is non-constant, two flip-flops are required. The first flip-flop is configured the same as when assignment condition Z(v) has a logic zero value. The output signal of the first flip-flop drives the data input line of a three-state element. The data input line of the second flip-flop is driven by assignment condition Z(v) and the clock terminal of the second flip-flop is driven by the clock edge. The output line of the second flip-flop drives an invertor which in turn drives the data enable line of the three state element. In this case, high impedance function Z() is in fact synchronous high impedance function SZ() because the function takes on a value only on a clock edge.

To illustrate this example more completely, consider the user description in TABLE 26 which is the basis of the row of the assignment condition matrix illustrated in TABLE 27.

TABLE 26 ______________________________________ An Example of User Description 110 ______________________________________ If ( positive.sub.-- edge(CLOCK)) If ( COND ) Q := "Z" else Q := b + c endif else endif. ______________________________________

Again, characters b and c represent logic variables and string "COND" is a condition.

TABLE 27 ______________________________________ Assignment Conditions Variable AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q 0 0 1 (b + c)* 0 COND COND ______________________________________

As described above, when assignment condition SL(Q) is non-zero, a first flip-flop 344-1 (FIG. 14A) is built, as described above, so that assignment condition SD(Q) drives the input terminal of flip-flop 344-1. Similarly, since the assignment condition Z(Q) is non-zero and driven on a clock edge, the output signal of flip-flop 344-1 drives a three-state element 343. Also, an additional flip-flop 344-2 is required to generate the three-state enable signal. The data input line of flip-flop
344-2 is driven by assignment condition Z(Q). The clock input line of flip-flop 344-2 is connected to the clock signal associated with the synchronous function, and the inverted output signal of flip-flop 344-2 drives the enable line of three-state driver 343. Logic circuit 357 performs the operations specified by the user description in TABLE 27. However, logic circuit 357 may be further optimized.

In a matter analogous to the asynchronous functions described above, assignment condition SD(Q) is boolean minimized with assignment condition Z(Q) as a don't care condition. This optimization results in the assignment condition SD(Q)' becoming "b+c." For the optimized assignment condition, logic circuit generator 124 produces logic circuit 357-1 (FIG. 14B).

With respect to function DC(v), again consider variable Q and the assignment condition matrix row given in TABLE 29 for variable Q as defined in the user description of TABLE 28:

TABLE 28 ______________________________________ An Example of User Description 110 ______________________________________ If ( positive.sub.-- edge(CLOCK) If ( COND ) Q := "X" else Q := b + c endif else endif. ______________________________________

TABLE 29 ______________________________________ Assignment Conditions Variable AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q 0 0 1 (b + c)* COND 0 COND ______________________________________

Again in a manner similar to the asynchronous functions described above, assignment condition SD(Q) is optimized with assignment condition DC(Q) as a don't care condition. The result of the optimization is that assignment condition SD(Q)' is "b+c". Thus, the logic circuit generated for the row of the assignment condition matrix in TABLE 29 is illustrated in FIG. 15. Since the circuit in FIG. 15 is the same as circuit 355 in FIG. 12, the description of FIG. 12 is incorporated herein by reference.

The previous examples demonstrated building logic circuits based upon a row in the assignment condition matrix that included either only synchronous or only asynchronous functions coupled with the don't care or high impedance functions. However, a row in the assignment condition matrix may contain assignment conditions for both synchronous and asynchronous functions.

Consider first a row in the assignment condition matrix for variable v which has non-zero entries for assignment conditions AL(v), SL(v) and SD(v). The assignment condition AD(v) is a logic zero. Since SL(v) and SD(v) are non-zero, a flip-flop is generated, as in the synchronous examples described above. However, the flip-flop has a clear-direct line. The clear-direct line is driven by the value of assignment condition AL(v).

As another example, consider a row in the assignment condition matrix for variable v which has non-zero entries for assignment conditions AL(v), AD(v), SL(v) and SD(v) where assignment condition AD(v) is a logic one. Again, since synchronous assignment conditions SL(v) and SD(v) are non-zero, a flip-flop is generated, as in the synchronous examples described above. However, in this situation the flip-flop has a set-direct line. The set-direct line is driven by assignment condition AL(v). If assignment condition AD(v) has an unknown value instead of a logic one, the flip-flop has both a set-direct terminal and an clear-direct terminal, as described more completely below. In this case, additional logic nodes may be generated so that the logic circuit performs the operations specified by the row of the assignment condition matrix.

Note that in these cases, the values of assignment conditions SL(v) and SD(v) are not important when assignment condition AL(v) is true. Thus, in one embodiment, assignment conditions SL(v) and SD(v) are boolean minimized with assignment condition AL(v) as don't care condition prior to logic circuit generation.

To further illustrate the logic circuit generated for a row in the assignment condition matrix having non-zero entries for both synchronous and asynchronous functions consider variable Q and the assignment condition matrix row given in TABLE 31
for variable Q as defined in the user description given in TABLE 30:

TABLE 30 ______________________________________ An Example of User Description 110 ______________________________________ if (COND) Q := 0 else if ( positive.sub.-- edge(CLOCK)) Q := b + c else endif endif. ______________________________________

Characters b and c represent logic variables and string "COND" is a condition.

TABLE 31 ______________________________________ Assignment Conditions Variable AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q COND 0 1* COND (b + c)* 0 0 COND ______________________________________

As explained above, preferably before hardware generation, assignment conditions SL(Q) and SD(Q) are boolean minimized with assignment condition AL(Q) as don't care condition. Hence, after minimization, assignment condition SL(Q)' has a logic one value and assignment condition SD(Q) has the value "b+c." Recall that in the example above when assignment condition SL(Q) had a non-constant value, a multiplexer was required. Thus, the minimization eliminated the need for this circuit element. Similarly, minimization of assignment condition SD(Q) eliminated the need for other logic nodes.

Accordingly, the logic circuit generated for the row of the assignment condition matrix in TABLE 31 after the boolean minimization is a D-type flip-flop 344 and an OR gate 341 (FIG. 16). D-type flip-flop 344 has a clear direct terminal 344-CD such that when a true signal is applied to terminal 344-CD, the output signal of flip-flop 344 is a logic zero. Signals b and c drive OR gate 341 and the output signal of OR gate 341 in turn drives the input line of D-type flip-flop 344. Clock terminal
344-CL is driven by the clock edge, in this embodiment a positive clock edge, associated with the synchronous functions. Signal "COND", i.e., assignment condition AL(Q) drives clear-direct terminal 344-CD of flip-flop 344.

An even more complex configuration for variable Q is given by the assignment condition matrix row in TABLE 33 for the user description given in TABLE 32:

TABLE 32 ______________________________________ An Example of User Description 110 ______________________________________ if (COND) Q := s else if ( positive.sub.-- edge(CLOCK) ) Q := b + c else endif endif. ______________________________________

Characters b, c and s represent logic variables and string "COND" is a condition.

TABLE 33 ______________________________________ Assignment Conditions Variable AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q COND s 1* COND (b + c)* 0 0 COND ______________________________________

Again, assignment conditions SL(v) and SD(v) are boolean minimized using assignment condition AL(Q) as a don't care condition, as described in the preceding example for TABLES 30 and 31. Logic circuit 360 (FIG. 17) generated for variable Q again includes a D-type flip-flop 344 and an OR gate 341, but D-type flip-flop 344 has both a set-direct terminal 344-SD and a clear-direct terminal 344-CD. When a true signal is applied to clear-direct terminal 344-CD, the output signal of flip-flop 344 is a logic zero. Conversely, when a true signal is applied to set-direct terminal 344-SD, the output signal of flip-flop 344 is a logic one.

Signals b and c drive OR gate 341 and the output signal of OR gate 341 in turn drives the input line of D-type flip-flop 344. Clock terminal 344-CL is driven by the clock edge, in this embodiment a positive clock edge, associated with the synchronous functions. The remainder of the circuit depends on the value of variable s. In one embodiment, the value of variable s is assumed to be unknown, e.g., variable s is an input signal to the user's logic circuit. If condition "COND" is true and the value of variable s is a logic zero, the output signal from flip-flop must be a logic zero, i.e., an active signal must be applied to clear-direct terminal 344-CD. Conversely, if condition "COND" is true and the value of variable s is a logic one, the output signal from flip-flop must be a logic one, i.e., an active signal must be applied to set-direct terminal 344-SD of flip-flop 344. Thus, in one embodiment, two AND gates 340-1, 340-2 and an invertor 346 are generated to provide the appropriate signals to terminals 344-SD and 344-CD of flip-flop 344.

In each of the above examples, only a single row of the assignment condition matrix was considered. However, an assignment condition matrix may have one or more rows and a variable assigned a value by a row of the matrix may be subsequently used in an assignment condition for another variable. For example, in TABLE 7 above, the variable B is first assigned a value and then variable B is used in assigning a value to variable Q. In this situation, the logic circuit for each row is simply generated and then the output value of variable B is connected to the input value of variable B for the circuit that generates the variable Q. If the value of variable B is not generated by a logic circuit, the variable B is an input signal and so, in this case, the input value of variable B is obtained from an input pin.

Thus, in one embodiment, the activation conditions for edges exiting directive nodes representing directive statements are used to generate an assignment condition matrix. The assignment condition for a particular variable is determined by locating all the directive nodes were the variable is assigned a value and then combining the conditions under which that variable is assigned a value with a logic OR function. Since the assignment condition is a global attribute of the control flow graph, the assignment condition may become very complex.

In each of the above examples, all paths from the source to the sink of the control flow graph contain no more than one directive node which assigned a value to a particular variable. When a first directive node assigns a value to a variable that is over-ridden by a subsequent assignment at subsequent directive nodes, the activation condition used for the first node is the logic AND function of the first directive node's activation condition with the logic NOT function of the logic OR function of the activation conditions for all overriding assignments. To demonstrate this, consider the following user instructions (TABLE 34) which are illustrated in FIG. 18 as control flow graph 390.

TABLE 34 ______________________________________ An Example of User Description 110 ______________________________________ Q := B if ( COND ) Q := C; else endif. ______________________________________

The assignment to variable Q at node 370 (FIG. 18) is over-ridden by the assignment at node 375. Thus, the activation condition used at node 370 is modified as described above. The original activation condition is "1". In this example, there is only one overriding assignment, so that the logical OR is just the single activation condition "COND". The modified activation condition is:

Or, more simply:

Table 35 shows the assignment conditions for the user description in TABLE 34.

TABLE 35 ______________________________________ Vari- Assignment Conditions able AL( ) AD( ) SL( ) SD( ) DC( ) Z( ) ______________________________________ Q 1 ( COND*B) + 0 0 0 0 (COND*C) _________________________________