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United States Patent
5551043
Crump , ; et al.
August 27, 1996
Title
Standby checkpoint to prevent data loss
Abstract
A computer system having at least three states of power management: a normal operating state, a standby state, and a suspend state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. As the standby state is entered, the state of the computer system is saved to a file on the hard drive in such a manner that if system power is accidently removed after the state of the computer system is saved to the hard drive, then the state of the computer system can be resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The data saved as the system enters the standby state is invalidated if the system meets certain conditions.
Inventors:
Crump; Dwayne T.
(Lexington,
KY
)
, Pancoast; Steven T.
(Lexington,
KY
)
, Benson, IV; Paul H.
(Lexington,
KY
)
, Steelman; Herbert S.
(Lawrenceburg,
KY
)
Assignee:
International Business Machines Corporation
(Armonk,
NY
)
Appl. No.:
303103
Filed:
September 7, 1994
Current U.S. Class:
713/323
714/15
Field of Search:
395/750,575,375
U.S. Patent Documents
4740969
April 1988
Fremont
4852092
July 1989
Makita
5012406
April 1991
Martin
5167024
November 1992
Smith et al.
5301309
April 1994
Sugano
5313647
May 1994
Kaufman et al.
5386552
January 1995
Garney
5410711
April 1995
Stewart
5410713
April 1995
White et al.
Other References
Technique for Virtual Memory Architecture to Support Checkpoint and Rollback Recovery, IBM Technical Disclosure Bulletin, vol. 34, No. 4B, Sep., 1991..~
Primary Examiner:
Harvey; Jack B.
Assistant Examiner:
Wiley; David A.
Attorney, Agent or Firm:
Moorhead; Sean T. Magistrale; Anthony N.
Claims
What is claimed is:
1. A computer system operating in any selected one of four states of power management, namely a normal operating state in which code is executed normally by said computer system, a standby state, a checkpoint state, and a suspend state, the system comprising:
(a) a CPU for executing code;
(b) a control unit electrically connected to said CPU for changing said computer system between each of said states and at least one other of said states in response to at least one of a first plurality of preselected events;
(c) a peripheral device electrically connected to said CPU and said control unit and operating in a selected one of a relatively high electrical power usage state and a relatively low electrical power usage state, said peripheral device changing between said high and low electrical power usage states in response to said control unit;
(d) a power supply electrically connected to said CPU and said control unit and said peripheral device and comprising power selection circuitry for selectively providing system power from an external source to said computer system, said power supply being operating in a selected one of a first power supply state and a second power supply state, said power supply changing between said first and second power supply states responsive to said control unit;
(e) an electromechanical non-volatile storage unit electrically connected to said CPU for receiving and storing and delivering data;
(f) volatile memory for storing volatile memory data and electrically connected to said CPU; and
(g) volatile registers for storing volatile register data and electrically connected to said CPU;
(1) wherein in said normal operating state, said power supply is in said first power supply state, said peripheral device is in said high electrical power usage state, and code is executed normally by said computer system;
(2) wherein in said standby state, said power supply is in said first power supply state, said peripheral device is in said low electrical power usage state, and code continues being executed by said computer system;
(3) wherein in said checkpoint state, said power supply is in said first power supply state, said peripheral device is in said low electrical power usage state, code continues being executed by said computer system, if power from the external source to said power supply is interrupted then volatile register data and volatile memory data would be lost from the volatile memory and volatile registers, and volatile memory data and the volatile register data at a point in time are stored on said electromechanical non-volatile storage unit;
(4) wherein in said suspend state, said power supply is in said second power supply state and the code executing on said CPU has been reversibly interrupted such that the execution of the code on said CPU may be resumed after said power supply changes to said first power supply state.
2. A computer system according to claim 1 wherein the stored volatile register data and volatile memory data are transferred from said electromechanical non-volatile storage unit to the volatile memory and volatile registers in response to the interruption of power from the external source to said power supply while said computer system is in said checkpoint state.
3. A computer system according to claim 1 wherein said electromechanical non-volatile storage unit comprises a fixed disk storage device.
4. A computer system according to claim 2 wherein said electromechanical non-volatile storage unit comprises a fixed disk storage device.
5. A computer system according to claim 1 further comprising a flag electrically connected to said CPU and wherein said CPU writes a value to said flag responsive to said computer system exiting said checkpoint state, said value indicating that the volatile memory data and the volatile register data stored on said electromechanical non-volatile storage unit are not to be written back to said volatile memory and said volatile registers.
6. A computer system according to claim 1 further comprising a flag electrically connected to said CPU and wherein said CPU writes a value to said flag responsive to said computer system accessing said electromechanical non-volatile storage unit, said value indicating that the volatile memory data and the volatile register data stored on said electromechanical non-volatile storage unit are not to be written back to said volatile memory and said volatile registers.
7. A computer system according to claim 1 further comprising (i) an operating system using a swap file stored on said electromechanical non-volatile storage unit and (ii) a flag electrically connected to said CPU and wherein said CPU writes a value to said flag responsive to said computer system accessing a region of said electromechanical non-volatile storage unit corresponding to said swap file, said value indicating that the volatile memory data and the volatile register data stored on said electromechanical non-volatile storage unit are not to be written back to said volatile memory and said volatile registers.
8. In a computer system having at least two states of power management, namely (i) a normal operating state in which code is executed normally by the computer system and (ii) a power conservation state in which the code continues executing and the computer system consumes less electrical power than in said normal operating state, a method of controlling transitions between computer system power management states, comprising the steps of:
(a) providing regulated system power from an external source to electronic devices of the computer system;
(b) writing volatile memory data and volatile register data to the powered electronic devices;
(c) operating the computer system in the normal operating state until the occurrence of a first preselected event;
(d) transitioning the computer system to the power conservation state responsive to the occurrence of the first preselected event, such that if system power from the external source to the electronic devices is interrupted then the volatile register data and volatile memory data would be lost from the electronic devices;
(e) saving the state of the computer system to an electromechanical non-volatile storage device and writing a first value to a flag indicating that the state of the computer system has been saved to the electromechanical non-volatile storage device; then (f) operating the computer system in a hybrid power conservation state until the occurrence of a second preselected event, while in the hybrid power conservation state: (i) the code continues executing, (ii) the computer system consumes less electrical power than in said normal operating state, (iii) if system power from the external source to the electronic devices is interrupted then volatile register data and volatile memory data would be lost from the electronic devices, and (iv) the state of the computer system at a previous point in time remains saved on the electromechanical non-volatile storage device;
(g) transitioning the computer system to the normal operating state, without loading the state of the computer system from the electromechanical non-volatile storage device to the computer system, responsive to the occurrence of the second preselected event; and
(h) responsive to an interruption of system power from the external source to the electronic devices containing volatile register data and volatile memory data while the system is in the hybrid power conservation state, loading the state of the computer system from the electromechanical non-volatile storage device to the electronic devices and resuming code execution.
9. A method of controlling transitions between computer system power management states according to claim 8 wherein the state of the computer system comprises the volatile register data and the volatile memory data.
10. A method of controlling transitions between computer system power management states according to claim 8 further comprising the step of writing a second value to the flag responsive to transitioning the computer system to the normal operating state responsive to the occurrence of the second preselected event.
11. A method of controlling transitions between computer system power management states according to claim 8 further comprising the steps of:
(a) starting an inactivity timer to expire after a first preselected time interval;
(b) operating the computer system in the normal operating state until expiration of the first time interval; and
(c) restarting the inactivity timer responsive to user activity occurring while the computer system is in the normal operating state; and
wherein the first preselected event comprises expiration of the first time interval.
12. A method of controlling transitions between computer system power management states according to claim 11 wherein the second preselected event comprises detection of user activity.
13. A method of controlling transitions between computer system power management states according to claim 8 wherein the second preselected event comprises detection of user activity.
14. A computer system having at least two states of power management, namely (i) a normal operating state in which code is executed normally by the computer system and (ii) a power conservation state in which the code continues executing and the computer system consumes less electrical power than in said normal operating state, said computer system comprising:
(a) means for providing regulated system power from an external source to electronic devices of the computer system;
(b) means for writing volatile memory data and volatile register data to the powered electronic devices;
(c) means for operating the computer system in the normal operating state until the occurrence of a first preselected event;
(d) means for transitioning the computer system to the power conservation state responsive to the occurrence of the first preselected event, such that if system power from the external source to the electronic devices is interrupted then the volatile register data and volatile memory data would be lost from the electronic devices;
(e) means for saving the state of the computer system to an electromechanical non-volatile storage device and writing a first value to a flag indicating that the state of the computer system has been saved to the electromechanical non-volatile storage device; then
(f) means for operating the computer system in a hybrid power conservation state until the occurrence of a second preselected event, while in the hybrid power conservation state: (i) the code continues executing, (ii) the computer system consumes less electrical power than in said normal operating state, (iii) if system power from the external source to the electronic devices is interrupted then volatile register data and volatile memory data would be lost from the electronic devices, and (iv) the state of the computer system at a previous point in time remains saved on the electromechanical non-volatile storage device;
(g) means for transitioning the computer system to the normal operating state, without loading the state of the computer system from the electromechanical non-volatile storage device to the computer system, responsive to the occurrence of the second preselected event; and
(h) means, responsive to an interruption of system power from the external source to the electronic devices containing volatile register data and volatile memory data while the system is in the hybrid power conservation state, for loading the state of the computer system from the electromechanical non-volatile storage device to the electronic devices and resuming code execution.
15. A computer system according to claim 14 wherein the state of the computer system comprises the volatile register data and the volatile memory data.
16. A computer system according to claim 14 further comprising means for writing a second value to the flag responsive to transitioning the computer system to the normal operating state responsive to the occurrence of the second preselected event.
17. A computer system according to claim 14 further comprising:
(a) means for starting an inactivity timer to expire after a first preselected time interval;
(b) means for operating the computer system in the normal operating state until expiration of the first time interval; and
(c) means for restarting the inactivity timer responsive to user activity occurring while the computer system is in the normal operating state; and
wherein the first preselected event comprises expiration of the first time interval.
18. A computer system according to claim 17 wherein the second preselected event comprises detection of user activity.
19. A computer system according to claim 14 wherein the second preselected event comprises detection of user activity.
20. A method of controlling transitions between computer system power management states according to claim 8 further comprising the step of writing a second value to the flag responsive to an access to the electromechanical non-volatile storage device.
21. A computer system according to claim 14 further comprising means for writing a second value to the flag responsive to an access to the electromechanical non-volatile storage device.
Description
RELATED APPLICATIONS
The present invention is believed to be related to the following pending applications:
Application Ser. No. 08/097,334, filed Jul. 23, 1993, and entitled "DESKTOP COMPUTER HAVING A SINGLE SWITCH SUSPEND/RESUME FUNCTION", now U.S. Pat. No. 5,513,359;
Application Ser. No. 08/097,250, filed Jul. 26, 1993, and entitled "DESKTOP COMPUTER SYSTEM HAVING ZERO VOLT SYSTEM SUSPEND", now U.S. Pat. No. 5,511,202;
Application Ser. No. 08/097,246, filed Jul. 23, 1993, and entitled "METHOD OF SAVING AND RESTORING THE STATE OF A CPU EXECUTING CODE IN A PROTECTED MODE", now U.S. Pat. No. 5,497,494;
Application Ser. No. 08/097,251, filed Jul. 26, 1993, and entitled "DESKTOP COMPUTER SYSTEM HAVING MULTI-LEVEL POWER MANAGEMENT";
Application Ser. No. 08/303,102, filed Sep. 7, 1994, and entitled "AUTOMATIC CLEARING OF POWER SUPPLY FAULT CONDITION IN SUSPEND SYSTEM",
Application Ser. No. 08/302,148, filed Sep. 7, 1994, and entitled "AUTOMATIC ALLOCATION OF SUSPEND FILE";
Application Ser. No. 08/301,466, filed Sep. 7, 1994, and entitled "POWER MANAGEMENT PROCESSOR FOR SUSPEND SYSTEMS";
Application Ser. No. 08/302,147, filed Sep. 7, 1994, and entitled "MULTIFUNCTION POWER SWITCH AND FEEDBACK LED FOR SUSPEND SYSTEMS";
Application Ser. No. 08/302,157, filed Sep. 7, 1994, and entitled "LOW POWER RING DETECT FOR COMPUTER SYSTEM WAKEUP";
Application Ser. No. 08/301,464, filed Sep. 7, 1994, and entitled "PERFORMING SYSTEM TASKS AT POWEROFF USING SYSTEM MANAGEMENT INTERRUPT", now U.S. Pat. No. 5,511,204;
Application Ser. No. 08/302,066, filed Sep. 7, 1994, and entitled "AUTOMATIC RESTORATION OF USER OPTIONS AFTER POWER LOSS";
Application Ser. No. 08/301,943, filed Sep. 7, 1994, and entitled "AUTOMATIC BACKUP SYSTEM FOR ADVANCED POWER MANAGEMENT (APM)".
FIELD OF THE INVENTION
The present invention relates generally to computer system architecture and, more specifically, to a desktop computer system having a system suspend/resume capability and the capability of periodically saving the state of the computer system to a hard drive and restoring the computer state if power is lost.
BACKGROUND OF THE INVENTION
Personal computer systems are well known in the art. Personal computer systems in general, and IBM Personal Computers in particular, have attained widespread use for providing computer power to many segments of today's modern society. Personal computers can typically be defined as a desktop, floor standing, or portable microcomputer that is comprised of a system unit having a single central processing unit (CPU) and associated volatile and nonvolatile memory, including all RAM and BIOS ROM, a system monitor, a keyboard, one or more flexible diskette drives, a fixed disk storage drive (also known as a "hard drive"), a so-called "mouse" pointing device, and an optional printer. One of the distinguishing characteristics of these systems is the use of a motherboard or system planar to electrically connect these components together. These systems are designed primarily to give independent computing power to a single user and are inexpensively priced for purchase by individuals or small businesses. Examples of such personal computer systems are IBM's PERSONAL COMPUTER AT and IBM's PERSONAL SYSTEM/1 (IBM PS/1).
Personal computer systems are typically used to run software to perform such diverse activities as word processing, manipulation of data via spread-sheets, collection and relation of data in databases, displays of graphics, design of electrical or mechanical systems using system-design software, etc.
The first four related applications disclose a computer system having four power management states: a normal operating state, a standby state, a suspend state, and an off state. One switch is used to change between the off state, the normal operating state, and the suspend state.
The normal operating state of the computer system of the present invention is virtually identical to the normal operating state of any typical desktop computer. Users may use applications and basically treat the computer as any other. One difference is the presence of a power management driver, which runs in the background (in the BIOS and the operating system), transparent to the user. The portion of the power management driver in the operating system (OS) is the Advanced Power Management (APM) advanced programming interface written by Intel and Microsoft, which is now present in most operating systems written to operate on Intel's 80X86 family of processors. The portion of the power management driver in BIOS (APM BIOS) communicates with the APM OS driver. The APM OS driver and the APM BIOS routines together control the computer's transition to and from the other three states.
The second state, the standby state, uses less power than the normal operating state, yet leaves any applications executing as they would otherwise execute. In general, power is conserved in the standby state by placing devices in their respective low-power modes. For example, power is conserved in the standby state by ceasing the revolutions of the fixed disk within the hard drive and by ceasing generating the video signal.
The third state is the suspend state. In the suspend state, computer system consumes an extremely small amount of power. The suspended computer consumes very little power from the wall outlet. The only power consumed is small amount of power to maintain the circuitry that monitors the switch from a battery inside the computer system (when the system is not receiving AC power) or a small amount of power generated at an auxiliary power line by the power supply (when the system is receiving AC power).
This small use of power is accomplished by saving the state of the computer system to the fixed disk storage device (the hard drive) before the power supply is turned "off." To enter the suspend state, the computer system interrupts any executing code and transfers control of the computer to the power management driver. The power management driver ascertains the state of the computer system and writes the state of the computer system to the fixed disk storage device. The state of the CPU registers, the CPU cache, the system memory, the system cache, the video registers, the video memory, and the other devices' registers are all written to the fixed disk. The entire state of the system is saved in such a way that it can be restored without the code applications being adversely affected by the interruption. The computer then writes data to the non-volatile CMOS memory indicating that the system was suspended. Lastly, the computer causes the power supply to stop producing power. The entire state of the computer is safely saved to the fixed disk storage device, system power is now "off," and computer is now only receiving a small amount of regulated power from the power supply to power the circuitry that monitors the switch.
The fourth and final state is the off state. In this state, the power supply ceases providing regulated power to the computer system, but the state of the computer system has not been saved to the fixed disk. The off state is virtually identical to typical desktop computers being turned off in the usual manner.
Switching from state to state is handled by the power management driver and is typically based on closure events of a single switch, a flag, and two timers: the inactivity standby timer and the inactivity suspend timer. The system has a single power button. This button can be used to turn on the computer system, suspend the state of the system, restore the state of the system, and turn off the system.
When a typical computer system is being actively used, large amounts of data are typically stored in volatile storage, e.g., random access memory (RAM). Until data files are saved to non-volatile storage, e.g., a hard disk drive, there is an exposure to data loss. If AC power to the system power supply is interrupted, as occurs during AC power blackouts and brownouts, all data stored in volatile storage is lost.
One approach to protecting volatile storage through a blackout condition is to incorporate an uninterruptable power supply (UPS). A UPS typically has some sort of battery backup to continue supplying AC power to the system when AC power from the wall outlet is lost. One problem with using a UPS is that typically, UPSs are bulky and expensive. Yet for extremely critical applications, it may be the only acceptable solution.
For the typical user, the cost of a UPS cannot be justified. While suspended, the system data is inherently immune to power outages because all state information is stored in non-volatile storage. Significantly, the system is still exposed to data loss when it is in the normal operating state or the standby state.
SUMMARY OF THE INVENTION
According to the present invention, periodically a suspend-like data Checkpoint is taken and used to restore the system if AC power is lost while the Checkpoint is valid. The solution is to merge the favorable aspects of the standby state and the suspend state to provide more protection against data loss without any inconvenience when in the standby state. The result is Standby Checkpointing.
When the system is about to enter the standby state, it performs a partial suspend and saves most of the system state to the hard drive. If the system loses AC power while it is in standby, the state of the system can be restored to what it was before it entered Standby. After exiting Standby, the state is invalidated when the hard disk is first updated. The reason for state invalidation will be discussed in more detail later. A valid checkpoint will be obtained the next time the system enters Standby.
If AC is lost while the checkpoint is valid, it can be used to restore the state of the system when AC returns.
It is an advantage of the present invention to provide protection against loss of data due to power outages without adding significant cost to the product.
It is a further advantage of the present invention to provide against loss of data in a background process, transparent to the user and the application programs. Any hardware interrupts or other forms of activity that can be detected abort the current checkpoint to provide immediate service to the foreground application. The checkpoint is effectively delayed until the next interval.
These and other advantages of the present invention will become more apparent from a detailed description of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings, which are incorporated in and constitute a part of this specification, embodiments of the invention are illustrated, which, together with a general description of the invention given above, and the detailed description given below serve to example the principles of this invention.
FIG. 1 is a perspective view of a personal computer embodying this invention;
FIG. 2 is an exploded perspective view of certain elements of the personal computer of FIG. 1 including a chassis, a cover, an electromechanical direct access storage device and a planar board and illustrating certain relationships among those elements;
FIGS. 3A and 3B show a block diagram of certain components of the personal computer of FIGS. 1 and 2;
FIG. 4 is a state diagram of the computer system of the present invention, showing the four system states: normal, standby, suspend, and off;
FIG. 5 is a block diagram showing the relevant portions of the power supply;
FIG. 6A is an electrical schematic diagram of the power management circuitry of the present invention, showing the various interfaces to other Figures;
FIG. 6B is an electrical schematic diagram of the connection of the power management circuitry to the internal modem;
FIG. 6C is a waveform diagram showing the various signals within the reset circuit for the power management circuitry;
FIG. 6D is an electrical schematic diagram of a second embodiment of the power supply fault detection and correction circuit;
FIG. 7 is a state diagram of one of the switch states maintained by the power management processor of the present invention;
FIG. 8 is a flow chart showing generally the powerup routine of the present invention;
FIG. 9A is a flow chart showing the details of the Supervisor Routine, which is called by the APM device driver in the operating system approximately every second;
FIG. 9B is a flow chart showing the details of the APM Working On Last Request Routine;
FIG. 9C is a flow chart showing the details of the APM Reject Last Request Routine;
FIG. 10 is a flow chart showing the details of the Suspend Routine of the present invention;
FIG. 11 is a flow chart showing the details of the Boot-Up Routine of the present invention;
FIG. 12 is a flow chart showing the details of the Resume Routine of the present invention;
FIG. 13 is a flow chart showing the details of the Save CPU State Routine of the present invention;
FIG. 14 is a flow chart showing the details of the Restore CPU State Routine of the present invention;
FIG. 15 is a flow chart showing the details of the Save 8959 State Routine of the present invention;
FIG. 16 is a flow chart showing the details of the Dynamic Save File Allocation Routine of the present invention;
FIG. 17 is a flow chart showing the details of the Exit Standby Routine of the present invention;
FIG. 18 is a flow chart showing the details of the Enter Standby Routine of the present invention; and
FIG. 19 is a flow chart showing the details of the Power management Processor Routines of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
While the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which a preferred embodiment of the present invention is shown, it is to be understood at the outset of the description which follows that persons of skill in the appropriate arts may modify the invention here described while still achieving the favorable results of this invention. Accordingly, the description which follows is to be understood as being a broad, teaching disclosure directed to persons of skill in the appropriate arts, and not as limiting upon the present invention. The present invention deals with the complete design of a computer system, including, but not limited to computer architecture design, digital design, BIOS design, protected mode 80486 code design, application code design, operating system code design, and Advanced Power Management advanced programming interface usage. This application is written for those very familiar with all aspects of computer system design.
The checkpointing process is very similar to the save that occurs when transitioning from the normal operating state to the suspend state with the following exceptions. First, power is not turned off after all state information is saved to non-volatile storage. Instead, control is immediately returned to the application or the OS as in the case of a resume.
The second difference between a Checkpoint and a suspend is that state save is not coordinated with the OS through Advance Power Management (APM) as it is as the system changes from the normal operating state to the suspend state. Depending on the level of support that the OS's APM driver provides, suspend notification could result in network disconnections or other destructive behavior. Instead, the state is saved completely "behind the back" of the OS.
The third difference between a Checkpoint and a suspend is that any hardware interrupt activity immediately aborts the checkpoint. Hardware interrupts cannot be serviced while the state is being saved because the CPU must be put into a known mode for the save to occur. The interrupt service routines and vectors that are called responsive to a hardware interrupt in all likelihood will not be compatible with the processor mode used to save system state. For this reason, all interrupts are masked during the save. The save is aborted if an interrupt occurs and it is allowed to be serviced once the CPU state has been restored. Minimizing interrupt latency contributes toward the transparency of the checkpointing operation. In the alternative, hardware interrupts can be ignored by the system while the Checkpoint is being taken.
The final difference between a Checkpoint and a suspend is that the Checkpoint save state is completely non-destructive. On the other hand, in the case of a suspend, the state save is somewhat destructive. For example, if interrupts are pending during a suspend, those interrupts will be lost as the system resumes. Also if a modem is on-line, the connection must be broken and the modem taken off line in order to save the state of the modem. This is acceptable in the case of a suspend because the connection will be lost anyway once power is removed. For a Checkpoint however, destroying any state information is unacceptable. Consequently, it is not possible to save certain information during a Checkpoint. However, the state that can be saved will usually be sufficient to allow the user to recover data in case of a power outage.
The state that is saved during the checkpoint operation contains information that is stored in volatile memory--RAM, device registers, etc. But the entire state of the computer actually consists of volatile and non-volatile state information. Therefore the "state" of the hard disk must also be considered as part of the overall system state. During a suspend, the volatile state is saved to a special area on the hard disk and power is turned off without ever returning execution control to the operating system or the application programs. Thus, state of the file system on the hard disk cannot be changed while in the suspend state. Therefore the computer system will be in exactly the same state when the volatile memory is restored during the resume and the overall state of the system will be exactly the same as before the suspend (except the Suspend File area will probably be different, which has no effect on the rest of the system state).
However, after a Checkpoint, the volatile state information has been saved, but control is returned to the operating system and the application programs. If the state of the hard disk file system is modified by either the OS or the application programs, then the checkpoint must be invalidated to avoid the possibility of creating a mismatch that could result in massive data loss on the hard drive, e.g., resuming from the Checkpoint data after defragmenting the hard drive. This may seem a little extreme to invalidate the checkpoint immediately on any modification to the hard disk; there are many cases where resuming with the checkpoint data along with the modified hard disk image that would not cause any problems. But the few examples where problems do arise could be catastrophic. For example, many OS's use a virtual memory technique where pages of virtual memory are swapped in and out from hard disk on demand. Therefore the state of RAM must always be synchronized with the virtual memory data area on the disk.
Checkpoints on entry to standby are performed simply for convenience. By definition, the system will be in a quiescent state on entry to standby. This not only improves the likelihood of getting a valid and transparent checkpoint but also poses little or no inconvenience to the user. In the alternative, the checkpoint can be driven from a dedicated timer that can have a fixed interval or automatically reloaded on certain activity.
In addition, as mentioned above, the checkpoint is invalidated as the standby state is exited or on any access to the hard disk. In the alternative, the checkpoint can be invalidated on disk writes to an area of disk corresponding to the virtual memory data area on the disk, which can be accomplished by adding additional hardware detection circuitry and software drivers. Also, a modification to the APM drivers whereby the OS notifies the power management firmware of critical hard disk updates would simplify the invalidation routines.
Referring now more particularly to the accompanying drawings, a microcomputer system embodying the present invention is there shown and generally indicated at 10 (FIG. 1). As mentioned hereinabove, the computer 10 may have an associated display monitor 11, keyboard 12, mouse 13, and printer or plotter 14. The computer 10 has a cover 15 formed by a decorative outer member 16 (FIG. 2) and an inner shield member 18 which cooperate with a chassis 19 in defining an enclosed, shielded volume for receiving electrically powered data processing and storage components for processing and storing digital data. At least certain of these components are mounted on a multilayer planar 20 or motherboard which is mounted on the chassis 19 and provides a means for electrically interconnecting the components of the computer 10 including those identified above and such other associated elements as floppy disk drives, various forms of direct access storage devices, accessory adapter cards or boards, and the like. As pointed out more fully hereinafter, provisions are made in the planar 20 for the passage of input/output signals to and from the operating components of the microcomputer.
The computer system has a power supply 17, a power button 21, also hereinafter the switch 21, and a power/feedback LED 23. Unlike in the usual power switch in a typical system, the power button 21 does not switch AC line power to and from the power supply 17, as will be explained below. The chassis 19 has a base indicated at 22, a front panel indicated at 24, and a rear panel indicated at 25 (FIG. 2). The front panel 24 defines at least one open bay (and in the form illustrated, four bays) for receiving a data storage device such as a disk drive for magnetic or optical disks, a tape backup drive, or the like. In the illustrated form, a pair of upper bays 26, 28 and a pair of lower bays 29, 30 are provided. One of the upper bays 26 is adapted to receive peripheral drives of a first size (such as those known as 3.5 inch drives) while the other 28 is adapted to receive drives of a selected one of two sizes (such as 3.5 and 5.25 inch) and the lower bays are adapted to receive devices of only one size (3.5 inch). One floppy disk drive is indicated at 27 in FIG. 1, and is a removable medium direct access storage device capable of receiving a diskette inserted thereinto and using the diskette to receive, store and deliver data as is generally known. One hard disk drive is indicated at 31 and is a fixed medium direct access storage device capable of storing and delivering data as is generally known.
Prior to relating the above structure to the present invention, a summary of the operation in general of the personal computer system 10 may merit review. Referring to FIGS. 3A and 3B, there is shown a block diagram of a personal computer system illustrating the various components of the computer system such as the system 10 in accordance with the present invention, including components mounted on the planar 20 and the connection of the planar to the I/O slots and other hardware of the personal computer system. Connected to the planar is the system processor 40, also herein CPU 40, comprised of a microprocessor, which is connected by a high speed CPU local bus 42 through a memory control unit 46, which is further connected to a volatile random access memory (RAM) 53. The memory control unit 46 is comprised of a memory controller 48, an address multiplexer 50, and a data buffer 52. The memory control unit 46 is further connected to a random access memory 53 as represented by the four RAM modules 54. The memory controller 48 includes the logic for mapping addresses to and from the microprocessor 40 to particular areas of RAM 53. This logic is used to reclaim RAM previously occupied by BIOS. Further generated by memory controller 48 is a ROM select signal (ROMSEL), that is used to enable or disable ROM 88. While any appropriate microprocessor can be used for system processor 40, one suitable microprocessor is the 80486 which is sold by INTEL. The Intel 80486 has an internal cache, therefore, any CPU 40 that is an Intel 80486 will have a CPU cache 41.
While the present invention is described hereinafter with particular reference to the system block diagram of FIGS. 3A and 3B, it is to be understood at the outset of the description which follows that it is contemplated that the apparatus and methods in accordance with the present invention may be used with other hardware configurations of the planar board. For example, the system processor 40 could be an Intel 80286 or 80386 microprocessor. As used herein, reference to an 80286 or 80386 or
80486 generally intends such a microprocessor as obtained from Intel. However, in recent times other manufacturers have developed microprocessors which are capable of executing the instruction set of the Intel X86 architecture, and usage of the terms stated. is intended to encompass any microprocessor capable of executing that instruction set. As known to persons skilled in the applicable arts, early personal computers typically used the then popular Intel 8088 or 8086 microprocessor as the system processor. These processors have the ability to address one megabyte of memory. More recently, personal computers typically use the high speed Intel 80286, 80386, and 80486 microprocessors which can operate in a virtual or real mode to emulate the slower speed 8086 microprocessor or a protected mode which extends the addressing range from 1 megabyte to 4 Gigabytes for some models. In essence, the real mode feature of the 80286, 80386, and 80486 processors provide hardware compatibility with software written for the 8086 and 8088 microprocessors. Processors in the Intel family described are frequently identified by a three digit reference to only the last three digits of the full type designator, as "486".
Returning now to FIGS. 3A and 3B, the CPU local bus 42 (comprising data, address and control components, not shown) provides for the connection of the microprocessor 40, a math coprocessor 44 (if not internal to the CPU 40), a video controller
56, a system cache memory 60, and a cache controller 62. The video controller 56 has associated with it a monitor (or video display terminal) 11 and a video memory 58. Also coupled on the CPU local bus 42 is a buffer 64. The buffer 64 is itself connected to a slower speed (compared to the CPU local bus 42) system bus 66, also comprising address, data and control components. The system bus 66 extends between the buffer 64 and a further buffer 68. The system bus 66 is further connected to a bus control and timing unit 70 and a DMAunit 71. The DMA unit 71 is comprised of a central arbiter 82 and a DMA controller 72. An additional buffer 74 provides an interface between the system bus 66 and an optional feature bus such as the Industry Standard Architecture (ISA) bus 76. Connected to the bus 76 are a plurality of I/O slots 78 for receiving ISA adapter cards (not shown). ISA adapter cards are pluggably connected to the I/O slots 78 and may provide additional I/O devices or memory for the system 10.
An arbitration control bus 80 couples the DMA controller 72 and central arbiter 82 to the I/O slots 78, a diskette adapter 84, and an Integrated Drive Electronics (IDE) fixed disk controller 86.
While the microcomputer system 10 is shown with a basic 4 megabyte RAM module 53, it is understood that additional memory can be interconnected as represented in FIGS. 3A and 3B by the addition of optional higher-density memory modules 54. For purposes of illustration only, the present invention is described with reference to the basic four megabyte memory module.
A latch buffer 68 is coupled between the system bus 66 and a planar I/O bus 90. The planar I/O bus 90 includes address, data, and control components respectively. Coupled along the planar I/O bus 90 are a variety of I/O adapters and other components such as the diskette adapter 84, the IDE disk adapter 86, an interrupt controller 92, an RS-232 adapter 94, nonvolatile CMOS RAM 96, also herein referred to as NVRAM, a CMOS real-time clock (RTC) 98, a parallel adapter 100, a plurality of timers 102, the read only memory (ROM) 88, the 8042 104, and the power management circuitry 106. The 8042, shown at 104, is the slave microprocessor that interfaces with the keyboard 12 and the mouse 13. The power management circuitry 106 is in circuit communication with the power supply 17, the power switch 21, the power/feedback LED 23, and an internal modem 900 and/or an external modem 902. The external modem is typically connected to a transformer 904, which is connected to a typical wall outlet, as is known to those skilled in the art. The modems 900, 902 are connected to a typical telephone outlet. The power management circuitry 106 is shown in FIG. 6A and 6B and is more fully described in the text accompanying FIGS. 6A, 6B, 6C, and 7. The read only memory 88 includes the BIOS that is used to interface between the I/O devices and the operating system of the microprocessor 40. BIOS stored in ROM 88 can be copied into RAM 53 to decrease the execution time of BIOS. ROM 88 is further responsive (via ROMSEL signal) to memory controller 48. If ROM 88 is enabled by memory controller 48, BIOS is executed out of ROM. If ROM 88 is disabled by memory controller 48, ROM is not responsive to address inquiries from the microprocessor 40
(i.e. BIOS is executed out of RAM).
The real-time clock 98 is used for time of day calculations and the NVRAM 96 is used to store system configuration data. That is, the NVRAM 96 will contain values which describe the present configuration of the system. For example, NVRAM 96
contains information describing the capacity of a fixed disk or diskette, the type of display, the amount of memory, time, date, etc. Furthermore, these data are stored in NVRAM whenever a special configuration program, such as SET Configuration, is executed. The purpose of the SET Configuration program is to store values characterizing the configuration of the system to NVRAM.
Nearly all of the above devices comprise volatile registers. To prevent the unnecessary cluttering of the drawings, the registers of a particular device will be referenced to that device. For example, the CPU registers will be referred to as the CPU 40 registers and the video controller registers will be referenced as the video controller 56 registers.
As mentioned hereinabove, the computer has a cover indicated generally at 15 which cooperates with the chassis 19 in forming an enclosed, shielded volume for containing the above identified components of the microcomputer. The cover 15
preferably is formed with an outer decorative cover member 16 which is a unitary molded component made of a moldable synthetic material and a metallic thin sheet liner 18 formed to conform to the configuration of the decorative cover member. However, the cover can be made in other known ways and the utility of this invention is not limited to enclosures of the type described.
States of Operation
Referring now to FIG. 4, a state diagram of the computer system of the present invention is shown. The computer system 10 of the present invention has four states: a normal operating state 150, a standby state 152, a suspend state 154, and an off state 156. The transitions between the states shown in FIG. 4 are meant to be descriptive of the preferred embodiment, but not limiting. Consequently, additional events may alternatively be used to cause state transitions.
The normal operating state 150 of the computer system 10 of the present invention is virtually identical to the normal operating state of any typical desktop computer. Users may use applications and basically treat the computer as any other. One difference, transparent to the user, is the presence of a power management driver in the operating system (the "APM OS driver"), which runs in the background, and various APM BIOS routines. The APM BIOS routines are discussed in the text below and include the Suspend Routine, the Resume Routine, the Boot-Up Routine, the Supervisor Routine, the Save CPU State Routine, and the Restore CPU State Routine. One APM BIOS routine not shown on any of the Figures is the APM BIOS Routing Routine. The APM BIOS Routing Routine essentially accepts commands from the APM OS driver, and calls the appropriate APM BIOS routine. For example, when the APM OS driver issues the Suspend Command, the APM BIOS Routing Routine calls the Suspend Routine. As another example, whenever the APM OS driver issues the Get Event command, the APM BIOS Routing Routine calls the Supervisor Routine. These routines are located in BIOS and are shadowed when the BIOS is shadowed. The power management driver in the OS and the APM BIOS routines control the computer's transition between the four states. A reference to the word "APM" by itself generally is a reference to the APM OS driver, although the context may dictate otherwise.
The second state, the standby state 152, uses less electrical power than the normal operating state 150, yet leaves any applications executing as they would otherwise execute. In general power is saved in the standby state 152 by the code placing devices into respective low power modes. In the preferred embodiment, electrical power is conserved in the standby state 152 by ceasing the revolutions of the fixed disk (not shown) within the fixed disk storage device 31, by ceasing generating the video signal, and by putting the CPU 40 in a low power mode, as will be more fully explained below. However, this is not intended to be limiting and other methods may be used to reduce power consumption, such as slowing or stopping the CPU clock.
In the preferred embodiment, electrical power is conserved in three separate ways. First, in the normal operating state 150, the fixed disk within the fixed disk storage device 31 is constantly spinning at, e.g., 3600, 4500, or 5400 revolutions per minute (RPM). In the standby state 152, the IDE disk controller 86 is given the command to cause the fixed disk storage device 31 to enter a lowpower mode (the fixed disk inside the fixed disk storage device 31 ceases spinning), thereby conserving the power the motor (not shown) inside the fixed disk storage device 31 typically consumes while spinning the fixed disk.
Second, in the normal operating state 150, the video controller 56 of the computer system constantly generates a video signal (HSYNC, VSYNC, R, G, B, etc. as is well known in the art) corresponding to the image seen on the video display terminal
11. In the standby state 152 the video controller 56 ceases generating the video signal, thereby conserving the electrical power normally consumed by the video controller 56; HSYNC, VSYNC, R, G, and B are all driven to approximately 0.00 VDC. Using a VESA (Video Electronics Standards Association) compliant monitor allows further power savings because VESA compliant monitors turn themselves off when HSYNC and VSYNC are at approximately 0.00 VDC.
Third, in the normal operating state 150, the CPU 40 constantly executes commands, thereby consuming electrical power. In the standby state 152 the BIOS issues a HALT instruction in response to the APM CPU Idle Call. Executing a HALT instruction significantly reduces CPU power consumption until the next hardware interrupt occurs. When truly idle, the CPU can remain halted more than 90% of the time.
Note that some systems have "screen-savers," which cause the screen 11 to become dark to prevent phosphor burn-in of the front surface of the video display terminal. In most of such systems, the video controller 56 is still generating a video signal; it is merely generating a video signal corresponding to a dark screen or a dynamic display. Thus, a computer system executing a screen-saver still consumes the electrical power necessary to generate the video signal.
The third state is the suspend state 154. In the suspend state 154, computer system consumes an extremely small amount of electrical power. The suspended computer consumes less than 100 milliwatts of electrical power in the preferred embodiment. The only power consumed is approximately 5 watts consumed due to inefficiencies in the power supply 17 and a small amount of power used by the power management circuitry 106.
This small use of electrical power is accomplished by saving the state of the computer system to the fixed disk storage device (the hard drive) 31 prior to turning the power supply "off." To enter the suspend state 154, the CPU 40 interrupts any applications and transfers program execution control of the CPU to the power management driver. The power management driver ascertains the state of the computer system 10 and writes the entire state of the computer system to the fixed disk storage device 31. The state of the CPU 40 registers, the CPU cache 41, the system RAM 53, the system cache 60, the video controller 56 registers, the video memory 56, and the remaining volatile registers are all written to the fixed disk drive 31. The entire state of the system 10 is saved in such a way that it can be restored without significant usability penalties. That is, the user need not wait for the system to load the operating system, and load the graphical user interface, and application programs as it normally would.
The computer then writes data to the non-volatile CMOS memory 96 indicating that the system was suspended. Lastly, the CPU 40 commands the microcontroller U2 to cause the power supply 17 to stop providing regulated power to the system through the .+-.5 VDC and .+-.12 VDC lines. The computer system 10 is now powered down with the entire state of the computer safely saved to the fixed disk storage device 31.
The word "state" is used throughout this document in two similar, but possibly confusing ways. Devices can be "in" a particular state. The four system states--normal 150, standby 152, suspend 154, and off 156--refer to the general state of the computer system 10 of the present invention. These "states" describe the computer system 10 in a general way. For example, while in the normal operating state 150, the CPU 40 is still executing code and changing a plurality of registers within the system 10. Likewise, similar activity occurs while in the standby state 152. Thus, the memory and register configuration of the computer system 10 is dynamic while the system 10 is in the normal operating state 150 and the standby state 152.
Other devices can also be "in" certain states. The power management circuitry 106 preferably uses a second processor as a power management processor, such as a microcontroller U2 shown in FIG. 6A, to implement the various power management features. Many such processors are suitable; in this particular embodiment, the power management processor is a preprogrammed 83C750 microcontroller. The variables and pins of the microcontroller U2 can be in several states, as will be explained in the text accompanying FIG. 6A.
Contrast the above with the "state of" a device, for example, the "state of the computer system 10" or the "state of the CPU 40." The "state of" a device refers to the condition of that device at a particular computer cycle. All memory locations and registers will have particular binary values. The "state of" a device is a static binary snapshot of the contents of that device.
The "state of" the computer system 10 refers to operational equivalents and not necessarily exact copies. For example, a computer system in a state A may have certain memory in either CPU cache 41 or system cache 60. It is possible to "flush" the contents of either cache back to the system RAM 53, putting the computer system in a state B. Purely speaking, the state of the computer system in state A is different from the state of the computer system in state B, because the contents of cache and system RAM are different. However, from a software operational perspective, state A and state B are the same, because, aside from a slight decrease in system speed (caused by the program not having the benefit of executing out of cache), the executing programs are not affected. That is, a computer in state A and a computer in state B are software operationally equivalent, even though the computer whose cache was flushed will experience a slight decrease in performance until the cache areas are reloaded with helpful code.
The word "power" is also used in two similar, but possibly confusing ways. "Power" most often refers to electrical power. However, "power" also refers to computational power occasionally. The context should make the intended usage obvious.
A "circuit" is generally a reference to a physical electronic device or a plurality of devices electrically interconnected. However, the term "circuit" also is intended to encompass CPU code equivalents of physical electronic devices. For example, on the one hand, a two-input NAND gate can be implemented via a 74LS00 or, equivalently, in a programmable device. These two devices are physical electronic devices. On the other hand a NAND gate can also be implemented by having the CPU 40
read two inputs from two CPU-readable input ports, generate the NAND result using a CPU command, and output the result via a CPU-writable output port. These CPU-interfacable ports can be simple, such as decoded latches, or their programmable device equivalent, or complex, such as PIAs, which are well-known in the art. The term "circuit" is meant to be broad enough to include all three examples of NAND gate implementations, above. In some cases, "circuit" may refer to merely an electrical pathway. Types of electrical pathways include a wire, a trace or via on a printed circuit board, etc., or any combination of types of electrical pathways that form a single electrically connected pathway.
A "signal" may refer to a single electrical waveform or a plurality of waveforms. For example, the video controller generates a video signal. The video signal is actually a plurality of signals on a plurality of electrical conductors: HSYNC, VSYNC, R, G, B, etc. as is well known in the art.
Returning now to FIG. 4, the fourth and final state is the off state 156. The off state 156 is virtually identical to any typical computer system that has been turned off in the ordinary sense. In this state, the primary/regulation unit 172 of the power supply 17 ceases providing regulated power to the computer system 10, (with the exception of a small amount of regulated power through AUX5, as will be more fully explained in the text accompanying FIG. 5) but the state of the computer system
10 has not been saved to the fixed disk 31. The suspend state 154 and the off state 156 are similar in that the power supply 17 no longer generates regulated power. They differ in that in the off state 156, the state of the computer system 10 is not saved to the hard drive 31, as it is in the suspend state 154. Moreover, when leaving the off state 156, the computer 10 "boots" as if it is being turned on. That is, any executing code must be started either by the user or automatically by a means such as the AUTOEXEC.BAT file. However, when leaving the suspend state 154, the computer 10 resumes executing where it was when it was interrupted.
FIG. 4 also shows a general overview of the events that cause transitions between the four states. These events will be further explained in the text accompanying FIGS. 6 through 8; however, a cursory explanation may be helpful. The power button 21, two timers (the inactivity standby timer and the inactivity suspend timer, see FIG. 9 and accompanying text), a minutes to wake timer, and a Suspend Enable Flag (see FIGS. 6A and 7 and accompanying text) all affect which state the computer enters. In general, the two timers can be either hardware or CPU code timers, executing on the CPU as a program. In the preferred embodiment, they are both CPU code timers, executing from the BIOS data segments. However, the two timers could conceivably be hardware timers, which would be a better solution, in that it would reduce the overhead of the system. The timers are more fully explained in the text accompanying FIG. 9. Both timers are active when the computer 10 is in either the normal operating state 150 or the standby state 152. The timers are in communication with other routines such that the expiration of either timer causes a transition as outlined below. Either or both timers can be configured to expire after a certain period of time, depending on the particular needs of the user. In the preferred embodiment, the inactivity standby timer and the inactivity suspend timer can be set to expire after 10 to 90 minutes. Either or both timers can be stopped, that is, configured to never expire. "Stopping" the timers can take the form of actually ceasing the incremental counting action of the timers or merely ignoring their expiration. In the preferred embodiment, setting a zero value in the timer expiration value causes the timer expiration not to be tested. The user of a networked computer may, for example, not want the computer to enter the suspend state 154 because doing so may cause the LAN to fail with respect to that computer.
In theory, the timers can count up or count down and can be reset to a fixed predetermined state and expected to count to another fixed predetermined state when the timer is started (or restarted) or the present value can be used and a difference or sum calculated as the endpoint expiration trigger. In the preferred embodiment, when the timers are reset, the present value of the minutes variable from the real-time clock 98 is stored. The timers are checked for expiration by subtracting the current minutes value from the saved minutes value and comparing the difference to the values selected by the user.
Both timers are affected by certain system activity. For example, in the preferred embodiment, user activity in the form of keyboard 12 keys being pressed, the mouse 13 being moved, mouse 13 buttons being pressed, or hard drive 31 activity causes each timer to be restarted, as more fully explained in the text accompanying FIG. 9; therefore, while a user is pressing keyboard 12 keys or using the mouse 13, or while an application is accessing the hard drive 31, neither timer will expire. In addition other system events might be used to reset the timers. Any of the hardware interrupts might alternatively be monitored for activity. Thus, it might be desirable to have printing (IRQ5 or IRQ7) or a COMMport access (IRQ2 or IRQ3) prevent the system from entering the suspend state 154.
The Suspend Enable Flag is a CPU-manipulable and readable latch within the microcontroller U2, which will be more fully explained in the text accompanying FIG. 6A. In short, putting the microcontroller U2 in one mode causes a press of the switch
21 to place the system 10 into the off state 156 and putting the microcontroller U2 into another mode causes a press of the switch 21 to place the system 10 into the suspend state 154. If the computer system 10 is in the normal operating state 150 and the power button 21 is pressed while the Suspend Enable Flag written to the microcontroller U2 is CLEARed, then the computer system 10 enters the off state 156, as shown at 158. If the computer system 10 is in the off state 156 and the power button 21
is pressed, then the computer system enters the normal operating state 150, as shown at 160. In addition, several "external events," which are explained more fully below, can cause the system to transition from the off state 156 to the normal operating state 150.
If the computer system 10 is in the normal operating state 150, one event can cause the computer to enter the standby state 152: if the inactivity standby timer expires, the computer system 10 will change to the standby state 152, as shown at
162. In the alternative, the system can provide a means, such as a dialog box, a switch, or other input device, for the user to force the system into the standby state immediately. While in the standby state 152, any system or user activity of the kind previously described, including the user pressing the power button 21, will cause the computer 10 to leave the standby state 152 and re-enter the normal operating state 150, as shown at 164.
Pressing the power button 21 causes the system to change from the standby state 152 to the normal operating state 150 to prevent user confusion. As mentioned above, while in the standby state, the monitor 11 is blanked and the power/feedback LED
23 is either on or blinking, depending on how the flags in the microcontroller U2 are configured. A user approaching the system might notice that the monitor 11 is blank and, thinking that the system is in the suspend state 154 or the off state 156, press the power button 21 in an attempt to cause the system to enter the normal operating state 150. If a press of the power button 21 causes the system to enter either the suspend state 154 or the off state 156, then the user above will have just either turned off or suspended the computer, which is directly contrary to the user's intention. Therefore, when in the standby state 152, a press of the power button 21 causes the system to change from the standby state to the normal operating state. Even if idle, the CPU 40 will soon test whether the switch was pressed. Hardware interrupts remove the CPU 40 from the idle state approximately 20 times per second; thereafter during the next APM Get Event, the microcontroller U2 is queried to determine whether the switch 21 was pressed.
If the computer 10 is in the normal operating state 150, two events can cause it to enter the suspend state 154. First, if the inactivity suspend timer expires, the computer system 10 will change to the suspend state 154, as shown at 166. Second, the user can cause the computer 10 to enter the suspend state 154 immediately by pressing the power button 21 while the Suspend Enable Flag written to the microcontroller U2 is SET, also shown at 166. In the alternative, additionally, the APM driver can issue a suspend request via a "Set Power State: Suspend" command, which causes the APM BIOS driver to call the Suspend Routine. While in the suspend state 154, the user changes to the normal operating state 150 by pressing the power button
21, as shown at 168.
In addition, several external events can be used to change the system 10 from the suspend state 154 to the normal operating state 150, at 168, or from the off state 156 to the normal operating state 150, at 160. For example, a telephone ring detect circuit in the microcontroller U2 in the circuitry of FIG. 6A is configured to cause the system 10 to leave the off state 156 or the suspend state 154 and enter the normal operating state 150 when an attached telephone line rings. Such a feature is useful for a system receiving telefax data or digital data. The system enters the normal operating state responsive to the telephone ring, performs the preset functions, such as accepting an incoming facsimile transmission, uploading or downloading files, allowing remote access to the system, etc., and enters the suspend mode again responsive to the expiration of the Inactivity Suspend Timer, only consuming power while the system is in the normal operating state.
Likewise the microcontroller U2 implements a minutes to wake alarm counter, which allows an alarm-type event to cause the system 10 to leave the suspend state 154 or the off state 156 and enter the normal operating state 150. Such a system is useful in sending telefax or digital data at a certain time of day to take advantage of lower telephone usage rates, and performing system maintenance functions, such as backing up the system hard drive 31 with a tape backup system. In the latter case, the minutes to wake alarm is set to turn the machine on a fixed period of time before the scheduler causes the tape backup program to be executed. In the alternative, the APM BIOS scheduler can be used to cause the execution of the tape backup program.
Lastly, if the computer system 10 is in the standby state 152 and the inactivity suspend timer expires, then the computer 10 changes to the suspend state 154 as shown at 170. The computer system 10 cannot change back from the suspend state 154
to the standby state 152, but may only transition to the normal operating state 150 as described in the text accompanying transition 168.
Obviously, the computer system 10 cannot instantaneously change states. In each transition from one of the four states, a certain period of time will be required to make the necessary system changes. The details of each transition period will be explained in the text accompanying FIGS. 6 through 15.
System Hardware
Before discussing the details of the code executing on the CPU 40, it may be helpful first to discuss the hardware required to achieve the four states. A block diagram of the power supply 17 is shown in FIG. 5. The power supply 17 has two units: a control unit 174 and a primary/regulation unit 172. The power supply 17 has several inputs: Line-In, which accepts either 115 VAC or 220 VAC from a typical wall outlet, and ON, which controls the regulation activity of the power supply 17. The power supply 17 has several outputs: AC Line-Out, .+-.5 VDC, .+-.12 VDC, AUX5, GND, and POWERGOOD. The AC Line-Out is 115 VAC that is typically passed to the electrical power input (not shown) of the video display terminal 11. The control unit 174
accepts the ON input and generates the POWERGOOD output. The primary/regulation unit 172 selectively regulates the 115 VAC from the Line-In input down to .+-.5 VDC, .+-.12 VDC. Whether the primary/regulation unit 172 regulates power at the .+-.5 VDC and .+-.12 VDC lines depends on the value of ON, as interfaced by the control unit 174. In the preferred embodiment, the control unit 174 should provide isolation for the circuitry generating the ON signal using, for example, an appropriate optoisolator.
The Line-In input and the AC Line-Out, .+-.5 VDC, .+-.12 VDC, GND, and POWERGOOD outputs are well known in the art. When the power supply 17 is "off," that is not providing, regulated voltages from the Line-In, the POWERGOOD signal is a logical ZERO. When the power supply 17 is "on," the power supply 17 generates the .+-.5 VDC and .+-.12 VDC regulated voltages from the 115 VAC Line-In. These four regulated voltages and their associated GND are the "system power" as is commonly known in the art. When the regulated voltages attain levels within acceptable tolerances, the POWERGOOD signal changes to a logical ONE. Whenever either the +5 or +12 Volt lines fall out of tolerance, the POWERGOOD signal becomes a logical ZERO, thereby indicating this condition.
The AUX5 output provides an auxiliary +5 VDC to the planar. When the power supply 17 is plugged into a typical wall outlet supplying a nominal 115 VAC, the primary/regulation unit 172 provides regulated +5 VDC at AUX5, whether the power supply is "on" or "off." Thus, while receiving AC power, the power supply 17 is always providing a nominal +5 VDC at AUX5. The AUX5 output differs from the +5 output in that the primary/regulation unit 172 only generates regulated +5 VDC through the +5 output while the power supply 17 is "on." The AUX5 output further differs from the +5 output in that in the preferred embodiment, the primary/regulation unit 172 supplies several amps of current at +5 VDC through the +5 output, while the primary/regulation unit
172 supplies less than an amp at +5 VDC though the AUX5 output.
Typical prior power supplies use a high-amperage double-throw switch to connect and disconnect the Line-In input to and from the regulation section of the power supply. The power supply 17 in the present invention does not use a high-amperage double-throw switch. Rather, the switch 21 controls circuitry that generates the ON signal. In the preferred embodiment, the switch 21 is a momentary single pole, single throw pushbutton switch; however, those skilled in the art could adapt the circuitry of FIG. 6A to make use of other types of switches such as a single-pole, double throw switch. The AC Line-In is always connected to the primary/regulation unit 172 from the wall outlet. When ON is a logical ONE (approximately AUX5, nominally +5 VDC), the primary/regulation unit 172 does not regulate the 115 VAC Line-In to .+-.5 VDC or .+-.12 VDC through the .+-.5 or .+-.12 outputs. The primary/regulation unit 172 merely provides a low-amperage nominal +5 VDC at the AUX5 output. On the other hand, when ON is a logical ZERO (approximately GND), the primary/regulation unit 172 does regulate the 115 VAC Line-In to .+-.5 VDC and .+-.12 VDC through the four .+-.5 and .+-.12 outputs, respectively. Thus, when ON is a ONE, the power supply 17
is "off" and when ON is a ZERO, the power supply 17 is "on."
If specified, power supplies having an AUX5 output and an ON input, like the power supply 17 described above, can be obtained from suppliers of more conventional power supplies.
Referring now to FIG. 6A, a schematic drawing of the electronic circuitry of the computer system 10 of the present invention is shown. The circuitry in FIG. 6A is responsible for interfacing between the switch 21, the power/feedback LED 23, the power supply 17, the video display terminal 11, and code executing on the CPU 40.
The circuitry comprises four (4) integrated circuits--U1, a first preprogrammed PAL16L8; U2, a preprogrammed 83C750 microcontroller; U3, a 74LS05, which is well known in the art; and U4, a second preprogrammed PAL16L8 (not shown)--and the various discrete components in circuit communication as shown in FIG. 6A. In general, the PALs U1 and U4 (not shown) interface between the planar I/O bus 90 of FIGS. 3A and 3B and the microcontroller U2, which interfaces to the remaining circuitry of FIG. 6A, which interfaces to the switch 21, the power supply 17, the video display terminal 11, and a programmable clock synthesizer 906. The clock synthesizer 906 can be one of many such devices known to those of ordinary skill in the art. One such part is the CH9055A, which is manufactured by Chrontel, and widely available from numerous sources.
The circuitry of FIG. 6A further comprises the switch 21, a 16 MHz crystal Y1, eighteen resistors R1-R18, eight capacitors C1-C8, three N-type MOSFETs Q1-Q3, which are standard low-current NMOS FETs suitable for acting as a logic switch in the preferred embodiment, and six (6) 1N4148 small signal diodes CR1-CR6, all configured and connected as shown in FIG. 6A. The resistors R1-R18 are 1/4 Watt resistors and are of values shown in FIG. 6A, .+-.5%. The capacitor C1 is a 10 .mu.F (.+-.10%) electrolytic capacitor. The capacitors C2 & C3 are 22 pF (.+-.10%) tantalum capacitors. The capacitors C4-C8 are 0.1 .mu.F (.+-.10%) ceramic capacitors. Finally, the capacitor C9 is a 1000 pF (.+-.10%) ceramic capacitor.
The crystal Y1 and the capacitors C2 and C3 generate signals used by the microcontroller U2 to control the timing of operations, as is known in the art. The diodes CR1 and CR3 and the resistor R14 isolate the AUX5 signal from the VBAT signal, while at the same time allowing the AUX5 signal to supplement the VBAT signal in that while the power supply 17 generates the AUX5 signal, the battery 171 is not drained. Rather, the AUX5 signal is stepped down through the diodes CR1 and CR3 to supply the proper voltage to the devices connected to VBAT. In the alternative, the VBAT line is isolated from the AUX5 line.
The second PAL U4 (not shown) is connected to address lines SA(1) through SA(15) and the AEN (address enable) line. SA(1) through SA(15) and AEN are part of the planar I/O bus 90 shown in FIGS. 3A and 3B. The second PAL U4 is programmed to be merely an address decoder, presenting an active low signal DCD# when a predetermined address is presented on address lines SA(1) through SA(15) and the AEN (address enable) line is active. In this particular embodiment, the second PAL U4 is preprogrammed to decode two consecutive 8-bit I/O ports at addresses 0ECH and 0EDH. In the alternative, the DCD# signal can be generated by another electronic device, such as a memory controller or an ISA controller chipset, as is known to those skilled in the art.
The first PAL U1 is programmed to provide several functions: (i) a read/write interface between the CPU and the microcontroller U2 to allow commands and data to be transferred between the CPU 40 and the microcontroller U2, (ii) a logical ORing of the mouse interrupt INT12 and the keyboard interrupt INT1; and (iii) a reset output to reset the microcontroller U2 responsive to commands from the CPU 40.
The first PAL U1 makes use of two consecutive I/O ports, also herein referred to as the "power management ports." The first PAL U1 has eight (8) inputs from the planar I/O bus 90: SD(4), SD(0), SA(0), IOW#, IOR#, RST.sub.-- DRV, IRQ1, and IRQ12. The first PAL U1 is reset to a known initial condition by the active high signal RST.sub.-- DRV input at pin 7 (I6), which is generated by the memory controller 46, as is well known to those skilled in the art.
A reset line RST751 of the microcontroller U2 is at pin 9. A reset subcircuit 920 is responsible for generating the RST751 signal and comprises the four resistors R4, R16, R17, and R18, the two capacitors C1 and C8, and the two MOSFETS Q2 and Q3, in circuit communication with the first PAL U1 and the microcontroller U2 as shown in FIG. 6A. The reset subcircuit 920 interfaces the reset output signal RESET from the first PAL U1 to the reset input signal RST751 of the microcontroller U2 such that when the RESET line is at a logical ONE, the RST751 line is pulled to a logical ONE, thereby resetting the microcontroller U2.
The first PAL U1 resets the microcontroller U2 responsive to the CPU 40 writing a logical ONE to bit 0 of control port 0EDH. Writing a logical ONE to bit 0 of control port 0EDH causes the first PAL U1 to pull the RESET line to a logical ONE, which pulls the RST751 line to a logical ONE, thereby resetting the microcontroller U2. The CPU 40 clears the reset request by writing a logical ZERO to bit 0 of control port 0EDH.
In addition, the reset subcircuit pulls the RST751 line to a logical ONE, thereby resetting the microcontroller U2, whenever the voltage of AUX5 signal raises by a given amount, as would occur after the AUX5 voltage lowers during a "brownout" or "blackout" of the AC source to the power supply 17 occurs, as shown in FIG. 6C. The manufacturer of the 83C750, Philips, suggests using a simple RC circuit to prevent reset problems; however, a simple RC circuit can allow the 83C750 to latch up during power supply brownouts. In the particular configuration of FIG. 6A, the RST751 line is pulled to a logical ONE for a period of time determined by R17 and C8 (thereby resetting the microcontroller U2) when the AUX5 voltage raises by a threshold amount in a period of time greater than the time constant determined by R4, R16, and C1. This would occur after a typical brownout or blackout. The threshold value is approximately 1.5 VDC in the embodiment shown in FIG. 6A.
Referring now to FIG. 6C waveforms for the reset circuit 920 are shown for a period of time as AUX5 rises as AC power is applied to the power supply 17 and a period of time during which a "brownout" occurs. Before t0, the power supply is not generating AUX5, VBAT is at approximately 3.3 Volts, Q3 is conducting and pulling the RST751 line to ground. At t0, the power supply begins generating AUX5 and the voltage begins rising at a rate based on the load and the capacitors in the power supply affecting AUX5. Node1, the node between C1 and R4, is capacitively coupled to AUX5; therefore, it rises as AUX5 rises.
At t1, Node1 reaches approximately 1.5 Volts, which is sufficient to trigger Q2, which pulls Node2 to ground. At t2, as Node2 passes 2.5 Volts, Q3 ceases conducting and the RST751 line jumps to the level of AUX5 via R18 and rises with AUX5 to approximately 5 Volts. As the RST751 line becomes approximately 3 Volts, the microcontroller U2 is reset.
At t3, AUX5 stops rising, therefore, Node1 stops rising and begins discharging to ground (the RESET line of the first PAL U1 is LOW) at a rate determined by C1 and R4. At t4, as Node1 passes through approximately 1.5 Volts, Q2 stops conducting and Node2 charges at a rate determined by C8 and R17. At t5, as Node2 passes approximately 2.5 Volts, Q3 conducts, pulling the RST751 line to ground. Thus, the reset on power-on is complete; the system is usually in the state with AUX5 at 5 Volts, VBAT at 3.3 Volts, and Node1 at ground and Node2 at VBAT.
At t6, a brownout starts at the AUX5 line and AUX5 discharges. Being capacitively coupled to AUX5, Node1 tries to follow AUX5, but cannot, because diodes in the first PAL U1 prevent it from going much lower than -0.5 Volts. At t7, AUX5 is at its lowest point and starts rising again. Again, Node1 follows AUX5 and rises. At t8, Node2 reaches approximately 1.5 Volts, which is sufficient to trigger Q2, which pulls Node2 to ground. At t9, as Node2 passes 2.5 Volts, Q3 ceases conducting and the RST751 line jumps to the level of AUX5 via R18 and rises with AUX5 to approximately 5 Volts. As the RST751 line becomes approximately 3 Volts, the microcontroller U2 is reset.
At t10, AUX5 stops rising, therefore, Node1 stops rising and begins discharging to ground (the RESET line of the first PAL U1 is LOW) at a rate determined by C1 and R4. At t11, as Node1 passes through approximately 1.5 Volts, Q2 stops conducting and Node2 charges at a rate determined by C8 and R17. At t12, as Node2 passes approximately 2.5 Volts, Q3 conducts, pulling the RST751 line to ground. Thus, the brownout-induced reset cycle is complete. Notice that during this particular brownout, Node1 did not rise above 3 Volts and, therefore, could not have reset the microcontroller if connected to the RST751 pin. However, the voltage of AUX5 lowered below 4 Volts, which would have been enough to cause the microcontroller U2 to enter an undefined state.
The threshold for triggering a reset is tied to the reference value; therefore, to raise or lower the threshold voltage, the value of the reference (in this case VBAT), must be raised or lowered, respectively. The reset circuit provides the benefits of increased reset protection for the microcontroller U2, while being very inexpensive and consuming virtually no power when not resetting the microcontroller U2.
Referring back to FIG. 6A, the microcontroller U2 is interfaced to the CPU 40 via the first PAL U1 and has a number of inputs, outputs, and internally controllable functions.
The SWITCH signal is input at pin 8 (P0.0) and reflects the current state of the pushbutton 21. The pushbutton 21 is normally open. While the pushbutton 21 is open, the SWITCH line is pulled to a logical ZERO (ground) through resistor R1. When the pushbutton 21 is pressed, thereby causing a closure event, the SWITCH line is pulled up to a logical ONE (AUX5) through resistor R13. Capacitor C6 acts to debounce the switch closure event; any further debouncing of closure events of the switch 21
are performed within the microcontroller U2 by reading the SWITCH a predetermined number of times, e.g., 50 times, and assuring that the SWITCH line is the same for all those reads, as is known to those skilled in the art.
The regulation of the power supply 17 is directly controllable by the microcontroller U2. As shown in FIG. 6A, the ON signal is output at pin 5 (P3.0) and is wire-ORed with the SWITCH signal via resistor R6 to control the ON# signal of the power supply. When the ON signal is a logical ONE, MOSFET Q1 conducts, thereby pulling the ON# line (pin 2 of JP2) to a logical ZERO (GND), thereby causing the power supply 17 to begin providing regulated power to the system through the .+-.5 VDC and .+-.12
VDC lines. On the other hand, when the ON line is a logical ZERO, MOSFET Q1 does not conduct, therefore the ON# line (pin 2 of JP2) is pulled to a logical ONE (AUX5) by resistor R7, thereby causing the power supply 17 to cease providing regulated power through the .+-.5 VDC and .+-.12 VDC lines.
The state of the ON line is controlled by the microcontroller U2 responsive to a closure event of the switch 21 and responsive to the CPU 40 via a writable register bit within the microcontroller U2, which can be written by the CPU 40. The microcontroller U2 is powered by AUX5; therefore, the microcontroller U2 is always powered, executing code, and controlling the system. If the power supply 17 is not providing regulated power to the system through the .+-.5 VDC and .+-.12 VDC lines and either (i) the switch 21 is pressed or (ii) one of the external events occurs, then the microcontroller U2 asserts the ON signal, thereby causing the power supply 17 to provide regulated power to the system through the .+-.5 VDC and .+-.12 VDC lines. The microcontroller continues asserting the ON signal after the switch 21 is released.
As a backup system, the power supply 17 can also be turned on under the direct control of the user via the pushbutton 21. This option will typically only be used if the microcontroller U2 ceases functioning as expected, as will be evidenced by the system not powering up responsive to a press of the power button 21. As shown in FIG. 6A, the switch 21 also controls the ON# line of the power supply 17 via the diode CR2, the MOSFET Q1, the resistor R7, and the connector JP2. Normally the pushbutton 21 is open and the SWITCH line is pulled to a logical ZERO through R1 and MOSFET Q1 does not conduct; therefore the ON# line (pin 2 of JP2) is pulled to a logical ONE (AUX5) by resistor R7, and the power supply 17 is not providing regulated power through the .+-.5 VDC and .+-.12 VDC lines. When the pushbutton 21 is pressed and held by the user, the SWITCH line is pulled to a logical ONE and MOSFET Q1 conducts, thereby pulling the ON# line (pin 2 of JP2) to a logical ZERO (GND), thereby causing the power supply 17 to begin providing regulated power through the .+-.5 VDC and .+-.12 VDC lines. With the button 21 still held in, after the system is powered, the BIOS causes the CPU 40 to test whether the microcontroller U2 is still functioning. If not, the CPU 40 resets the microcontroller U2, which, after being reset, detects that the switch 21 is being pressed. Consequently, with the button 21 still held, the microcontroller asserts the ON signal and the user can finally release the switch 21 with the knowledge that the microcontroller is now controlling the power supply 17. To use this backup option, the user must press the button 21 for a period of time on the order of seconds--approximately two seconds after the logo appears.
The microcontroller U2 only turns off the system responsive to either (i) the switch 21 being pressed or (ii) the CPU 40 commanding the microcontroller to turn off the system. To the microcontroller, these events are the same, because the microcontroller is configured such that a switch press can be caused either by a closure event of the switch 21 or by the CPU 40; a hardware button press/release is treated virtually the same as a software button press/release. The microcontroller U2
only turns off the system without a command by the CPU if the Suspend Enable Flag in the microcontroller U2 is cleared. In this case, when the system is powered and the Suspend Enable Flag is CLEARed, responsive to a closure event of the switch 21, the microcontroller U2 clears the ON signal, thereby causing the power supply 17 to cease providing regulated power to the system through the .+-.5 VDC and .+-.12 VDC lines. The ON signal remains cleared after the switch 21 is released.
The microcontroller U2 also turns off the system responsive to a command by the CPU, as would be issued after a the system state has been successfully saved to the hard disk drive (suspended). Responsive to such a command, the microcontroller U2
clears the ON signal, thereby causing the power supply 17 to cease providing regulated power to the system through the .+-.5 VDC and .+-.12 VDC lines.
The microcontroller U2 can also detect and affect the system when certain external events occur. The EXT.sub.-- RING signal is input at pin 7 (P0.1) and allows the microcontroller U2 to detect a ring from the powered external modem 902. As known to those skilled in the art, typical external modems supply a ring signal that toggles to a logical ONE in the well known RS-232C format when a ring signal is detected across the tip and ring telephone lines. This signal is interfaced to the microcontroller U2 via diode CR6 and divided with resistors R10 and R11 and finally input into the microcontroller U2 via the EXT.sub.-- RING line. The toggling signal is sampled every 25 milliseconds and analyzed by the microcontroller U2, which deems that a ring is present whenever this input is a logical ONE for two consecutive samples. Responsive to this condition being met, the microcontroller U2 asserts the ON signal, thereby causing the power supply 17 to being providing regulated power to the system through the .+-.5 VDC and .+-.12 VDC lines. For the EXT RING signal to be used to detect an incoming telephone call, an externally powered modem 902 must be present.
In the alternative, another device that provides a binary signal conforming to the RS-232 specification (or close enough that it asserts the EXT.sub.-- RING signal) can be interfaced to the EXT.sub.-- RING line and used to awaken the system, for example, motion sensors, burglar alarm sensors, voice activated sensors, light sensors, infrared light sensors, "clapper" type sensors, etc.
As shown in FIGS. 6A and 6B, the present embodiment also has a provision for detecting a telephone ring signal from an internal modem 900 having an optoisolator OPTO1 based ring-detect circuit. Many suitable optoisolators are manufactured by e.g., Hewlett Packard, and widely available from numerous sources. The internal modem 900 can either be designed into the circuitry of the system planar 20 or placed into one of the expansion slots 78. In the latter case, the modem 900 must be modified to provide a Berg or similar connector to allow the signal from the optoisolator OPTO1 to be electrically connected to the circuitry of the power management circuitry of FIG. 6A. Many manufacturers of modems are modifying their internal modems to provide a connector suitable for use with the circuitry of the present invention. The EXT.sub.-- WAKEUP#signal is input at pin 4 (P0.2) of the microcontroller U2 and is used to input a signal from the ring-detect optoisolator OPTO1 from the internal modem 900. This signal is interfaced via resistors R9 and R5, diode CR6, and capacitor C9 and finally input into the microcontroller U2 via the EXT.sub.-- WAKEUP# line.
The threshold and protection portion 905 of the internal modem 900 is connected to the standard Tip and Ring telephone lines, and (i) provides protection from lightning and other electrical events that might damage the modem 900 and (ii) sets the ring threshold voltage, as known to those skilled in the art of modem design.
The toggling signal from the optoisolator OPTO1 is detected and analyzed by the microcontroller U2, which deems that a ring is present whenever three (3) consecutive signal periods of the signal on EXT.sub.-- WAKEUP have a frequency of between
15.1 Hz and 69.1 Hz. Unlike the EXT.sub.-- RING signal circuit, which must be powered to provide the ring signal along EXT.sub.-- RING, the internal modem 900 need not be powered for the optoisolator OPTO1 to supply a suitable signal along the EXT.sub.-- WAKEUP# line, which is normally pulled up to AUX5 by R5.
The microcontroller U2 can interrupt the CPU 40 via the CPU's system management interrupt (SMI), if the CPU 40 has an SMI (the CPU 40 need not have an SMI for the system to take advantage of many of the benefits of the present invention). The SMI.sub.-- OUT#signal is output at pin 3 (P3.2) of the microcontroller U2 and allows the microcontroller U2 to immediately interrupt the CPU 40 without waiting for the operating system to validate or otherwise allow the interrupt. The state of the SMI.sub.-- OUT# line is controlled by a writable register bit, which can be written by the CPU 40, located within the microcontroller U2. In addition the microcontroller U2 can assert the SMI.sub.-- OUT# signal and thereby interrupt the CPU 40 (i) responsive to activity being detected on the ACTIVITY# line or (ii) before the microcontroller U2 causes the power supply 17 to stop providing regulated power to the system. Either or both of these events can be enabled and disabled by commands from the CPU to the microcontroller U2.
Each SMI, the microcode in the CPU 40 saves the state of the CPU to the special CPU state save area to or from memory. Thereafter, the CPU 40 executes the SMI interrupt handler, which performs the functions below. To restore the state of the CPU, the SMI interrupt handler issues the RSM (resume) instruction, which causes the CPU 40 to restore its own state from the special save area.
Before the CPU 40 causes the microcontroller U2 to interrupt the CPU 40 via the CPU's SMI, the CPU 40 writes a value to a variable in CMOS NVRAM indicating the reason for the SMI. This value in CMOS NVRAM defaults to 00H, which indicates to the CPU 40 that the microcontroller U2 is interrupting the CPU 40 asynchronously, as occurs before the microcontroller U2 causes the power supply 17 to stop providing regulated power. After each SMI, the CPU 40 sets that variable in CMOS NVRAM to 00H. Responsive to this value, the CPU 40 performs certain tasks under the assumption that the system is going to be powered down imminently by the microcontroller U2. The CPU 40 can extend the period of time before which the microcontroller U2 powers down the system by periodically restarting the power down extend timer within the microcontroller U2.
During this period of time before the system powers down, the CPU 40 can perform numerous tasks. For example, since the user may have changed one or more of the parameters that affect the wake alarm, the CPU recalculates and writes to the microcontroller U2 a fresh minutes to wake value. In addition, the CPU writes to the CMOS NVRAM certain information that is to be written to the hard drive 31 later, such as the period of time the computer system was operating since its last power on.
Other values written by the CPU 40 include 01H, which indicates that the CPU 40 is to jump to the Suspend Routine at 254; 02H, which indicates that the CPU 40 is to jump to the Resume Routine at 454; and OFFH, which indicates that the CPU 40 is to set up the special CPU state save area in the segment E000H data structure.
In the present embodiment, the microcontroller is given control over blanking the display 11. The DISP.sub.-- BLANK signal is output via pin 1 (P3.4) of the microcontroller U2 and directly controls the blanking of the display 11. Two inverters U3D and U3E interface the DISP BLANK signal with the ESYNC# and BLANK# lines. With the ESYNC# and BLANK# lines at a logical ONE (VCC), the video controller 56 generates a video signal. When BLANK# and ESYNC# are at a logical zero (GND) the video controller 56 ceases generating the video signal. The state of the DISP.sub.-- BLANK line is controlled by a writable register bit, which can be written by the CPU 40, located within the microcontroller U2. The CPU 40 instructs the microcontroller U2
to blank the display when the system enters the standby state 152. In addition, the DISP.sub.-- BLANK line is sequentially SET then CLEARed responsive to closure events of the switch 21. Similarly, activity at any one of the activity interrupts, in this case INT1 and INT12, causes the microcontroller to CLEAR the DISP.sub.-- BLANK line, thereby allowing the video controller 56 to generate the video signal.
In addition, the microcontroller U2 controls the frequency of the clock signals generated by the clock synthesizer 906. Three Berg-type jumpers (not shown) JP0, JP1, and JP2 control the clock synthesizer as follows: when JP0=0, JP1=1, and JP2=0, the clock synthesizer generates a 33 MHz clock signal; when JP0=1, JP1=1, and JP2=0, the clock synthesizer generates a 25 MHz clock signal; and when JP0=0, JP1=1, and JP2=1, the clock synthesizer generates an 8 MHz clock signal. The clock synthesizer
906 is further controlled by three clock lines CLK0, CLK1, and CLK2, which correspond to JP0, JP1, and JP2. As shown in FIG. 6A, these clock lines CLK0, CLK1, and CLK2 are controlled by the microcontroller U2 via the CLK.sub.-- SLOW# signal, which is output at pin 2 (P3.3) of the microcontroller U2. As shown, the CLK.sub.-- SLOW# signal is doubly inverted by the inverters with open collector outputs U3A, U3B, and U3C. Also, resistors R15 and R8 are pullup resistors used to pull the open collector output of U3A and the CLK0 input to the clock synthesizer 906 to a logical ONE, respectively.
The three clock signals CLK0, CLK1, and CLK2 and the three jumpers JP0, JP1, and JP2 control the clock synthesizer as follows: when the CLK.sub.-- SLOW# signal is a logical ONE, the CLK1 and CLK2 signals are also a logical ONE and, consequently, the clock synthesizer 906 is controlled by the jumpers JP1, JP2 and generates the higher 25 MHz or 33 MHz clock signal for use by the system. On the other hand, when the CLK.sub.-- SLOW# signal is a logical ZERO, the CLK1 and CLK2 signals are also a logical ZERO and, consequently, the clock synthesizer 906 generates the lower 8 MHz signals for use by the system, thereby causing the system to consume less power. As shown in FIG. 6A, a Berg-type jumper separates the CLK.sub.-- SLOW# line from the CLK0 line. If a jumper is in place, the CLK0 line follows the CLK.sub.-- SLOW# signal. On the other hand, if no jumper is in place, the CLK0 line remains pulled to a logical ONE by resistor R8 regardless of the state of the CLK.sub.-- SLOW#signal. The state of the CLK.sub.-- SLOW# line is controlled by a writable register bit, which can be written by the CPU 40, located within the microcontroller U2. In addition, the CLK SLOW# line can be cleared by the microcontroller U2 in response to activity at the ACTIVITY# line. As is apparent to those skilled in the art, other clock synthesizers can be used in the present invention; the interconnections between the microcontroller U2 and the clock synthesizer might need to be changed to match the specific specifications of the particular synthesizer used.
Additionally, the microcontroller U2 directly controls the illumination of the power/feedback LED 23. The LED.sub.-- CNTRL signal is output at pin 22 (P3.6) and allows direct control of the power/feedback LED 23 by the microcontroller U2. The resistors R2 and R3 and diodes CR4 and CR5 allow the Dower/feedback LED 23 to be driven by either the AUX5 power line or the VCC power line in response to the LED.sub.-- CNTRL line being at a logical ZERO. When the LED.sub.-- CNTRL line is at a logical ONE, the power/feedback LED 23 is not illuminated. As described more fully below, the state of the LED.sub.-- CNTRL line is controlled by the microcontroller U2 in response to a closure event of the switch 21, in response to the wake alarm, in response to one or more rings at either ring-detect input, or in response to the system being placed in the standby mode.
The microcontroller U2 can control the LED 23 to be a simple power LED. As such, the LED 23 is illuminated after a closure event of the switch 21 that causes the system to change from either the off state 156 or the suspend state 154 to the normal operating state 150. Likewise, the microcontroller U2 extinguishes the LED 23 after a release event of the switch 21 that causes the system to change from the normal operating state 150 to either the suspend state 154 or the off state 156.
In addition, the LED 23 can be selectively flashed at a particular rate, e.g., every second, by the microcontroller U2 to indicate that the system is in the standby state 152. In addition, the LED 23 can be selectively flashed at a different rate, e.g., every half-second, by the microcontroller U2 to indicate that the system was awakened by a ring or by the alarm and the system is in either the off state or the suspend state. In the alternative, while in the suspend state, the LED 23 can be selectively flashed in groups of flashes by the microcontroller U2 to indicate the number of times the system was powered up by external events, such as a ring, alarm, etc., and was powered back down by the expiration of the inactivity suspend timer. In this case, the BIOS is provided with one or more functions to allow the OS and application programs to modify the number of times the microcontroller U2 is to flash the LED 23. For example, if the system is awakened by a ring and an incoming facsimile transmission is received, the telecommunications application program can call the particular BIOS function to add one to the number of flashes. Thereafter, the BIOS causes the CPU 40 to write the new flash value to the microcontroller U2, which then causes the LED 23 to flash the commanded number of times.
The POWERGOOD signal is input at pin 4 (P3.1) of the microcontroller U2 and allows this signal to be used by the microcontroller U2 and the CPU 40. Specifically, the microcontroller uses the POWERGOOD signal to implement a feedback-based fault detection and correction circuit to determine if the power supply 17 has faulted and to clear the faulted condition. As described elsewhere in this specification, if the ON signal has been asserted for a period of time (e.g., three seconds) and the POWERGOOD signal is at a logical zero, indicating that the power supply 17 is not providing regulated voltages at proper levels, then the microcontroller U2 assumes that the power supply 17 has faulted from, e.g., an overcurrent condition. Consequently, to possibly clear the faulted condition, the microcontroller U2 ceases asserting the ON signal for a period of time (e.g., five seconds) to allow the fault to clear. Thereafter, the microcontroller U2 reasserts the ON signal and waits for the POWERGOOD signal to become a logical ONE, indicating that the power supply 17 is now providing regulated power to the system. Without this feedback-based fault detection and correction, the power supply 17 would remain faulted and the microcontroller U2 would continue to assert the ON signal in an attempt to cause the power supply 17 to begin generating regulated power. The only solution would be to remove AC power from the power supply to clear the fault.
An alternative embodiment of the power supply fault detection and correction circuit is shown in FIG. 6D. This embodiment uses four FETs Q10-Q13, resistors R20-R23, a capacitor C20, and a 74HC132 to detect when the power supply 17 is faulted and clear the fault. Q12 pulls the ON signal LOW for a period of time determined by R22 and C20, when the ON signal is HIGH, AUX5 is being powered, and VCC is below the threshold for triggering Q11, thereby clearing the fault condition in the power supply.
The ACTIVITY# signal is input at pin 19 (INT1) of the microcontroller U2 and is used by the microcontroller U2 to respond to activity at the keyboard 12 and mouse 13. IRQ1 is the keyboard hardware interrupt signal, which is input at pin 8 (I7) of the first PAL U1; pressing a key on the keyboard 12 causes the IRQ1 signal to pulse. IRQ12 is the mouse hardware interrupt signal, which is input at pin 11 (I9) of the first PAL U1; moving the mouse 13 or pressing a button on the mouse 13 causes the IRQ12 signal to pulse. The IRQ1 and IRQ12 signals are logically Ored in the first PAL U1 and output as the ACTIVITY# signal. Using the ACTIVITY# signal allows the microcontroller U2 to never miss activity of either the keyboard 12 or the mouse 13.
While in the standby state, activity on either interrupt causes the microcontroller to restore immediately the video display. Using the interrupts IRQ1 and IRQ12 in this manner gives the user immediate feedback in the form of a restored video display when returning from the standby state 152 to the normal operating state 154. Without it, the user might not receive feedback until possibly seconds later when the APMchecks for user activity, as explained in the text accompanying FIG. 9.
Communications between the CPU 40 and the microcontroller U2 are performed using SD(0), which is input at pin 18 (I/06) of the first PAL U1 and input to the microcontroller U2 via the RWD0 line, which is output at pin 13 (I/03) of the first PAL U1 and input at pin 13 (P1.0) of the microcontroller U2, SD(1), which is input at pin 14 (pl.1) of the microcontroller U2, SD(2), which is input at pin 15 (p1.2) of the microcontroller U2, SD(3), which is input at pin 16 (p1.3) of the microcontroller U2, SD(4), which is input at pin 6 (I5) of the first PAL U1, IO.sub.-- STROBE#, which is input at pin 18 (INTO) of the microcontroller U2, and PROC RDY, which is output at pin 20 (P1.7) of the microcontroller U2. The first PAL U1 and the microcontroller U2
are configured and programmed to provide (i) four-bit parallel writes from the CPU 40 to the microcontroller U2 along SD(0) via RWD0, SD(1), SD(2), and SD(3), with one address being essentially a one-bit write to reset the microcontroller U2 and the other being a nibble written to the microcontroller U2 that is only valid when data bit SD(4) is HIGH, and (ii) serial (one-bit) reads from the microcontroller U2 by the CPU 40 along SD(0) via RWD0, with one address corresponding to the status bit and the other corresponding to the data bit from the microcontroller U2.
Referring now to FIG. 19, several of the routines executing on the microcontroller U2 are shown beginning at 1160. The microcontroller U2 is usually executing one of two main routines: the Power On Routine, at tasks 1168 through 1216, or the Power Off Routine, at tasks 1260 through 1308. The Power On Routine is executed by the microcontroller U2 when the power supply 17 is providing regulated power at the .+-.5 and .+-.12 lines or power supply 17 is not providing regulated power at the .+-.5 and .+-.12 lines, but the system is in the process of powering on. The Power Off Routine is executed by the microcontroller U2 when the power supply 17 is not providing regulated power at the .+-.5 and .+-.12 lines or the power supply 17 is providing regulated power at the .+-.5 and .+-.12 lines, but the system is in the process of powering off. In addition, there are three interrupt-driven routines: one for communicating with the CPU 40, at 1220 through 1232, one for detecting activity of the mouse 13 or keyboard 12, at 1236 through 1244, and one that provides a time-base with 25 millisecond, half-second, second, and minute resolutions, at 1248 through 1256.
First, the microcontroller U2 is initialized, at 1164, during which time all the variables are initialized, the counter variables are initialized, the timer interrupt is initialized and enabled, and external interrupts, which control the communication routine and the activity routine, are initialized.
The communication routine is an interrupt-driven routine beginning at 1220 that executes responsive to the IO.sub.-- STROBE line being pulled to a logical ZERO by the first PAL U1, which indicates that the CPU 40 is beginning a command or query, in short, this routine receives a one- or more nibble command or query from the CPU 40, at 1224, implements the command and/or returns the data responsive to the query, at 1228, and returns program execution control to the interrupted code, at 1232.
The microcontroller sequentially receives the nibbles from the CPU that form the command or query. After receiving a nibble, the microcontroller pulls the PROC.sub.-- RDY LOW. When it is ready for the next nibble, it pulls PROC.sub.-- RDY HIGH again. Upon seeing this LOW to HIGH transition at PROC.sub.-- RDY, the CPU 40 then can write the next command nibble.
While the microcontroller U2 is implementing the command or query from the CPU 40, it cannot receive another command; therefore, the microcontroller U2 asserts the PROC.sub.-- RDY line to a logical ZERO, indicating to the CPU 40 (via reads of the status port) that the microcontroller cannot accept the next command/query yet. When the implementation is finished, the PROC.sub.-- RDY line is asserted at a logical ONE, indicating to the CPU 40 (via reads of the status port) that the microcontroller U2 is ready to accept the next command/query.
The activity routine is an interrupt-driven routine beginning at 1236 that executes responsive to the ACTIVITY# line being pulled to a logical ZERO by the first PAL U1, which indicates that the user has used either the mouse 13 or the keyboard
12. In short, responsive to receiving the interrupt, this routine (i) SETs a bit indicating that there was either mouse 13 or keyboard 12 activity, (ii) restores the clock speed if clock slowing is enabled, (iii) unblanks the screen 11 if blanking is enabled, (iv) restarts the failsafe timer, and (v) generates an SMI to the CPU, if enabled, at 1240. Thereafter, the routine returns program execution control to the interrupted code, at 1244. The bit set by this routine is then queried by the Supervisor Routine every APM "get event," as detailed elsewhere in this specification.
The timer routine is an interrupt-driven routine beginning at 1248 that executes responsive to the internal timer interrupt, which is based on a 16-bit free-running counter configured to generate the interrupt every 25 milliseconds to provide a time-base for the microcontroller U2. The timer routine provides the following time-bases: 25 milliseconds, half-seconds, seconds, and minutes. In short, this routine receives the interrupt, determines when the various times have occurred, performs the appropriate activity, at 1252, and returns program execution control to the interrupted code, at 1256.
Every tick (every 25 milliseconds), if the power supply is not providing regulated power and the microcontroller is configured to respond to rings, the timer routine checks for an RS-232 ring on the EXT.sub.-- RING line and SETs a bit if one occurred.
Every half-second while in either the off state or the suspend state, the timer routine determines whether it should toggle the LED 23 to implement the awake on external ring indicator flashing sequence, detailed elsewhere in this specification.
Every second while in either the standby state, the timer routine determines whether it should toggle the LED 23 to implement the suspend indicator flashing sequence, detailed elsewhere in this specification.
Also, every second, the timer routine decrements the failsafe timer, decrements the APM fail-suspend timer, and decrements the power supply fault timer, if appropriate, and SETs a corresponding bit if any have expired. The failsafe timer is a
20-second timer that causes the microcontroller to turn the system power off when it expires. The failsafe timer is frequently restarted (reset) by the Supervisor Routine in response to APM get events; therefore, as long as the code executing on the CPU
40 is executing properly, the failsafe timer never expires. However, if the code ceases executing properly, the failsafe timer expires and, responsive to a press and release of the power button 21, the microcontroller U2 causes the power supply 17 to stop providing regulated power at the .+-.5 and .+-.12 lines under the assumption that the BIOS and other routines have failed.
The APM fail-suspend timer is an 18-second timer that is enabled when the switch 21 is in the off/release state (indicating that the user is trying to turn the system off) and that causes the system to attempt to suspend when it expires, hopefully before the failsafe timer expires, causing the microcontroller to turn the system off. Like the failsafe timer, the APM fail-suspend timer is frequently restarted (reset) by the code executing on the CPU 40, e.g., APM Get Events, APM Working on Last Request, and APM Reject Last Request; therefore, as long as the code executing on the CPU 40 is executing properly, the APM fail-suspend timer never expires. However, if the code ceases executing properly, the APM fail-suspend timer expires.
When the APM fail-suspend timer expires, the microcontroller U2 SETs a bit. This bit is checked during each timer level 0 interrupt, which occurs approximately every 55 milliseconds, as is known to those skilled in the art. In addition, the timer level 0 interrupt service routine restarts the failsafe timer. If the timer level 0 interrupt service routine detects that the APM fail-suspend timer has expired, it jumps to the Suspend Routine in an attempt to suspend the system, as described in the text accompanying FIG. 10.
The suspend started by the timer level 0 interrupt service routine is not the preferred method of suspending. Many application programs and adapters are APM aware and perform tasks in response to the system being suspended. A suspend started by the timer level 0 interrupt service routine cannot use APM to indicate to these APM aware entities that a suspend is imminent. Consequently, the system is suspended without these entities being properly prepared. As such, the system will be saved by a suspend started by the timer level 0 interrupt service routine, therefore data in memory will not be lost; however, the user may need to reboot the machine to place the system into its proper state after saving the desired data.
The APM fail-suspend timer is particularly helpful in patching "holes" in the APM driver in the OS. For example, when a Microsoft Windows 3.1 modal dialog box is displayed, the Windows APM driver ceases issuing APM get events. Consequently, if a modal dialog box is displayed when the user presses the power button 21 in an attempt to su