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United States Patent
5539652
Tegethoff
July 23, 1996
Title
Method for manufacturing test simulation in electronic circuit design
Abstract
A manufacturing and test simulation method for electronic circuit design integrated with computer aided design tools to provide concurrent engineering of manufacturing and testability aspects of a product concurrent with the functional design of a product. The manufacturing and test simulator (MTSIM) simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and the design for testability. All simulation by the methods of the present invention applies manufacturing and test models down to the component level. The methods of the simulator include a new yield model for boards and MCMs which accounts for the clustering of solder defects. MTSIM models solder faults, manufacturing workmanship faults, component performance faults, and reliability faults. Fault probabilities for the circuit design are estimated based on the component type, the component functionality, and the assembly process used. Up to seven manufacturing test steps can be simulated by MTSIM. Test coverage models will support all commonly used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, selftest, diagnostics, and burn-in. Pareto and iterative "what-if" analysis may be used to locate particular enhancements which most benefit the manufacturability and testability of the product.
Inventors:
Tegethoff; Mauro V.
(Fort Collins,
CO
)
Assignee:
Hewlett-Packard Company
(Palo Alto,
CA
)
Appl. No.:
384909
Filed:
February 7, 1995
Current U.S. Class:
703/14
716/4
700/108
700/97
703/13
Field of Search:
364/488,489,490,491,578,468
U.S. Patent Documents
4342090
July 1982
Caccoma et al.
4949275
August 1990
Nonaka
5313398
May 1994
Rohrer et al.
5355320
October 1994
Erjavic et al.
5379237
January 1995
Morgan et al.
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Primary Examiner:
Teska; Kevin J.
Assistant Examiner:
Frejd; Russell W.
Claims
What is claimed is:
1. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of:
providing a description of the design of said electronic assembly;
providing pre-determined test and quality information relating to each component in said electronic assembly;
providing a description of a manufacturing test process; and
simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes.
2. The method of claim 1 wherein the step of simulating further comprises the steps of:
estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component; and
simulating application of said manufacturing test process to said incoming fault probability value to estimate said manufacturing test and quality attributes.
3. The method of claim 2 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
4. The method of claim 2 wherein the step of simulating application of said manufacturing test process further comprises the steps of:
estimating the average number of defects (Do) in said electronic assembly as: ##EQU37## where: Pfi.sub.j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly,
TC.sub.j is a test coverage value corresponding to the j'th said component in said electronic assembly, and
N is the number of components in said electronic assembly; and
estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
5. The method of claim 4 wherein the incoming fault probability value (Pfi) of said j'th component is determined as:
where:
n is the number of trials for a fault type in a component and is derived from said pre-determined test and quality information,
fp is the fault probability and is derived from said pre-determined test and quality information.
6. The method of claim 4 wherein yield (Y) is determined as:
where:
Ycl is a yield determined from clustered solder defects, and
Yncl is a yield determined from non-clustered assembly defects and functional defects.
7. The method of claim 6 wherein said Ycl is determined as: ##EQU38## where: .alpha. is the clustering factor.
8. The method of claim 7 further comprising the step of:
providing information relating to the assembly process used for said electronic assembly;
estimating the clustering factor (.alpha.) as: ##EQU39## where: .mu. is the mean number of defects for said assembly process, and
.sigma. is the standard deviation of said number of defects for said assembly process.
9. The method of claim 6 wherein said Yncl is determined as:
10. The method of claim 4:
wherein said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and
wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly.
11. The method of claim 1 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect a contribution of each component to said manufacturing test and quality attributes.
12. The method of claim 1 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
13. The method of claim 1 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
14. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly comprising the steps of:
(a) providing a description of the design of said electronic assembly;
(b) providing pre-determined test and quality information relating to each component in said electronic assembly;
(c) providing a description of a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps;
(d) estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps;
(e) assigning the first of said sequential test steps as the current test step;
(f) simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes;
(g) determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of step (f);
(h) assigning the next of said sequential test steps as the current test step; and
(h) repeating steps (f) and (g) and (h) for each of said plurality of test steps of said manufacturing test process.
15. The method of claim 14 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
16. The method of claim 14 wherein the step of simulating application of said manufacturing test process further comprises the steps of:
estimating the average number of defects (Do) in said electronic assembly as: ##EQU40## where: Pfi.sub.j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly,
TC.sub.j is a test coverage value corresponding to the j'th said component in said electronic assembly, and
N is the number of components in said electronic assembly; and
estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
17. The method of claim 16 wherein the incoming fault probability value (Pfi) of said j'th component is determined as:
where:
n is the number of trials for the a fault type of a component and is derived from said pre-determined test and quality information,
fp is the fault probability and is derived from said pre-determined test and quality information.
18. The method of claim 16 wherein a yield (Y) is determined as:
where:
Ycl is a yield determined from clustered solder defects, and
Yncl is a yield determined from non-clustered assembly defects and functional defects.
19. The method of claim 18 wherein said Ycl is determined as: ##EQU41## where: .alpha. is the clustering factor.
20. The method of claim 19 further comprising the step of:
providing information relating to the assembly process used for said electronic assembly;
estimating the clustering factor (.alpha.) as: ##EQU42## where: .mu. is the mean number of defects for said assembly process, and
.sigma. is the standard deviation of said number of defects for said assembly process.
21. The method of claim 18 wherein said Yncl is determined as:
22. The method of claim 16:
wherein each test step of said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and
wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly of said current test step.
23. The method of claim 14 wherein the outgoing fault probability value (Pfo) of said j'th component is determined as:
24. The method of claim 14 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to a contribution of each component to said manufacturing test and quality attributes.
25. The method of claim 14 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
26. The method of claim 14 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
27. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing test process, said method comprising the steps of:
providing a description of the design of said electronic assembly;
providing pre-determined test and quality information relating to each component in said electronic assembly; and
simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
28. The method of claim 27 wherein the step of simulating further comprises the steps of:
estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component; and
simulating application of said manufacturing test process to said incoming fault probability value to estimate said manufacturing test and quality attributes.
29. The method of claim 28 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
30. The method of claim 28 wherein the step of simulating application of said manufacturing test process further comprises the steps of:
estimating the average number of defects (Do) in said electronic assembly as: ##EQU43## where: Pfi.sub.j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly,
TC.sub.j is a test coverage value corresponding to the j'th said component in said electronic assembly, and
N is the number of components in said electronic assembly; and
estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
31. The method of claim 30 wherein the incoming fault probability value (Pfi) of said j'th component is determined as:
where:
n is the number of trials for a fault type of a component and is derived from said pre-determined test and quality information,
fp is the fault probability and is derived from said pre-determined test and quality information.
32. The method of claim 30 wherein a yield (Y) is determined as:
where:
Ycl is a yield determined from clustered solder defects, and
Yncl is a yield determined from non-clustered assembly defects and functional defects.
33. The method of claim 32 wherein said Ycl is determined as: ##EQU44## where: .alpha. is the clustering factor.
34. The method of claim 33 further comprising the step of:
providing information relating to the assembly process used for said electronic assembly;
estimating the clustering factor (.alpha.) as: ##EQU45## where: .mu. is the mean number of defects for said assembly process, and
.sigma. is the standard deviation of said number of defects for said assembly process.
35. The method of claim 32 wherein said Yncl is determined as:
36. The method of claim 30:
wherein said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and
wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly.
37. The method of claim 27 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to a contribution of each component to said manufacturing test and quality attributes.
38. The method of claim 27 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
39. The method of claim 27 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
40. A method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a predetermined manufacturing assembly process, said method comprising the steps of:
providing a description of the design of said electronic assembly;
providing pre-determined test and quality information relating to each component in said electronic assembly;
providing a description of a manufacturing test process; and
simulating said manufacturing test process, responsive to the description of the design of said electronic assembly and to the predetermined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
41. The method of claim 40 wherein the step of simulating further comprises the steps of:
estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component; and
simulating application of said manufacturing test process to said incoming fault probability value to estimate said manufacturing test and quality attributes.
42. The method of claim 41 wherein said manufacturing test and quality attributes comprise at least one attribute selected from the group consisting of: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
43. The method of claim 41 wherein the step of simulating application of said manufacturing test process further comprises the steps of:
estimating the average number of defects (Do) in said electronic assembly as: ##EQU46## where: Pfi.sub.j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly,
TC.sub.j is a test coverage value corresponding to the j'th said component in said electronic assembly, and
N is the number of components in said electronic assembly; and
estimating the yield of said electronic assembly in response to the application of said manufacturing process and in response to the estimation of said average number of defects (Do).
44. The method of claim 43 wherein the incoming fault probability value (Pfi) of said j'th component is determined as:
where:
n is the number of trials for a fault type of a component and is derived from said pre-determined test and quality information,
fp is the fault probability and is derived from said pre-determined test and quality information.
45. The method of claim 43 wherein a yield (Y) is determined as:
where:
Ycl is a yield determined from clustered solder defects, and
Yncl is a yield determined from non-clustered assembly defects and functional defects.
46. The method of claim 45 wherein said Ycl is determined as: ##EQU47## where: .alpha. is the clustering factor.
47. The method of claim 46 further comprising the step of:
providing information relating to the assembly process used for said electronic assembly;
estimating the clustering factor (.alpha.) as: ##EQU48## where: .mu. is the mean number of defects for said assembly process, and
.sigma. is the standard deviation of said number of defects for said assembly process.
48. The method of claim 45 wherein said Yncl is determined as:
49. The method of claim 43:
wherein said manufacturing test process comprises at least one test attribute applicable to each of said components of said electronic assembly, said at least one test attribute selected from the group consisting of: in-circuit, boundary scan, self test, functional test, stress test, and inspection; and
wherein said test coverage value (TC) of said j'th component is determined as the largest test coverage value of all test attributes applicable to the j'th component of said electronic assembly.
50. The method of claim 40 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to a contribution of each component to said manufacturing test and quality attributes.
51. The method of claim 40 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each unique part number of all components used in said electronic assembly with respect to a contribution of each unique part number to said manufacturing test and quality attributes.
52. The method of claim 40 further comprising the steps of:
performing pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each category of components used in said electronic assembly with respect to a contribution of each category of components to said manufacturing test and quality attributes.
53. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising:
means for providing information on the design of said electronic assembly;
means for providing pre-determined test and quality information relating to each component in said electronic assembly;
means for providing information on a manufacturing test process; and
means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes.
54. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly concurrent with the design of said electronic assembly, comprising:
(a) means for providing information on the design of said electronic assembly;
(b) means for providing pre-determined test and quality information relating to each component in said electronic assembly;
(c) means for providing information on a manufacturing test process wherein said manufacturing test process comprises a plurality of sequential test steps;
(d) means for estimating an incoming fault probability value for said each component in said electronic assembly by applying said pre-determined test and quality information corresponding to said each component, wherein said incoming fault probability corresponds to a first of said sequential test steps;
(e) means for assigning the first of said sequential test steps as the current test step;
(f) means for simulating application of the current test step to said incoming fault probability value to estimate said manufacturing test and quality attributes;
(g) means for determining an outgoing fault probability corresponding to the fault probability for each component in said electronic assembly following application of said next test step, wherein said outgoing fault probability is usable as an incoming fault probability value in subsequent invocations of said stimulating means;
(h) means for assigning the next of said sequential test steps as the current test step; and
(i) means for activating said simulating means, said determining means, and said second assigning means for each of said plurality of test steps of said manufacturing test process.
55. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing test process, said system comprising:
means for providing information on the design of said electronic assembly;
means for providing pre-determined test and quality information relating to each component in said electronic assembly; and
means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and to the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing test process.
56. A system, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly attributable to a pre-determined manufacturing assembly process, said system comprising:
means for providing information on the design of said electronic assembly;
means for providing pre-determined test and quality information relating to each component in said electronic assembly;
means for providing information on a manufacturing test process; and
means for simulating said manufacturing test process, responsive to the information on the design of said electronic assembly and the pre-determined test and quality information, to estimate said manufacturing test and quality attributes attributable to said pre-determined manufacturing assembly process.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the field of computer aided electronic circuit design tools and in particular to a computer based method for providing manufacturing test simulation in the circuit design process to enable improved design for test and design for manufacturability earlier in the circuit design process.
2. Description of related art
Electronic products of today are designed under tremendous internal and external pressures. Competitive market pressure relating to time to market dictates new product announcements every one to two years and a particular product may be viable for only six months to one year. Rapidly increasing performance capability of circuits adds to the pressures on circuit designers to complete a design before new technology obsoletes a product design.
Modern circuit designs are rapidly increasing in complexity. In addition, several factors contribute to a demand for smaller electronic product size. In addition to market concerns for reducing product size, the performance of modern electronic circuits is frequently impacted by the size of the circuit. Signal propagation delays can render modern high speed circuits non-functional. The technology of circuit board assembly is evolving to support density demands of many modern circuit designs. Multi-chip modules (MCMs) and twelve-mil pitch surface mount technology (SMT) are frequently used to improve circuit density. SMT chip packages with lead counts of over 1000 are not uncommon. New fabrication processes which are used to enable higher circuit densities usually have higher defect rates than older low density fabrication technologies. Faster circuits are less tolerant of delay faults, resulting in the increase in the component functional defect rate. Higher defect rates imply lower yields and higher costs in manufacturing.
Another trend in the electronics industry is the focus on quality control and quality improvement at all stages of a product's life cycle. To achieve such quality control and defect reduction, there is an emphasis on design for test (DFT), design for quality (DFQ), and design for manufacturing (DFM) in the early design of electronic circuits. However, time and cost factors tend to make such design efforts difficult to justify in a short term, profit oriented, perspective. In order to maximize short term profits, a company needs to justify a return on investment of all features implemented in a product. Testability features, such as the IEEE 1149.1 boundary scan standard, are no exception since they require significant hardware investment which needs to be justified (See "IEEE 1149.1: How to Justify Implementation," Proceedings of the 1993 International Test Conference, 265, October 1993).
Often, such DFT/DFQ/DFM features are ignored during the early design phases of a circuit to minimize the time in design. Such features are sometimes added later in the design as a designer begins to consider manufacturing issues relating to the product. An example of this practice is DFM violations in board layout. For example, designers would like to minimize the area of surface mount pads to increase board density and minimize interconnect parasitic. However, SMT design rules require minimum pad geometries, and violation of these rules will result in increased solder defects in manufacturing. Another example is the placement of test pads on a board for in-circuit test access. Designers will usually wait until the board is completely routed before placing test pads. At that late stage in the design, the board is often too dense to allow the addition of desirable test points. The result is the reduction of test coverage for in-circuit board test. The solder defects not covered by in-circuit test will typically be detected later at the functional test step, with an increased cost for defect isolation and repair.
Many electronic products (especially computing products) are designed to meet high performance specifications dictated by the marketplace. The design engineer's first priority is to get a product to market within the narrow time-to-market window, and to meet the product price/performance specifications. DFM and DFT aspects of the product frequently are relegated to secondary concerns. DFM and DFT activity is usually performed by consulting with the manufacturing expert at selected times in the design cycle. This consultation is usually in the form of design reviews or enforcement of guidelines. There is a limited understanding of the trade-offs available in board manufacturing because, designers and manufacturing experts have different goals for the product. In this environment, the added manufacturing costs caused by poor quality and inefficient test process are not visible to the designer due to the lack of reliable design specific data. The result is that the DFT and DFM of the product suffers, and the product is not optimized for manufacturability and testability.
A fundamental problem exists in that design tools used by circuit designers are focused on functionality and tend to neglect manufacturing and testability issues. Designers are not accustomed to addressing manufacturability issues in their design processes. To effectively address manufacturability issues during design is frequently called Concurrent Engineering. Concurrent Engineering is defined as the product development paradigm where, the manufacturing aspects of the product are developed concurrently with the functional design of the product. However, in order to practice concurrent engineering successfully, designers need tools to help them understand manufacturing issues and trade-offs.
Typical prior approaches to measuring and testing for manufacturing include the stuck-at fault coverage metric and its failure rate estimations, automatic test pattern generation, scan methodologies, and built-in self test (BIST) methodologies (see T. W. Williams & K. P. Parker, "Design For Testability--A Survey," Proceedings of the IEEE, Vol. 71, 98-112, January 1983). Several DFT and test development techniques have evolved, and have been bench-marked against the stuck-at coverage metric. The major concern in board manufacturing has been the integrated circuit (IC) defect level, that is, what is the probability of a defect in an IC after it undergoes all of its IC level testing (See T. W. Williams & N. C. Brown, "Defect level as a function of fault coverage," IEEE Transactions on Computers, Vol. C-30, No. 12, 987-988, December 1981). IC defect level is important to board manufacturing but does not fully evaluate design quality from the overall perspective of manufacturing. In addition, ICs and systems are merging, requiring quality assurance methods more robust than what stuck-at model based fault simulation can provide. In computer products faults arise in a system, involving delay faults, chip to chip interactions, an ever changing fault spectrum (not characterized by defect density), and faults that need to be efficiently isolated to the defect and be repaired.
Work at Hewlett-Packard's Colorado Computer Manufacturing Operation (see M. V. Tegethoff et al., "Board Test DFT Model for Computer Products," Proceedings of the 1992 International Test Conference, 367-71), demonstrated that modeling aspects of the test process is quite effective in fostering DFT techniques. However, the HP work only covered the cost and quality aspects of the product assuming that critical manufacturing attributes, such as defect rates and test coverage, were otherwise known. In addition, all calculations were performed based on categories, making some of the statistical assumptions questionable, since the defect levels can become large on a parts per million basis. The yield modeling of the HP work was based on binomial statistics which is clearly insufficient in dealing with complex SMT. Finally, the spreadsheet model used in the HP work did not allow for more than two test steps and it was targeted to be used by expert manufacturing test engineers rather than circuit designers.
The prior approaches in board manufacturing can be broken into five categories (discussed below), board level report card tools, board level economic models, DFM tools, semiconductor tools, and test equipment analysis.
Report Card Tools
Report card tools have as objective grading the manufacturability of a board based on the manufacturing attributes of the parts used on that board. To set up a report card tool, a manufacturing expert has to grade each part available to designers on the manufacturing attributes of interest. Examples of manufacturing attributes include assembly process yield, reliability, component defect rate, in-circuit test coverage, diagnosibility, placement (manual vs. machine), etc. The report card tool takes as input the component list for the board and gives an overall score for the board based on the score of the individual parts. There is also the ability to weigh certain manufacturing attributes heavier than others. Once the result is available, the user can rerun the tool with different components and optimize the report card grade.
Mentor Graphics and Texas Instruments have a product called Manufacturing Advisor PCB (sold by Mentor Graphics, ibid.). This manufacturing advisor is based on a report card technique and it focuses solely on the mechanical aspects of design for manufacturing, not addressing any of the test issues. The manufacturing attributes scored in the Manufacturing Advisor are board density, board height, part auto inserted and part quality problems.
Another example of a report card tool is IBM's Design Report Card (see J. Hume et al., "Design Report Card: A method for Measuring Design for Manufacturability." Proceedings of the 1993 International Test Conference, 986-91). Designs are graded from A to D in the following areas: assembly process yield, reliability, component defect rate, in-circuit test coverage, diagnosibility, placement (manual vs. machine), connector type, handling problems, and repairability. The areas graded are selected based on manufacturing and field failure data. Weighted numerical values are assigned to each design alternative depending upon the significance of each manufacturing attribute as far as ease of manufacture and quality level is concerned. This allows the grading of each board design early in the design process.
Report card tools will give an indication of the manufacturability of a board based on the manufacturing attributes scored. However, the output is qualitative in nature, providing users only an indication that the design is improved.
Economic Models
The motivation of economic modeling is to reduce the cost of test in manufacturing by selecting the optimal test strategy for a product, and by selecting the appropriate DFT features to support the selected test strategy. An example of economic models is the research by Dislis et al. (see C. Dislis, et al., "Economic Modelling for the Determination of Test Strategies for Complex VLSI Boards," Proceedings of the 1993 International Test Conference, 210-17), which employs economic modeling to determine the optimum board test strategy. The Dislis work models a large number of manufacturing faults, requiring manufacturing defect data on open faults in edge connector area, open faults in component area, open faults in the interconnect area, shorts in edge connector area, shorts in component area, shorts in the interconnect area, static component faults, dynamic component faults, functional dynamic board faults, calibration faults, resistor defects, capacitor defects, memory faults, and parametric faults. The model also requires financial information such as pay raises of employees, and depreciation of equipment. Obtaining and maintaining accurate data for all these fault models, if possible, would require an unjustifiable effort in a manufacturing operation, thus making the practical use of the model unrealistic. In addition, defect clustering and its effect on yield is not modeled, details of the test coverage model are not described, and validation of model results with real manufacturing data are not provided.
Another example of economic models is the High Level Test Economics Advisor by Abadir et al. (see M. Abadir et al., "High Level Test Economics Advisor," Proceedings of the 2nd International Workshop on the Economics of Design and Test for Electronic Circuits and Systems, Austin (1993)). This is a tool developed by the Microelectronics and Computer Technology Corporation (MCC of Austin Texas) to analyze the economics of different test strategies for multi-chip module designs. MCC is a consortium of various industrial companies, and has a very broad effort to model the MCM manufacturing line, from bare die testing to module testing. From the published results, much of the inputs to the model are reasonable estimates provided by a test and a manufacturing expert. When using the MCC model for test strategy selection the user instantiates this template as needed to model the desired test strategy. Next, the user assigns values for the yields and test coverages based on his or her experience or data from previous products. The resulting prediction is a direct result of the subjective user inputs. The MCC economic model provides an environment where a test expert can perform trade-off analysis and arrive at an optimum test strategy, provided that the estimates used for yield and test coverage are accurate. However, its broad use as a concurrent engineering tool is not feasible because the typical board designer lacks the necessary expertise to run the tool. Also the accuracy of the MCC model is directly proportional to the accuracy of the expert estimates provided by users.
Economic models have been used to determine the optimum test strategy for a product. Although this is an important issue, a more pressing problem in DFM and DFT is the optimization of quality, testability and manufacturing costs for each new design, even when the test process is already established. The economic models described above were not developed for this purpose as evidenced by the fact that clustering of defects is not considered, a significant number of inputs is necessary, and the model inputs are subjective and need to be estimated by manufacturing experts, rather than design engineers.
SMT assembly yield modeling in particular, is an important part of Design for Manufacturing (DFM) and of Design for Test (DFT) of electronic products. If the yield can be estimated accurately, the manufacturing cost, the capacity of a manufacturing line, the procurement of material, and the on-time-delivery of the product can be properly managed. On the other hand, if yield predictions are inaccurate, the effects will be felt in the manufacturing process and also in the profit margin of the product. An accurate yield model is particularly needed when the product is in the design stage, when trade-offs in DFM and testability can still be made.
DFM Tools
Alexander et al. developed a cost advisor for a DFM environment (see M. Alexander et al., "Cost Based Surface Mount PCB Design Evaluation," Proceedings of the 2nd International Workshop on the Economics of Design and Test for Electronic Circuits and Systems, Austin (1993)). It evaluates the design based on the cost of assembling the board. SMT machines are selected based on the size and type of components, size and type of board, and solder paste used. The input is CAD data and the outputs are the assembly sequence, assembly cost and throughput rate. This tool does not address test at all but rather focuses exclusively on manufacturing cost issues.
Semiconductor Tools
In the semiconductor industry, economic manufacturing models have been focused on wafer yield. ICs cannot be repaired so the focus is to increase yield to minimize cost. Testing also adds a significant cost due to the high price of semiconductor test equipment. Currently used IC yield models account for clustering of defects (see J. A. Cunningham, "The Use and Evaluation of Yield Models in Integrated Circuits Manufacturing," IEEE Transactions on Semiconductor Manufacturing, Vol.
3, No. 2, 60-71, May 1990).
Test Equipment Analysis Tools
In addition, others have analyzed optimum board test strategy selection which shows a user how to write simple models to justify a given test strategy or how to justify the purchase of certain test equipment. These analysis have value in exposing contributors to total costs of manufacturing, but could not be used as a concurrent engineering tool due to the post manufacturing nature of the measurements and metrics used by board test equipment.
It is clear from the above discussion that a need exists for circuit design tools and methodologies which integrate manufacturing test issues at all stages of the circuit design process.
SUMMARY OF THE INVENTION
The present invention solves the above problems by providing computer operable methods to enable effective Concurrent Engineering of an electronic product to thereby improve manufacturability of the product in a cost effective manner. The methods of the present invention estimate costs and quality of a circuit design by applying various models in conjunction with information regarding the circuit design. Exemplary of such estimates are yield, defects, cost, testability and other manufacturing issues. The methods of the present invention are integrated with standard computer aided electronic design tools to permit the circuit designer to effectively estimate the impact of various design decisions on issues of manufacturability. Integration with the design tools permits these trade-offs between functional design and manufacturability to be considered at all stages of the product design cycle.
The present invention comprises a circuit board and Multi-Chip Module (MCM) manufacturing test simulator (hereinafter referred to as MTSIM). MTSIM is a concurrent engineering tool used to simulate the manufacturing test and repair aspects of boards and MCMs from design concept through manufacturing release. MTSIM helps designers during the design phases to select assembly process, specify Design For Test (DFT) features, select board test coverage, specify Application Specific Integrated Circuit (ASIC) defect level goals, establish product feasibility, and predict manufacturing quality and cost goals.
MTSIM models solder faults, manufacturing workmanship faults, component performance faults and reliability faults. Fault probabilities for the board are estimated based on the component type, component functionality and the assembly process used. Up to seven manufacturing test steps can be simulated. Test coverage models will support all currently used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, self-test, diagnostics and burn-in.
The present invention further comprises a new yield model for boards and MCMs which accounts for the clustering of solder defects. The new yield model is used to predict the yield at each test step. In addition, MTSIM estimates the average number of defects per board detected at each test step, and estimates costs incurred in test execution, fault isolation and repair.
MTSIM was developed to be used by designers in the optimization of the design for test and the design for manufacturability of their products. Therefore, MTSIM was implemented in the Mentor Falcon Framework (made and sold by Mentor Graphics Corporation, Wilsonville, Oreg.). This integration with standard design tools provides MTSIM with the same look and feel of other Mentor design tools to thereby encourage designers to test their designs at various design stages for testability and manufacturability.
MTSIM provides more precise estimates of manufacturability and test parameters of a circuit design to permit the designer to effectively design for manufacture and design for test. MTSIM provides quantitative estimates of fault probability, test coverage, test costs, and repair costs to thereby improve the design process over the use of prior report card tools.
MTSIM, in contrast with economic models, is a concurrent engineering tool, that is, a tool to predict manufacturing behavior while a product is still in the design phase. MTSIM provides "what-if" and pareto analysis capability, requiring minimum amount of user inputs and manufacturing data, and accurately simulating all aspects of manufacturing test early in the design phase. MTSIM has provides a better balance than do economic modeling tools between the needed user inputs and simulation accuracy. Fault clustering phenomena are accurately modeled in MTSIM. MTSIM is also suitable for test strategy optimization and assembly process defect simulation.
MTSIM requires minimum amount of inputs from designers and it is used to simulate the manufacturing test process of every new design. All simulations are performed at the component level, that is data is generated and simulated for each component instantiated in a board. A default library included in MTSIM models all manufacturing attributes necessary to predict quality, reliability, test coverage, fault isolation costs, repair costs and yields. In addition to simulation results, MTSIM provides pareto analysis to aid in maximizing benefit to manufacturability by selected design changes. This pareto analysis is provided at three different levels. The category pareto provides detailed simulation results grouped by component category. Each component is assigned a category based on its type. Pareto data is also available at the part number level, which groups results for multiple instances of the same part, and pareto data is also available on a per component basis.
The Manufacturing Test Simulator (MTSIM) of the present invention is a concurrent engineering simulation tool for manufacturing test, that is, a tool to predict manufacturing test behavior while a product is still being designed. Early prediction of manufacturing behavior drives design changes which optimize the product's manufacturability and testability, thus improving product quality and reducing cost.
Specifically, the present invention provides a method, operable on a computer, for estimating manufacturing test and quality attributes of an electronic assembly (including SMT circuit boards and MCM circuits) concurrent with the design of said electronic assembly. The method receives a description of the electronic assembly design from the user and pre-determined test and quality information relating to each component in said electronic assembly. The method also receives a description of a manufacturing test process.
The method then applies the pre-determined test and quality information to the supplied description of the electronic circuit design to simulate said manufacturing test process and thereby estimate said manufacturing test and quality attributes.
To simulate the operation of a manufacturing test, the predetermined test and quality information is applied to the electronic circuit design description to estimate an incoming fault probability value for each component in said electronic assembly. Next the manufacturing test process is applied to the electronic circuit design description and to said incoming fault probability value to estimate said manufacturing test and quality attributes.
The manufacturing test and quality attributes include: manufacturing test coverage, manufacturing test isolation, manufacturing test costs, assembly reliability, assembly repair costs, and assembly yield.
The incoming fault probability value (Pfi) of a component is determined as:
where:
n is the number of trials of a test step and is derived from said predetermined test and quality information,
fp is the probability of a fault occurring in a component in a test step and is derived from said pre-determined test and quality information.
The methods of the present invention includes a new model to determine assembly yield (Y) which accounts for the clustering effects typical of solder assembly defects. The yield is determined as:
where:
Ycl is the yield determined from clustered solder defects, and
Yncl is the yield determined from non-clustered assembly defects including functional defects. The clustered yield (Ycl) is determined as: ##EQU1## where: .alpha. is the clustering factor, and
Do is the estimated average faults per assembly as discussed below.
The non-clustered yield (Yncl) is determined as:
The average number of defects (Do) in said electronic assembly is estimated as: ##EQU2## where: Pfi.sub.j is the incoming fault probability value corresponding to the j'th said component in said electronic assembly as above,
TC.sub.j is a test coverage value corresponding to the j'th said component in said electronic assembly discussed below, and
N is the number of components in said electronic assembly.
The simulator of the present invention provides pre-determined test and quality information defining test attributes including: in-circuit, boundary scan, self test, functional test, incoming inspection, and visual inspection. The present invention also provides test coverage and isolation information for each test attribute appropriate for each component of said electronic assembly. The test coverage value used above to determine the average defects per assembly is determined to be the highest test coverage value of all test attributes appropriate to the component. This pre-determined information and other information known to manufacturing experts associated with the manufacture of electronic assemblies are contained in library files stored in the computer system on which the methods operate. The library files provide the expertise of manufacturing engineers and history to the user of the present invention to aid in design for manufacturability and design for testability of electronic assemblies concurrent with the functional design of those electronic assemblies.
The simulator of the present invention may also be utilized, in conjunction with a fixed electronic assembly design, to evaluate improvements in testability and quality attributable to changes in the manufacturing test process or changes in the manufacturing assembly process.
The present invention also provides pareto analysis ranking of said electronic assembly with respect to said manufacturing test and quality attributes of said electronic assembly, wherein said pareto analysis ranks each component used in said electronic assembly with respect to contribution to said manufacturing test and quality attributes. The pareto analysis may also be performed to rank unique part numbers as well as categories of components.
These and numerous other features, objects, and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 depicts an exemplary computer system which comprises the manufacturing test simulation methods of the present invention;
FIG. 2 is a high level flowchart indicating describing typical use of the simulation methods of the present invention for DFT and DFM design processes;
FIG. 3 is a block diagram indicating the relationship of inputs and outputs with the simulation methods of the present invention;
FIG. 4 is a flowchart indicating the overall flow of the simulation methods of the present invention;
FIG. 5 is a flowchart showing additional detail of the simulation steps of FIG. 4 which simulate each configured test step defined by a given test process;
FIG. 6 is a flowchart of a typical test process capable of being modelled by the simulation methods of the present invention;
FIG. 7 is a flowchart showing the detail of steps in FIG. 4 which estimate test coverage and isolation values;
FIG. 8 is a plot of a typical "bathtub" curve showing the failure rate of an electronic circuit as a function of its lifetime;
FIG. 9 is a family of plots of yield as a function of average number of defects for various alpha weighting factors;
FIG. 10 is a flowchart showing additional detail the initialization of the simulation methods shown in FIG. 4;
FIG. 11 is a block diagram indicating the relationships between elements of the simulators database and the simulation methods associated therewith;
FIG. 12 is an image of a user display screen and menu which is used to control the operation of the simulator of the present invention and to display simulation results;
FIG. 13 is a block diagram indicating the relationship of various simulation models to portions of the simulation methods of the present invention; and
FIG. 14 is a detailed flowchart describing the accumulation of test information through simulated operation of the test process used in the simulation methods of FIG. 4.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
OVERVIEW
FIG. 1 shows a block diagram of the manufacturing and test simulation system 120 of the present invention. In FIG. 1, a computer system 100 contains a processing element 102 which communicates to other elements within the computer system 100
over a system bus 104. A keyboard/mouse 106 is used to input information from a user of the system, and a display 108 is used to output information to the user. A network interface 112 is used to interface the system 100 to a network 118 to allow the computer system 100 to act as a node on a network and to thereby communicate with other nodes on the network. A disk 114 is used to store the software of the manufacturing and test simulation system of the present invention and to store the data relating to product designs and simulations. A printer 116 can be used to provide a hard copy output of the simulation results.
A main memory 110 within the system 100 contains the software methods of the manufacturing and test simulation system 120 of the present invention. A computer aided electronic design program 126 is integrated with the simulation system 120. Both rely on services supplied by an operating system 122 and storage management software 124 to perform the manufacturing and test simulations requested by the product designer. The computer aided electronic design programs 126 may operate locally, within computer system 100 or may operate on other computer systems attached to, and communicating over, network 118. It will also be recognized by those of ordinary skill in the art that the information stored locally on disk 114, may also be stored locally in main memory 110, or may be distributed over other computer systems accessible via network 118, or in any combination of storage devices. More generally, the information used by the design program 126 and the simulation system 120 may be stored in any memory device having suitable capacity and performance characteristics.
The simulator of the present invention operates in cooperation with computer aided electronic design tools to predict behavior of an electronic circuit design based on software models of the key components of the product being modeled. Simulation output is based on the circuit board topology (the layout of the board and the components used), the testability attributes of the circuit board, models of the manufacturing process, and models of the test process. By using this approach, circuit designers are able to simulate manufacturing test of their designs, and based on the simulation outputs, make changes to the design which will improve the quality and reduce the manufacturing cost of the product. Without the simulator of the present invention, the need for design changes will not be apparent until the product reaches volume manufacturing. Once the product is in volume manufacturing, the only alternative to implement changes is a costly redesign.
At the highest level, the simulation approach of the present invention models fault probability, test coverage, isolation costs, and repair costs for each component, at all test steps in manufacturing. Aggregate board measures of quality and cost are derived from the per component simulation data.
The selection of fault models in the simulator of the present invention reflects a delicate balance between modeling detail, and availability of input data. As discussed above, previous approaches attempted to provide accurate models by modeling a large number of fault classes, thus rendering the model practically unusable in the manufacturing environment due to lack of input data. In the simulator of the present invention, the fault models selected were solder faults, workmanship faults, functional faults, and reliability faults. This selection was based on examining historical failure data in manufacturing environments to conclude that this fault breakdown is sufficient to obtain simulation results accurate to within 10% of manufacturing historical data. These selected fault classes in the simulator of the present invention require only manufacturing defect data which is readily available on databases of most manufacturers. Validation of these fault models with actual manufacturing data demonstrates accurate simulation results.
The statistical models respect the underlying assumptions of the distribution theory on which they are based. Namely, all simulation is performed on a per component basis, thus insuring that defect rates are sufficiently small. This allows the usage of average PPM (parts per million) failure rates as model inputs. Average PPM failure rates are commonly available in manufacturing databases.
Current board yield models are based on a binomial distribution of defects. This approach predicts the yield well for assemblies which are not very complex. However for complex SMT (surface mount technology) boards, namely boards for which the average number of defects is greater than one, the binomial model will underestimate the yield since there is significant clustering of defects in a SMT production line. The manufacturing test simulator (MTSIM) of the present invention introduces a clustered yield model based on the negative binomial distribution, and discussed below.
Test coverage and test isolation models were developed to estimate the test coverage and the fault isolation capability of each test step. This innovation replaces the need of a manufacturing test expert to subjectively estimate test coverage and test isolation levels, as is the case in all previous approaches discussed above.
Finally, the present invention provides accurate quantitative results, including fault probabilities, test coverages, test costs, and repair costs, as discussed below. The approach also supports "what-if" and pareto analysis of any manufacturing attribute simulated as discussed below.
MTSIM METHODS
The methods of present invention are integrated with the circuit design environment with the same look and feel of other design tools. In addition MTSIM's test coverage model shelters the user from intimate knowledge of manufacturing test techniques, providing estimates for test coverage and test isolation of all test techniques available in board test. The test steps are fully configurable by a designer/user of the simulator, and repair and shipping can be enabled or disabled at each step.
One of the key objectives of MTSIM is to be a part of the design cycle. To this end, MTSIM minimizes the need for user input, as compared to prior approaches, by providing a library containing manufacturing data. This library is used by the simulator models to predict the manufacturing attributes of a board. The library is originally set up by a manufacturing expert, and then used by numerous designers. The result is that designers can simulate manufacturing test issues without becoming manufacturing experts. In contrast, all the previous work, described above, requires a manufacturing expert to run the model for each individual board design.
"What-if" and pareto analysis are also unique contributions of MTSIM. During pareto analysis, the user can evaluate simulation results sorted to determine the top pareto contributors in faults, test coverage, isolation time, repair cost etc. Pareto analysis can be done at three levels of abstraction, namely: individual components, groups of components with the same part number, and groups of components with the same component category. All part numbers are assigned a category based on the type of package, level of integration and functionality. "What-if" analysis assists the user in optimizing the test process flow, optimizing test coverage, minimizing defect rates, establishing appropriate levels of DFT investment, and establishing a reliability screen. Usually, "what-if" analysis will follow pareto analysis. During pareto analysis, major contributors to poor quality and test/repair costs are exposed, which drives the changes made in the next "what-if" analysis. This cycle continues until the optimum trade-offs are achieved.
Finally, the implementation of reliability models completes the tool, providing estimates on failures which will appear once the board has left the manufacturing floor and entered the warranty period in the customer environment. A bathtub curve can be generated based on data from a life test and an appropriate screen can be set up as part of the test process.
MTSIM USE
FIG. 2 shows a block diagram of MTSIM use. One purpose of the simulator is the designer's use for DFT and DFM of electronic circuit assemblies. When products are in their inception, a developer would perform a market analysis and estimate the size of the market and the retail value of the product. In addition, manufacturing is expected to provide an estimate of the manufacturing cost of the product. A large portion of the manufacturing cost is test and repair. The developer is also concerned with yields and outgoing quality from the manufacturing process. Designers using prior approaches make these estimates in a vacuum without any feedback.
MTSIM is used in this early phase, labelled "Level 1" in FIG. 2, to accept information regarding the circuit design and product goals then simulate the manufacturing and test processes and their key attributes. DFT of the product, including part selection and assembly process selection, will greatly influence the manufacturing test and repair. MTSIM exposes these sensitivities, providing feedback to the designer and ultimately driving changes in the design and DFT which optimize the product.
Once the original goals are agreed upon and the product enters the design phase, MTSIM can be used to predict the effect of unforeseen changes that occur during product development phase labelled "Level 2" in FIG. 2.
In addition, MTSIM is useful in conjunction with manufacturing process development. New assembly and test processes can be simulated before they are introduced, allowing for process tuning without affecting product ramps. This use of the simulator of the present invention is discussed below with respect to Test Process Simulation and Assembly Process Simulation.
DFT AND DFM SIMULATION (LEVEL 1 AND LEVEL 2)
All projects go through an early phase of validation and feasibility in the market place, which culminates at a review milestone when the project is either cancelled or proceeds to product development. It is preferable to negotiate testability features at this early planning phase. This is also the appropriate time to select the assembly technology used and the level of integration of ASICs. This early planning phase is labelled "Level 1" in FIG. 2.
Element 200 of FIG. 2 is representative of the planning for the desired circuit functionality (not necessarily the circuit design). Element 202 next operates to evaluate the planned functionality with respect to market requirements. Element 204
operates in conjunction with element 200 to iteratively refine the planned functionality to improve the product functionality with respect to manufacturing issues. The simulator use in this early phase is summarized in the following flow:
Establish preliminary cost and quality goals for the product
Create preliminary board placement or components list from desired architecture
Outline known testability features
Select assembly process
Build simulator model
Use MTSIM to predict and optimize testability, quality, cost, integration and technology
The optimization described above with respect to element 204 is driven by pareto analysis of top contributors to poor quality and high cost. For example, MTSIM can compare the available assembly processes and determine the best yield versus assembly technology trade off.
Once the product proceeds to the development phase, the same simulator model is updated as more information becomes available. The simulator of the present invention is utilized in conjunction with the circuit design tools to refine the circuit design with respect to manufacturing test issues. Element 206 represents the operation of the computer aided electronic design tools. At any time in this design process, the circuit designer may invoke the simulator, represented by element 208 to evaluate the design with respect to manufacturing issues. In this phase, labelled "Level 2" in FIG. 2, the simulator is used to:
Define DFT needs on ASICs and board
Optimize ASIC defect level goals
Validate design partition
Validate assembly process choices
Optimize board test coverage levels
Predict effects in manufacturing test due to changes on the proposed DFT strategy
As the product is ready for manufacturing, the actual cost and quality goals are obtained directly from MTSIM simulation output. These cost and quality figures can be validated once the product reaches production. The validation can be used to continually improve MTSIM's accuracy. The outputs generated by the simulator are discussed in detail below.
TEST PROCESS SIMULATION
The test process is defined as the physical flow of a board through the test equipment and the kind of test equipment selected. A test engineer can use MTSIM to compare various test process and test equipment options. The simulator is used to model an existing board to establish a known starting point. Next, the simulator may be re-run with changes to the physical test process or test attributes of the test steps. Changes in the simulated product manufacturability may then be attributed to the change in physical test process.
ASSEMBLY PROCESS SIMULATION
MTSIM may be used to predict improvements attributable to changes in the assembly process. A process engineer uses MTSIM to estimate the manufacturability of a product design, then may iteratively evaluate the improvement in the product due to changes in the simulated assembly process used by the simulator. Such an assembly process evaluation is outlined as follows:
Simulating a product in the released process to establish a valid starting point
Create an assembly library for the new assembly process, simulate the same product again, and observe the predicted changes in the product quality, yield and cost
MTSIM is used to target resources, capacity, yields, coverage, cost and other production changes due to the new assembly process.
MTSIM ARCHITECTURE
FIG. 3 depicts a high level description of the Manufacturing Test Simulator (MTSIM). The inputs 350 to the simulator 300 are depicted collectively at the left hand side of the simulator 300. The outputs 352 of the simulator 300 are depicted collectively at the right hand side of the simulator 300. The outputs 352 of MTSIM are manufacturing metrics which clearly communicate to designers how to improve the manufacturability of a board.
Inputs 350 to simulator 300 include several parts supplied by the circuit designer or by manufacturing process/test engineers. DFT features 304 of the design include test points, IEEE 1149.1 implementation, and BIST implementation. DFT features
304 are used to estimate coverage and isolation capabilities of a test. The VHDL model 306 of a board and its functional test code are used by other tools to estimate test coverage of the functional test code 308. The test coverage is read in by MTSIM and used in its test coverage modeling.
Design data 302 is supplied to simulator 300 by the circuit designer through operation of the computer aided electronic design system (e.g. Mentor's design database). This input describes the components and other design selections of the circuit designer in the creation of the product.
Outputs 352 of simulator 300 include fault probability 312, an estimate of the probability of faults on the board. Fault probability 312 estimation is useful in "what-if" exercises with different assembly processes and component failure rates. Test coverage 314 is a measure of the effectiveness of each test step in terms of fault detection. Test coverage 314 is a function of the DFT of the board. Test coverage 314 determines the output quality for a given fault spectrum. Test Isolation 316
is a measure of the test process' ability to isolate a fault to a given component, to a functional block or to a defect. Test isolation 316 to a defect via root cause analysis is extremely important in both the cost and the quality improvement cycle. Yield 318 gives the quantity of boards which will pass each step of the test process without failures. Yield 318 also determines manufacturing capacity. Reliability 320 gives an estimate of both the infant mortality failure rate and the useful life failure rate of a manufactured circuit design. Cost of test 322 estimates the cost of testing and repairing a board, including the cost of labor, test time, component cost and capital equipment cost. Defect rate 324 is the probability of faults left in a board after it has passed the board test process, which is a measure of the quality of a product.
MTSIM INTERNAL DESIGN
The MTSIM simulator 300 handles I/O operations, models the relationships between the design and the manufacturing processes, calculates all significant attributes, generates outputs, generates pareto analysis and controls "what-if" analysis. The simulator 300 is shown in additional detail in FIG. 13.
As shown in FIG. 13, the simulator core 1300 has various components which serve to simulate different attributes of the manufacturing process of an electronic circuit design. The segments of the simulator core 1300 are labelled "CORE", "YIELD", "AVG # DEFS", and "COSTS". The simulator core 1300 is associated with the MTSIM library 1302 which is set up by an administrator and contains information on the manufacturing test process, the SMT assembly process, and the components used in the board. The library only needs to be set up once for the target manufacturing site, and then is used in the simulation of multiple assemblies.
Various models are utilized by simulator core 1300 to emulate assembly and test processes. In some cases, statistical models are used, and in other cases deterministic measures are used. These models, are shown in FIG. 13 as elements 1306
through 1324. Since manufacturing is not an exact science, the goal for these models is to provide a first order approximation of the manufacturing process based on empirical data gathered from past manufacturing experience. However, the modular architecture of simulator core 1300 of the present invention allows for inclusion of later developed, more accurate models. The ability to add new models is shown in FIG. 13 as future models 1326 with a dashed line to indicate its optional addition to the present invention. The various models used with the present invention are discussed in detail below.
USER INTERFACE
When running the simulator core 1300, a user needs to select the assembly process, and to specify the test process if different than the default provided. These data are provided by user interface 1304 of FIG. 13 to the simulator core 1300. The user interface 1304 represents the provision of information from the user to the simulator core 1300. This information may be provided as interactive input via keyboard/mouse 106 and display 108 of FIG. 1 or by files previously entered and stored on disk 114 also of FIG. 1. In addition, information may be required from the user as follows:
COMPONENT FILE--file containing the component part number, reference designator, Mentor design geometry, and component count. The component file can be obtained directly from the Mentor design database (design data 302 of FIG. 3), or provided in ASCII format by the user either interactively or through standard text editors to create an input file.
TEST ACCESS FILE--optional file which contains the number of component pins that have test access either via test points or boundary scan cells. The test access file is to be supplied by the user who obtains the information from the Mentor design database (design data 302 of FIG. 3).
COVERAGE FILE--optional file which contains self-test coverage for each component, if available from a VHDL coverage metric tool (VHDL model 306 of FIG. 3).
MTSIM CONTROL
Control of simulator 300 (of FIG. 3) is carried out by methods operable on computer system 100 of FIG. 1 which perform and coordinate interactions among the user, the various internal databases, and the models. In general these methods have two modes, direct mode and "what-if" mode. In the direct mode the simulator 300 uses the assembly and test processes, selected by the user, to perform the simulation and deliver the outputs back to the user for further use in improving the DFT and DFM of the electronic circuit. In the "what-if" analysis mode, the user can modify any of the available libraries and parameters, rerun the simulation and compare the results. FIG. 4 depicts the overall flow of control in the operation of simulator 300.
As depicted in FIG. 4, the simulation methods control all MTSIM activities. Boxes in dotted lines represent a step dependent on user interaction or user supplied information. Elements 400, 402, and 404 represent the start of a typical simulation. By operation of these elements, the user supplies basic setup information such as the directory or name which identifies the product design object to be simulated. This directory or name is used to identify and locate files which needed for the circuit design simulation and also serve to identify the location of database files created by operation of the simulator. It should be noted that multiple simulations can be created for the same design object. Each of these multiple simulations is self contained and can be rerun at any time. Once the user provides a simulation name, MTSIM checks if the simulation with that name already exists. If one exists, MTSIM asks the user whether the simulation is to be rerun with previous setup values or with new setup values and whether the results are to be appended to previous results or overwrite previous results. If this is a new simulation, MTSIM creates a directory with the simulation name under the appropriate directory. Next MTSIM asks the user if a Mentor component file is to be used, or a custom component file. Based on the answer MTSIM parses the input file to read in the parts list from the component file. Next MTSIM checks for the existence of library files required to run the requested simulation on the requested product. If any library files are missing or otherwise unusable, the process terminates with an error as shown in element 406.
The first step on a new simulation is to make copies of the MTSIM default libraries under the newly created simulation directory. Other files are created in the identified directory as needed for the requested simulation as follows:
______________________________________ "comp.sub.-- file.sim" Parsed version of the input component file "mtsim.sub.-- lib.sim" MTSIM library file for each component used "tst.sub.-- proc.sub.-- lib.sim" Test process library simulation file "tst.sub.-- para.sub.-- lib.sim" Test parameter library simulation file "assy.sub.-- proc.sub.-- lib.sim" Assembly process library simulation file "func.sub.-- dr.sub.-- lib.sim" Functional defect rate library simulation file "reli.sub.-- dr.sub.-- lib.sim" Reliability defect rate library simulation file "repl.sub.-- time.sub.-- lib.sim" Replacement times library simulation file "tst.sub.-- access.sub.-- file.sim" Test access library simulation file "funccov.sub.-- file.sim" Functional coverage library simulation file "reli.sub.-- dat.sub.-- lib.dss" Reliability life test data library simulation file "reli.sub.-- plot.sub.-- lib.dss" Reliability life test plot simulation file "comp.par" Component pareto file "pnum.par" Part number pareto file "categ.par" Category pareto file "tst.sub.-- pareto.sub.-- file.sim" Test access pareto simulation file "report.sim" ASCII output of the simulation results ______________________________________
Once all the simulation files are created, MTSIM element 408 of FIG. 4 starts building a database for the simulation on a per component basis. For each component, the simulation libraries containing manufacturing test data for each component are evaluated and the data used by the circuit design is loaded. Also the library information for various defect rates, test process, and repair profile is loaded.
The next step in the simulation is to evaluate the models, including the assembly defect model, the functional defect model, the test coverage model, the test isolation model, and the repair model. All these models are evaluated on a per component basis by operation of element 410 of FIG. 4.
Next, MTSIM starts simulating the circuit by operation of element 412. For each test step enabled, and for each component, MTSIM calculates the fault probability in and out of a test step, the average number of defects detected at a test step, the isolation and repair times at the test step, and the volume into the next step. The yield and cost of each step is also calculated. Reliability estimations are made, aggregate output is generated and the output is displayed in the user interface window by operation of element 416.
MTSIM is capable of performing "what-if" analysis for every parameter of the simulation wherein a particular parameter or set of parameters is changed and the entire simulation re-run. In this manner, the contributions of individual parameters to the overall product manufacturability can be isolated and evaluated. Based on top pareto output information, the user can modify an entry in one of the library file menus and re-run the simulation, generating new results for comparison. These what-if simulations can be stored for further evaluation. Typical what-if simulations will include changes in the test process flow, sensitivity analysis on defect rates, sensitivity analysis on test coverages, and comparison of assembly processes.
Element 418 is operable to determine whether the user wishes to perform "what-if" analysis. The user is then prompted to enter the desired "what-if" changes and element 418 continues operation of the process with element 402, 410, or 412
depending upon the nature of the changed parameters. Certain changes may require re-reading the parts list by operation of element 402, while others may require the re-evaluation of the manufacturing models by operation of element 410.
Element 420 is operable to save the present settings for the operation of the simulator. Saving the state of the simulator permits later continuation of the "what-if" analysis by the user. If a user desires to resume "what-if" analysis from a previous simulation run, the previous simulation is identified as described above by operation of element 400, and then processing continues with operation of element 414 to read all required settings from the previously saved simulation run.
FIG. 14 provides additional detail of the operation of element 412 of FIG. 4 which calculates quality and cost measures for the selected test steps in the test process model supplied to the simulator. Element 1400 is operational to loop over all defined test steps in the current test process model provided to the simulator. As discussed below, up to seven test steps are allowed in the preferred embodiment of the simulator though any number may be selected for a particular implementation. If more test steps are yet to be simulated, element 1400 continues processing with element 1402. Otherwise, element 1400 continues processing with element 1420 to total all estimated yields and costs for reporting to the user.
Element 1402 reads information defining the next test process step to be simulated from the test process definition library files discussed below. Element 1404 then operates determine the incoming fault probability. The incoming fault probability is the outgoing fault probability of the preceding step as discussed below with respect to element 1416. For the first test step, the incoming fault probability is estimated from the circuit design information supplied by the circuit designer. Element 1406 is then operable to simulate the defined test step to determine the coverage, isolation and costs of the test step.
Element 1408 determines whether or not the circuit would pass the test step, simulated by operation of element 1406, given the incoming fault probability. If the test would fail to pass the circuit, element 1410 is operable to determine whether the repair option is enabled for the current test step. If the repair option is enabled, element 1412 determines and accumulates the additional costs associated with repair and re-test of the circuit. Processing then continues by looping back to element 1408 to determine if the simulated re-test would pass the circuit. Additional repair and re-test loops are possible and element 1412 operates each time to accumulate the additional repair and re-test costs.
If the circuit fails to pass the simulated test step of element 1406 (or re-test of element 1412) and the repair option is disabled for this test step, then repair and further testing is skipped and processing continues with element 1416.
If the circuit passes the simulated test step of element 1406 (or retest of element 1412), then element 1414 determines whether the ship option is set to stop simulation of later test steps. If the ship option is set, then the circuit, having passed the simulated test or re-test, has completed the simulated test process and the method continues with operation of element 1420 to total the costs and yield as described above.
If the ship option is not set, then the process continues the test process by determining the outgoing fault probability after the simulated test step. This outgoing fault probability is used as the incoming fault probability of the next test step defined in the test process. Element 1418 is then operable to determine the product yield resulting from the operation of the current test step. Processing then continues by looping back to operation of element 1400 to process further test steps in the test process as described above.
This test process simulation provides the designer the flexibility to estimate costs and yields for many different models of manufacturing test. A variable number of test steps may be defined. Each test step may include or exclude a repair and re-test cycle. Each test step may optionally terminate testing if a circuit passes the simulated test step.
MTSIM MODELS
As mentioned above, the MTSIM methods of the present invention utilize a number of models to describe various process and product parameters useful in simulating the manufacturing test of an electronic circuit design. Listed below are the models as depicted in FIG. 13 followed by a more detailed description of the purpose and content of each model:
1. SMT XYZ MODEL (1306) and MCM MODEL (1308)--Estimates the expected assembly failure rates from the process being used. Statistical model of the assembly process used.
2. ASIC MODEL (1310) and MERCHANT MODEL (1312)--Models the functional defect rate of a custom ASIC or merchant components.
3. COST PROFILE MODEL (1314)--Models the cost of executing a particular test process in the manufacturing floor. Includes the cost of operators, technicians and capital equipment.
4. TEST PROCESS MODEL (1316)--Models the dynamics of the test process as implemented in manufacturing.
5. TEST COVERAGE MODEL (1318) and TEST ISOLATION MODEL 1320)--Models the coverage and isolation of the test attributes of each test step. Test attributes include in-circuit, Boundary scan, self test, functional test, incoming inspection, visual inspection and others.
6. RELIABILITY MODEL (1322)--Estimates the useful life defect rate and infant mortality of the boards being simulated.
7. REPAIR PROFILE MODEL (1324)--Provides the repair profile for standard packages and faults.
An accurate characterization of the fault probability is the first step in board and MCM simulation. Fault probability and test coverage are used to estimate the average number of defects per board. The fault probability spectrum can be broken into three major parts: the assembly faults caused by the SMT manufacturing process (such as solder opens, solder shorts, misloads, cracked etc.), functional faults, which include single component performance faults and multiple component interaction faults, and reliability faults which accounts for failures in time. The SMT XYZ (1306) and MCM (1308) models address the assembly fault probability, the ASIC (1310) and Merchant (1312) models address the functional fault probability and the Reliability model (1322) addresses the reliability fault probability. Various of the above identified models are discussed in detail below.
FAULT PROBABILITY MODELS
The assembly fault probability model and functional probability model are based on a binomial distribution of defects. To calculate the fault probability before test, consider a series of n independent trials, each resulting in either a fault or no fault, with fp being the fault probability in any trial. Further assume that fp remains constant from trial to trial. Then defining X as the random variable for the number of faults in n trials, the probability of k faults in n trials has a binomial distribution given by: ##EQU3## In the MTSIM methods, we are interested in the probability of at least one fault, which is one minus the probability of zero faults. To obtain the probability of zero faults in n trials, we set k to zero in the Equation (3.1) and obtain:
Then the probability of at least one fault before test, Pfi, in n trials with fault probability fp is:
In practice, it is not easy to obtain the fault probability fp for every component and every type of solder joint. In order to apply this model in the real world of manufacturing, we need to estimate the fault probability fp by defining the average point estimate fault probability, AvgFP, as: ##EQU4## where NF is the number of units that failed a certain test and NT is the total number that participated in that test. In the case of manufacturing data we approximate this average point estimate of the probability of a failure with data collected over the manufacturing life of components and solder joints. This data is usually kept in an average parts per million basis (PPM). In the case of new assembly process, estimates of the average point estimate of the probability of a failure are obtained from the research and development of the new process. In the case of new ASIC designs, estimates are obtained from defect level models. For released processes and for components that are already part of inventory, this is a matter of characterizing current products to obtain the failure data.
The fault probability after test, Pfo, can be derived as follows. Assume there are n faults in the component, and m out of the n faults are covered by the test, that is, the test coverage is m/n. Define A as the event in which the component has
0 faults, and define B as the event in which m out of n faults have been tested and were found good. The probability of zero faults after test is equal to the probability that the component has zero faults given that m out of n b have been tested good. This probability is the conditional probability of event A given event B, expressed as: ##EQU5## but, the probability of A intersect B is equal to the probability of A which from
The probability of B is the probability of zero faults out of the m tested faults, given as:
by substitution we have: ##EQU6## or:
rearranging, we obtain: ##EQU7## however, we are interested in the probability of at least one or more faults after test, Pfo, which is one minus the probability of zero faults after test, or one minus the probability of A given B. We also substitute the test coverage for m/n in Equation (3.10), obtaining:
Putting this in terms of the incoming probability of zero faults Yi, we obtain:
Putting this in terms of the incoming probability of at least one fault Pfi, we obtain:
where the probability of faults after test, Pfo, equal to one minus the incoming yield (1-Pfi) to the power of one minus the test coverage. From these equations it can be seen that high test coverage is imperative to minimize the probability of at least one fault after test.
In MTSIM all simulations are performed on a per component basis. When aggregate calculations are performed, statistical independence is assumed to calculate fault probability for multiple components. This statistical technique is known as multiplying the yields. When using this technique for n components, each with its own independent fault probability, then the probability of zero failures in the n components is equal to the product of the probability of zero faults in the individual components.
However, there is a potential problem with this independence assumption. When dealing with complex boards, the average number of defects per board can be greater than one, that is, a board will have on average more than one defect. In this case the overall PPM level for assembly failures will become very close to one million or a probability of one. Since we are multiplying the yields, the overall fault probability of the board will be limited to a maximum of one million PPM and that would underestimate the average number of defects per board.
MTSIM methods of the present invention avoid this problem by using the following methodology: since all calculations are performed on a per component basis, the probability of at least one fault is small enough such that the statistical assumptions hold on a per component basis. When aggregate board calculations are performed, they are based on the average number of defects per board which is not limited by the PPM ceiling when the computation saturates. Rather, it is an averaging of all of the defects on the board. The average number of defects per board, Do, found after test for each type of test is computed as follows: ##EQU8## where N is the total number of components, the fault probability, Pf, includes all types of faults modeled in MTSIM, and TC is the test coverage. These statistical techniques (equations (3.3) and (3.13)) are used in the development of the fault probability models for assembly and functional defects.
ASSEMBLY FAULT PROBABILITY
The SMT XYZ (1306) and MCM (1308) models take the defect rate per joint given in the assembly library file, and assume a binomial distribution of defects to compute the probability of at least one fault per component before and after test.
The first aspect of assembly defects is the solder joint fault probability. Let Psfi be the probability of at least one fault per component before test, Psfo be the probability of at least one fault per component after test, sDR be the defect rate per joint from the SMT XYZ (1306) or MCM (1308) model (also referred to herein as library), N be the number of leads in the component and aTC be the assembly test coverage. Then Psfi and Psfo are expressed as:
where, sDR/1000000 is the average point estimate for solder joint fault probability obtained from the PPM based solder joint defect rate sDR, [1-sDR/1000000].sup.N is the probability of zero solder joint faults in a component with N solder joints, and
[1-Psfi].sup.(1-aTC) is the probability of zero solder joint faults for the component after test.
The other aspect of assembly defects is the workmanship fault probability. Workmanship defects are defined as defects which occur during the manufacturing assembly process, but are not solder related defects. We assume that workmanship defects occur on a per component basis and include reversed components, wrong value components, wrong revision components, etc. Let Pwfi be the probability of at least one fault per component before test, Pwfo be the probability of at least one fault per component after test, wDR be the component workmanship defect rate from the SMT XYZ or MCM library, and aTC be the assembly test coverage. Then Pwfi and Pwfo are expressed as:
where, wDR/1000000 is the average point estimate for component workmanship fault probability obtained from the PPM based workmanship defect rate wDR, and
[1=Pwfi].sup.(1-aTC) is the probability of zero workmanship faults for the component after test.
FUNCTIONAL FAULT PROBABILITY
In the case of functional defects the incoming functional defect level is obtained either from the functional defect rate library or from the component library. The model assumes a binomial distribution of defects to compute the probability of at least one fault per component before test. Let Pffi be the probability of at least one fault per component before test, Pffo be the probability of at least one fault per component after test, fDR be the component functional defect rate, and fTC be the functional test coverage. Then Pffi and Pffo are expressed as:
where fDR/1000000 is the average point estimate for component functional fault probability obtained from the PPM based functional defect rate fDR, and [1=Pffi].sup.(1-fTC) is the probability of zero functional faults for the component after test.
COST PROFILE
The cost profile model (1314) estimates the overall cost of testing the board. It is a model of the factory floor. Given the test times, the test process, the isolation and the repair information, it will estimate the cost of testing the assembly.
The cost profile model provides an accurate view of the financial aspects of testing the board. The labor and equipment rates given in the test process library need to account for utilization and efficiency. Also, overhead charges due to information system transactions or extra handling are to be included in the test operator time. There are four contributors to the cost of testing the board:
TEST OPERATOR COST--Operator cost to test and retest boards
TEST CAPITAL COST--Equipment cost to test and retest boards
TEST ISOLATION COST--Technician cost to isolate defects
COMPONENT REPAIR COST--Operator cost to repair boards
These costs are based on the average number of defects per board for each test step. The test operator time and test equipment time are functions of the board volume and of the number of defects. The board volume may decrease during the test process if boards are shipped after a given test step. MTSIM assumes that all boards that have a defect and are repaired in a given test step are also re-tested on that step. Isolation time and repair time are calculated on a component basis based on the type of fault and the type of component. Test times, isolation times and repair times are turned into costs by using the test and labor rates provided in the test process library as follows:
OPERA.sub.-- RATE--Labor rate for operator in test execution $/hr
CAP.sub.-- RATE--Rate for equipment used in test execution Cost $/hr
ISOL.sub.-- RATE--Labor rate for operator or technician in fault Isolation $/hr
REPL.sub.-- RATE--Labor rate for operator or technician in fault repair $/hr
TEST PROCESS
The test process simulates the physical test process of board manufacturing, that is, the physical test steps which will be performed in the manufacturing of the board. Once the physical process is established, the structure of the simulator is derived from the test process model (1316). The data needed for test coverage, test costs, and repair costs is obtained from the appropriate models (e.g. 1318, 1320, 1314, and 1324).
FIG. 5 is a general block diagram for the test process. The designer/user of the present invention specifies the test process via the test process library menu, described below. The test process model (1316 of FIG. 13) creates a linear flow for boards. Boards start at the test step which is declared in the test process library menu as the first step 500 of FIG. 5 (TEST.sub.-- ORDER=1), and follows on through all of the enabled test processes. If the simulated test of the product by operation of element 500 fails then repair can be performed, or not performed, at each step as determined by operation of element 502 (REPL.sub.-- ENABLED flag). If the simulated test of the product succeeds in operation of element 500, then boards may exit to the next level of system integration at any step as determined by operation of element 506 (SHIP.sub.-- ENABLED flag). It is assumed that all boards will ship to the next level of system integration from the last test step with the fault probability remaining in the boards. This remaining fault probability can be interpreted as the incoming fault probability in the next level of integration such as system test. If the simulated test failed in operation of element 500 and the repair simulation option is enabled as determined in operation of element 502, then element 504 operates to simulate the repair efforts to repair the failed product. Costs associated with such a repair are estimated by the simulator operation of element 504. The repaired product is then retested by repeated operation of element 500 as described above.
If repair of simulated product failure is disabled as determined by operation of element 502, or if the product passes the simulated test and the modelled product is not shipped following the test success as determined by operation of element
506, then the test process continues to the next simulated test at element 508 of FIG. 5 (TEST.sub.-- ORDER=2). Elements 508-514 operate identically to elements 500-506, respectively, to perform a second simulated manufacturing test. Additional elements, indicated by dotted line descending from element 514, may be included to simulate additional manufacturing test steps. The test process model depicted in FIG. 5 is extendible to include optimization simulations.
FIG. 6 depicts a more complex example of a test process flow which may be simulated by the methods of the present invention. In this example the user has defined several test steps to be simulated. The visual inspection test step of element 600
is an operator manual screening process to detect assembly defects. If the inspection reveals assembly faults, repair procedures are simulated by operation of element 602. The aging step of element 604 simulates the aging of the board to reduce infant-mortality failures. The nature of an aging step of element 604 is such that there is no mode of failure for the simulated test step. The repair option is thus irrelevant with respect to this test step. The pre-test step of element 606 is used to provide a high level of functional coverage early in the test process. The repair process associated with the failure of this pretest step of element 606 has been disabled as configured by the designer/user of the simulator. Thus, products which fail the pre-test element 606 are sent directly to the ATE test element 612 because element 608 always determines that repair is not required. However, the boards which pass the pre-test step are optionally shipped and do not have to go through the remainder of the test. Operation of element 610 determines whether products which pass the pre-test element 606 go directly to shipping or must first go on to more rigorous testing in further test elements, beginning with ATE test in element 612.
ATE test element 612 provides high levels of coverage and efficient isolation for assembly faults. Circuits which fail the simulated ATE test element 612 are next routed through a simulated repair element 614 to estimate the costs of required repairs. Repaired circuits are then re-tested by operation of ATE test element 612 until the circuit passes the ATE test element 612. Selftest element 616 and diagnostic test element 620 and their respective repair elements 618 and 622 operate identically to elements 612 and 614 to simulate further manufacturing test and repair operations. Self-test element 616 and diagnostic test element 620 provide high levels of coverage for both assembly and functional faults.
TEST COVERAGE MODELS
The most difficult parameter to estimate in the simulator of the present invention is the test coverage. Unlike prior approaches which merely guess at test coverage and isolation values, the simulator of the present invention derives a coverage and isolation estimate based on the attributes of the test step and the DFT attributes of the components and circuit design. FIG. 7 is a high level view of the test coverage model algorithm.
As shown in FIG. 7, element 706 is operated within three nested loops. The innermost loop invokes element 706 once for each test attribute of a component under control of element 704. This innermost loop, comprising elements 704 and 706, is operated by the next loop once for each component in the circuit design under the control of element 702. This middle loop, comprising elements 702-706, is operated by the outermost loop once for each test step selected in the simulator test models under control of element 700.
Each invocation of element 706 in the triple nested loops of FIG. 7 computes the test coverage and test isolation for a particular test attribute of a particular component in a particular simulated test step of the manufacturing test process. Element 708 is operable at the completion of the triple nested loop execution of element 706. Element 708 saves the best values computed by operation of element 706 for test coverage and isolation. The best coverage value is the highest test coverage while the best test isolation value is the shortest isolation time computed by element 706.
This derivation of test coverage and test isolation allows for coverages from multiple test attributes to overlap with the highest coverage prevailing. The modeling of coverages for each test attribute is based on intimate knowledge of each of the test techniques used in manufacturing and shelters designers from having to gain that expertise. For instance, self-test and diagnostics will typically cover the same functional faults on a component. Diagnostics will usually have higher coverage, while self-test will have better isolation capabilities (i.e. shorter time to isolate the problem). If both test att