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United States Patent5212652
Agrawal , ; et al.May 18, 1993
Title
Programmable gate array with improved interconnect structure
Abstract
A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of contact signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.
Inventors:Agrawal; Om P. (San Jose, CA), Wright; Michael J.  (Menlo Park, CA), Shen; Ju  (San Jose, CA)
Assignee:Advanced Micro Devices, Inc. (Sunnyvale, CA)
Appl. No.:394221
Filed:August 15, 1989
Current U.S. Class:326/41 340/14.3 708/232 716/14 716/17 
Field of Search:364/490,489,488,716 340/825.79,825.83 307/465
U.S. Patent Documents
4536859August 1985Kamuro
4609986September 1986Hartmann et al.
4642487February 1987Carter
4677318June 1987Veenstra
4706216October 1987Carter
4713557December 1987Carter
4758985July 1988Carter
4870302September 1989Freeman
5128871July 1992Schmitz
Foreign Patent Documents
0358501Mar., 1990EP
0398552Nov., 1990EP
Other References
XCELL, The Newsletter for Xilinx Programmable Gate Array users, Second Third Quarter 1989, Issue 3. .
The Programmable Gate Array Design handbook, First Edition, published by Xilinx, pp. 1--1 through 1--31. .
XC3000 Logic Cell Array Family, (technical data handbook), published by Xilinx, pp. 1-31. .
"The XC4000 Logic Cell Array Family-Data Book" published by XILINX, 1991, pp. 1-64. .
"The XC4000 Logic Cell Array Family-Technical Data" published by XILINX, 1990, pp. 1-53. .
"On-Chip RAM and Hierarchical Routing Improve Programmable-Array Flexibility" by D. Bursky, Electronic Design, Jul. 12, 1990, pp. 35-36. .
"Third-Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays", by Peter Alfke, XILINX, Jun. 1990, pp. 1-12. .
"Optimizing Programmable Gate Array Design" by Knapp, IRE WESCON Convention Record, vol. 32, Nov. 1988, pp. 421-427. .
"An Approach to Highly Integrated, Computer-Maintained Cellular Arrays" by Manning, IEEE Trans. on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536-552..~
Primary Examiner: Trans; Vincent N.
Attorney, Agent or Firm:Fleisler, Dubb, Meyer & Lovejoy
Claims

What is claimed is:
1. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL.sub.c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means, including a tristate output means supplying one of the respective plurality of output signals or presenting a high impedance state in response to a tristate control signal and means for supplying the tristate control signal configurable in response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means;
configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means.

2. The configurable logic array of claim 1, wherein the configurable interconnect means includes:
a plurality of horizontal buses along the rows in the array, and a plurality of vertical buses along the columns of the array and at least one bus of the plurality of horizontal buses includes an uncommitted long line extending across the array;
a first plurality of programmable interconnect points, each connected to a tristate output means in a configurable logic means and connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory; and
a second plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting the uncommitted long line with one of the plurality of vertical buses in response to program data in the configuration memory.

3. The configurable logic array of claim 1, wherein the configurable interconnect means includes:
a plurality of horizontal buses along the rows in the array, and a plurality of vertical buses along the columns of the array and at least one bus of the plurality of vertical buses includes an uncommitted long line extending across the array;
a first plurality of programmable interconnect points, each connected to a tristate output means in a configurable logic means and connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory; and
a second plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting the uncommitted long line with one of the plurality of horizontal buses in response to program data in the configuration memory.

4. The configurable logic array of claim 1, wherein the configurable interconnect means includes a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j, for j equal to 1 through C-1, and a second end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j+2, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs from the tristate output means of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory;
the plurality of vertical buses including a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i, for i equal to 1 through R-1, and a second end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i+2, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs from the tristate output means of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory.

5. The configurable logic array of claim 1 wherein the plurality of configurable input/output means includes a first subset without storage elements and a second subset with storage elements.

6. The configurable logic array of claim 1, wherein the configurable interconnect means includes a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, so that each of the plurality of configurable logic means has four adjacent buses in the configurable interconnect means, and wherein each of the plurality of configurable logic means has at least one tristate output means coupled to each of the four adjacent buses.

7. The configurable logic array of claim 1, wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j, and a second end connected to a horizontal connection of a switching matrix at the intersection with another vertical bus VB.sub.k, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs from the tristate output means of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory;
the plurality of vertical buses including a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i, and a second end connected to a vertical connection of a switching matrix at the intersection with another horizontal bus HB.sub.m, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs from the tristate output means of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory; and
configurable repowering means, coupled to at least one horizontal segment, configurable for repowering signals on the one horizontal segment propagating in a first direction, for repowering signals on the one horizontal segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration memory.

8. The configurable logic array of claim 1, wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, along the rows in the array, and a plurality of vertical buses VB.sub.j, along the columns of the array, each bus including a control line extending across the array;
a first plurality of programmable interconnect points, each connected to the control line in an adjacent bus, for interconnecting respective outputs from the tristate output means of configurable logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration memory;
a second plurality of interconnect points, each connected to the control line in an adjacent bus, for interconnecting respective inputs of configurable logic cells and input/output cells adjacent to the respective control line;
means for driving a control signal to a conducting line; and
a plurality of configurable control line driving means, each coupled to the control line in a respective bus and to the conducting line, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration memory.

9. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user defined data processing function;
(b) a plurality of configurable logic means, CL.sub.1,1 to CL.sub.C,R, arranged as an array consisting of C columns and R rows, each of said configurable logic means being designated by CL.sub.c,r where c designates a column in the range 1 to C, and r designates a row in the range 1 to R,
(b.1) each of the configurable logic means CL.sub.c,r being coupled to the configuration storage means and having a plurality of inputs and outputs, and
(b.2) each of the configurable logic means CL.sub.c,r being for generating cell output signals at a respective one or more signal outputs thereof in response to cell input signals supplied to a respective one or more signal inputs thereof and in response to program data in the configuration storage means;
(c) a plurality of input/output pads;
(d) a plurality of configurable input/output means, each being coupled to an input/output pad, each having an input and an output, and each being coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs thereof in response to program data in the configuration storage means; and
(e) configurable interconnect means, coupled to the configuration storage means and having first interconnect resources and second interconnect resources extending respectively in first and second different directions, the first and second interconnect resources of the configurable interconnect means being coupled to the inputs and outputs of the plurality of configurable logic means and of the plurality of configurable input/output means for programmably interconnecting respective inputs and outputs of said plurality of configurable logic means with one another and with respective inputs and outputs of said plurality of configurable input/output means in response to program data in the configuration storage means to thereby define one or more logical networks configured according to said program data;
wherein the first and second interconnect resources of the configurable interconnect means are symmetrically disposed relative to the signal inputs and outputs of said plurality of configurable logic means CL.sub.1,1 -CL.sub.C,R such that substantially similar interconnection may be made to each configurable logic means CL.sub.c,r using either of the first and second interconnect resources for conducting cell input and cell output signals respectively to and from each configurable logic means CL.sub.c,r.

10. The configurable logic array of claim 9, wherein:
(a) the first interconnect resources of the configurable interconnect means include
first double-wide direct-connection means for directly connecting one signal output of each configurable logic means CL.sub.c,r to one signal input of a neighboring second configurable logic means, the second configurable logic means (CL.sub.c-2,r or CL.sub.c+2,4) being positioned in the same row, r, as said each configurable logic means CL.sub.c,r but spaced one column apart; and wherein:
(b) the second interconnect resources of the configurable interconnect means include
second double-wide direct-connection means for directly connecting one signal output of each configurable logic means CL.sub.c,r to one signal input of a neighboring third configurable logic means, the third configurable logic means (CL.sub.c,r-2
or CL.sub.c,r+2) being positioned in the same column, c, as said each configurable logic means CL.sub.c,r but spaced one row apart.

11. The configurable logic array of claim 9, wherein the first interconnect resources of the configurable interconnect means include
a plurality of horizontal buses HB.sub.i, for i equal to 1 to
R+1, extending along the rows in the array, wherein the second interconnect resources of the configurable interconnect means include
a plurality of vertical buses VB.sub.j, for j equal to 1 to
C+1, extending along the columns of the array, such that each configurable logic means, CL.sub.c,r, has four buses of the configurable interconnect means extending adjacent thereto, and
wherein each configurable logic means has at least four signal outputs of substantially equivalent usage, each coupled to a respective one of its four adjacent buses.

12. The configurable logic array of claim 9, wherein the first interconnect resources of the configurable interconnect means include
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array,
wherein the second interconnect resources of the configurable interconnect means include a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, such that each configurable logic means, CL.sub.c,r, has four buses of the configurable interconnect means extending adjacent thereto, and
wherein each configurable logic means has at least four signal inputs of substantially equivalent usage, each coupled to a respective one of its four adjacent buses.

13. The configurable logic array of claim 9, wherein the first interconnect resources of the configurable interconnect means include
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array,
wherein the second interconnect resources of the configurable interconnect means include
a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, such that each configurable logic means, CL.sub.c,r, has four buses of the configurable interconnect means extending adjacent thereto,
wherein each configurable logic means has at least four signal outputs of substantially equivalent usage, each coupled to a respective one of its four adjacent buses and
wherein each configurable logic means further has at least four signal inputs of substantially equivalent usage, each coupled to a respective one of its four adjacent buses.

14. The configurable logic array of claim 9, wherein the configurable interconnect means includes:
means for directly connecting a subset of the plurality of outputs of a given configurable logic means to inputs of eight other configurable logic means arranged in the array symmetrically about the given configurable logic means.

15. The configurable logic array of claim 9, wherein the first interconnect resources of the configurable interconnect means include
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, each including lines extending along the rows in the array,
wherein the second interconnect resources of the configurable interconnect means include
a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, each including lines extending along the columns of the array to cross with the lines of said horizontal buses, and
wherein the interconnect means further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses,
each switching matrix having a plurality of horizontal-line receiving terminals and a plurality of vertical-line receiving terminals respectively positioned for receiving lines of the horizontal and vertical buses,
each switching matrix including programmable interconnect means for providing interconnections between programmably selected ones of the horizontal-line receiving and vertical-line receiving terminals in response to program data in the configuration storage means;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, where at least one of the plurality of horizontal segments belonging to a first horizontal bus HB.sub.i has a first end connected to a first horizontal-line receiving terminal of a corresponding first switching matrix located at the intersection of a first vertical bus VB.sub.j with said first horizontal bus HB.sub.i, and a second end connected to a second horizontal-line receiving terminal of a corresponding second switching matrix located at the intersection of said first horizontal bus HB.sub.i with another vertical bus VB.sub.k,
a first plurality of programmable interconnect points (PIP's) for interconnecting respective signal inputs or outputs of said configurable logic means and input/output means with respective horizontal segments of adjacent horizontal buses in response to program data in the configuration storage means;
the plurality of vertical buses each including a plurality of conductive vertical segments, where at least one of the plurality of vertical segments belonging to one vertical bus VB.sub.j has a first end connected to a first vertical-line receiving terminal of a corresponding first switching matrix located at the intersection of the one vertical bus VB.sub.j with a horizontal bus HB.sub.i, and a second end connected to a vertical-line receiving terminal of a switching matrix located at the intersection of the one vertical bus VB.sub.j with another horizontal bus HB.sub.m,
a second plurality of programmable interconnect points (PIP's) for interconnecting respective signal inputs or outputs of said configurable logic means and input/output means with respective vertical segments of adjacent vertical buses in response to program data in the configuration storage means;
a first configurable repowering means, coupled to at least one horizontal segment, said first repower means being configurable in response to program data in the configuration storage means for repowering signals on the one horizontal segment propagating in a first horizontal direction, for repowering signals on the one horizontal segment propagating in a second horizontal direction, or for passing signals propagating in either the first horizontal direction or the second horizontal direction; and
a second configurable repowering means, coupled to at least one vertical segment, said second repower means being configurable in response to program data in the configuration storage means for repowering signals on the one vertical segment propagating in a first vertical direction, for repowering signals on the one vertical segment propagating in a second vertical direction, or for passing signals propagating in either the first vertical direction or the second vertical direction.

16. The configurable logic array of claim 9, wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, extending along the rows in the array, and a plurality of vertical buses VB.sub.j, extending along the columns of the array so that there is a bus on four sides of each configurable logic means,
where each bus of said horizontal and vertical buses includes a control line extending across the array for carrying a control signal either to or from at least one adjacent configurable logic means;
a first plurality of programmable interconnect points, each connected to a given control line in a given horizontal or vertical bus, for programmably interconnecting respective control signal outputs of configurable logic means and input/output means adjacent to the given bus with the given control line in response to program data in the configuration storage means;
a second plurality of interconnect points, each connected to the given control line in the given bus, for interconnecting respective control signal inputs of configurable logic means and input/output means adjacent to the respective given horizontal or vertical control line;
a first conducting line extending horizontally across the array for conducting control signals;
a second conducting line extending vertically across the array for conducting control signals;
a plurality of configurable control line driving means, one for each horizontal bus and one for each vertical bus, where each configurable control line driving means is coupled to the control line in a respective bus and to one of the first and second conducting lines, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration storage means.

17. The configurable logic array of claim 9, wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, extending along the rows in the array, and a plurality of vertical buses VB.sub.j, extending along the columns of the array so that there is a bus on four sides of each configurable logic means,
where each bus of said horizontal and vertical buses includes a control line extending across the array for carrying a control signal either to or from at least one adjacent configurable logic means;
a first plurality of programmable interconnect points, each connected to a given control line in a given horizontal or vertical bus, for programmably interconnecting respective control signal outputs of configurable logic means and input/output means adjacent to the given bus with the given control line in response to program data in the configuration storage means;
a second plurality of interconnect points, each connected to the given control line in the given bus, for interconnecting respective control signal inputs of configurable logic means and input/output means adjacent to the respective given horizontal or vertical control line;
a first conducting line extending horizontally across the array for conducting control signals;
a second conducting line extending vertically across the array for conducting control signals;
first configurable buffer means for optionally supplying a control signal to said first conducting line from a plurality of sources in response to program data in said configuration storage means;
second configurable buffer means for optionally supplying a control signal to said second conducting line from a plurality of sources in response to program data in said configuration storage means;
a first plurality of configurable control line driving means, one for each horizontal bus, and each coupled to the control line in a respective horizontal bus and to the first conducting line, for optionally driving a signal from the control line in the respective horizontal bus to the first conducting line, or for optionally driving a signal from the fist conducting line to the control line in the respective horizontal bus, in response to program data in the configuration storage means; and
a second plurality of configurable control line driving means, one for each vertical bus, an each coupled to the control line in a respective vertical bus and to the second conducting line, for optionally driving a signal from the control line in the respective vertical bus to the second conducting line, or for optionally driving a signal from the second conducting line to the control line in the respective vertical bus, in response to program data in the configuration storage means.

18. The configurable logic array of claim 9, wherein for a given column, c, and a given row, r, the configurable interconnect means includes:
first double-wide direct-interconnect means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.3+2,r ;
second double-wide direct-interconnect means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r+2 ; and
third double-wide direct-interconnect means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.3-2,r ; and
fourth double-wide direct-interconnect means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r-2.

19. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user defined data processing function;
(b) a plurality of configurable logic means, CL.sub.1,1 -CL.sub.C,R, arranged as an array consisting of C columns and R rows, each of said configurable logic means being designated by CL.sub.c,r where c designates a column in the range 1 to C, and r designates a row in the range 1 to R,
(b.1). each of the configurable logic means CL.sub.c,r being coupled to the configuration storage means and having a plurality of inputs and outputs, and
(b.2) each of the configurable logic means CL.sub.c,r being for generating cell output signals at a respective one or more signal outputs thereof in response to cell input signals supplied to a respective one or more signal inputs thereof and in response to program data in the configuration storage means;
(c) a plurality of input/output terminals;
(d) a plurality of configurable input/output means, each being coupled to an input/output terminal, each having an input and an output, and each being coupled to the configuration storage means, for providing configurable interfaces between the respective input/output terminals and the respective inputs and outputs thereof in response to program data in the configuration storage means; and
(e) configurable interconnect means, coupled to the configuration storage means and having first interconnect resources and second interconnect resources extending respectively in first and second different directions, the first and second interconnect resources of the configurable interconnect means being coupled to the inputs and outputs of the plurality of configurable logic means and of the plurality of configurable input/output means for programmably interconnecting respective inputs and outputs of said plurality of configurable logic means with one another and with respective inputs and outputs of said plurality of configurable input/output means in response to program data in the configuration storage means to thereby define one or more logic networks configured according to said program data;
wherein the first interconnect resources of the configurable interconnect means include:
a plurality of horizontal buses HB.sub.i, for i equal to 1 to
R+1, extending along the rows in the array, wherein the second interconnect resources of the configurable interconnect means include
a plurality of vertical buses VB.sub.j, for j equal to 1 to
C+1, extending along the columns of the array, such that each configurable logic means, CL.sub.c,r, has four buses of the configurable interconnect means extending adjacent thereto,
wherein each configurable logic means has at least four signal outputs of substantially equivalent usage, each coupled to a respective one of the four adjacent buses; and
wherein each configurable logic means has at least four signal inputs of substantially equivalent usage, each coupled to a respective one of the four adjacent buses.

20. The configurable logic array of claim 19,
wherein each horizontal bus HB.sub.i includes a plurality of C uncommitted lines extending across the logic array;
wherein each vertical bus VB.sub.j includes a plurality of R uncommitted lines extending across the logic array; and
wherein the configurable logic array further comprises:
a first plurality of interconnect pints, connected to respective uncommitted long lines of buses adjacent each configurable logic means, for interconnecting respective signal outputs of each configurable logic means with a corresponding uncommitted long line in an adjacent bus; and
a second plurality of programmable interconnect points, connected to respective uncommitted long lines, for interconnecting each uncommitted long line with a line in an intersecting bus in response to program data in the configuration storage means.

21. The configurable logic array of claim 19, wherein the first interconnect resources of the configurable interconnect means includes double-wide direct-connect first means for directly connecting one signal output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c+2,r for c equal 1 to C-2; and
wherein the second interconnect resources of the configurable interconnect means includes double-wide direct-connect second means for directly connecting one signal output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r+2 for r equal 1 to R-2.

22. The configurable logic array of claim 19, wherein the configurable interconnect means includes:
means for directly connecting a subset of the plurality of outputs of a given configurable logic means to inputs of eight other configurable logic means in the array.

23. The configurable logic array of claim 19, wherein each of the plurality of horizontal buses and of the plurality of vertical buses includes a control line that extends across the array for carrying a control signal either to or from at least one adjacent configurable logic means, and wherein the configurable interconnect means further includes:
a first plurality of programmable interconnect points, each connected to a given control line in a given horizontal or vertical bus, for programmably interconnecting respective control signal outputs of configurable logic means adjacent to the given bus with the given control line in response to program data in the configuration storage means;
a second plurality of interconnect points, each connected to the given control line in the given bus, for interconnecting respective control signal inputs of configurable logic means adjacent to the respective given horizontal or vertical control line;
a first conducting line extending horizontally across the array for conducting control signals;
a second conducting line extending vertically across the array for conducting control signals;
a plurality of configurable control line driving means, one for each horizontal bus and one for each vertical bus,
where each configurable control line driving means is coupled to the control line in a respective bus and to one of the first and second conducting lines, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration storage means.

24. The configurable logic array of claim 19, wherein the configurable interconnect means includes
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c=2,r ;
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r+2 ; and
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c-2,r ; and
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r-2.

25. The configurable logic array of claim 19, wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, along the rows in the array, and a plurality of vertical buses VB.sub.j, along the columns of the array, each vertical and horizontal bus including a control line extending across the array;
a first plurality of programmable interconnect points, each connected to the control line in a given bus, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration memory;
a second plurality of interconnect points, each connected to the control line in a given bus, for interconnecting respective inputs of configurable logic cells and input/output cells adjacent to the respective control line;
first means for driving a control signal to a first conducting line;
second means for driving a control signal to a second conducting line;
a first plurality of configurable control line driving means, one for each horizontal bus, and each coupled to the control line in a respective horizontal bus and to the first conducting line, for driving a signal from the control line in the respective horizontal bus to the first conducting line, or for driving a signal from the first conducting line to the control line in the respective horizontal bus, in response to program data in the configuration memory; and
a second plurality of configurable control line driving means, one for each vertical bus, and each coupled to the control line in a respective vertical bus and to the second conducting line, for driving a signal from the control line in the respective vertical bus to the second conducting line, or for driving a signal from the second conducting line to the control line in the respective vertical bus, in response to program data in the configuration memory.

26. The configurable logic array of claim 19, wherein all of the plurality of configurable logic means has an equal number N of outputs coupled to each of the four adjacent buses, and an equal number M of inputs coupled to each of the four adjacent buses.

27. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user defined data processing function;
(b) a plurality of configurable logic means, CL.sub.1,1 -CL.sub.C,R, arranged as an array consisting of C columns and R rows, each of said configurable logic means being designated by CL.sub.c,r where c designates a column in the range 1 to C, and r designates a row in the range 1 to R,
(b.1) each of the configurable logic means CL.sub.c,r being coupled to the configuration storage means and having a plurality of inputs and outputs, and
(b.2) each of the configurable logic means CL.sub.c,r being for generating cell output signals at a respective one or more signal outputs thereof in response to cell input signals supplied to a respective one or more signal inputs thereof and in response to program data in the configuration storage means;
(c) a plurality of input/output terminals;
(d) a plurality of configurable input/output means, each being coupled to an input/output terminal, each having an input and an output, and each being coupled to the configuration storage means, for providing configurable interfaces between the respective input/output terminals and the respective inputs and outputs thereof in response to program data in the configuration storage means; and
(e) configurable interconnect means, coupled to the configuration storage means and having first interconnect resources and second interconnect resources extending respectively in first and second different directions, the first and second interconnect resources of the configurable interconnect means being coupled to the inputs and outputs of the plurality of configurable logic means and of the plurality of configurable input/output means for programmably interconnecting respective inputs and outputs of said plurality of configurable logic means with one another and with respective inputs and outputs of said plurality of configurable input/output means in response to program data in the configuration storage means to thereby define one or more logical networks configured according to said program data;
wherein the first interconnect resources of the configurable interconnect means include:
first double-wide direct-connect means for directly connecting one output of each given configurable logic means to one input of a next adjacent configurable logic means which is spaced apart by one row from the given configurable logic means; and
wherein the second interconnect resources of the configurable interconnect means include:
second double-wide direct-connect means for directly connecting one output of each given configurable logic means to one input of a next adjacent configurable logic means which is spaced apart by one column from the given configurable logic means.

28. The configurable logic array of claim 27, wherein the first interconnect resources of the configurable interconnect means include
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, each having plural lines and extending along the rows in the array,
wherein the second interconnect resources of the configurable interconnect means include
a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, each having plural lines and extending along the columns of the array to intersect with said horizontal buses, and
wherein the interconnect means further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses,
each switching matrix having a plurality of horizontal-line receiving terminals and a plurality of vertical-line receiving terminals respectively positioned for receiving lines of the horizontal and vertical buses,
each switching matrix including programmable interconnect means for providing interconnections between programmably selected ones of the horizontal-line receiving and vertical-line receiving terminals in response to program data in the configuration storage means;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, where at least one of the plurality of horizontal segments belonging to a first horizontal bus HB.sub.i has a first end connected to a first horizontal-line receiving terminal of a corresponding first switching matrix located at the intersection of said first horizontal bus HB.sub.i, with vertical bus VB.sub.j, for j equal to 1 through C-1, and a second end connected to a second horizontal-line receiving terminal of a corresponding second switching matrix located at the intersection of said first horizontal bus HB.sub.i with vertical bus VB.sub.j+2,
a first plurality of programmable interconnect points (PIP's) for interconnecting respective signal inputs or outputs of said configurable logic means with respective horizontal segments of adjacent horizontal buses in response to program data in the configuration storage means;
the plurality of vertical buses each including a plurality of conductive vertical segments, where at least one of the plurality of vertical segments belonging to one vertical bus VB.sub.j has a first end connected to a first vertical-line receiving terminal of a corresponding first switching matrix located at the intersection of the one vertical bus VB.sub.j with a horizontal bus HB.sub.i, for i equal 1 through R-1, and a second end connected to a vertical-line receiving terminal of a switching matrix located at the intersection of the one vertical bus VB.sub.j with horizontal bus HB.sub.i+2, and
a second plurality of programmable interconnect points (PIP's) for interconnecting respective signal inputs or outputs of said configurable logic means with respective vertical segments of adjacent vertical buses in response to program data in the configuration storage means.

29. The configurable logic array of claim 27 wherein the plurality of configurable input/output means includes a first subset without storage elements and a second subset with storage elements; and
wherein the interconnect means includes means for interconnecting each configurable logic means with a configurable input/output means belonging to the first subset and with a configurable input/output means belonging to the second subset.

30. The configurable logic array of claim 27,
wherein the first interconnect resources of the configurable interconnect means include
a plurality of horizontal buses HB.sub.i, for i equal to 1 to
R+1, extending along the rows in the array, wherein the second interconnect resources of the configurable interconnect means include
a plurality of vertical buses VB.sub.j, for j equal to 1 to
C+1 extending along the columns of the array, such that each configurable logic means, CL.sub.c,r, has four buses of the configurable interconnect means extending adjacent thereto, and
wherein each configurable logic means has at least four signal outputs of substantially equivalent usage, each coupled to a respective one of its four adjacent buses.

31. The configurable logic array of claim 27, wherein each of the configurable logic means includes:
a plurality of tristate output means, each for selectively supplying one of the respective plurality of cell output signals or presenting a high impedance state at a corresponding signal output of the configurable logic means in response to a supplied tristate control signal; and
configurable supply means for supplying the tristate control signal to each tristate output means, said supply means being configurable in response to program data in the configuration storage means.

32. The configurable logic array of claim 27, wherein the configurable interconnect means includes:
means for directly connecting a subset of the plurality of outputs of a given configurable logic means to inputs of eight other configurable logic means in the array.

33. The configurable logic array of claim 27, wherein the configurable interconnect means includes:
means for directly connecting an output of a configurable input/output means adjacent to column 1 to an input of a configurable logic means in column 2.

34. The configurable logic array of claim 27, wherein the configurable interconnect means includes:
means for directly connecting an output of a configurable input/output means adjacent to column C to an input of a configurable logic means in column C-1.

35. The configurable logic array of claim 27, wherein the configurable interconnect means includes:
means for directly connecting an output of a configurable input/output means adjacent to row 1 to an input of a configurable logic means in row 2.

36. The configurable logic array of claim 27, wherein the configurable interconnect means includes:
means for directly connecting an output of a configurable input/output means adjacent to row R to an input of a configurable logic means in row R-1.

37. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user defined data processing function;
(b) a plurality of configurable logic means, CL.sub.1,1 -CL.sub.C,R, arranged as an array consisting of C columns and R rows, each of said configurable logic means being designated by CL.sub.c,r where c designates a column in the range 1 to C, and r designates a row in the range 1 to R,
(b.1) each of the configurable logic means CL.sub.c,r being coupled to the configuration storage means and having a plurality of inputs and outputs, and
(b.2) each of the configurable logic means CL.sub.c,r being for generating cell output signals at a respective one or more signal outputs thereof in response to cell input signals supplied to a respective one or more signal inputs thereof and in response to program data in the configuration storage means;
(c) a plurality of input/output pads;
(d) a plurality of configurable input/output means, each being coupled to an input/output pad, each having an input and an output, and each being coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs thereof in response to program data in the configuration storage means; and
(e) configurable interconnect means, coupled to the configuration storage means and to the inputs and outputs of the plurality of configurable logic means and to the inputs and outputs of the plurality of configurable input/output means, for programmably interconnecting respective inputs and outputs of said plurality of configurable logic means with one another and with respective inputs and outputs of said plurality of configurable input/output means in response to program data in the configuration storage means to thereby define one or more logical networks configured according to said program data;
wherein the configurable interconnect means includes:
direct-connect means for directly connecting a subset of the plurality of signal outputs of each given configurable logic means CL.sub.c,r to corresponding signal inputs of more than four other configurable logic means in the logic array.

38. The configurable logic array of claim 37, wherein for c equals 1 through C-2, and r equals 1 through R, the direct-connect means of the configurable interconnect means includes means for directly connecting one output of each configurable logic means CL.sub.c,r to one input of a corresponding configurable logic means CL.sub.c+2,r.

39. The configurable logic array of claim 37, wherein for c equals 1 through C, and r equals 1 through R-2, the direct-connect means of the configurable interconnect means includes means for directly connecting one output of each configurable logic means CL.sub.c,r to one input of a corresponding configurable logic means CL.sub.c,r+2.

40. The configurable logic array of claim 37, wherein for c equals 1 through C-1, and r equals 1 through R-1, the direct-connect means of the configurable interconnect means includes means for directly connecting one output of each configurable logic means CL.sub.c,r to one input of a corresponding configurable logic means CL.sub.c+1,r+1.

41. The configurable logic array of claim 37, wherein for c equals 3 through C-2, and r equals 3 through R-2, the direct-connect means of the configurable interconnect means includes
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c+2,r ;
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r+2 ; and
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c-2,r ; and
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c,r-2.

42. The configurable logic array of claim 37, wherein for c equals 1 through C-1, and r equals 1 through R-1, the direct-connect means of the configurable interconnect means includes
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.C+1,r+1 ;
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c-1,r+1 ; and
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c-1,r-1 ; and
means for directly connecting one output of configurable logic means CL.sub.c,r to one input of configurable logic means CL.sub.c+1,r-1.

43. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL.sub.c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means;
configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means;
wherein the configurable interconnect means includes a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j, for j equal to 1 through C-1, and a second end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j+2, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory;
the plurality of vertical buses including a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i, for i equal to 1 through R-1, and a second end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i+2, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory.

44. The configurable logic array of claim 43, wherein each of the configurable logic means includes:
a tristate output means supplying one of the respective plurality of output signals or presenting a high impedance state in response to a tristate control signal; and
means for supplying the tristate control signal configurable in response to program data in the configuration storage means.

45. The configurable logic array of claim 43, wherein the configurable interconnect means, wherein at least one bus of the plurality of horizontal buses includes an uncommitted long line extending across the array; and further including:
a first plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory; and
a second plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting the uncommitted long line with one of the plurality of vertical segments in response to program data in the configuration memory.

46. The configurable logic array of claim 43, wherein the configurable interconnect means, wherein at least one bus of the plurality of vertical buses includes an uncommitted long line extending across the array; and further including:
a first plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory; and
a second plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting the uncommitted long line with one of the plurality of horizontal segments in response to program data in the configuration memory.

47. The configurable logic array of claim 43 wherein the plurality of configurable input/output means includes a first subset without storage elements and a second subset with storage elements.

48. The configurable logic array of claim 43, wherein the configurable interconnect means includes:
configurable repowering means, coupled to at least one horizontal segment, configurable for repowering signals on the one horizontal segment propagating in a first direction, for repowering signals on the one horizontal segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration memory.

49. The configurable logic array of claim 43, wherein the configurable interconnect means includes:
configurable repowering means, coupled to at least one vertical segment, configurable for repowering signals on the one vertical segment propagating in a first direction, for repowering signals on the one vertical segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration memory.

50. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL.sub.c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means;
configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means;
wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j, and a second end connected to a horizontal connection of a switching matrix at the intersection with another vertical bus VB.sub.k, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory;
the plurality of vertical buses including a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i, and a second end connected to a vertical connection of a switching matrix at the intersection with another horizontal bus HB.sub.m, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory; and
configurable repowering means, coupled to at least one horizontal segment, configurable for repowering signals on the one horizontal segment propagating in a first direction, for repowering signals on the one horizontal segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration memory.

51. The configurable logic array of claim 50, wherein each of the configurable logic means includes:
a tristate output means supplying one of the respective plurality of output signals or presenting a high impedance state in response to a tristate control signal; and
means for supplying the tristate control signal configurable in response to program data in the configuration storage means.

52. The configurable logic array of claim 50, wherein at least one bus of the plurality of horizontal buses includes an uncommitted long line extending across the array; and the configurable interconnect means further includes:
a first plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory; and
a second plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting the uncommitted long line with the plurality of vertical segments in response to program data in the configuration memory.

53. The configurable logic array of claim 50, wherein at least one bus of the plurality of vertical buses includes an uncommitted long line extending across the array; and the configurable interconnect means further includes:
a first plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory; and
a second plurality of programmable interconnect points, connected to the uncommitted long line, for interconnecting the uncommitted long line with the plurality of horizontal segments in response to program data in the configuration memory.

54. The configurable logic array of claim 50 wherein the plurality of configurable input/output means includes a first subset without storage elements and a second subset with storage elements.

55. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL.sub.c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means;
configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means;
wherein the configurable interconnect means includes:
a plurality of buses including a set of horizontal buses along the rows in the array, and a set of vertical buses along the columns of the array and at least one bus of the plurality of buses includes an uncommitted long line extending across the array,
a first plurality of programmable interconnect points, each connected to the uncommitted long line, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the one bus with the uncommitted long line in response to program data in the configuration memory, and
a second plurality of programmable interconnect points, each connected to the uncommitted long line, for interconnecting the uncommitted long line with another of the plurality of buses in response to program data in the configuration memory.

56. The configurable logic array of claim 55, wherein at least one of the configurable logic means includes:
a tristate output means, coupled with the uncommitted long line, for supplying one of the respective plurality of output signals or presenting a high impedance state in response to a tristate control signal; and
means for supplying the tristate control signal configurable in response to program data in the configuration storage means.

57. The configurable logic array of claim 55 wherein the plurality of configurable input/output means includes a first subset without storage elements and a second subset with storage elements.

58. The configurable logic array of claim 55, wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, for i equal to 1 to R+1, along the rows in the array, and a plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the horizontal and vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory;
the plurality of horizontal buses each including a plurality of conductive horizontal segments, at least one of the plurality of horizontal segments having a first end connected to a horizontal connection of a switching matrix at the intersection with vertical bus VB.sub.j, and a second end connected to a horizontal connection of a switching matrix at the intersection with another vertical bus VB.sub.k, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory;
the plurality of vertical buses including a plurality of conductive vertical segments, at least one of plurality of vertical segments having a first end connected to a vertical connection of a switching matrix at the intersection with horizontal bus HB.sub.i, and a second end connected to a vertical connection of a switching matrix at the intersection with another horizontal bus HB.sub.m, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory;
wherein the second plurality of programmable interconnect points includes a subset coupled to the segments intersecting the uncommitted long line.

59. The configurable logic array of claim 55, further including:
a third plurality of programmable interconnect points, each connected to the uncommitted long line and to an input of one of the plurality of configurable input/output means.

60. The configurable logic array of claim 55, further including:
a third plurality of programmable interconnect points, each connected to the uncommitted long line and to an output of one of the plurality of configurable input/output means.

61. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array consisting of C columns and R rows, where c designates a column in the range 1 to C, and r designates a row in the range 1 to R, each of the configurable logic means CL.sub.c,r having a plurality of inputs and outputs, and coupled to the configuration storage means, for generating cell output signals at the respective plurality of outputs in response to cell input signals supplied to the respective plurality of inputs and in response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an input/output pad and having an input and an output, and coupled to the configuration storage means, for providing configurable interfaces between the respective input/output pads and the respective inputs and outputs in response to program data in the configuration storage means;
configurable interconnect means, coupled to the plurality of configurable logic means, the plurality of configurable input/output means and the configuration storage means, for connecting inputs and outputs of configurable logic means and configurable input/output means into logical networks in response to program data in the configuration storage means;
wherein the configurable interconnect means includes:
a plurality of horizontal buses HB.sub.i, along the rows in the array, and a plurality of vertical buses VB.sub.j, along the columns of the array, each bus including a control line extending across the array;
a first plurality of programmable interconnect points, each connected to the control line in an adjacent bus, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration memory;
a second plurality of interconnect points, each connected to the control line in an adjacent bus, for interconnecting respective inputs of configurable logic cells and input/output cells adjacent to the respective control line;
means for driving a control signal to a conducting line; and
a plurality of configurable control line driving means, each coupled to the control line in a respective bus and to the conducting line, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration memory.

62. The configurable logic array of claim 61, wherein each of the configurable logic means includes:
a tristate output means supplying one of the respective plurality of output signals or presenting a high impedance state in response to a tristate control signal; and
means for supplying the tristate control signal configurable in response to program data in the configuration storage means.

63. The configurable logic array of claim 61 wherein the plurality of configurable input/output means includes a first subset without storage elements and a second subset with storage elements.

64. The configurable logic array of claim 61, wherein each of the plurality of configurable logic means has four adjacent buses in the configurable interconnect means, and wherein each of the plurality of configurable logic means has at least one output coupled by a programmable interconnect point to the control line in each of the four adjacent buses.

65. The configurable logic array of claim 61, wherein the means for driving includes
first means for driving a control signal to a first conducting line;
second means for driving a control signal to a second conducting line; and the plurality of configurable control line driving means includes
a first set having one configurable control line driving means for each horizontal bus, and each coupled to the control line in a respective horizontal bus and to the first conducting line, for driving a signal from the control line in the respective horizontal bus to the first conducting line, or for driving a signal from the first conducting line to the control line in the respective horizontal bus, in response to program data in the configuration memory; and
a second set having one configurable control line driving means for each vertical bus, and each coupled to the control line in a respective vertical bus and to the second conducting line, for driving a signal from the control line in the respective vertical bus to the second conducting line, or for driving a signal from the second conducting line to the control line in the respective vertical bus, in response to program data in the configuration memory.

66. The configurable logic array of claim 61, wherein the means for driving includes:
selector means, coupled to the configuration storage means and to receive a plurality of signals, for selecting the control signal from the plurality of signals; and
means for directly connecting an output from a configurable logic means in the array as one of the plurality of signals.

67. A configurable interconnect for a programmable logic device having an array of N columns and M rows of configurable logic cells, and a plurality of configurable input/output cells arranged peripherally around the array, each logic cell having a plurality of inputs and outputs, comprising:
a plurality of horizontal buses along the rows of configurable logic cells;
a plurality of vertical buses along the columns of configurable logic cells;
a plurality of switching matrices, at intersections of the plurality of horizontal buses with the plurality of vertical buses, each having a plurality of horizontal connections and a plurality of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration memory;
a plurality of conductive horizontal segments in the plurality of horizontal buses, each having a first end connected to a horizontal connection of a switching matrix and a second end connected to a horizontal connection of a different switching matrix, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal segment in response to program data in the configuration memory;
a plurality of conductive vertical segments in the plurality of vertical buses, each having a first end connected to a vertical connection of a switching matrix and a second end connected to a vertical connection of a different switching matrix, and each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical segment in response to program data in the configuration memory;
a plurality of horizontal long lines in the plurality of horizontal buses, each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective horizontal long line in response to program data in the configuration memory;
a plurality of vertical long lines in the plurality of vertical buses, each connected to a plurality of programmable interconnect points for interconnecting respective inputs or outputs of configurable logic cells and input/output cells with the respective vertical long line in response to program data in the configuration memory;
a plurality of uncommitted horizontal long lines in the plurality of horizontal buses, each connected to a first plurality of programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective horizontal long line in response to program data in the configuration memory, and each connected to a second plurality of programmable interconnect points for interconnecting the respective uncommitted horizontal long line with one of a respective subset of the plurality of vertical segments in response to program data in the configuration memory; and
a plurality of uncommitted vertical long lines in the plurality of vertical buses, each connected to a first plurality of programmable interconnect points for interconnecting respective outputs of configurable logic cells and input/output cells with the respective vertical long line in response to program data in the configuration memory, and each connected to a second plurality of programmable interconnect points for interconnecting the respective uncommitted vertical long line with one of a respective subset of the plurality of horizontal segments in response to program data in the configuration memory; and
a plurality of direct connections, each directly connecting one output of a one configurable logic cell to one input of another configurable logic cell or input/output cell.

68. The configurable interconnect of claim 67, wherein each member of a subset of the plurality of horizontal segments is connected at the first end to a switching matrix at the intersection with a vertical bus along column i, and is connected at the second end to a switching matrix at the intersection with a vertical bus along column i+j, where j is greater than one.

69. The configurable interconnect of claim 67, wherein each horizontal bus includes N horizontal segments, and each member of a subset of the plurality of switching matrices includes M horizontal connections on a left side of the matrix and M horizontal connections on a right side of the matrix, where M is less than N, and wherein at least N-M horizontal segments through the intersection at which a member of the subset is located spans two or more columns of configurable logic cells.

70. The configurable interconnect of claim 67, further including:
a horizontal control line in each of the horizontal buses;
a vertical control line in each of the vertical buses;
a first plurality of programmable interconnect points, each connected to the control line in a given bus, for interconnecting respective outputs of configurable logic cells and input/output cells adjacent to the given bus with the control line in response to program data in the configuration memory;
a second plurality of interconnect points, each connected to the control line in a given bus, for interconnecting respective inputs of configurable logic cells and input/output cells adjacent to the control line;
means for driving a control signal to a conducting line; and
a plurality of configurable control line driving means, each coupled to the control line in a respective bus and to the conducting line, for driving a signal from the control line in the respective bus to the conducting line, or for driving a signal from the conducting line to the control line in the respective bus, in response to program data in the configuration memory.

71. The configurable interconnect of claim 67, further including:
configurable repowering means, coupled to at least one horizontal segment, configurable for repowering signals on the one horizontal segment propagating in a first direction, for repowering signals on the one horizontal segment propagating in a second direction, or for passing signals propagating in either the first direction or the second direction, in response to program data in the configuration memory.

72. The configurable interconnect of claim 67, wherein the plurality of direct connections includes:
means for directly connecting an output of each configurable logic cell to an adjacent configurable logic cell; and
means for directly connecting an output of each configurable logic cell to a next adjacent configurable logic cell.

73. The configurable interconnect of claim 67, wherein the plurality of direct connections include means for directly connecting outputs of each member of a subset of the configurable logic cells to inputs of eight other configurable logic cells or configurable input/output cells.

74. The configurable interconnect of claim 67, wherein the configurable interconnect is symmetrically disposed relative to the inputs and outputs of the configurable logic cells.
Description
FIELD OF THE INVENTION

The present invention relates generally to programmable logic devices and, more particularly, to programmable gate arrays consisting of an array of logic blocks and input/output blocks with an interconnection structure, each of which are configurable by a configuration program stored in on chip memory.

DESCRIPTION OF RELATED ART

The programmable gate array is a high performance, user programmable device containing three types of configurable elements that are customized to a user system design. The three elements are (1) an array of configurable logic blocks (CLBs), (2) with input/output blocks (IOBs) around a perimeter, all linked by (3) a flexible programmable interconnect network.

The system design desired by a user is implemented in the device by configuring programmable RAM cells. These RA cells control the logic functionality performed by the CLBs, IOBs and the interconnect. The configuration is implemented using PGA design software tools.

It is generally accepted that the programmable gate array was first commercially introduced by Xilinx of San Jose, Calif. Xilinx originally introduced the XC2000 series of logic cell arrays and has more recently introduced a second generation XC3000 family of integrated circuit programmable gate arrays. A description of the 2000 series, as well as related programmable logic device art, can be found in THE PROGRAMMABLE GATE ARRAY DESIGN HANDBOOK, First Edition, published by Xilinx, pages 1-1
through 1-31. The architecture for the XC3000 family is provided in a technical data handbook published by Xilinx entitled XC3000 LOGIC CELL ARRAY FAMILY, pages 1-31. Each of these Xilinx publications is incorporated by reference in this application as providing a description of the prior art.

The prior art in programmable gate arrays is further exemplified by U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is assigned to Xilinx, Inc. These U.S. Patents are incorporated by reference as setting forth detailed descriptions of the programmable gate array architecture and implementations of the same.

As mentioned above, the programmable gate array consists of a configurable interconnect, a ring of configurable input/output blocks, and an array of configurable logic blocks. It is the combination of these three major features that provides flexibility and data processing power for programmable gate arrays. However, the programmable gate arrays of the prior art suffer certain limitations in each of the interconnect structure, the input/output block structures, and the configurable logic block structures.

The configurable interconnect structure must provide the ability to form networks on the programmable gate array which optimize utilization of the resources on the chip. The prior art interconnect systems have tended to force connection in the logical network to configurable blocks in a relatively small area. For instance, a prior system provides direct connections only between adjacent configurable logic blocks. The inputs and outputs on the configurable logic blocks are arranged in a left to right or otherwise asymmetrical layout that forces signal flow in a certain direction across the chip. This causes congestion on the interconnect structure for applications requiring a large number of inputs or outputs. Also, this forces the printed circuit board layout, which includes one of these asymmetrically designed logic cell arrays, to provide for inputs on one side of the logic cell array and outputs on the other.

In addition, the prior art interconnect structures are limited in the number of multi-source networks that can be implemented.

The input/output blocks in the prior art programmable gate arrays are relatively complex macro cells in order to provide flexibility needed for the wide variety of applications intended for the devices. However, these complex macro cells include resources that are unused in many configurations of the input/output blocks. Further, the blocks are relatively slow because of the complexity, requiring passage through a number of buffers, multiplexers and registers between the logic cells and the input/output pad. Furthermore, the input/output blocks cause congestion on the peripheral logic blocks in the device for applications involving a lot of input and output.

The configurable logic blocks themselves also suffer limitations which impact the flexibility of the device. The logic blocks of the prior art have operated upon a relatively small set of input variables. Thus, wide gating functions, such as decoding a 16 bit instruction or a wide multiplexing function, required cascading of many configurable blocks. Thus, a very simple function can utilize a large number of configurable logic blocks in the array. Further, when cascading blocks, due to the limitation of the number of direct interconnections between the logic blocks, many of the signals have to be transmitted across the programmable general connect. This causes delay because of the number of programmable interconnection points used. Further, for critical paths requiring fast operation, the cascading of blocks becomes impractical.

In the prior art configurable logic blocks, typically four input signals are used for the logic function. In order to obtain a five variable gating function, the configurable logic blocks used a sharing of inputs scheme. This sharing of inputs greatly limits the logic flexibility for these five variable functions in the prior art.

Prior art configurable logic blocks also suffered speed penalties because of the relatively complex structure required for the blocks to achieve user flexibility. For a block which is being used for a simple function, the logic would be propagated at a relatively slow rate because of the complex structures required.

It is desirable to provide a programmable gate array which provides for greater flexibility and logic power than provided by prior art devices.

SUMMARY OF THE INVENTION

The present invention provides an architecture for a configurable logic array with an interconnect structure which improves flexibility in creating networks to allow for greater utilization of the configurable logic blocks and input/output blocks on the device.

Accordingly, the present invention is an improved configurable logic array comprising a configuration memory storing program data specifying a user defined data processing function. In addition, a plurality of configurable logic blocks are arranged in an array consisting of C columns and R rows. Each configurable logic block is coupled to the configuration memory and has a plurality of inputs and outputs for generating output signals at the respective outputs in response to the input signals at the respective inputs and in response to program data in the configuration store. A plurality of configurable input/output blocks is included, each coupled to an input/output pad and to the configuration store, and having at least one input and at least one output. The configurable input/output blocks provide configurable interfaces between the respective pads and the respective inputs and outputs in response to the program data. A configurable interconnect is coupled to the configurable logic blocks, configurable input/output blocks and to the configuration store, for connecting the inputs and outputs of configurable logic blocks and configurable input/output blocks into logical networks in response to the program data in the configuration store.

According to one aspect of the invention, the configurable interconnect is symmetrically disposed relative to the inputs and outputs of the configurable logic blocks. Thus, inputs of the CLBs can be derived from four sides and outputs can be driven to four sides of the respective CLB into a symmetrical interconnect structure.

The interconnect includes a plurality of horizontal buses along the rows of CLBs and a plurality of vertical buses along the columns of CLBs. The intersections of the horizontal and vertical buses are configurable to route networks across the device.

Another aspect of the interconnect includes a plurality of switching matrices at the intersections of horizontal and vertical buses, each having a set of horizontal connections and a set of vertical connections, for interconnecting respective ones of the horizontal or vertical connections in response to program data in the configuration store. A plurality of horizontal conductive segments in the horizontal bus are connected between the horizontal connections of the switching matrices. A plurality of programmable interconnect points coupled to respective inputs and outputs of the configurable logic blocks and input/output blocks provide connectability to respective horizontal segments in response to program data. Likewise, a plurality of vertical conductive segments in the vertical bus are connected between the vertical connections of the adjacent switching matrices. Programmable interconnect points interconnect the respective inputs and outputs of configurable logic blocks and input/output blocks with respective vertical segments in response to the program data. The vertical and horizontal segments, according to one aspect of the invention, are characterized by extending from a switching matrix in a vertical or horizontal bus "i" to switch matrix in bus "i+2", so that each segment spans two columns or rows of logic blocks.

The buses in the interconnect are further characterized by a plurality of horizontal and vertical long conductive lines which extend across the entire chip. Each long line is connected to a plurality of programmable interconnect points for interconnecting the respective inputs or outputs of configurable logic cells with the respective long line in response to program data in the configuration memory. The long lines ar characterized by having programmable interconnect points coupling an output of a configurable logic block which is supplied by a tristate buffer to the respective long lines.

In another aspect, the buses in the interconnect structure are characterized by uncommitted horizontal and vertical long lines. Each uncommitted long line is connected to a first plurality of programmable interconnect points for interconnecting the respective outputs of configurable logic blocks or input/output blocks with the respective long line in response to program data, and a second plurality of programmable interconnect points for interconnecting respective uncommitted long line with the horizontal or vertical segments that are coupled to the switching matrices.

The interconnect structure further includes a plurality of direct connections interconnecting an output of a configurable logic block or input/output block to an input of another configurable logic block or input/output block. The direct connections are characterized by including at least a first subset which are connected between adjacent input/output blocks or configurable logic blocks, and a second subset which are connected between the output of a configurable logic block or input/output block and a next adjacent configurable logic block or input/output block. In one aspect of the invention, each CLB is directly connected to 8 neighbor CLBs.

The plurality of configurable input/output blocks is characterized by group of input/output blocks associated with each row or column of configurable logic blocks. Within each group, at least one complex input/output block is included and at least one simple input/output block. The complex input/output blocks provide the flexible functionality required for many applications, while the simple input/output block provides a fast access path into or out of the configurable array.

Further, all of the input/output logic blocks are characterized by tristatable output buffers to pads and to the internal interconnect which are controlled in response to the program data and/or a control signal generated in the configurable logic array.

Also, the outputs of the configurable logic blocks include a plurality of tristate buffers which receive respective ones of the output signals of the combinational logic and tristate control signals. The tristate output buffers supply a respective output signals or present a high impedance state as output from the logic block in response to the tristate control signal. The tristate control signal is generated in response to the program data in the configuration store and an input to the configurable logic block.

Another aspect of the invention is configurable repowering buffers with a bypass path coupled to the horizontal and vertical segments that go through switching matrices. Also, provision is made through the interconnect to supply control signals to all CLBs in the array from a single source.

The configurable logic blocks, according to the present invention, are characterized by a number of improvements over the prior art. In particular, the configurable logic blocks provide for a mixture of narrow gating and wide gating functions, which suffer a speed penalty only for the wide gating functions. Also, the configurable logic blocks are symmetrical, accepting inputs on four sides of each block and providing outputs on four sides. The output structures themselves provide the ability for tristating outputs connected to the configurable interconnect, and for directly driving signals to other configurable logic blocks.

The input structures on all four sides of the configurable logic blocks are independently configurable in response to the configuration program. Likewise, the four output macro cells in each configurable logic block are independently configurable.

As a feature that allows greater utilization of resources on the array, the registers in each of the output macro cells are accessible independently of the combinational logic in the configurable logic block. This allows these registers to be used in networks that are independent of the combinational logic.

According to one aspect, the configurable logic block can be characterized as having an input multiplexing tree which receives J input signals and selects a subset K signals, where K is less than or equal to J, in response to the program data. Combinational logic is coupled to the configuration memory and the input multiplexing tree, for generating a plurality of L logic signals in response to the K signals and the program data. Four independent output macro cells are included, each of which select output signals from the plurality of L logic signals.

Each of the output macro cells includes a tristatable output buffer for driving a selected output signal to the configurable interconnect. Also, each output macro cell includes a second output buffer, for driving a signal that is selected independently of the tristatable output buffer, for driving signals onto direct connections to other configurable logic blocks.

The input multiplexing tree is characterized by providing that any one of the K signals can be supplied from any of the four sides of the configurable logic block.

The combinational logic is implemented with a first lookup table in the program data consisting of 64 bits which are grouped into eight 8 bit arrays. The 8 bit arrays are paired so that three independently supplied signals from the subset of K signals supplied by the input multiplexing tree are used to address each of the four pairs of 8 bit arrays. The two outputs of each pair are coupled to a cross-multiplexer which is configurable in response to the program data to directly pass through the two outputs supplied by the two 8 bit arrays in the pair, or to select one of the two outputs as a primary output in response to a fourth independently supplied signal from the subset K signals. The output of the cross-multiplexer is supplied through a third multiplexing level consisting of two multiplexers, each independently controllable by respective ones of the subset of K signals. The output of the third level of multiplexing is then supplied to a fourth level of multiplexing which is controlled by one of the subset of K signals, providing output which is a full lookup function of the 64 bit array in response to six inputs.

The combinational logic further includes a special 16 bit array in the program data which is coupled to a sixteen to one multiplexer. Control inputs to the sixteen to one multiplexer are the pass through outputs of the four cross-multiplexers referred to above. Each of these inputs is a function of four independent variables. The output of the sixteen to one multiplexer provides a special output, which provides a limited lookup function of the 16 independent variables. The special output is combined with the output of the fourth level multiplexer in a fifth level multiplexer, which is controlled in response to an input signal of the subset of K signals, or by the program data.

According to another aspect, the configurable logic block is characterized by a preload capability. During programming of the configurable logic array, each of the storage elements in the output macro cells of the configurable logic blocks is enabled to receive data as if it were a location in the configuration memory.

The configurable input/output architecture, according to the present invention, is characterized by a number of improvements over the prior art. In particular, the architecture provides for groups of input/output blocks associated with each row and column of configurable logic blocks in the array. Each of the groups is further characterized by having a plurality of complex input/output blocks, which provide flexible structures for implementing interfaces between the configurable logic array and outside devices, and at least one simple input/output block which provides a fast path from outside the device to the configurable logic array if required by a particular application.

Further, both the simple and complex input/output blocks are characterized by having at least one tristatable output buffer for driving signals onto the configurable interconnect structure, and a second buffer for driving direct connections to configurable logic blocks in the device.

The complex input/output blocks include an input storage element and an output storage element. A direct connection is provided from the input storage element of one complex input/output cell to a next adjacent complex input/output around the perimeter of the device. The output storage elements of the complex input/output cells are similarly connected. Thus, the storage elements in the complex input/output blocks can be linked into a configurable data path where they can be operated as a shift register or other similar circuit.

The storage elements in the complex input/output blocks are further configured to provide for synchronization functions, local readback functions, and buried register functions.

The input/output blocks, according to the present invention, are further characterized by control signal generation from the long lines in the programmable interconnect structure. This allows utilization of networks in the configurable logic array to control the operation and configuration of the configurable input/output blocks in a dynamic fashion. Also, the long lines are configured to propagate signals completely around the perimeter of the array, so that a common signal can be used to control all of the input/output blocks.

The configurable logic array provided, according to the present invention, greatly improves the flexibility and performance of programmable gate arrays over those available in the prior art. This is accomplished in part by a interconnect structure which supports networks with long reach across the device, multi-source networks, and symmetrical connections to the configurable logic blocks.

Further, a unique configurable logic block architecture supports efficient utilization of the resources in the array, wide gating functions, narrow gating functions without speed penalty and implementation of symmetrical networks in the array.

Finally, a unique input/output architecture supports efficient utilization of the resources in the input/output structures, allows for both fast signal propagation through the simple input/output blocks and high function signal propagation through the complex input/output blocks into the array, and has improved flexibility in the source of control signals for the input/output structure.

Further aspects and advantages of the present invention will be found upon review of the drawings, the detailed description and the claims which follow.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is schematic diagram illustrating the layout of the programmable gate array according to the present invention.

FIG. 2 is a schematic diagram of the configuration memory in the programmable gate array according to the present invention.

FIG. 3 is a diagram of the configuration memory storage cell.

FIG. 4 illustrates a notation scheme for vertical buses in the programmable gate array.

FIG. 5 illustrates a notation scheme for the horizontal buses in the programmable gate array.

FIG. 6 illustrates the placement of the switch matrices in lines 5-14 of the horizontal and vertical buses in the programmable gate array.

FIG. 7 illustrates the intersection of a vertical bus with a horizontal bus.

FIG. 8 illustrates an alternative intersection of a vertical bus with a horizontal.

FIG. 9 illustrates the intersection of vertical buses 1 and 9 with even numbered horizontal buses and horizontal buses 1 and 9 with even numbered vertical buses.

FIG. 10 illustrates the intersection of vertical buses 1 and 9 with the odd numbered horizontal buses and horizontal buses and 9 with the odd numbered vertical buses.

FIG. 11 illustrates the intersection of horizontal bus 1 with vertical bus 1 at the corner.

FIG. 12 illustrates the intersection of horizontal bus 1 with vertical bus 9 at the corner.

FIG. 13 illustrates the intersection of horizontal bus 9 with vertical bus 1 at the corner.

FIG. 14 illustrates the intersection of horizontal bus 9 with vertical bus 9 at the corner.

FIG. 14A illustrates an alternative corner connection scheme that can be used at all four corner intersections, replacing the schemes of FIGS. 11-14.

FIG. 15 illustrates the connection of lines 16 and 17 of the vertical buses with the global reset and global clock buffers.

FIG. 15A illustrates the connection of the vertical lines 16 and 17 with the configurable logic blocks.

FIG. 15B illustrates the signal path from an input/output pad bypassing internal IOB logic for connection to the global clock buffer, horizontal alternate buffer or vertical alternate buffer.

FIG. 15C illustrates the inputs to the global clock buffer.

FIG. 16 illustrates the connection of the horizontal alternate buffers with line 15 on the horizontal buses and the vertical alternate buffers with line 15 on the vertical buses

FIG. 16A illustrates the connection of the input/output blocks and the configurable logic blocks with line 15.

FIG. 16B illustrates the input paths to the vertical alternate buffer.

FIG. 16C illustrates the input paths to the horizontal alternate buffer.

FIG. 16D illustrates the crystal oscillator circuit by which the oscillator signal OSC is generated on the chip.

FIG. 16E illustrates the external connections for the oscillator of FIG. 16D.

FIG. 17 illustrates one implementation of a programmable interconnect point using bidirectional pass transistors.

FIG. 18 illustrates an alternative configuration of a programmable interconnect point using a unidirectional multiplexer technique.

FIG. 19 illustrates the interconnect structure of the switch matrix.

FIG. 20 illustrates the repowering buffer used in the programmable interconnect.

FIG. 21 shows the switch matrix interconnection options for each connection to the switch matrix.

FIG. 22 illustrates the interconnection in the segment boxes on vertical buses 1 and 9.

FIG. 23 illustrates the interconnection in the segment boxes on horizontal buses 1 and 9.

FIG. 24 illustrates the segment box interconnection options for each connection to the segment box.

FIG. 25 is an overview block diagram of the configurable logic block.

FIG. 26 schematically illustrates the inputs and outputs and provides a notation for the configurable logic block.

FIG. 27 is a schematic diagram of the combinational logic in the configurable logic block.

FIG. 28 is a schematic diagram of the special output stage which is coupled to the combinational logic of FIG. 27.

FIG. 29 is a schematic diagram of the macro cell for outputs X1 and Y1 on the configurable logic block.

FIG. 29A illustrates the connection of the register in the macro cell which provides for preload during programming of the configurable logic array.

FIG. 30 is a schematic diagram of the macro cell for outputs X2 and Y2 on the configurable logic block.

FIG. 31 is a schematic diagram of the macro cell for outputs X3 and Y3 on the configurable logic block.

FIG. 32 is a schematic diagram of the macro cell for outputs X4 and Y4 on the configurable logic block.

FIG. 33 is a diagram of the input multiplexing structure for signals VA1-VA4 which are used in the first level multiplexing in the combinational logic section of the configurable logic block.

FIG. 34 is a schematic diagram of the input multiplexing structure for signals VB1-VB4 which are used in the first level multiplexing in the combinational logic section of the configurable logic block.

FIG. 35 is a schematic diagram of the input multiplexer structure for signals VC1-VC4 which are used in the first level multiplexing in the combinational logic section of the configurable logic block.

FIG. 36 is a schematic diagram of the input multiplexing structure for signals VD1-VD4 which are used in the second level multiplexing in the combinational logic section of the configurable logic block.

FIG. 37 is a diagram of the input multiplexing structure for VE1 and VE2 used in the third level multiplexing of the combinational logic.

FIG. 38 is a diagram of the input multiplexing structure for the fourth level multiplexing signal VF in the combinational logic.

FIG. 39 is a schematic diagram of the input multiplexing structure for the control signal VG used in providing the special output.

FIGS. 40A-40H show respectively the input multiplexing for the general purpose control lines CT1-CT8.

FIG. 41 is a schematic diagram of the circuit generating output enable control signals OE1-OE4 in the configurable logic block.

FIG. 42 is a diagram illustrating selection of the clock signal in the configurable logic block.

FIG. 43 is the schematic diagram illustrating generation of the clock enable signal in the configurable logic block.

FIG. 44 is a schematic diagram illustrating selection of the reset signal in the configurable logic block.

FIG. 45 is a schematic diagram of a simple input/output cell according to the present invention.

FIG. 46 is a schematic diagram of a complex input/output cell according to the present invention.

FIG. 47 illustrates the inputs and outputs of the complex input/output block.

FIG. 48 illustrates the inputs and outputs of the simple input/output block.

FIG. 49 schematically illustrates the connection of the complex input/output blocks in a shift register configuration.

FIG. 50 illustrates the direct connections from outputs of next adjacent configurable logic blocks to the inputs of a given logic block.

FIG. 51 illustrates direct connections from adjacent configurable logic blocks to the inputs of the center configurable logic block.

FIG. 52 illustrates direct connections from the output of the center configurable logic block to adjacent and next adjacent configurable logic blocks.

FIG. 53 illustrates direct connection of the outputs X1-X4 on peripheral configurable logic blocks.

FIG. 54 illustrates direct connection to the inputs of a peripheral configurable logic block.

FIG. 55 illustrates direct connections to the inputs F1-F4 on a peripheral configurable logic block.

FIG. 56 illustrates the programmable connections between the interconnect structure and the configurable logic blocks.

FIG. 57 illustrates the fixed connections between the interconnect structure and the configurable logic blocks.

FIG. 58 illustrates the programmable connection of the configurable logic blocks in the array to uncommitted long lines.

FIG. 59 illustrates the programmable connections to the outer long lines from the CLBs.

FIG. 60 illustrates the reach between input/output blocks and configurable logic blocks on long lines.

FIG. 61 illustrates the programmable connections between the input/output blocks on the top side of the configurable array and horizontal bus 1.

FIG. 62 illustrates the programmable connections between horizontal bus 9 and the input/output blocks on the bottom side of the configurable array.

FIG. 63 illustrates the programmable interconnects between the vertical bus 1 and the input/output blocks on the left side of the array.

FIG. 64 illustrates the programmable interconnects between vertical bus 9 and the input/output blocks on the right side of the array.

FIG. 65 illustrates the connection of the clock and reset signals to the complex logic blocks, as well as the programmable connections of the inputs and the outputs of the input/output blocks on the top side of the array to the vertical buses.

FIG. 66 illustrates the connection of the clock and reset signals to the input/output blocks on the bottom side of the array, and connection of these bottom side input/output blocks to the vertical buses.

FIG. 67 illustrates the connection of the clock and reset signals to the input/output blocks on the left side, and connection of these left side input/output blocks to horizontal buses.

FIG. 68 illustrates the connection of the clock and the reset signals to the input/output blocks on the right side of the array, and connection of these right side input/output blocks to the horizontal buses.

FIG. 69 illustrates the connection of the control signal inputs on the input/output blocks on the top and left side of the array to the adjacent interconnect buses.

FIG. 70 illustrates the connection of the control signal inputs to the input/output blocks on the right and bottom side of the array to the adjacent interconnect buses.

DETAILED DESCRIPTION

With reference to the figures, a detailed description of a preferred embodiment of the present invention is provided.

First, with reference to FIGS. 1-3, the basic layout and programming structure of the programmable gate array is described. Next, a detailed description of the interconnect structure is set out with reference to FIGS. 4-24. Implementation of the configurable logic block utilized in the programmable gate array is described with re