Home
Patent Search
IMT Blog
REGISTER
|
SIGN IN
United States Patent
5182811
Sakamura
January 26, 1993
Title
Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt
Abstract
A data processor executes the exception process, interrupt process and the trap instruction of internal interrupt instructions in a unified manner. The data processor is adapted to read an internal state variable simultaneously with reading the head address of an EIT process handler from an external memory when an EIT process is started so that it enables the internal state to be set on the basis of the information of the variable when the EIT process handler starts. The data processor is provided with multiple EIT process means which, when a plurality of EIT process requests are generated, decides the process order on the basis of priority from the content of the request. The data processor is also provided with means which specially treats the EIT process acceptance condition after returning from one EIT process handler, and thereby is generously free in programming.
Inventors:
Sakamura; Ken
(Tokyo,
JP
)
Assignee:
Mitsubishi Denki Kabushiki Kaisha
(Tokyo,
JP
)
Appl. No.:
554945
Filed:
July 10, 1990
Foreign Application Priority Data
Oct 02, 1987 [JP] 62-250216
Current U.S. Class:
710/264
Field of Search:
364/2MSFile,9MSFile 395/500,275,425,729
U.S. Patent Documents
4349873
September 1982
Gunter et al.
4403284
September 1983
Salarisen et al.
4418385
November 1983
Bourrez
4758950
July 1988
Cruess et al.
4768149
August 1988
Konopik et al.
4975836
December 1990
Hirosawa et al.
Other References
MC32-Bit Microprocessor User's Manual, Motorola Corp., Prentice-Hall, Inc..~
Primary Examiner:
Lee; Thomas C.
Assistant Examiner:
Treat; William M.
Attorney, Agent or Firm:
Townsend and Townsend
Parent Case Text
This is a continuation of application Ser. No. 07/172,035, filed Mar. 23, 1988, now abandoned.
Claims
What is claimed is:
1. In a data processor which can execute a plurality of instructions which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting exception, interrupt, and trap events, including instruction exceptions, interrupt request signals, and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:
a read-write memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, said read-write memory storing a plurality of fetchable executable event handlers, each event handler being a sequence of instructions stored at memory locations starting at an entry address;
means, coupled to said memory, for storing, in said read-write memory, a first information group that includes information indicative of the data processor internal state, said first information group including at least a part of the information stored in said at least one control register;
means, coupled to said read-write memory, for holding an entry address of an executable event handler;
means, coupled to said read-write memory, for storing in said read-write memory, under program control, a second information group, different from said first information group, that includes information indicative of a data processor internal state to permit setting an internal state for each event handler under program control, said second information group stored in said read-write memory at a location obtainable when one of said fetchable event handlers is fetched; and
means, coupled to said read-write memory, being the same read-write memory in which said first information group is stored, for fetching from said read-write memory said second information group and for providing at least a part of said second information group to at least a part of said at least one control register in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group.
2. Apparatus, as claimed in claim 1, further comprising:
means, coupled to said means for fetching a second information group, for forming a new information group, using at least a part of said second information group, which is usable to define the data processor internal state at the time of starting execution of an executable event handler which has said fetched entry address.
3. Apparatus, as claimed in claim 2, wherein said means for forming a new information group comprises means for comparing at least part of said first information group with at least part of said second information group.
4. A data processor, as claimed in claim 1, wherein said interrupt request signal includes a first interrupt priority indication and wherein said second information group includes a second interrupt priority indication, and further comprising:
means for comparing said first interrupt priority indication with said second interrupt priority indication, and generating at least a portion of said new internal state based on the results of said comparison.
5. A data processor, as claimed in claim 1, wherein said data processor has the capability for simultaneously detecting a first event and a second event, each of said first and second events being one of said exception, interrupt, and trap events, wherein said first event has a higher predefined priority level than said second event, said first and second events having corresponding first and second executable handlers stored in external memory, further comprising:
means for determining whether to execute said second handler corresponding to said second event before the execution of the first instruction of said first handler corresponding to said first event.
6. A data processor, as claimed in claim 1, wherein said data processor includes an events detection device having the capability of being in one of a plurality of conditions, said data processor being capable of executing a return instruction which returns from one of said event handlers to an instruction stream, further comprising:
means for changing said events detection device wherein the events detection condition, after execution of said return instruction, is different from said events detection condition after execution of other instructions.
7. Apparatus, as claimed in claim 1, wherein said data processor has the capability for detecting a debug exception and the capability of executing a return instruction for returning from an event handler to an instruction stream, further comprising:
means for preventing handling of a debug exception immediately after execution of a return instruction when said return instruction is a return from a debug exception event handler.
8. Apparatus, as claimed in claim 1, wherein a plurality of said second information groups, each corresponding to one of said entry addresses, are stored in said memory.
9. Apparatus, as claimed in claim 8, wherein each second information group stored in said memory is stored at a predetermined distance from each of said corresponding entry addresses.
10. In a data processor which can execute a plurality of instructions and which contains at least one control register for storing information which has a capability for detecting exception, interrupt, and trap events, including instruction exceptions, interrupt request, and execution traps of an internal interrupt instruction, said events having predefined priority levels, said data processor having a read-write memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, including a plurality of executable event handlers comprising instructions, each handler being fetchable using an entry address corresponding to at least one of said events, a method for handling said events comprising:
selecting an event among a plurality of detected events according to said priority;
storing into said read-write memory a first information group that includes information indicative of the data processor internal state at the time said selected event is selected;
storing into said read-write memory, under progrm control, a second information group that includes information indicative of a data processor internal state;
fetching from said read-write memory, being the same read-write memory in which said first information group is stored, an entry address of an executable event handler corresponding to said selected event and said second information group in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group; and
forming a new information group, using at least a part of said second information group, which is usable to define the data processor internal state at the time of starting executing of an executable event handler which has said fetched entry address to permit setting an internal state for each event handler.
11. A method, as claimed in claim 10, wherein said step of forming a new information group comprises comparing at least part of said first information group with at least part of said second information group.
12. A method, as claimed in claim 10, wherein said interrupt request signal includes a first interrupt priority indication, and wherein said second information group includes a second interrupt priority indication, further comprising:
comparing said first interrupt priority indication with said second interrupt priority indication, and generating at least a portion of said new internal state based on the results of said comparison.
13. A method, as claimed in claim 10, wherein said data processor has the capability for simultaneously detecting first and second exception, interrupt, and trap events, wherein said first event has a higher predefined priority level than said second event, said first and second events having corresponding first and second executable handlers stored in external memory, and further comprising:
determining whether to start said second handler corresponding to said second event before the execution of the first instruction of said first handler corresponding to said first event.
14. A method, as claimed in claim 10, wherein said data processor includes an EIT events detection device having the capability of being in one of a plurality of conditions, said data processor being capable of executing a return instruction which returns from one of said event handlers to an instruction stream, and further comprising:
changing said events detection device, wherein the events detection condition, after execution of said return instruction, is different from said events detection condition after execution of other instructions.
15. A method, as claimed in claim 10, wherein said data processor has the capability for detecting a debug exception and the capability of executing a return instruction for returning from an event handler to an instruction stream, further comprising:
preventing handling of a debug exception immediately after execution of a return instruction when said return instruction is a return from a debug exception event handler.
16. A method, as claimed in claim 10, wherein said step of fetching a second information group includes fetching a second information group from among a plurality of said second information groups, each corresponding to one of said entry addresses.
17. A method, as claimed in claim 10, wherein said step of fetching said second information group comprises fetching a second information group from a memory location which is a predetermined distance from said corresponding entry address.
18. In a data processor which can execute a plurality of instructions and which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting exception, interrupt, and trap events, said data processor including a device for storing a current processor status word for at least partially indicating the internal state of the data processor and having a read-write memory which receives address signals and control signals from said data processor, a method for handling said events, using stored event handlers, comprising:
generating an address of a location in the read-write memory at which an indication of the start address of a process handler is stored;
storing at least a part of a candidate processor status word in a location in said read-write memory, under program control;
reading said part of a candidate processor status word from said location in said read-write memory, being the same read-write memory in which said indication of a start address is stored, said location being a predetermined distance from said generated address, wherein said reading is performed in response to the fetching of an EIT handler and in the absence of a separate instruction for fetching said candidate processor status word;
comparing said current processor status word with said candidate processor status word and forming a new processor status word based on the results of said comparing;
saving said current processor status word to a location in read-write memory;
using said new processor status word to define a new internal state for said data processor to permit setting an internal state for each event handler; and
starting an event handler while said data processor is in said new internal state.
19. In a data processor which can execute a plurality of instructions, and which has a capability for detecting exception, interrupt and trap events, including instruction exceptions, interrupt request signals and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:
a read-write memory for storing data and instructions, including a plurality of executable event handlers comprising instructions, each handler being fetchable using an entry address corresponding to at least one of said events;
means, coupled to said read-write memory, for storing a first information group that includes information indicative of the data processor internal state;
means, coupled to said read-write memory, for storing, under program control second and third information groups in said read-write memory, said second and third information groups being different from said first information group and being different from each other, said second and third information groups each including information indicative of a data processor internal state;
means, coupled to said read-write memory, for holding an entry address of an executable event handler;
means, coupled to said read-write memory, for selecting one of said second and third information groups; and
means, coupled to said read-write memory, being the same read-write memory in which said first information group is stored, for fetching from said read-write memory said selected one of said second and third information groups to permit setting an internal state for each event handler in response to the fetching of said event handler and in the absence of a separate instruction for fetching said selected one of said second and third information groups.
20. In a data processor which can execute a plurality of instructions which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting an exception, interrupt, and trap events, including instruction exceptions, interrupt request signals, and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:
a memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, said memory storing a plurality of fetchable, executable event handlers, each event handler being a sequence of instructions stored at memory locations starting at an entry address;
means, coupled to said memory, for storing, in said memory, a first information group that includes information indicative of the data processor internal state, said information group including at least part of the information stored in said at least one control register;
means, coupled to said memory, for holding an entry address of an executable event handler;
means, coupled to said memory, for storing in said memory, under program control, a second information group, different from said first information group, that includes information indicative of a data processor internal state; and
means, coupled to said at least one control register, for fetching from a memory which is not a read-only memory, and storing into said at least one control register, said second information group, in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor, and more particularly to a data processor which performs in a unified manner the exception processing of interrupt process and the trap instruction of internal interrupt instruction.
2. Description of the Prior Art
In the conventional data processor provided with an EIT process, a mechanism, such as an interrupt process mechanism, an exception process mechanism and an internal interrupt instruction process mechanism, when an EIT process request occurs is accepted to start the EIT process. After the information showing the internal state is saved to an external memory, an internal register value is automatically reloaded onto a value of an internal state variable previously determined as a function of the data processor, thereby performing the processing. A flow chart of the conventional EIT process starting method is shown in FIG. 1. Upon accepting an EIT process request at a step 1007 in FIG. 1, at a step 1008 an address of the external memory in the data processor in which the head address of an EIT process handler is stored is generated, and at a step 1009 a program status word (to be hereinafter referred to as PSW), which reads the head address of the EIT process handler and stores data showing the internal state of the data processor, is updated into a predetermined value for the EIT process in the data processor. For example, when the external interrupt is accepted, the variable showing the acceptance priority level of external interrupt in the PSW is automatically reloaded for the purpose of inhibiting the acceptance of external interrupt with higher priority level than that of the accepted external interrupt until the EIT process ends. Next, at a step 1010 in FIG. 1, the internal state of the data processor is saved to the stack, and thereafter at a step 1011 the EIT process handler previously programmed with respect to the content of the EIT is started.
Such method, however, uniquely decides the internal state of the data processor when the EIT process handler starts, so that a programmer is largely restricted. Especially it is complicated for him to set the state of the data processor where a multiple EIT process is carried out. In other words, as above-mentioned, the EIT process handler has hitherto started only under the internal state predetermined by the data processor, which has been one restriction on programming for the programmer. Also, the programmer had to fully recognize the internal state of the data processor when the EIT process handler starts, and sometimes needed to change by himself the internal state variable, whereby the processing has been troublesome.
SUMMARY OF THE INVENTION
In order to solve the above problem, the data processor of the present invention has been designed. The object of this invention is to provide a data processor which is adapted to read some of internal state variables, usually stored in PSW
2010, of the data processor with the head address of the EIT process handler from the external memory 2020 when an EIT process is started, and which has multiple EIT process 2022 means which determines the process order according to the content of the EIT process when there are a plurality of EIT process requests, and which has a device for specially treating the EIT process acceptance condition after restoring from one EIT process handler, thereby facilitating programming.
The data processor of the present invention which processes programs comprising a plurality of instructions, is characterized by; providing a device for accepting at the boundary of each instruction processing an interrupt request signal from the exterior by detecting the interrupt process, a device for detecting exceptional events of instructions, and a device for detecting a trap process, execution of an internal interrupt instruction 2024, so that a plurality of EIT processes sorted to either one of the above three kinds of processes can each have an inherent priority and processing method; having a device for selecting which EIT process, among the EITs detected corresponding to the above-mentioned priority, is started 2022, a device for storing 2024 in an external memory 2020 the first information group to be an internal state that is the initial state of the selected EIT process, and a device for generating 2026 the head address of each EIT process uniquely and storing in the generated address of the external memory a second information group to be a candidate for part or all of a new internal state with the head address of the EIT process handler when the EIT process handler starts in execution, with respect to each selected EIT process.
The data processor of the invention can read from the external memory 2020 the internal state variable of the data processor together with the head address of the EIT process handler, so that the programmer can beforehand write-in the internal sate variable of the data processor when each EIT process is carried out together with the head address of the EIT process handler, at a ratio of 1 to 1 with respect to each EIT process, thereby enabling the internal state of the data processor to be programmed separately in each EIT process. Since the internal state variable is positioned adjacently to the head address of the EIT process handler and automatically read during the EIT processing, the programmer need not separately specify reload of the internal state variable for every EIT process. Also, such function includes information specifying the priority of an EIT process in the stored internal state variable, whereby when multiple EIT processes occur, an EIT process of higher priority can inhibit start of an EIT process of lower priority. Thus, as above-mentioned, the programmer can specify a wide process without difficulty. Also, the function of especially treating the detection process of an EIT process after execution thereof is provided so that, when the exception process carries out single step execution, the repeated occurrence of an EIT process not to proceed with the instruction execution can be avoided.
The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow chart of an EIT process starting method of a conventional data processor,
FIG. 2 is a flow chart of an EIT process starting method of a data processor in the present invention,
FIG. 3 shows a format of EITVTE including the head address of an EIT process handler fetched from an external memory and part of an internal state variable of the data processor when the EIT process occurs in a data processor of the invention,
FIG. 4 shows a stack format made when the EIT process of the data processor of the invention starts,
FIG. 5 shows a stack format corresponding to the kind of the EIT process at the data processor of the invention, and
FIG. 6 shows a stack format and PC and PSW data formed when the data processor of the invention performs the multiple EIT process.
FIG. 7 is an illustration of a register set of the same,
FIG. 8 is an illustration of data type of bits of the same,
FIG. 9 is an illustration of data type as to a bit field of the same,
FIG. 10 is an illustration of data type as to the bit field of unsigned number of the same,
FIG. 11 is an illustration of data type as to the integer of the same,
FIG. 12 is an illustration of data type as to the decimal number of the same,
FIG. 13 is an illustration of data type as to a string of the same,
FIG. 14 is an illustration of data type as to a queue at the same,
FIG. 15 is an illustration exemplary of description of the instruction format of the same,
FIG. 16 shows a bit pattern thereof,
FIGS. 17 to 27 show instruction formats of the data processor of the invention respectively,
FIGS. 28 to 39 show the format of the addressing mode of the same,
FIG. 40 is an illustration exemplary of arrangement of local variations of the same,
FIGS. 41 to 44 show the format of the addressing mode of the same,
FIG. 45 is an illustration of cautioun at the instruction MOV,
FIG. 46 shows the format of PSW,
FIG. 47 shows the format of PSS,
FIG. 48 shows the format of PSH,
FIG. 49 shows the format of description example of the instruction set,
FIG. 50 (a) shows the format of instruction MOV,
FIG. 50 (b) is an illustration of status flags thereof,
FIG. 51 shows the format of instruction MOVU,
FIG. 52 is an illustration of the flag change thereof,
FIG. 53 shows the format of instruction PUSH,
FIG. 54 is an illustration of the flag change thereof,
FIG. 55 shows the format of instruction POP,
FIG. 56 is an illustration of the flag change,
FIG. 57 shows the format of the instruction LDM,
FIG. 58 is an illustration of the flag change thereof,
FIG. 59 is an illustration of bit map specifying,
FIG. 60 shows the format of an instruction STM,
FIG. 61 is an illustration of flag change thereof,
FIGS. 62 and 63 are illustrations of the bit map specifying,
FIG. 64 shows the format of the instruction MOVA,
FIG. 65 is an illustration of flag change thereof,
FIG. 66 shows the format of instruction PUSHA,
FIG. 67 is an illustration of flag change thereof,
FIG. 68 shows the format of instruction CMP,
FIG. 69 is an illustration of flag change thereof,
FIG. 70 shows the format of instruction CMPU,
FIG. 71 is an illustration of flag change thereof,
FIG. 72 shows the format of instruction CHK,
FIG. 73 is an illustration of flag change thereof,
FIG. 74 is an illustration of operation by the instruction CHK,
FIG. 75 shows the format of instruction ADD,
FIG. 76 is an illustration of flag change,
FIG. 77 shows the format of instruction ADDU,
FIG. 78 is an illustration of flag change thereof,
FIG. 79 shows the format of instruction ADDX,
FIG. 80 is an illustration of flag change thereof,
FIG. 81 shows the format of instruction SUB,
FIG. 82 is an illustration of flag change thereof,
FIG. 83 shows the format of instruction SUBU,
FIG. 84 is an illustration of flag change thereof,
FIG. 85 shows the format of instruction SUBX,
FIG. 86 is an illustration of flag change thereof,
FIG. 87 shows the format of instruction MUL,
FIG. 88 is an illustration of flag change thereof,
FIG. 89 shows the format of instruction MULU,
FIG. 90 is an illustration of flag change thereof,
FIG. 91 shows the format of instruction MULX,
FIG. 92 is an illustration of flag change thereof,
FIG. 93 shows the format of instruction DIV,
FIG. 94 is an illustration of flag change thereof,
FIG. 95 shows the format of instruction DIVU,
FIG. 96 is an illustration of flag change thereof,
FIG. 97 is a view showing the format of instruction DIVX,
FIG. 98 is an illustration of flag change thereof,
FIG. 99 is a view of format of instruction REM,
FIG. 100 is an illustration of flag change thereof,
FIG. 101 is a view of the format of instruction REMU,
FIG. 102 is an illustration of flag change thereof,
FIG. 103 shows the format of instruction NEG,
FIG. 104 is an illustration of flag change thereof,
FIG. 105 is a view of the format of instruction INDZX,
FIG. 106 is an illustration of flag change thereof,
FIG. 107 is a view of the format of instruction AND,
FIG. 108 is an illustration of flag change thereof,
FIG. 109 is a view of the format of instruction OR,
FIG. 110 is an illustration of flag change thereof,
FIG. 111 is a view of the format of instruction XOR,
FIG. 112 is an illustration of flag change thereof,
FIG. 113 is a view of the format of instruction NOT,
FIG. 114 is an illustration of flag change thereof,
FIG. 115 is a view of the format of instruction SHA,
FIG. 116 is an illustration of flag change thereof,
FIG. 117 is an illustration of the left-side shift,
FIG. 118 is an illustration of the right-side shift,
FIG. 119 is a view of the format of instruction SHL,
FIG. 120 is an illustration of flag change thereof,
FIG. 121 is an illustration of the left-side shift,
FIG. 122 is an illustration of the right-side shift,
FIG. 123 is a view of the format of instruction ROT,
FIG. 124 is an illustration of flag change thereof,
FIG. 125 is an illustration of counterclockwise rotation,
FIG. 126 is an illustration of clockwise rotation,
FIG. 127 is a view of the format of instruction SHXL,
FIG. 128 is an illustration of flag change thereof,
FIG. 129 is a view of the format of instruction XHXL,
FIG. 130 is an illustration of flag change thereof,
FIG. 131 is a view of the format of instruction SHXR,
FIG. 132 is a view of the format of instruction SHXR,
FIG. 133 is a view of the format of instruction RVBY,
FIG. 134 is an illustration of flag change thereof,
FIG. 135 is a view of the format of instruction RVBI,
FIG. 136 is an illustration of flag change thereof,
FIGS. 137 and 138 are illustrations of bit operation instruction,
FIG. 139 is a view of the format of instruction BTST,
FIG. 140 is an illustration of flag change thereof,
FIG. 141 is a view of the format of instruction BSET,
FIG. 142 is an illustration of flag change thereof,
FIG. 143 is a view of the format of instruction BCLR,
FIG. 144 is an illustration of flag change thereof,
FIG. 145 is a view of the format of instruction BNOT,
FIG. 146 is an illustration of flag change thereof,
FIG. 147 is a view of the format of instruction BSCH,
FIG. 148 is an illustration of flag change thereof,
FIG. 149 is an illustration of fixed length bit field operation instruction,
FIGS. 150(a-b) is a view of the format of instruction of bit field instruction,
FIG. 151 is a view of the format of instruction BFEXT,
FIG. 152 is an illustration of flag change thereof,
FIG. 153 is a view of the format of instruction BFEXTU,
FIG. 154 is an illustration of flag change thereof,
FIG. 155 is a view of the format of instruction BFINS,
FIG. 156 is an illustration of flag change thereof,
FIG. 157 is a view of the format of instruction BFINSU,
FIG. 158 is an illustration of flag change thereof,
FIG. 159 is a view of the format of instruction BFCMP,
FIG. 160 is an illustration of flag change thereof,
FIG. 161 is a view of the format of instruction BFCMPU,
FIG. 162 is an illustration of flag change thereof,
FIGS. 163(a-b) are views of the format of instruction BVSCH,
FIG. 164 is an illustration of flag change thereof,
FIG. 165 is a view of the format of instruction BVMAP,
FIG. 166 is an illustration of flag change thereof,
FIGS. 167 to 169 are views of format of instruction BVMAT,
FIG. 170 is a view of the format of instruction BVCPY,
FIG. 171 is an illustration of flag change thereof,
FIG. 172 is a view of the format of instruction BVPAT,
FIG. 173 is an illustration of flag change thereof,
FIG. 174 is a view of the format of instruction ADDDX,
FIG. 175 is an illustration of flag change thereof,
FIG. 176 is a view of the format of instruction SUBDX,
FIG. 177 is an illustration of flag change thereof,
FIG. 178 is a view of the format of instruction PACKss,
FIG. 179 is an illustration of flag change thereof,
FIG. 180 is a view of the format of instruction UNPKss,
FIG. 181 is an illustration of flag change thereof,
FIG. 182 is an illustration of instruction UNPKss,
FIG. 183 is an illustration of termination condition,
FIG. 184 is a view of the format of instruction SMOV,
FIG. 185 is an illustration of flag change thereof,
FIG. 186 is an illustration of instruction SCMP,
FIGS. 187 and 188 are illustrations of flag change thereof,
FIG. 189 is a view of the format of instruction SSCH,
FIG. 190 is an illustration of the flag change thereof,
FIG. 191 is a view of the format of the instruction SSTR,
FIG. 192 is an illustration of the flag change thereof,
FIG. 193 is a view of the format of instruction QINS,
FIG. 194 is an illustration of the flag change thereof,
FIGS. 195 to 197 are illustrations of the instruction QINS,
FIG. 198 is a view of the format of instruction QDEL,
FIG. 199 is an illustration of the flag change thereof,
FIGS. 200 to 202 are illustrations of the instruction QDEL,
FIGS. 203(a-b) is a view of the format of instruction QSCH,
FIG. 204 is an illustration of the flag change thereof,
FIGS. 205(a-b), 206, and 207 are illustrations of the instruction QSCH,
FIG. 208 is a view of the format of instruction BRA,
FIG. 209 is an illustration of the flag change thereof,
FIG. 210 is a view of the format of instruction Bcc,
FIG. 211 is an illustration of the flag change thereof,
FIG. 212 is an illustration of the detail and mnemonic of the portions,
FIG. 213 is a view of the format of instruction BSR,
FIG. 214 is an illustration of the flag change thereof,
FIG. 215 is a view of the format of instruction JMP,
FIG. 216 is an illustration of the flag change thereof,
FIG. 217 is a view of the format of instruction JSR,
FIG. 218 is an illustration of the flag change thereof,
FIG. 219 is a view of the format of instruction of ACB,
FIG. 220 is an illustration of the flag change thereof,
FIG. 221 is a view of the format of instruction SCB,
FIG. 222 is an illustration of the flag change thereof,
FIG. 223 is a view of the format of instruction ENTER,
FIG. 224 is an illustration of the flag change thereof,
FIG. 225 is an illustration of the instruction ENTER,
FIG. 226 shows the format of instruction EXITD,
FIG. 227 is an illustration of the flag change thereof,
FIG. 228 is an illustration of the instruction EXITD,
FIG. 229 is a view of the format of instruction RTS,
FIG. 230 is an illustration of the flag change thereof,
FIG. 231 is a view of the format of instruction NOP,
FIG. 232 is an illustration of the flag change thereof,
FIG. 233 is a view of the format of instruction PIB,
FIG. 234 is an illustration of the flag change thereof,
FIG. 235 is a view of the format of instruction BSETI,
FIG. 236 is an illustration of the flag change thereof,
FIG. 237 is a view of the format of instruction BCLRI,
FIG. 238 is an illustration of the flag change thereof,
FIG. 239 is a view of the format of instruction CSI,
FIG. 240 is an illustration of the flag change thereof,
FIG. 241 is a view of the format of instruction LDC,
FIG. 242 is an illustration of the flag change thereof,
FIG. 243 is a view of the format of instruction STC,
FIG. 244 is an illustration of the flag change thereof,
FIG. 245 is a view of the format of instruction LDPSB,
FIG. 246 is an illustration of the flag change thereof,
FIG. 247 is a view of the format of instruction LDPSM,
FIG. 248 is an illustration of the flag change thereof,
FIG. 249 is a view of the format of instruction STPSB,
FIG. 250 is an illustration of the flag change thereof,
FIG. 251 is a view of the format of instruction STPSM,
FIG. 252 is an illustration of the flag change thereof,
FIG. 253 is a view of the format of instruction LDP,
FIG. 254 is an illustration of the flag change thereof,
FIG. 255 is a view of the format of instruction STP,
FIG. 256 is an illustration of the flag change thereof,
FIG. 257 is a view of the format of instruction JRNG,
FIG. 258 is an illustration of the flag change thereof,
FIGS. 259 to 264 are illustration of the instruction JRNG,
FIG. 265 is a view of the format of instruction RRNG,
FIG. 266 is an illustration of the flag change thereof,
FIGS. 267 to 269 are illustrations of the instruction RRNG,
FIG. 270 is a view of the format of instruction TRAPA,
FIG. 271 is an illustration of the flag change thereof,
FIG. 272 is a view of the format of instruction TRAP,
FIG. 273 is an illustration of the flag change thereof,
FIG. 274 is a view of the format of instruction REIT,
FIG. 275 is an illustration of the flag change thereof,
FIG. 276 is an illustration of the instruction REIT,
FIG. 277 is a view of the format of instruction WAIT,
FIG. 278 is an illustration of the flag change thereof,
FIG. 279 is a view of the format of instruction LDCTX,
FIG. 280 is an illustration of the flag change thereof,
FIG. 281 is a view of the format of instruction STCTX,
FIG. 282 is an illustration of the flag change thereof,
FIG. 283 is a view of the format of instruction ACS,
FIG. 284 is an illustration of the flag change thereof,
FIG. 285 is a view of the format of instruction MOVPA,
FIG. 286 is an illustration of the flag change thereof,
FIGS. 287 and 288 are views of the format of instruction MOVPA,
FIG. 289 is an illustration of instruction LDATE,
FIGS. 290 and 291 are illustrations of the flag change thereof,
FIG. 292 is a view of the format of instruction STATE,
FIGS. 293 and 294 are illustrations of the flag change thereof,
FIG. 295 is a view of the format of instruction PTLB,
FIG. 296 is an illustration of the flag change thereof,
FIG. 297 is a view of the format of instruction PSTLB,
FIG. 298 is an illustration of the flag change thereof,
FIG. 299 is an illustration of an AT field,
FIG. 300 is an illustration of an AT field,
FIGS. 301 and 302 show the memory map relative to the logical address extension of the invention,
FIG. 303 is an illustration of the flag change in the data transfer instruction,
FIG. 304 is an illustration of the flag change in the comparison test instruction,
FIG. 305 is an illustration of the flag change of the arithmetic operation instruction,
FIG. 306 is an illustration of the flag change in the logical operation instruction,
FIG. 307 is an illustration of the flag change in the shift instruction,
FIG. 308 is an illustration of the flag change in the bit control instruction,
FIGS. 309 and 310 are illustrations of the flag change in the fixed table bit field instruction,
FIG. 311 is an illustration of the flag change in the free table bit field,
FIG. 312 is an illustration of the flag change in the decimal number operation instruction,
FIG. 323 is an illustration of the flag change in the string instruction,
FIG. 314 is an illustration of the flag change in the queue control instruction,
FIG. 315 is an illustration of the flag change in the jump instruction,
FIG. 316 is an illustration of the flag change in the multiprocessor instruction,
FIG. 317 is an illustration of the flag change in the control space and physical space control instruction,
FIG. 318 is an illustration of the flag change in the OS relevant instruction,
FIG. 319 is an illustration of the flag change in the MMU relevant introduction,
FIG. 320 is an illustration of subroutine call,
FIG. 321 is an illustration of stack frame,
FIGS. 322 and 323 are illustrations of instruction sequence,
FIG. 324 is an illustration showing a program example,
FIG. 325 is an illustration of subroutine call,
FIG. 326 is an illustration of control space,
FIG. 327 is a view of the format of PSW,
FIG. 328 is a view of the format of IMASK,
FIG. 329 is a view of the format of SMRNG,
FIG. 330 is a view of the format of CTXBB,
FIG. 331 is a view of the format of DI,
FIG. 332 is a view of the format of CSW,
FIG. 333 is a view of the format of DCE,
FIG. 334 is a view of the format of CTXBFM,
FIG. 335 is a view of the format of EITVB,
FIG. 336 is a view of the format of JRNGVB,
FIG. 337 is a view of the format of SP0 to SP3,
FIG. 338 is a view of the format of SP1,
FIG. 339 is a view of the format of 10ADDR and 10MASK,
FIG. 340 is a view of the format of UATB,
FIG. 341 is a view of the format of SATB,
FIG. 342 is a view of the format of LSID,
FIG. 343 is a view of the format of CTXB,
FIG. 344 is a view of the format of CTXBFM,
FIG. 345 is a view of the format of EITVTE,
FIG. 346 is an illustration of stack frame,
FIGS. 347 and 348 are views of the stack format of EIT,
FIG. 349 is a view of the format of 10 INF,
FIGS. 350(a-d) are vector tables of EIT,
FIG. 351 is an illustration of JRNG,
FIGS. 352 and 353 are illustrations of EIT,
FIG. 354 is an illustration of IMASK,
FIGS. 355 and 356 are illustrations of system call,
FIG. 357 is an illustration of DCE,
FIG. 358 shows comparison of DCE, DI and EI with each other,
FIG. 359 is an illustration of an example of the use of DCE,
FIGS. 360(a-o) are views of bit allocation,
FIGS. 361(a-e) show an index of operand field names,
FIG. 362 shows the cccc allocation,
FIG. 363 shows eeee allocation,
FIG. 364 is an illustration of M-flag,
FIG. 365 is a view of operation code of the BVMAP instruction,
FIGS. 366(a-e) are views correspondent to the addressing mode.
FIG. 367 shows an apparatus for handling exception, interrupt, and trap events.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A flow chart of an EIT process starting method in an embodiment of a data processor of the invention is shown in FIG. 2, in which where an EIT process request is accepted at Step 1001, an EIT vector number is formed corresponding to the content of the EIT process accepted at Step 1002, so that a base address value (EITVTB) of an EIT table 2028 storing therein the EIT process handler is added to a multiple of 8 of the EIT vector number, thereby generating the address of the external memory in which the head address of EIT process handler and part of PSW (to be hereinafter referred to as EITVTE) are stored. The EITVTE of data of the address is read at Step 1003, and compared 2030 in part with the PSW value during the generation of an EIT process which is then updated at Step 1004. Under the internal state of the data processor specified by the updated PSW value, the stack 2032 save of the processor information (at Step 1005) and start of the EIT process handler 2034 (at Step 1006) are executed respectively.
A format of EITVTE of an embodiment of the invention is shown in FIG. 3, in which EITVTE is of an 8-byte structure, 4 bytes thereof being adapted to specify a value of VPC (1025): the head address of the EIT process handler and two bytes of the same to specify part of PSTV and the remainder two bytes are empty in consideration of the degree of freedom and expandability. In FIG. 3, reference numeral VS (1020) designates 1-bit data for specifying a stack point using mode when the EIT process handler starts, VX (1021) designates 1-bit data showing whether the data size of the context, when the same starts, is of 32 or 64 bits, V AT (1022) designates 2-bit data showing a specification of the address conversion mode, when the same starts, VD (1023) designates 1-bit data showing the existence of a debug mode, when the same starts, and VIMASK (1024) designates 4-bit data specifying an interrupt acceptance level, when the same starts.
When the EIT process starts, these five fields are updatable. Also the fields are not simply updated but some thereof are decidable as to whether or not they are updated by comparison of a value under EITVTE with that when EIT is detected. For example, the interrupt acceptance level specifying field, when other than the external interrupt, has as a new value a value which is the higher level (smaller value) either of the value in EITVTE or that prior to the update. The external interrupt has as a new value a value which is the higher level (smaller value) of either the priority of the generated external interrupt or EITVTE.
FIG. 4 shows an embodiment of the information groups showing the internal state of the data processor saved to the external memory specified by a stack pointer (SP) when the EIT process starts. In the drawing, a reference numeral 1026 designates PSW at the data processor at the point of time when EIT process starts, 1027 designates 1-byte data showing the kind of a stack format corresponding to that of EIT process, 1028 designates 1-byte data showing the kind of EIT process, 1029 designates
10-bit data showing the EIT vector number, 1030 designates a 4-byte area storing therein a value of PC (program counter) of the data processor, and 1031 designates several byte areas storing therein various additional information corresponding to the kind of EIT process.
In FIG. 5, stack formats are shown corresponding to the kinds of EIT process as in the embodiment of the data processor of the invention, in which reference numeral 1032 designates a stack format at format 0, 1033 designates the same at format 1,
1034 designates the same at format 2, and 1035 designates the same at format 3 at the EIT process respectively, the embodiments being different, in the content of the additional information, from each other.
FIG. 6 shows a program counter 2036 updated to the final value, PSW, and stack frames formed when the multiple EIT process is carried out in the embodiment of the data processor of the invention. In FIG. 6, an example of generating a trap instruction (TRAP), an internal interrupt instruction and an external interrupt request (EI) in a multiple manner.
The data processor in FIG. 6 includes an EIT process in which the trap instruction is higher in priority than the external interrupt request, so that the EIT process at first starts with respect to the trap instruction and thereafter the same with respect to the external interrupt starts. Accordingly, after the multiple EIT process is accepted, the head address of the EIT process handler with respect to the external interrupt is fetched into PC designated by 1036, the value compared and updated with EITVTE fetched in the external interrupt process is written in PSW 1037. Next, explanation will be given on the content firstly stored in the stack frame, that is, the content stored in the higher address. At first, into the frame 1044 a value of PC (EXPC) at the point of time when the trap instruction is issued, into 1043 a value of PC of the next trap instruction, into 1042 the EIT process information corresponding to 1027, 1028 and 1029 of the trap instructions shown in FIG. 4, into
1041 a value of PSW before the trap instruction execution, into 1040 the head address of EIT process handler with respect to the trap instruction, into 1039 the EIT process information of external interrupt, and into 1038 a value of PSW compared with and set by EITVTE of trap instruction, are stored respectively. Thus, when the EIT process handler is started, the EIT process handler starts first with respect to the external interrupt and then that with respect to the trap instruction from the stack frame information starts, thereby enabling the multiple EIT to be processed.
Next, explanation will be given on the embodiment of the data processor of the present invention in greater detail. The explanation is voluminous and thus is attached with a table of contents, with parts requiring detailed description being made in the form of appendix. Regarding EIT, appendix 9 especially describes it in detail.
CONTENTS
1. Features of The Data Processor of the Present Invention
1-1. Basic Design Concept
1-2. OS Oriented Architecture
1-3. Instruction Set Being Tuned
1-4. Instruction Set for Compiler
2. The Data Processor 32 of the Present Invention and Data Processor 64 of the Present Invention
3. Classification of The Data Processor Specifications of the Present Invention.
4. Register Set
5. Data Type
5-1. Bit
5-2. Bit Field
5-3. Integer
5-4. Floating Point
5-5. Decimal
5-6. String
5-7. Queue
6. Instruction Format
6-1. Two-Operand Short Format
6-1-1. Register and Memory (S-Format and L-Format)
6-1-2. Between Registers (R-Format)
6-1-3. Between Literal and Memory (Q-Format)
6-1-4. Between Immediate and Memory (I-Format)
6-2. One-Operand General Type (Gl-Format)
6-3. Two-Operand General Type
6-3-1. First Operand for Memory Read (G-Format)
6-3-2. First Operand for 8-Bit Immediate (E-Format)
6-3-3. First Operand for Address Calculation (GA-Format)
6-3-4. Other Two-Operand Instructions
6-4. Short Branch
6-5. Others
7. Addressing Mode
7-1. P Bit
7-2. Symbols Used in Format
7-3. Register Direct
7-4. Register Indirect
7-5. Register Relative Indirect
7-6. Immediate
7-7. Absolute
7-8. PC Relative Indirect
7-9. Stack Pop
7-10. Stack Push
7-11. Register Relation Additional Mode
7-12. PC Relative Additional Mode
7-13. Absolute Additional Mode
7-14. FP Relative Indirect
7-15. SP Relative Indirect
7-16. Format of Additional Mode
7-17. Levels of Additional Mode Specification
8. Description Relating to Implementation
8-1. Supporting Virtual Storage
8-2. Rewrite of Instruction
9. EIT Processing
10. Structure of PSW
10-1. Structure of PSS
10-2. Structure of PSH
10-3. Flag Change
11. Instruction Set Description Format
11-1. Outline of Descriptive Format
11-2. Instruction Bit Pattern and Assembler Syntax
11-3. Field Name
11-4. Operand Field Name
11-5. Restrictions for Addressing Mode
11-6. Notes for Description
12. Instruction Set of The Data Processor of the Present Invention
12-1. Data Transfer Instructions
12-2. Comparison and Test Instructions
12-3. Arithmetic Instructions
12-4. Logical Instructions
12-5. Shift Instructions
12-6. Bit Manipulation Instructions
12-7. Fixed-Length Bit Field Operation Instructions
12-8. Variable-Length Bit Field Operation Instructions
12-9. BCD Arithmetic Instructions
12-10. String Manipulation Instructions
12-11. Queue Manipulation Instructions
12-12. Control Transfer Instructions
12-13. Multiprocessor Support Instructions
12-14. Control Space, Address Space Operation Instructions
12-15. OS-Support Instructions
12-16. MMU Support Instructions
Appendix 1: Instruction Set Reference of The Data Processor of the Present Invention
Appendix 2: Assembler Syntax of The Data Processor of the Present Invention
Appendix 3: Memory Management System of The Data Processor of the Present Invention
Appendix 4: Flag Change of The Data Processor of the Present Invention
Appendix 5: Operation between Different Size Data Sets
Appendix 6: Subroutine Calls for High Level Languages
Appendix 7: Control Registers and Control Space
Appendix 8: CTXB of The Data Processor of the Present Invention
Appendix 9: EIT Processing of The Data Processor of the Present Invention
Appendix 10: Instruction Bit Pattern of The Data Processor of the Invention
Appendix 11: Detail Specification of High Level Instructions and Register Values in End State.
1. Features of The Data Processor of the Present Invention (The Data Processor of the Present Invention)
1-1. Basic Design Concept
The data processor of the present invention is not RISC. The first target of the data processor of the present invention is to execute basic instructions at a high speed. In addition, high level instructions are added.
The data processor 32 of the present invention, which is a 32-bit microprocessor, and the data processor 64 of the present invention, which is a 64-bit microprocessor, have been developed at the same time as a series. From the beginning, the expandability to 64-bit addressing has been considered.
The data processor of the present invention series has been developed along with the OS, so that I-TRON (industrial-TRON), which is a real time OS, and B-TRON (business-TRON), which is a work-station type OS, can be executed at a high speed. The data processor of the present invention meets the data processor of the present invention <<L1R>> specification. In particular, it is focused on the high speed processing in a real storage environment, i.e., virtual memory is not supported.
The data processor of the present invention is a microprocessor which will become the core of an ASIC LSI.
1-2. OS Oriented Architecture
Bit Map Operation Supporting Instructions: Instructions which serve to move and operate the bit map necessary for B-TRON
Context Switch Instructions: Instructions which serve to switch tasks for I-TRON at a high speed
Queue Operation Instructions: Instructions which serve to operate the ready queue and wait queue for I-TRON
Memory Management Using 2-Level Ring Protection: Extra 2-level ring is provided for future expansion.
1-3. Instruction Set Being Tuned
The instruction set is tuned so that frequently used instructions and addressing modes can be described in a short format: Shortening the length of the instructions for operation between registers and of those for the literal operation.
1-4. Instruction Set for Compiler
Instruction set being orthogonalized
16 general-purpose registers used for various purposes such as storing data, addresses and index values.
Sophisticated addressing mode: Additional mode allows index addition and indirect reference in any level.
Arithmetic operations between different size data sets: Different sizes can be specified for the source operand and destination operand.
Sophisticated jump instructions suitable for high level languages
2. The Data Processor 32 of the Present Invention and The Data Processor 64 of the Present Invention
The data processor of the present invention has a 32-bit version, the data processor 32 of the present invention, and a 64-bit version, the data processor 64 of the present invention. From the beginning, expandability to the 64-bit version has been considered. The data processor of the present invention 64 can handle 64-bit integers in addition to the data types handled by the data processor 32 of the present invention.
The 32-bit mode/64-bit mode of the data processor 64 of the present invention is switched in the following manner:
Data Size of Operand
The 32-bit mode/64-bit mode is selected using the size specification bit which exists in each instruction and operand. It is also possible to use an 8-bit mode or a 16-bit mode. The data size is selected from the four types from a two bit field.
The data processor 32 of the present invention does not handle 64-bit data. Consequently, if the 64-bit data size is specified, the instruction in use is treated as an error.
Size of Pointer
Normally, the data processor 32 of the present invention uses a 32-bit pointer, while the data processor 64 of the present invention uses a 64-bit pointer. However, since the data processor 64 of the present invention executes an object code for the data processor 32 of the present invention, it provides a mode which changes the pointer size to 32 bits. Since this mode is specified in PSW, it is possible to use a 32-bit type program and 64-bit type program in a context (process or task).
As an extension bit for 64-bit addressing, a reserved bit named "P bit" is provided every operand which accesses the memory.
Due to the following reasons, the 32-bit size/64-bit size of the pointer is switched by the mode rather than every instruction.
It is difficult to use pointers which differ in size, because they serve to identify the location. If there is a 64-bit size pointer together with a 32-bit size pointer, the location cannot be identified unless the size of all the pointers is 64
bits. Therefore, even if a 32-bit pointer and 64-bit pointer are switched in each instruction, the same specification is repeated in each context. Therefore, its efficiency is low. In such a situation, it is suitable to switch the bit size of the pointer by using the mode, rather than in each instruction.
When the bit size of the pointer is switched between 32 bits and 64 bits using the mode bit, a question about the compatibility between the data processor 32 of the present invention and the data processor 64 of the present invention may arise. However, in the structure where the bit size of the pointer defaults to 32 bits and the mode is changed whenever the 64-bit address is used, a program for the data processor 32 of the present invention can be directly executed in the data processor 64 of the present invention. Even if the bit size of the pointer is switched in each instruction rather than by the mode, OS will know whether the bit size of each context is 32 bits or 64 bits to set the stack and to determine whether the bit size of the system call parameters is 32 bits or 64 bits. A bit size of 32 bits or 64 bits is determined by observing the mode in PSW (which is stored in the stack).
3. Classification of The Data Processor Specifications of the Present Invention
The data processor of the present invention provides optional implementations to meet various needs such as expandability to the 64-bit version, serialization, adaptability to many applications, and so forth. To clarify the optional functions of the data processor of the present invention, the specifications of the data processor of the present invention are classified as follows.
<<L0>> Specification (Level 0)
The minimum specification which will satisfy as the data processor of the present invention requirements: For example, the programming model viewed from the user program (most of ISP, general purpose registers and PSH), bit pattern in machine language, and so forth. Unless otherwise specified, the specification is <<L0>>.
<<L1>> Specification (Level 1)
This specification should usually be implemented, however, when a processor does not have special requirements the <<L1>> specification may not always need to be implemented. <<L1>> specification includes high level functional instructions such as string instructions, additional modes, queue operation instructions, and bit map instructions. The details of <<L1>> instructions will be described separately.
<<L1R>> Specification (Level 1 Real)
The <<L1R>> specification excludes the instruction rerun function and MMU related functions from the <<L1>> specification. This <<L1R>> specification is used to effectively operate I-TRON and micro-BTRON with real memory. The instruction set for <<L1R>> is nearly the same as that for <<L1>>, so the compiler and user program can be used in common with <<L1>>. However, part of the instructions relating to MMU (MOVPA and so forth) and OS (JRNG and so forth) may not be supported.
<<L2>> Specification (Level 2)
This specification will be introduced in accordance with an increase of hardware amount in future:
<<L2>> includes the specification which serves to enhance the symmetry of instructions and are newly added instructions to <<L0>>, <<L1>> or <<L1R>> for high speed operation.
The former includes the "/B" option of the BVSCH instruction, complicated termination conditions of the string instruction, additional mode in indefinite stages, while the latter includes the INDEX instruction.
The <<L2>> specification is represented as "<<L2>>".
<<LX>> Specification (Extension)
This specification will be introduced for the expansion to the data processor of the present invention 64. Although it has the same content as <<L2>>, it is treated as a different class because of the expandability to the data processor 64 of the present invention.
The <<LX>> specification is represented as "<<LX>>".
<<LU>> Specification (Undefined)
The specification which will be introduced for the future extension:
At present, the specification details have not been determined.
<<LV>> Specification (Variable)
The specification which can be freely determined by each manufacturer:
The <<LV>> specification includes the pin assignment of the chip, specification relating to the level and performance of the pipeline, bit pattern assigned to each manufacturer, usage of control registers and so forth. The bit patterns of the instructions assigned to each manufacturer are represented with LV reserved in the bit pattern reference.
<<LA>> Specification (Alternative)
Although the <<LA>> specification describes the standard specification for the data processor of the present invention (or will describe it), if necessary, it may be changed. However, if the specification is changed, the compatibility may be lost. In other words, the <<LA>> specification does not assure the compatibility of the data processor of the present invention.
The <<LA>> specification mainly includes the as memory management system, control registers, and part of the privileged instructions. The data processor of the present invention aims at high speed processing in a real storage environment without an MMU. Thus, the data processor of the present invention does not support most of the <<LA>> specification relating to the memory management.
4. Register Set: see FIG. 7.
The data processor 32 of the present invention provides 16 32-bit general purpose registers, while the data processor 64 of the present invention provides 16 64-bit general purpose registers.
The stack pointer (SP) and frame pointer (FP) are included in the general purpose registers. SP and FR are R15 and R14, respectively.
The program counter (PC) is not included in the general purpose registers.
The general purpose registers serve to store data and base addresses as well as serving as an index register which can be used for many purposes.
A processor status word (PSW) register is provided to store the status of the processor.
SP is switched according to the context (ring number or interrupt processing).
PSW consists of four bytes; the low-order first byte (processor status byte, or PSB) is used to indicate the status, the low-order second byte (processor status half word, or PSH, which is used along with PSB) is used to set the user mode, and the two high-order bytes are used to indicate the system status.
The data processor of the present invention is called a "big-endian" chip. It assigns 8-bit and 16-bit data in the register starting with the LSB side. Thus, an absolute bit number, irrespective of the data size, cannot be defined. A bit number can only defined along with the data size.
8-bit data in the register is assigned 0, 1, . . . , 7 starting with the MSB side. In addition, 16-bit data in the register is assigned 0, 1, . . . , 15 starting with the MSB side. 32-bit data in the register is assigned 0, 1, . . . , 31
starting with the MSB side. Consequently, bit position 7 of 8-bit data, bit position 15 of 16-bit data, and bit position 31 of 32-bit data all correspond to the same bit.
In instructions where the register is used as the destination operand, when the data size of the register is 8 bits or 16 bits, the high-order bytes are not influenced. They are not changed to comply with the specification of the operation in the memory. To influence the high-order bits, use a different data size operation.
EXAMPLE
______________________________________ MOV #H'12345678, R0.W MOV #H'aa, R0.B ______________________________________
When the above instructions are performed, R0 becomes H'123456aa.
When 8-bit data and 16-bit data are placed in a register, they are assigned from the LSB side. For example:
______________________________________ MOV.W #H'12345678,R0 MOV.B #H'aa,R0 MOV.W #R0,R1 ______________________________________
The result of the above instructions is R1=H'123456aa.
When the same operation is performed for the memory with the following instructions,
______________________________________ MOV.W #H'12345678, @R0 MOV.B #H'aa, @R0 MOV.W @R0, R1 ______________________________________
the 8-bit data and 16-bit data are assigned from the MSB side, resulting in R1=H'aa345678. Note that the result in the register differs from that in the memory.
5. Data Type
The data processor of the present invention uses "big-endian". In other words, when the byte address or bit number is assigned, the smaller number (address) is MSB (most significant bit/byte).
In the big-endian structure, the address of some data in the memory differs depending on whether it is treated as 8-bit data or 16(32)-bit data. For example, when
______________________________________ address: N N+1 N+2 N+3 data: 0 0 0 H'12 ______________________________________
although the content of the address N as 32-bit data is H'00000012, (where H' represents hexadecimal notation), when the data of the same content is treated as 8-bit data, it is necessary to refer to the address N+3.
However, since 8-bit data and 16-bit data in the register are assigned from the LSB side, they can be treated as different size data. For example,
______________________________________ MOV #0, R0.W MOV #H'12, R0.B MOV R0.W, R1.W ______________________________________
The result becomes R1=H'00000012. (For the meaning of the instructions, see the related chapter.)
On the other hand, when the same operation is performed for the memory.
______________________________________ MOV #0, @R0.W MOV #H'12, @R0.B MOV @R0.W, R1.W ______________________________________
cause the 8-bit data H'12 and MSB of the 32-bit data to be matched, resulting in R1=H'12000000.
The data types that the data processor of the present invention supports are as follows.
5-1. Bit
The related bit is indicated in FIG. 8. In the case of the bit operation in the memory, offset can be freely used.
In the case of the bit operation in the register, offset can be limited in one register (the upper bits of the offset is ignored).
The bit is assigned using a set of base.sub.-- address, size of base.sub.-- address and offset.
When a bit in the memory is assigned, MSB of the memory address represented by base.sub.-- address is the bit of offset=0. At the time, the assignment of the size of base.sub.-- address does not influence the bit which is actually operated. For the bit operation instruction, to assign the access size for the read-modify-write operation for the memory, the size of base.sub.-- address is assigned. However, the access size does not depend on the bit actually operated.
On the other hand, when a bit in the register is assigned, MSB in the data size which is assigned as the size of base.sub.-- address is the bit of offset=0. The bit actually operated depends on the size of base.sub.-- address.
5-2. Bit Field
Signed bit field
The related bit field is indicated in FIG. 9.
______________________________________ 0 < width .ltoreq. 32 (<<LX>> 0 < width .ltoreq. 64) S: Signed bit ______________________________________
The distance between MSB of base.sub.-- address and that of the related bit field (signed bit) is offset.
In the case of the bit field operation in the memory using the BF:G instruction, offset can be freely used.
In the case of the bit field operation in the memory using the BF:E instruction or the bit field operation in a register, the operation in the bit field which exceeds the one word (1-long word) of base.sub.-- address is not assured.
Unsigned bit field
The related bit field is indicated in FIG. 10.
______________________________________ 0 < width .ltoreq. 32 (<<LX>> 0 < width .ltoreq. 64) ______________________________________
The distance between MSB of base.sub.-- address and that of the related bit field is offset.
In the case of the bit field operation in the memory using the BF:G instruction, offset can be freely used.
In the case of the bit field operation in the memory using the BF:E instruction or the bit field operation in a register, the operation in the bit field which exceeds the one word (1-long word) of base.sub.-- address is not assured.
Unfixed length bit field
Both offset and width can be freely assigned in the condition of width >0.
5-3. Integer
The data type of integer is indicated in FIG. 11.
5-4. Floating Point
The floating point operation is processed by a co-processor. The format of the floating point is specified by IEEE standard. The details of the floating point will be separately specified.
Single precision 32-bit floating point <<Co-processor>>
Double precision 64-bit floating point <<Co-processor>>
80-bit floating point <<Co-processor>>.
5-5. Decimal
The addition, subtraction, multiplication and division in multiple length decimal notation are processed by a co-processor. The main processor of the data processor of the present invention only processes unsigned fixed-length PACKED format decimal numbers and signed PACKED format decimal numbers. However, all the instructions which process the signed PACKED format decimal numbers are <<L2>>. The data type is shown in FIG. 12.
5-6. String
In the string case, the data type is showin in FIG. 13.
5-7. Queue
The data type of linear list connected by double links is shown in FIG. 14.
6. Instruction Format
Any instruction is written in variable length every 16 bits. However, instructions whose length is odd bytes are not permissible.
Instructions with two operands are classified into two types: one is the general type, which has 4 bytes +extension portion and can use all the addressing modes (Ea), and another is the abbreviation type, which can use only frequently used instructions and the addressing mode (Sh). Depending on the instruction function and code size being required, the suitable type can be selected.
Although the instruction format of the data processor of the present invention can be classified into many types, we will roughly classify and describe the types of the instruction format so that the user can easily understand it. For detail types of the instruction format, see Appendix 10.
These are the abbreviations used for the codes described with the format.
-: Portion where an operation code is placed
#: Portion where a literal or immediate value is placed.
Ea: General type addressing mode specified with 8 bits (General Format)
Sh: Abbreviation type addressing mode specified with 6 bits (Short Format)
Rn: Portion where the register is specified.
The format is described assuming that the right side is LSB and the high-order address (big-endian).
Example of Format Description is shown in FIG. 15.
The instruction format can be determined by the two bytes of the address N and address N+1, because any instruction is fetched and decoded every 16 bits (2 bytes).
In any format, the extension portion of Ea or Sh of each operand should be located just after the half word containing the basic portion of Ea or Sh. It has higher precedence than the immediate data which is implicitly specified by an instruction and than the extension portion of an instruction. Therefore, the operation code of an instruction consisting of 4 bytes or more may be separated by the extension portion of Ea.
If extra extension portion is added to the extension portion of Ea in the additional mode, the extra extension portion has higher precedence than the operation code of the next instruction.
For example, consider a 6-byte instruction which consists of the first half word containing Ea1, the second half word containing Ea2, and the third half word. Since the additional mode is used for Ea1, the extension portion for the addition mode is also added as well as the conventional extension portion. At the time, the real instruction bit pattern is assigned in the following order.
First half word of the instruction (including the basic portion of Ea1)
Extension portion of Ea1
Extension portion of Ea1 in the additional mode
Second half word of the instruction (including the basic portion of Ea2)
Extension portion of Ea2
Third half word of the instruction.
When only 8 bits of the 16-bit field are used depending on the alignment, they are placed in the low order (to the higher address). It is applied when the #imm.sub.-- data mode is specified to EaR and ShR while the operand size is 8 bits, when the operand size is 8 bits in the I- format, or when BRA:G, Bcc:G, BSR:G and SS=00. For example, in the following case,
The first byte is an operation code of MOV:I.B.
The second byte is used to specify both part of the operation code and ShW(@RO).
The third byte is 0.
The fourth byte is H'12.
The bit pattern is represented in FIG. 16.
In this case, the upper (lower address) 8 bits of the 16-bit field should be filled with 0. When the upper 8 bits are not 0, the data is unstable depending on the implementation.
In other words, in the case of I-Format or #imm.sub.-- data mode, the operand depends on the implementation, while in the case of the instructions of BRA:G, Bcc:G and BSR:G, the destination to be jumped becomes unstable. In any case, they are not treated as EIT (exception).
6-1. Two Operand Short Format
6-1-1. Register and Memory (S-format, L-format): an example is shown in FIG. 17.
There are two types of instructions in the L-format and S-format: one type is where the size can be specified (MOV:L, MOV:S, CMP:L) and another type is where the size cannot be specified (ADD:L, SUB:L).
For instructions where the size can be specified, the specification of the size by RR and the like is only applied to the memory and the size of the memory is fixed to 32 bits. If the size of the register differs from that of the memory while the size of source is smaller than another, the sign extension is performed. If the size of the source is smaller than another, the high-order byte is truncated and overflow check is performed.
On the other hand, for the instructions of ADD:L and SUB:L where the size cannot be specified, both the operand sizes of the register and memory are fixed to 32 bits.
Since there is a rule for the data processor of the present invention where data in the register is usually treated as a 32-bit signed integer, the size of the register is fixed to 32 bits. This rule is also applied to the bit field instructions and instructions with advanced functions where an operand is placed in the register as well as the instructions in the L-format and S-format.
6-1-2. Between Registers (R-Format): an example is shown in FIG. 18.
6-1-3. Between Literal and Memory (Q-Format): an example is shown in FIG. 19.
6-1-4. Between Immediate and Memory (I-Format): an example is shown in FIG. 20.
The size of the immediate value in the I-format is 8, 16, 32 and 64 bits which are in common with the size of the destination operand. The zero extension and sign extension are not performed.
6-2. One Operand General Type (G1-Format): an example is shown in FIG. 21.
6-3. Two Operand General Type
Instructions which have two operands in the general type addressing mode and which are specified with 8 bits. Occasionally, the total number of operands becomes 3.
6-3-1. First Operand for Memory Read (G-Format): an example is shown in FIG. 22.
6-3-2. First Operand for 8-Bit Immediate (E-Format): an example is shown in FIG. 23.
Although the function of this format is similar to that between the immediate and memory (I-format), their concepts remarkably differ. Since the E-format is a derivation of the 2-operand general type (G-format), the size of the source operand is fixed to 8 bits and the size of the destination operand is selected from 8/16/32/64 bits. In other words, supposing the different size operation, for scr consisting of 8 bits, the zero extension or sign extension is performed in accordance with the size of dest.
On the other hand, in the I-format, the immediate pattern which is frequently used in MOV and CMP is changed to the short type and the size of the source is the same as that of the destination.
6-3-3. First Operand for Address Calculation (GA-Format): an example is shown in FIG. 24.
6-3-4. Other Two-Operand Instructions: an example is shown in FIG. 25.
6-4. Short Branch: an example is shown in FIG. 26.
6-5. Others: except above described, there are examples shown in FIG. 27.
7. Addressing Mode
The data processor of the present invention provides two addressing modes: the short format (Sh), which assigns the address for the memory and registers with a 6 bits field and the general format (Ea), which specifies with an 8 bits field.
If an addressing mode which has not been defined or an improper combination of addressing modes is specified, a reserved instruction exception (RIE) occurs like an execution of the undefined instruction and it causes the exception processing to start. It may occur when the destination is in the immediate mode or when the immediate mode is used for an instruction which calculates the address.
7-1. P Bit
The data processor of the present invention can assign a one-bit optional function assignment bit for accessing the memory. This bit is named the P bit. The P bit is used to add some additional capability whenever the memory is accessed.
The P bit is independently assigned whenever the memory is accessed. Therefore, in case of the register indirect addressing mode, absolute addressing mode, and the like, one P bit is assigned in accordance with the operand. In case of the multiple level indirect addressing mode where the additional mode is used, the P bit should be used for the number of times corresponding to the number of levels. The P bit is expected for tag checking, logical space switching, and switching between
32-bit addressing and 64-bit addressing for future expansion. Therefore, in the current specification, the P bit is reserved.
In the description of the P bit, the position of the P bit is represented with `P`. However, it should always be "0". If the P bit is not "0", a reserved instruction exception (RIE) will occur.
The function of the P bit should conform to the <<LU>> specification.
7-2. Symbols Used in Format
Rn: Assign the register.
P: P bit (always "0")
mem[EA]: Content of the memory at the address represented with EA.
The portion surrounded by dotted lines represents the extension portion.
7-3. Register Direct
Assembler syntax: Rn
Operand: Rn
Format: shown in FIG. 28.
7-4. Register Indirect
Assembler syntax: @Rn
Operand: mem[Rn]
Format: shown in FIG. 29.
7-5. Register Relative Indirect
Assembler syntax:
@(disp, Rn)
@(disp : 16, Rn)
@(disp : 32, Rn)
Operand: mem[disp +Rn]
Format: shown in FIG. 30.
Disp should be treated as a signed operand.
7-6. Immediate
Assembler syntax: #imm.sub.-- data
Operand: imm.sub.-- data
Format: shown in FIG. 31. The size of imm.sub.-- data is assigned in an instruction as the operand size.
7-7. Absolute
Assembler syntax:
@abs
@abs : 16
@abs : 32
@abs : 64 <<LX>>
Operand: mem[abs]
Format: shown in FIG. 32.
In the 32-bit addressing mode, the address specified is extended to the 32-bit signed address. On the other hand, in the 64-bit addressing mode, the address assigned by abs : 16, abs : 32 is extended to the 64-bit signed address.
7-8. PC Relative Indirect
Assembler syntax:
@(disp, PC)
@(disp : 16, PC)
@(disp : 32, PC)
Operand: mem[disp +PC]
Format: shown in FIG. 33.
The PC value being referenced in the PC relative indirect mode is the beginning address of the instruction which includes the operand. Thus, an endless loop can be produced by the following instruction.
When the PC value in the additional mode is referenced, the beginning address of the instruction is used as the reference value of the PC relative indirect mode.
7-9. Stack Pop
Assembler syntax: @SP+
Operand:
mem[SP]
SP is incremented.
Format: shown in FIG. 34.
In the @SP+mode, SP is incremented in accordance with the operand size. For example, when the data processor 64 of the present invention processes 64-bit data, SP is updated by +8. It is also possible to specify @SP+ for an operand which is the size of B and H, so that SP is updated for +1 and +2, respectively. However, it causes the stack alignment to be disordered, resulting in a slower processing speed.
If the @SP+mode is not used for the operand, a reserved instruction exception (RIE) occurs. Actually, a reserved instruction exception occurs when @SP+is used for the write operand and read-modify-write operand.
7-10. Stack Push
Assembler syntax: @-SP
Operand: SP is decremented.
Format: shown in FIG. 35.
In the @-SP mode, SP is decremented in accordance with the operand size. For example, when the data processor of the present invention 64 processes 64-bit data, SP is updated by -8. It is also possible to specify @-SP for an operand which is the size of B and H, so that SP is updated for -1 and -2, respectively. However, it causes the stack alignment to be disordered, resulting in a slower processing speed.
If the @-SP mode is not used for the operand, a reserved instruction exception (RIE) occurs. Actually, a reserved instruction exception occurs when @-SP is used for the read operand and read-modify-write operand.
7-11. Register Relation Additional Mode
Operand:
Rn.fwdarw.>tmp
Additional mode processing
Format: shown in FIG. 36.
For details of the additional mode, see section 7-16.
7-12. PC Relative Additional Mode
Operand:
PC.fwdarw.tmp
Additional mode processing
Format: shown in FIG. 37.
7-13. Absolute Additional Mode
Operand:
0.fwdarw.tmp
Additional mode processing
Format: shown in FIG. 38.
7-14. FP Relative Indirect
Assembler Syntax:
@(disp, FP)
@(disp : 4, FP)
Operand: mem[d4*4+ FP]
Format: shown in FIG. 39.
The prescaled displacement, d4, is treated as a signed operand. It should be used by multiplying by 4 irrespective of the size. Thus, the memory address of the multiples of 4 in the range from (FP-8*4) to (FP+7*4) can be referenced. When the address is described in the assembler representation, the value multiplied by 4 should be described for displacement. This addressing mode is <<L2>>. Since the data processor of the present invention does not provide the FP relative indirect mode, when this mode is specified, a reserved instruction exception (RIE> occurs.
Since this addressing mode cannot be used in the short format, for example,
becomes 4 bytes as follows.
Thus, the code is ambiguously selected, so that the mode is <<L2>>. This mode is expected to effectively use the short format when the rate of usage of the abbreviations is decreased in the data processor 64 of the present invention. In the modes of @(d4:4,FP) and @(d4:4,SP), d4 is used by multiplying by 4 irrespective of the operand size. Therefore, if the modes of @(d4:4,FP) and @(d4:4,SP) are used with variables of 8 bits, 16 bits and 32 bits lengths in the stack frame at the same time, it is necessary to left justify each variable to the word boundary, since the data processor of the present invention is big-endian.
Example of allocation of local variables for using modes of @(d4:4,FP) and @(d4:4,SP) is shown in FIG. 40.
7-15. SP Relative Indirect
Assembler syntax:
@(disp,SP)
@(disp:4,SP)
Operand: mem[d4*4+SP]
Format: shown in FIG. 41.
The prescaled displacement, d4, is treated as a signed operand. It should be used by multiplying by 4 irrespective of the size. However, the operation where d4 is negative is not described. Thus, the memory address of the multiplies of 4 in the range from (SP) to (SP+7*4) can be referenced. When the address is described in the assembler syntax, the value multiplied by 4 should be described for displacement. This addressing mode is <<L2>>. Since the data processor of the present invention does not provide the FP relative indirect mode, when this mode is specified, a reserved instruction exception (RIE) occurs.
Like @(disp:4,FP), this mode is expected to effectively use the short format when the rate of usage of the abbreviations is decreased in the data processor 64 of the present invention.
7-16. Format of Additional Mode
Complicated addressing can basically be separated into a combination of operations of addition and indirect reference. Therefore, when assigning the operations of addition and indirect reference as primitives of addressing, and combining them freely, any complicated addressing mode can be obtained.
The additional mode will be used for such a purpose. A complicated addressing mode is especially useful for data reference between modules and processing systems for artificial intelligent languages.
However, when the addressing mode is widely used for the data processor of the present invention, the processing speed may decrease. Thus, care should be taken to use the memory indirect addressing mode.
The additional mode is specified every 16 bits and repeated for the number of times required.
With only one occurence of the additional mode, the following operations are performed.
Addition of constant (displacement)
Scalling (.times.1, .times.2, .times.4 and .times.8) and addition of index register
Memory indirect reference
With the additional mode in n levels, the indirect reference of up to (N+1) levels can be performed.
Processes of basic additional modes:
Basic format: shown in FIG. 42.
EI=00: Absence of indirect reference; continuation of additional mode
EI=01: Indirect reference; continuation of additional mode
EI=10; Indirect reference; completion of additional mode
EI=11: Dual indirect reference; completion of additional mode
M=0: <Rx> is used as an index.
M=1: Special index
<Rx>=0: The indexes are not added. (Rx=0)
<Rx>=1: PC is used as the index Rx. (Rx=PC)
<Rx>=2 or more: reserved.
D=0:4-bit d4 in the additional mode is multiplied by 4, treated as disp, and then added. d4 should always be multiplied by 4 and used irrespective of the operand size.
D=1: dispx (16/32/64 bits) specified by the extension portion in the additional mode is treated as disp and then added. The size of the extension portion is specified by the d4 field.
d4=0001: dispx is 16 bits.
d4=0010: dispx is 32 bits.
d4=0011: dispx is 64 bits. <<LX>>
XX: Scale of index (scale=1/2/4/8).
S: Size of index register
S=0 <Rx> is extended to signed 32 bits.
S=1 <Rx> is 64 bits <<LX>>
P: P bit <<LU>>.
The P bit is placed in each level of the additional mode.
The P bit can be specified independent from all the memory references.
Whether the indirect reference is performed or not can be selected.
The level which does not perform the indirect reference is used for addition of the base register and index register with multiple levels (such as mem[R1+R2+R3]). It may be used for the relocation base register, etc. by the user.
Size of index register
Since 32-bit data will be frequently used even with a 64-bit address, 32/64-bit address size can be switched in each level of the additional mode.
@(disp:64,Rn) of the register relative indirect and the addressing mode of the memory indirect can be obtained by using the additional mode.
If the scaling of .times.2, .times.4 and .times.8 for PC is performed, the temporary value (tmp) after the processing of the level is completed, the value, depends on the hardware implementation. The effective address obtained by the additional mode cannot be predicted. However, an exception does no occur. Variation of format: shown in FIG. 43, 44.
7-17. Levels of Additional Mode Specification
The additional mode is used for normal indirect reference, as a table reference for external variables for modular object codes, and execution of AI oriented instructions. In particular, the applications of AI may use the indirect reference in many levels. However, the normal applications use it in 4 or less levels.
When the additional mode in any number of levels can be used, the classification by the number of levels in the compiler is not required, thus reducing the load of the compiler. Even if the frequency of the indirect reference in many levels is very small, the compiler should always generate correct codes.
However, from the point of view of implementation, if executing interrupts are accepted in any number of levels, the load on the compiler becomes heavy. Therefore, it is necessary to restrict the number of levels.
The versions of the data processor of the present invention which can use the additional mode with up to only 4 levels (4 basic formats of the additional mode) is defined as the <<L1>> specification. Versions that can use any number of levels are defined as the <<L2>> specification. Even in the <<L1>> specification, it is possible to perform the memory indirect reference up to 5 times. For the additional mode which exceeds 5 levels (5 half words), a reserved instruction exception (RIE) occurs. However, in the format where any number of levels can be used, the number of levels will be extended.
The data processor of the present invention can use the additional mode in any number of levels. However, when the memory indirect addressing is frequently used along with the additional mode, the processing speed may decrease. Especially, if the additional mode with many levels is used in the second operand, an interrupt cannot be accepted during the processing of the additional mode.
Since the data processor 32 of the present invention will use floating point, the scaling of `.times.8` is implemented. The scaling of `.times.8` is the <<L1>> specification rather than the <<LX>> specification.
8. Description Relating to Implementation
8-1. Supporting Virtual Storage
While the data processor of the present invention has provisions for virtual memory, they are not currentry implemented on the data processor of the present invention.
To provide the virtual storage, it is necessary to properly recover page faults which occur during execution of instructions. The data processor of the present invention generally uses the instruction re-execution system.
If a page fault occurs in the instruction re-execution system, the processor resets all the registers and activates the page-in process routine. Thus, even if the execution of instructions are resumed from the beginning, inconsistency does not occur.
In the instruction re-execution system, normally, it is not necessary to hold the status flags during execution. Therefore, the system is comparatively simple. When re-executing instructions, the data processor of the present invention does not use the instructions and addressing mode (such as auto-increment) which may cause side effects however, since the re-execution after the page fault may cause an unnecessary memory access. Therefore, care should be taken when OS operates the I/O device.
For example, if the first operand of a normal instruction serves to read the I/O device and the second operand causes a page fault by the re-executing the instruction, the I/O device is read again. Therefore, inconsistency may occur depending on the type of I/O device. Thus, when an I/O device causes a side effect is read and accessed, take care not to cause a page fault by another operand. Practically, it is possible that another operand is always a register or residual page.
If the source operand and destination operand are partially overlapped, inconsistency will occur when a simple execution is performed.
Example: Moving 2-byte data for 1 byte
The destination is located at the page boundary: shown in FIG. 45.
In FIG. 45, if the MOV.H instruction causes [N-2:N-1] to be moved to [N-1:N], the write cycle of the destination is separated with two sessions. First, the data of [N-2] is written to [N-1] and the former [N-1] is written to [N]. If page M-1
has a fault while the data is written to [N-1], after the page-in operation, [N-2:N-1].fwdarw.[N-1:N] is retried. Since the content of N-1 has been rewritten, inconsistency will occur.
For an instruction such as LDM which serves to transfer data in multiple sessions, if the source and destination are overlapped, care should be taken that inconsistency does not occur during re-execution of the instruction. For example, in the following case,
when R8 is read after loading R6 and R7, if a page fault occurs, R6 has been rewritten upon re-execution. Thus, if the instruction is re-executed from the beginning, inconsistency will occur. To avoid that, it is necessary to take the following countermeasures.
Check that a page fault has not occurred at the beginning of the instruction.
Save the temporary value which represents the address which is transferred during page fault to the stack (a kind of instruction continuous execution system).
Store the initial value of R6 and restore it if a page fault occurs.
These countermeasures should be applied to STM and other instructions.
To re-execute instructions without inconsistency, LDM, STM and LDCTX prohibit the additional mode. On the other hand, ENTER, EXIT and JRNG prohibit all the addressing modes which access the memory.
8-2. Rewrite of Instruction
Generally, a computer which has the stored program system can rewrite the instruction program to be executed by itself through a program. However, when an instruction is rewritten in the current high performance processors which provide prefetch and instruction cache functions and the operation must be assured, the load on the hardware is remarkably increased. The necessity of this function is not high and it is not suitable for software training. Therefore, the data processor of the present invention normally prohibits the instruction codes to be rewritten by software. If the instruction code is rewritten, its operation will not be assured.
In some special applications, instruction codes are produced by a user program and they are executed. Therefore, when some conditions are met, it is necessary to assure the execution operation of instruction codes being rewritten.
To do that, the data processor of the present invention has PIB instruction which informs the processor that instruction codes have been rewritten. By executing this instruction, the execution operation of the instruction codes being rewritten are assured. This instruction serves to inform the processor that the instruction codes to be executed have been probably rewritten (after the processor has been reset or the former PIB instruction has been executed). This instruction will serve to purge the pipeline, instruction queue and instruction cache.
9. EIT Processing
EIT stands for the initial letters of Exception (exceptional interrupt), Interrupt (external interrupt) and Trap (internal interrupt).
In the data processor of the present invention, a process which is asynchronous with the flow of the execution of the program is termed an EIT process.
The EIT processes are generally called exception and interrupt processes. The EIT process contains the following types.
Internal interrupt (call between rings, trap)
It is intentionally generated by the programmer when issuing a system call. It relates to the context which is executed at the time.
Exceptional interrupt (exception)
It occurs if some error is generated during execution of a conventional instruction. It relates to the context being executed at the time.
External interrupt (interrupt)
It occurs when a signal is generated by external hardware. It does not relate to the context being executed at the time.
For details of the EIT processing, see Appendix 9.
10. Structure of PSW
PSW (Processor Status Word) of the data processor of the present invention consists of 32 bits. The lower 16 bits of PSW (PSH--Processor Status Halfword) is used for the user program. It can be freely operated by the user process. On the other hand, the upper 16 bits of PSW (PSS--Processor Status halfword for System) is used for the system. Therefore, it cannot be operated by the user program (ring 3). The upper 8 bits of PSH serves to set various modes and are named PSM (Processor Status byte for Mode). In addition, the lower 8 bits of the PSH serves to display the operation result, which is named PSB (Processor Status Byte): shown in FIG. 46.
10-1. Structure of PSS: shown in FIG. 47.
Reserved to `0`.
If `1` is written, a reserved functional exception (RFE) occurs.
______________________________________ SM,RNG = 000 Uses the external interrupt stack pointer (SPI) at ring 0. SM,RNG = 001 reserved SM,RNG = 010 reserved SM,RNG = 011 reserved SM,RNG = 100 Uses the stack pointer for ring 0 (SP0) at ring 0. SM,RNG = 101 Reserved (for ring 1) SM,RNG = 110 Reserved (for ring 2) SM,RNG = 111 Uses the stack pointer for ring 3 (SP3) at ring 3. SM,RNG is <<LA>>. (SM: Stack Mode, RNG: Ring) XA = 0 32-bit context XA = 1 64-bit context <<LX>> AT = 00 Absence of address conversion AT = 01 Presence of address conversion (the data processor of the present invention standard MMU specification) AT = 10 Absence of address conversion, memory protection by address (<<L1R>>) AT = 11 reserved (AT: Address Translation mode) DB = 0 Context which is not currently debugged DB = 1 Context which is currently debugged IMASK Interrupt priority which inhibits an external interrupt and DI (Delayed Interrupt). IMASK = 0000 Accepts only NMI (unmaskable interrupt of priority 0) IMASK = 0001 Masked up to priority 1 (consequently, accepts NMI only). IMASK = 0010 Masked up to priority 2. represented by IMASK. IMASK = 1110 Masked up to priority 14. IMASK = 1111 Not masked ______________________________________
The data processor of the present invention controls the memory by 4 levels of ring protection as the <<LA>>specification. (See Appendix.) The data processor of the present invention controls the memory by 2 levels of ring protection. The RNG field represents which rings exist in the current processor. Even if the ring protection is not performed, this field is used to switch between the supervisor mode and the user mode.
The XA bit of the data processor of the present invention32 is reserved. If `1` is written to the bit, an exception occurs.
Since it is difficult to standardize the debug information such as trace in detail, it is stored in a different control register (DCR--Debug Control Register). However, only the information which represents the debugging condition is stored in PSW as DB.
the lower priority external interrupts of the data processor of the present invention are represented with higher numbers. The priority of the external interrupts consist of seven levels from 0 to 7. The priority 0 is the unmaskable interrupt (NMI).
Since it is difficult to completely standardize the control information of the cache and MMU, it is separated from PSW.
Since AT (address translation specified field) is placed in PSW, it is possible to convert the address any context, change the memory protection method, and temporarily stop the address translation only during execution of the EIT process handler.
When AT (address translation bit) in PSW is changed from `00` to `01` by starting LDC, REIT, LDCTX or EIT; TLB and cache purge are automatically conducted, so that TLB and matching with the logical cache is assured. In addition, when AT is changed from `01` to `00`, the matching of the cache (logical cache and physical cache) is assured.
10-2. Structure of PSH: shown in FIG. 48.
Reserved to `0`
If `1` is written, a reserved functional exception (RFE) occurs.
PRNG: Ring number just before entering this ring. PRNG is <<LA>>.
P: P-bit Error Flag <<LU>>
Set if an error relating to the P-bit function occurs. Otherwise, it is cleared. Reserved to `0` at present.
F: General Flag
Used to detect the cause of the termination of a high level instruction.
X: Extension Flag
The carry-out of a multiple length operation.
V: Overflow Flag
Indicates an overflow occurence.
L: Lower Flag
Indicates the contents of the first operand is smaller than those of the other operand in a comparison instruction for both signed with signed comparison and unsigned with unsigned comparison.
M: MSB Flag
Indicates the MSB of the operation result is `1`.
Z: Zero Flag
Indicates the operation result is `0`.
The "ring just before entering" in the PRNG field represents a "ring which is placed at one outer location" or a "ring which requests a service to the ring". Thus, when EIT occurs, PRNG changes as follows:
When EIT occurs in the return mode with the REIT instruction, PRNG changes as follows:
In the return mode, it is necessary to return from the stack rather than copying RNG. The relationship RNG.ltoreq.PRNG is always satisfied. PRNG is referenced by the ACS command. Actual ring transition uses the information of RNG.
In instruction flow from compared to the conditional jump, processors other than the data processor of the present invention usually distinguish signed data and unsigned data by using a conditional jump instruction rather than a comparison instruction.
For example, unsigned integers are compared using the following instructions:
______________________________________ CMP src1,src2 BLTS next Branch Lower Than (Signed) ______________________________________
Signed integers are compared using the following instructions:
______________________________________ CMP src1,src2 BLTU next Branch Lower Than (Unsigned) ______________________________________
Thus, in this type of flag implementation, information to distinguish the size of numbers and the presence or absence of signs is required.
In the data processor of the present invention, however, the distinction between the presence or absence of a sign is made by using different compare instructions such as the CMP and CMPU instructions. On the other hand, the conditional jump instruction can be used regardless of whether the contents are signed or unsigned. Thus, the flag structure is simplified.
The carry flag used in conventional processors has two functions: one serves to compare the size of unsigned integers and another serves to represent a carry-out in multiple length operations. However, for the latter function, since the data processor of the present invention uses X.sub.-- flag, the carry flag is used only for comparing the size of integers. Thus, the carry flag of the data processor of the present invention is defined as that which represents the relationship of size and is named L.sub.-- flag (Lower Flag). In the case of an unsigned operation, this flag works as conventional carry flag. In the case of a signed operation, it represents the true size since it includes the overflow, unlike conventional carry flags.
F.sub.-- flag (general flag), which represents the termination condition of a string instruction and queue instruction, and P.sub.-- flag (P-bit error flag) which represents an error of the P bit are provided. P.sub.-- flag is reserved to `0` in the specification at present.
Although conventional processors use a carry flag which can contain the dropped bit from a shift instruction, the data processor of the present invention has L.sub.-- flag rather than a carry flag, so that the dropped bit is placed in X.sub.-- flag.
10-3. Flag Change
All the addition, subtraction, comparison and logical operation instructions are 2-operand instructions which have the following format:
If the size of dest differs from that of src, the smaller size operand is sign-extended in accordance with the larger size operand (ADDU, SUBU and CMPU are zero-extended), calculated, the result of the operation is converted into the size of dest, and then stored in dest.
In the case of CMP, CMPU, SUB and SUBU, L.sub.-- flag indicates that the size of the first operand of the previous operation is smaller. For CMPU and SUBU, which are for unsigned operations, L.sub.-- flag functions like the carry (borrow) flag of the convention processors. In a signed operation, L.sub.-- flag represents the true size because it includes the overflow, rather than just copying the M.sub.-- flag. In the ADD instruction, L.sub.-- flag indicates whether the result is negative. It also represents true positive and negative as well as overflow rather than copying the M.sub.-- flag. In the ADDU, since the result always becomes positive, L.sub.-- flag is set to `0`.
V.sub.-- flag indicates the result of the operation cannot be shown by the size being specified. In other words, when the result of an operation cannot be represented by the signed integer of the size of dest (unsigned integer for ADDU and SUBU), V.sub.-- flag is set. In the CMP and CMPU instructions, the status of the V.sub.-- flag is unchanged.
X.sub.-- flag is used to maintain the status of a carry-out in multiple length operations. The flag status is changed regardless of whether the operation is signed or unsigned. Although it functions similar to the carry flag of conventional processors, only the addition, subtraction and shift instructions change X.sub.-- flag.
In the CMP, SUB, CMPU and SUBU instructions, the status of L.sub.-- flag is changed in a similar manner. While SUB, SUBU and SUBX instructions cause X.sub.-- flag to change, CMP and CMPU instructions do not cause it to changed.
In the case of MOV, MOVU, ADD, ADDU, ADDX, SUB, SUBU and SUBX instructions, the statuses of M.sub.-- flag and Z.sub.-- flag are changed depending on the value when the operation result is converted in the size of dest. Thus, if the size of dest is smaller than that of src, even if the operation result is not 0, Z.sub.-- flag may be set. On the other hand, in the CMP and CMPU instructions, the status of Z.sub.-- flag is changed depending on the value of the operation result regardless of the size of dest.
Example: If @dest.B=1
SUB #H'101.W,@dest.B.fwdarw.>Although the operation result 1-H'101 is not 0, since dest becomes 0, Z.sub.-- flag is set.
CMP #H'101.W,@dest.B.fwdarw.>Since the operation result 1-H'101 is not 0, Z.sub.-- flag is cleared.
In ADDX and SUBX instructions, the flag status is irregularly changed to some extent, so that it can be used for both the unsigned integer extended operation and signed integer extended operation. In this case, although it does not completely match the mnemonic of the conditional jump instruction, since the extended operation is not frequently used, this irregularity should be permissible.
L.sub.-- flag: Represents the relationship of size (SUBX) and positive and negative (ADDX) for signed operation.
V.sub.-- flag: Represents an overflow for signed operation.
X.sub.-- flag: In ADDX, represents a carry from the size of dest for the dest +src+X.sub.-- flag operation. In SUBX, it represents a borrow from the size of dest for the dest -src-X.sub.-- flag operation. However, if the size of src is smaller than that of dest, src is sign-extended. In SUBX, if the size of src is the same as that of dest, X.sub.-- flag consequently represents the result of the comparison as unsigned data.
When an operation between different size operands is performed with ADDX and SUBX, the smaller size operand is sign-extended. However, whether the value which is sign-extended is operated on as a signed value or an unsigned value depends on the status of the flag.
In the MOV instruction, MOVU instruction and logical operation instructions, the statuses of X.sub.-- flag and L.sub.-- flag are not changed.
In the logical operation instructions, the status of V.sub.-- flag is not changed.
The details of status flag changes are described in each instructions description. Special attention should be given descriptions marked with an astarisk.
11. Instruction Set Description Format
11-1. Outline of Descriptive Format
MNEMONIC: Represents the name (mnemonic) of the instruction.
OPERATION: Summarizes the function of the instruction.
OPTIONS: Represents the types of options available for the instruction. The options of the instruction serve to change the sub-functions of the instruction and are described as `/xxx` in the assembler syntax.
INSTRUCTION FORMAT AND ASSEMBLER SYNTAX: Represents the bit pattern, assembler syntax, size, and type of the instruction. In the data processor of the present invention, one instruction mnemonic may have multiple instruction formats such as the general format and short format, each of which is used depending on the addressing mode and size. This paragraph describes the addressing mode and size used in each instruction format.
STATUS FLAGS AFFECTED: Shows how the status flags (PSB) are changed after the instruction is executed.
DESCRIPTION: Describes the functions of the instruction. For details of the assembler mnemonics used in the description, see the Appendix at the end of the manual.
11-2. Instruction Bit Pattern and Assembler Syntax
The "INSTRUCTION FORMAT AND ASSEMBLER SYNTAX" portion is comprised of the mnemonic by format, operand name, operand field name and instruction bit pattern. Example of Description is shown in FIG. 49.
AND:G . . . Mnemonic-every-Format
Represents the mnemonic-every-format of the instruction bit pattern to be described (see Appendix).
src, dest . . . Operand Name
Varia