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United States Patent
4870704
Matelan , ; et al.
September 26, 1989
Title
Multicomputer digital processing system
Abstract
A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.
Inventors:
Matelan; M. Nicholas
(Dallas,
TX
)
, Leete; Thomas G.
(Plano,
TX
)
, Zsohar; Leslie
(Carrollton,
TX
)
, Blanchard; Michael K.
(Bedford,
TX
)
, Naeini; Abdolreza
(Carrollton,
TX
)
, Hsu; Jacob
(Farmers Branch,
TX
)
, Smith; Dennis K.
(Forth Worth,
TX
)
Assignee:
Flexible Computer Corporation
(Dallas,
TX
)
Appl. No.:
666991
Filed:
October 31, 1984
Current U.S. Class:
710/120
Field of Search:
364/2MSFile,9MSFile 371/9,10,11
U.S. Patent Documents
4219873
August 1980
Kober et al.
4228496
October 1980
Katzman et al.
4245306
January 1981
Besemer et al.
4263649
April 1981
Lapp, Jr.
4404628
September 1983
Angelo
4417303
November 1983
Korowitz et al.
4456965
June 1984
Graber et al.
4472771
September 1984
Bienvenu et al.
4484273
November 1984
Stiffler et al.
4490785
December 1984
Strecker et al.
4495569
January 1985
Kagawa
4495571
January 1985
Staplin, Jr. et al.
4543630
September 1985
Neches
4564900
January 1986
Smitt
4577273
March 1986
Hopper et al.
4733352
March 1988
Nakamura et al.
Other References
"VME Bus Specification Manual", Revision A, Oct. 1981, Motorola. .
IBM Synchronous Data Link Control General Information, Third Edition, 1979, IBM Corporation. .
Katsuki et al., "Pluribus-An Operational Fault-Tolerant Multiprocessor," Proceedings of the IEEE, vol. 66, No. 10, Oct. 1978, pp. 1146-1159..~
Primary Examiner:
Shaw; Gareth D.
Assistant Examiner:
Fairbanks; Jonathan C.
Attorney, Agent or Firm:
Hubbard, Thurman, Turner & Tucker
Claims
What is claimed is:
1. A data processing system comprising:
A. a first bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a first bus protocol that defines the timing, formats for the address, data, control and interrupt information, and response format, for an information transfer between a requestor device and a responder device of a plurality of devices connected to the first bus, said control signals including;
(1) an INTERLOCK signal from said requestor to the responder defining an interlock period, wherein the responder locks out all other information transfers to it except for information transfers with the requestor until the requestor information transfer does not include the INTERLOCK control signal, during the interlock period the responder is to transmit a RETRY control signal to all devices attempting access, all devices receiving a RETRY control signal are to store an identifier code of the device sending the RETRY control signal, lock out all other access attempts responding with a RETRY control signal, monitor all information transfers on the first bus and determined if the responder's identifier code is contained in the control signals, and upon occurrence of the code, an error indication or a timeout indication reinitiate the transfer to that responder device;
(2) a WAIT control signal from the responder in response to an access from the requestor and defining a requestor WAIT period, wherein the requestor locks out all attempted accesses responding with a RETRY control signal, monitors a plurality of control signals representing the source identifier code of the responder, responds only to access with theresponder's source identifier code, and remains in the WAIT period until the responder has transmitted a COMPLETE control signal or until an error indication or a timeout indication;
(3) an OVERRIDE control signal defining that a device receiving the OVERRIDE control signal must relinquish control of the first bus and reinitiate its bus transaction after the transaction by the device transmitting the OVERRIDE control signal; and
(4) a TYPE control signal indicating a process wherein the transmitter of the TYPE control signal will properly respond to the INTERLOCK, RETRY, WAIT, COMPLETE and OVERRIDE control signals;
said first bus including a first plurality of serially coupled connectors along said first bus lines;
B. at least two second buses including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a second bus protocol that defines the timing formats for the addresss, data, control and interrupt information, and response format, an information transfer between a requestor and a responder device of a plurality of devices connected to the second buses, said control signal including:
(1) an INTERLOCK signal from said requestor to the responder defining an INTERLOCK period when the responder is only to respond to information transfers from the requestor until the information transfer from the requestor does not include the INTERLOCK signal or until an error indication or a timeout indication;
(2) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the second bus and reinitiate its bus transaction after the transaction by the device sending the OVERRIDE signal; and
(3) a TYPE control signal indicating that the transmitter of the TYPE control signal will properly respond to the INTERLOCK and OVERRIDE control signals;
each of said second buses including a second plurality of connectors serially coupled to said second bus lines;
C. An input/output Bus,
D. a test bus including a plurality of lines for the serial transfer of information;
E. a plurality of computer units, each connected to one of the plurality of second buses and including:
(1) a Resource Monitor circuit connected to the test bus for controlling and monitoring the computer unit circuitry;
(2) a processor including a processor address decode means controlled by said Resource Monitor for providing addressable access to the processor for an internal bus;
(3) a computer unit clock means for providing at least one timing signal to the computer units circuitry;
(4) bus gate means for controlling the transfer of information between the internal bus, the second bus and the input/output bus;
(5) bus address decode means for decoding addresses from either the second bus or the input/output bus, and indicating when the address is within an address space provided by the Resource Monitor;
(6) an interrupt handler for receiving interrupts from the second or input/output buses and accordingly generating signals to the processor;
(7) a bus requestor for receiving requests for access to either the second or the input/output bus and interfacing with an arbiter circuit provided to generate bus access grants in accordance with an arbitration scheme from the Resource Monitor;
(8) access control means for controlling the transfer of information between the internal bus, the input/output bus, the processor, a memory, and the second bus by (a) generating enabling signals to enable transfer of information from either the second or input/output bus, the processor or the memory along the internal bus, (b) providing an appropriate response to transfers received from either the input/output bus or the second bus, (c) providing the appropriate signals to either the input/output bus or the second bus for a transfer of information from said processor, and (d) providing the appropriate signals for a transfer of information from either the second or input/output bus to the other;
F. a first bus control unit connected to the first bus and a unique one of the plurality of second buses and;
G. at least one first bus access unit connected to the first bus and each connected to a unique one of the remaining second buses;
said first bus control unit and first bus access unit each including;
(1) a bus requestor for transmitting a request for access to either the first or second bus and receiving access grants in response thereto;
(2) a bus address decode means for decoding addresses on either bus and indicating a transfer between buses;
(3) bus information interface means for transferring information from one bus to the other in response to control signals;
(4) protocol logic for (a) receiving address indications, (b) transmitting access requests in response thereto, (c) generating control signals to provide an information transfer (d) generating a response to the received address transfer;
(5) a unit Resource Monitor for controlling and monitoring the unit circuitry and connected to the Test Bus;
(6) a common lock interface for providing data to either bus, said data including the accessibility status of system addressable devices and for transmitting requests to access the devices;
(7) second bus arbiter for receiving second bus access requests and for providing grants for access to the second bus;
(8) an interrupt interface means connected to receive a time division multiplexed interrupt signal from the first bus and generate an interrupt to a computer unit on the second bus;
said first bus control unit further including;
(1) bus request arbitration logic means for receiving first bus access requests and providing first bus grants;
(2) a common lock arbitration means for receiving requests to access system addressable devices and for granting these requests in accordance with a device access arbitration scheme;
(3) InterComputer interupt control logic connected to the first bus and including (a) interrupt address decode means for indicating that a first bus information transfer is an interrupt control logic access, (b) an interrupt word register for storing of interrupt status information for each computer unit, the status accessible to first bus information transfers, (c) interrupt generation means to generate a time division multiplexed signal including an interrupt to a computer unit when its respective word register receives data from an information transfer, and (d) interrupt response logic for generating appropriate protocol responses to information transfers to the interrupt control logic unit;
said first bus access unit further including a memory connected to the first bus for responding to information transfers addressed thereto;
H. a system monitor including processing means connected to the Test Bus for monitoring and controlling system operation and further including a mass memory device for the storage of system configuration information and system monitoring information, and a network interface connectable to other system monitor units of other data processing systems.
2. A data processing system comprising:
A. a Common Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Common Bus protocol that defines the timing and formats for the address, data, control and interrupt information, and response, for an information transfer between a requestor device and a responder device of a plurality of devices connected to the Common Bus, said control information including;
(1) an INTERLOCK signal from said requestor to the responder defining an interlock period, wherein the responder locks out all other information transfers to it except for information transfers with the requestor until the requestor information transfer does not include the INTERLOCK control signal, during the interlock period the responder is to transmit a RETRY control signal to all devices attempting access, all devices receiving a RETRY control signal are to store an identifier code of the device sending the RETRY control signal, lock out all other access attempts responding with a RETRY control signal, monitor all information transfers on the Common Bus and determine if the responder's identifier code is contained in the control signals, and upon occurrence of the code, an error indication or a timeout indication reinitiate the transfer to that responder device;
(2) a WAIT control signal from the responder is response to an access from the requestor and defining a requestor WAIT period, wherein the requestor locks out all attempted accesses responding with a RETRY control signal, monitors a plurality of control signals representing the source identifier code of the responder, responds only to accesses with the responder's source identifier code, and remains in the WAIT period until the responder has transmitted a COMPLETE control signal or until an error indication or a timeout indication;
(3) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Common Bus and reinitiate its bus transaction after the transaction by the device transmitting the OVERRIDE control signal; and
(4) a TYPE control signal indicating that the transmitter of the TYPE control signal will properly respond to the INTERLOCK, RETRY, WAIT, COMPLETE and OVERRIDE control signals.
said Common Bus including a first plurality of serially coupled connectors along said Common Bus lines;
B. at least two Local Buses including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Local Bus protocol that defines the timing, formats for the address, data, control and interrupt information, and response format, and information transfer between a requestor and a responder device of a plurality of devices connected to the Local Buses, said control signals including:
(1) an INTERLOCK signal from said requestor to the responder defining an INTERLOCK period when the responder is only to respond to information transfers from the requestor until the information transfer from the requestor does not include the INTERLOCK signal or until an error indication or a timeout indication;
(2) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Local Bus and reinitiate its bus transaction after the transaction by the device sending the OVERRIDE signal; and
(3) a TYPE control signal indicating that the transmitter of the TYPE control signal with properly respond to the INTERLOCK and OVERRIDE control signals;
each of said Local Buses including a second plurality of connector serially coupled to said Local Bus lines;
C. a Peripheral Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a protocol similar to the Local Bus protocol;
D. a Test Bus including a plurality of lines for the serial transfer of information, said Test Bus serially connected to a selected plurality of said Local Bus connectors;
E. each of said Local Bus connectors positioned to receive a computer unit including:
(1) a Resource Monitor circuit connected to the Test Bus for controlling said monitoring the computer unit circuitry;
(2) a processor for independently executing instructions on data and connected to the Resource Monitor and a computer unit Internal Bus and further including an address decode circuit for receiving a processor address space from the Resource Monitor and for providing a signal to the processor when an address present on the Internal Bus is within the processor address space;
(3) a computer unit clock means for providing at least one timing signal to the computer unit circuitry;
(4) bus gate means for controlling the transfer of information between the Peripheral Bus and Local Bus and a computer unit Internal Bus;
(5) bus address decode means for receiving address information from either said Local Bus or Peripheral Bus, comparing the address with a computer unit address space provided from said Resource Monitor, determining when the address is within the address space, accordingly, generating an address decode signal;
(6) an Internal Bus gate means connected to the Local Bus and Peripheral Bus for controlling the transfer of information to an Internal Bus;
(7) an interrupt handler for receiving interrupt signals from either the Peripheral Bus or the Local Bus and generating signals to the processor indicating the reception of the interrupt, and generating response signals for transmission on the Peripheral Bus or Local bus indicating acknowledgement of the receipt of the interrupt;
(8) a bus requestor and arbiter means for receiving signals from said processor or one of the buses indicating a request for access to the other bus and for receiving signals from the Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of bus access on one of the arbitration lines, said Resource monitor controlling the operation of the arbiter means and controlling which of a plurality of arbitration schemes within the arbitration means determines which of the received requests is granted bus access;
(9) access control means for providing a plurality of control signals to regulate the transfer of information between the processor, a memory, the Local Bus and the Peripheral Bus and including;
(a) bus control signal circuitry means (i) and (A) receiving a plurality of control signals from either the processor or one bus representing a request for generating an information transfer on the other bus, (B) transmitting the request to the other bus requestor, (C) generating signals for an information transfer on the other bus in accordance with bus protocol, (d) generating control signals to the other bus gate means for transferring the information to the other bus upon the receipt of the grant, or, (ii) in response to information on the other bus, (A) generating control signals to the other bus gate means and Internal Bus gate means for receiving information from the other bus, (B) receiving the indication from the other bus address decode means and, (C) in accordance with such indication, (I) generating a plurality of synchronization signals to either the processor or the memory for the reception of information from said bus, or (II) for (a) generating control signals to initiate bus transfer from other bus to the bus gate means for the transfer of information from the other bus, (b) transmitting a request for access to the one bus requestor; (c) generating a response on the other bus to respond to the received information and (d) generating control signals to the one bus buffer for gating the information, in accordance with an access grant;
(b) an Internal Bus control means for regulating the information flow on the Internal Bus by controlling access to the Internal Bus by the processor, the memory, the Peripheral Bus and the Local Bus and including an internal arbiter for receiving Internal Bus request signals from the processor, the bus address decoder, the interrupt handler, and the bus requestor, and for generating an Internal Bus grant signal in accordance with a predetermined arbitration scheme, and providing enabling signals to Internal Bus gate logic for an information transfer over the Internal Bus;
F. a Common Bus control unit connected to the Common Bus and a unique one of the plurality of Local Buses and;
G. at least one Common Bus access unit connected to the Common Bus and each connected to a unique one of the remaining Local Buses;
said Common Bus control unit and Common Bus access unit each including;
(1) a Common Bus buffer means for gating the transfer of information between the Common Bus and a unit Internal Common Bus in accordance with received control signals;
(2) a Local Bus buffer means for gating information between the Local Bus and the buffered Local Bus in accordance with received control signals;
(3) a Common Bus requestor means for receiving a request for Common Bus access and for transmitting the request on one of a plurality of request lines, said lines selected by a unit Resource Monitor, and for receiving a grant indication upon the selected line;
(4) a Common Bus address decode means for receiving Common bus signals including a Common Bus address, comparing the received Common Bus address with a Local Bus address space provided from the unit Resource Monitor, determining when the Common Bus address is within the Local Bus address space and, accordingly, generating a signal indicating that the information present on the Common Bus is to be transferred to the connected Local Bus;
(5) a Local Bus to Common Bus address decode means for receiving Local Bus signals including a Local Bus address, comprising the received local Bus address with a Common Bus address space provided by the Resource Monitor, determining when the Local bus address is within the Common Bus address space and, accordingly, generating a signal indicating the information present on the connected Local Buses is to be transferred to the Common Bus;
(6) Common Bus/Local Bus interface means for latching information for transfer from the Internal Common Bus to the buffered Local Bus and for gating information from the buffered Local Bus to Common Bus in accordance with received control signals;
(7) a Local Bus requestor and arbiter for receiving signals indicating an access request Local Bus, transmitting the request to a connected arbitration circuit for generating a signal indicating a grant of Local Bus access, said Resource Monitor controlling the operation of the arbitration circuit by indicating which one of the plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted Local Bus access;
(8) protocol signal control logic means for, (A) in response to information on the connected Local Bus;
(1) generating control signals to the Local Bus buffer means for receiving information onto the buffered Local Bus;
(2) receiving said decode indication and, in accordance therewith;
(3) transmitting a request for Common Bus access,
(4) generating control signals to the Common Bus/Local Bus interface to transfer information;
(5) generating a response to the Local Bus;
(6) generating control signals to the Common Bus buffer for gating the information on the Internal Common Bus to the Common Bus in accordance with a grant;
and for, (B) in response to information on the Common Bus,
(1) generating control signals to the Common Bus buffer means for receiving information onto the Internal Common Bus;
(2) receiving said decode indication and, in accordance therewith;
(3) transmitting a request for Local Bus access;
(4) generating control signals to the Common Bus/Local Bus interface means to latch information;
(5) generating a response to the Common Bus;
(6) generating control signals to the Local Bus buffer for gating the information on the buffered Local Bus to the Local Bus in accordance with a grant signal form the Local Bus requestor;
(9) a unit Resource Monitor including means for controlling and monitoring unit circuitry and connected to the Test Bus;
(10) a unit clock means for providing at least one timing signal to the Common Bus control unit circuitry;
(11) common lock interface means connected to the buffered Local Bus for responding to the addresses specified by the Resource Monitor and providing status information of individual system addressable devices and further connected to a Lock Bus for transmitting requests for access to the individual system addressable devices and for receiving grants of such requests;
(12) an InterComputer interrupt interface means connected to the common Bus and the Local Bus for receiving a time division multiplexed interrupt signal, and including circuitry that receives inputs from the Resource Monitor for demultiplexing the interrupt signal and generating an InterComputer interrupt signal on the Local Bus in response thereto;
said Common Bus control unit further including;
(1) common lock arbitration means connected to the Lock Bus for receiving said requests and for providing grants to access the individual system addressable device in accordance with information from the Resource Monitor;
(2) Common Bus request arbitration logic means connected to receive requests for access to the Common Bus and for granting Common Bus requests in accordance with information from the Common Bus control unit Resource Monitor;
(13) Intercomputer interrupt control logic connected to the Internal Common Bus and including;
(a) interrupt control address decode means to receive address information from the Common Bus, comparing the received address with an InterComputer interrupt control address space provided by the Resource Monitor, determining when the received address is within the address space, and accordingly generating a signal indicating the information present on the Common Bus is to be received by the InterComputer interrupt control logic;
(b) interrupt word register means for receiving said indication signal and selecting one of a plurality of registers in accordance with said received address, and either, ORing the contents of the selected register with the Common Bus data and storing the ORed results in the register for a write operation, or clearing the contents of the register after a read operation;
(c) interrupt generation means for receiving said indication signal from the InterComputer interrupt decoder means, and, for a write operation, generating at time division multiplex signal including an interrupt in accordance with the received address, and transmitting the time division multiplexed interrupt signal on the Common Bus;
(d) InterComputer interrupt response logic means to generate response signals to the received Common Bus address, in accordance with the Common Bus protocol;
said Common Bus access unit further including;
(14) Common bus memory circuit including;
(a) Common Bus memory address decode means for receiving Common bus signals including a Common Bus address, comparing the received Common Bus address with a Common Bus memory address space provided by the Resource Monitor determining, when the received Common Bus address is within the Common Bus memory address space, and, accordingly generating a signal indicating that the information on the Common bus is to be transferred to the Common Bus memory;
(b) Common Bus memory interface logic means for receiving the indicating signal, generating access signals to the Common Bus memory for providing access to the Common Bus memory in accordance with the Common Bus address, data and control signals;
(c) Common Bus memory response logic means for generating a response on the Internal Common Bus to the Common Bus information and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common bus to the Common Bus;
H. a system monitor means including a first processor for transferring information via the Test bus to the Resource Monitors of the computer units, Common Bus access units and Common Bus control unit and connected to at least one environmental sensor, a first address specification device, a real time clock, a power relay for controlling power to the data processing system, a mass memory for storing program information including the configuration information for each Common Bus control unit, Common Bus access unit, and computer unit, and a first processor memory means for storing a program of instructions for execution by the first processor for (1) the transfer of the configuration information by the Test Bus to each Resource Monitor, (2) for monitoring the system operation from the Resource Monitors, (3) for receiving information from and providing information to an operator terminal, (4) for regulating power to the data processing system through the power relay in accordance with information received from the environmental sensor, said first processor connected to first and second data buffers, said data buffers further connected to a second processor, said first data buffer providing storage of data from said first processor to said second processor and said second data buffer providing storage of data from said second processor to said first processor, said second processor connected to a second address specification device, a network bus, and a second processor memory which includes instructions for execution by said second processor to provide: (1) transfer of information with said first processor via the first and second data buffers and (2) transfer of information via the network bus.
3. A data processing system comprising:
A. a Common Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Common Bus protocol that defines the timing and formats for the address, data, control and interrupt information, and response format, for an information transfer between a requestor device and a responder device of a plurality of devices connected to the Common Bus, said control information including;
(1) an INTERLOCK signal from said requestor to the responder defining an interlock period, wherein the responder locks out all other information transfers to it except for information transfers with the requestor until the requestor information transfer does not include the INTERLOCK control signal, during the interlock period the responder is to transmit a RETRY control signal to all devices attempting access, all devices receiving the RETRY control signal are to store an identifier code of the device sending the RETRY control signal, lock out all other access attempts responding with a RETRY control signal, monitor all information transfers on the Common Bus and determine if the responder's identifier code is contained in the control signals, and upon occurrence of the code, an error indication or timeout indication reinitiates the transfer to that responder device;
(2) a WAIT control signal from the responder in response to an access from the requestor and defining a requestor WAIT period, wherein the requestor locks out all attempted accesses responding with a RETRY control signal, monitors a plurality of control signals representing the source identifier code of the responder, responds only to accesses with the responder's source identifier code, and remains in the WAIT period until the responder has transmitted a COMPLETE control signal or until an error indication or a timeout indication;
(3) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Common bus and reinitiate its bus transaction after the transaction by the device transmitting the OVERRIDE control signal; and
(4) a TYPE control signal indicating that the transmitter of the TYPE control signal will propelly respond to the INTERLOCK, RETRY, WAIT COMPLETE and OVERRIDE control signals;
said Common bus including a first plurality of serially coupled connectors along said Common Bus lines;
B. at least two Local Buses including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Local bus protocol that defines the timing and formats for the address, data, control and interrupt information, and response format, an information transfer between a requestor and a responder device of a plurality of devices connected to the Local Buses, said control signals including:
(1) an INTERLOCK signal from said requestor to the responder defining an INTERLOCK period when the responder is only to respond to information transfers from the requestor until the information transfers from the requestor does not include the INTERLOCK signal or until an error indication or a timeout indication;
(2) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Local Bus and reinitiate its bus transaction after the transaction by the device sending the OVERRIDE signal; and
(3) a TYPE control signal indicating that the transmitter of the TYPE control signal will properly respond to the INTERLOCK and OVERRIDE control signals;
each of said Local Buses including a second plurality of connectors serially coupled to said Local Bus lines, and said Local Bus positioned approximately orthogonally to said Common Bus lines;
C. a Peripheral Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with the Local Bus protocol;
D. a Test Bus including a plurality of lines for the serial transfer of information, said Test Bus serially connected to a selected plurality of said Local bus connectors;
E. each of said Local Bus connectors positioned to receive a computer unit including:
(1) a Resource Monitor circuit connected to the Test Bus for controlling and monitoring the computer unit circuitry;
(2) a processor for independently executing instructions on data and connected to the Resource Monitor and a computer unit Internal Bus and further including an address decode circuit for receiving a processor address space from the Resource Monitor and for providing a signal to the processor when an address present on the Internal Bus is within the processor address space;
(3) a computer unit clock means for providing at least one timing signal to the computer unit circuitry;
(4) Peripheral Bus gate means for controlling the transfer of information between the Peripheral Bus and a computer unit Internal Peripheral Bus;
(5) a Local Bus gate means for controlling the transfer of information between the Local Bus and a computer unit Internal Local Bus;
(6) a Peripheral Bus address decoding circuit means for receiving Peripheral Bus signals including a Peripheral Bus address, comparing the received Peripheral Bus address with a computer unit Peripheral Bus address space and when the Peripheral Bus address is within the address space, generating a signal indication that the information present on the Peripheral Bus is to be transferred to the Internal Bus, said Peripheral Bus decoding means including circuitry connected to receive the address space from the Resource Monitor;
(7) a Local Bus address decoding circuit means for receiving Local Bus signals including a Local Bus address, comparing the received Local Bus address with a computer unit Local bus address space and when the Local Bus address is within the address space, generating a signal indicating that the information present on the Local Bus is to be transferred to the Internal Bus, said Local Bus decoding means including circuitry connected to receive the address space from the Resource Monitor;
(8) a Peripheral Bus interface means connected to the Internal Local Bus and the Internal Peripheral Bus for storing address translation information provided from the Resource Monitor and for providing a translated address to the Internal Local Bus in response to an address present on the Internal Peripheral Bus;
(9) an Internal Bus gate means connected to the Internal Local Bus, the Internal Peripheral Bus through the Peripheral Bus address interface means and the Internal Bus, for controlling the transfer of information from either the Internal Local Bus or the Internal Peripheral Bus to the Internal Bus;
(10) an interrupt handler for receiving interrupt signals from either the Peripheral Bus or the Local Bus and generating signals to the processor indicating the reception of the interrupt, and generating response signals for transmission indicating acknowledgement of the receipt of the interrupt;
(11) a Local Bus requestor and arbiter means for receiving signals form said processor or the Peripheral Bus indicating a request for access to the Local Bus and for receiving signals from the Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Local Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit controlling which of a plurality of arbitration schemes within the arbitration means determines which of the received requests is granted Local Bus access;
(12) a Peripheral Bus requestor and arbiter means for receiving signals from said processor of said Local Bus indicating a request for access to the Peripheral Bus and for receiving signals from the Resource monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Peripheral Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit and controlling which of a plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted a Peripheral Bus access;
(13) access control means for providing a plurality of control signals to regulate the transfer of information between the processor, a memory, the Local Bus and the Peripheral Bus and including;
(a) Peripheral Bus control signal circuitry means (i) for (A) receiving a plurality of control signals from either the processor representing a request for generating an information transfer on the peripheral Bus, (B) transmitting the request to the Peripheral Bus requestor, (C) generating signals for an information transfer on the Peripheral Bus in accordance with Peripheral Bus protocol, (D) generating control signals to the Peripheral Bus gate means for transferring the information to the Peripheral Bus upon the receipt of the Peripheral Bus grant from the Peripheral Bus requestor and arbiter means and, (ii) in response to information on the Peripheral bus, (A) generating control signals to the Peripheral Bus gate means and Internal Bus gate means for receiving information from the Peripheral Bus, (B) receiving the indication signal from the Peripheral Bus address decode circuit means and, (C) in accordance with such indication signal, (I) generating a plurality of synchronization signals to either the processor or the memory for the reception of information from said Peripheral Bus, or (II) for (a) generating control signals to initiate a Local Bus transfer and to the Local Bus gate means for the transfer of information from the Peripheral Bus to the Local Bus, (b) transmitting a request for access to the Local Bus to the Local bus requestor, (c) generating a response on the Peripheral Bus to respond to the received Peripheral Bus information and to the Peripheral Bus gate means to enable the transfer of the response information, and (d) generating control signals to the Local Bus buffer for gating the information to the Local bus, in accordance with a grant from the Local Bus requestor,
(b) Local bus control signal circuitry means (i) for (A) receiving a plurality of control signals from the processor representing a request for generating an information transfer on the Local Bus, (B) transmitting the request to the Local bus requestor, (C) generating signals for an information transfer on the Local Bus in accordance with Local bus protocol, (D) generating control signals to the Local Bus gate means for transferring the information to the Local bus upon the receipt of the Local Bus grant from the Local Bus requestor and arbiter means or, (ii) in response to information on the Local Bus, (a) generating control signals to the Local Bus gate means and Internal Bus gate means for receiving information from the Local Bus, (B) receiving the indication from the Local Bus address decode circuit means and, (C) in accordance with such indication, (I) generating a plurality of synchronization signals to either the processor or the memory for the reception of information from said Local Bus, or (II) for (a) generating control signals to initiate a Peripheral Bus transfer and generating control signals to the Peripheral Bus gate means for the transfer of information from the Local Bus to the Peripheral Bus, (b) transmitting a request for access to the Peripheral Bus to the Peripheral Bus requestor, (c) generating a response on the Local bus to respond to the received Local Bus information and to the Local Bus gate means to enable the transfer of the response information, and (d) generating control signals to the Peripheral Bus buffer for gating the information to the Peripheral Bus in accordance with a grant from the Peripheral Bus requestor;
(c) an Internal Bus control means for regulating the information flow on the Internal Bus by controlling access to the Internal Bus by the processor, the memory, the Internal Peripheral Bus and the Internal Local Bus and including an internal arbiter for receiving Internal Bus request signals from the processor, the Local Bus address decoder, the Peripheral Bus address decoder, the interrupt handler, the Local bus requestor and the Peripheral bus requestor, and for generating an Internal Bus access grant in accordance with a predetermined arbitration scheme, and providing enabling signals to Internal Bus gate logic for an information transfer over the Internal Bus;
(14) address processing circuit means for providing an address interface between the processor and the Internal Bus and including an address extension means initialized by the Resource monitor, and connected to the Internal Bus and the processor for providing a plurality of noncontiguous address spaces for the processor, and an address modifier means initialized by the Resource monitor, for providing additional address information for either the Peripheral Bus or Local Bus; and
(15) the memory for storage of information and connected to the Internal Bus and a memory control means, the memory control means connected to receive control signals from the access control means for enabling information to be read from and written to the memory via the Internal Bus, said memory control means further generating an access to the memory upon every operations cycle and completing the access if memory is being accessed via the Internal bus or providing a refresh signal to the memory if the memory is not being accessed by the Internal Bus;
F. a Common Bus control unit connected to the Common bus and a unique one of the plurality of Local Buses and including;
(1) a Common Bus buffer means for gating the transfer of information between the Common Bus and a unit Internal Common Bus in accordance with received control signals;
(2) a Local Bus buffer means for gating information between the Local Bus and the buffered Local Bus in accordance with received control signals;
(3) a Common bus requestor means for receiving a signal indicating a request for access to the Common Bus and for transmitting the request on one of a plurality of request lines, said line selected by a Common bus control unit Resource Monitor, and for receiving an access grant indication signal upon the selected line;
(4) a Common bus to Local Bus address decode means for receiving Common Bus signals including a Common Bus address, comparing the received Common Bus address with a Local Bus address space, determining when the common bus address is within the Local Bus address space, and accordingly, generating a signal indicating that the information present on the Common Bus is to be transferred to the connected Local Bus, said decoding means including circuitry connected to receive the Local Bus address space from the Resource Monitor;
(5) a Local Bus to Common Bus address decode means for receiving Local Bus signals including a Local Bus address, comparing the received Local Bus address with a Common bus address space, determining when the Local Bus address is within the Common bus address space and, accordingly, generating a signal indicating the information present on the connected Local Buses is to be transferred to the Common Bus, said decoding means including circuitry connected to receive the Common bus address space from the Resource monitor;
(6) Common Bus/Local Bus interface means for latching information for transfer from the Internal Common Bus to the buffered Local Bus and for gating information from the buffered Local Bus to Common Bus in accordance with received control signals;
(7) a Local Bus requestor and arbiter for receiving signals indicating a request for access to the connected Local Bus and for receiving signals from the Common Bus control unit Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Local Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit by indicating which one of the plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted Local Bus access;
(8) protocol signals control logic means for, (A) in response to information on the connected Local Bus,
(1) generating control signals to the Local Bus buffer means for receiving information onto the buffered Local Bus,
(2) receiving said indication signal from the Local Bus to Common Bus address decode means and, in accordance with such indication,
(3) transmitting a request for Common bus access to the Common Bus requestor means,
(4) generating control signals to the Common Bus/Local Bus interface means for transferring information from the buffered Local Bus to the Internal Common Bus,
(5) generating a response on the buffered Local Bus and generating control signals to the Local Bus buffer for transfer of the response from the buffered Local Bus to the Local Bus,
(6) generating control signals to the Common Bus buffer for gating the information on the Internal Common bus to the Common Bus in accordance with a grant signal from the Common Bus requestor;
or, (B) in response to information on the Common Bus,
(1) generating control signals to the Common Bus buffer means for receiving information onto the Internal Common Bus;
(2) receiving said indication from the Common Bus to Local Bus address decode means and in accordance with such indication;
(3) transmitting a request for Local Bus access to the Local Bus requestor means;
(4) generating control signals to the Common Bus/Local Bus interface means for latching information from the Internal Common Bus to the buffered Local Bus;
(5) generating a response on the Internal Common Bus and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common bus to the Common bus;
(6) generating control signals to the Local Bus buffer for gating the information on the buffered Local Bus to the Local Bus in accordance with a grant signal from the Local Bus requestor;
(9) the Common Bus control unit Resource Monitor including means for controlling and monitoring the Common Bus control unit circuitry and connected to the Test bus;
(10) Common bus control unit clock means for providing at least one timing signal to the Common Bus control unit circuitry;
(11) common lock interface means connected to the buffered Local Bus for responding to addresses specified by the Resource Monitor, providing status information of individual system addressable devices, and further connected to a Lock Bus for transmitting requests for access to the individual system addressable devices and for receiving grants to such requests;
(12) common lock arbitration means connected to the Lock Bus for receiving said requests and for providing grants to access the individual system addressable devices in accordance with information from the Resource Monitor;
(13) Common Bus request arbitration logic means connected to receive requests for access to the Common Bus and for granting Common Bus requests in accordance with information from the Common Bus control unit Resource Monitor;
(14) InterComputer interrupt control logic connected to the Internal Common Bus and including:
(a) interrupt control address decode means to receive address information from the Common Bus, comparing the received address with an InterComputer interrupt control address space provided by the Resource Monitor for determining when the received address is within the address space, and accordingly generating a signal indicating that information present on the Common Bus is to be received by the InterComputer interrupt control logic;
(b) interrupt word register means for receiving said indication signal and selecting one of a plurality of registers in accordance with said received address, and either, ORing the contents of the selected register with the Common Bus data and storing the ORed results in the register for a write operation, or clearing the contents of the register after a read operation;
(c) interrupt generation means for receiving said indication signal from the InterComputer interrupt decoder means, and, for a write operation, generating a time division multiplex signal including an interrupt signal in accordance with the received address, and transmitting the time division multiplexed interrupt signal on the Common Bus;
(d) InterComputer interrupt response logic means to generate response signals to the received Common Bus address, in accordance with the Common bus protocol;
(15) an InterComputer interrupt interface means connected to the Common Bus and the Local Bus for receiving a time division multiplexed interrupt signal, and including circuitry that receives inputs from the Resource Monitor for demultiplexing the interrupt signal and generating an InterComputer interrupt signal on the Local bus to a designated computer unit in response thereto;
G. at least one Common Bus access unit connected to the Common Bus and each connected to a unique one of the remaining plurality of Local Buses and including;
(1) a Common bus buffer means for gating the transfer of information between the Common Bus and a unit Internal Common Bus in accordance with received control signals;
(2) a Local Bus buffer means for gating information between the Local Bus and the buffered Local Bus in accordance with received control signals;
(3) a Common bus requestor means for receiving a signal indicating a request for access to the Common bus and for transmitting the request on one of a plurality of request lines, said lines selected by a Common Bus access unit Resource Monitor, and for receiving a grant indication upon the selected line;
(4) a Common bus to Local Bus address decode means for receiving Common Bus signals including a Common Bus address, comparing the received Common Bus address with a Local Bus address space, determining when the Common Bus address is within the Local Bus address space and, accordingly, generating a signal indicating that the information present on the Common bus is to be transferred to the connected Local Bus, said decoding means including circuitry connected to receive the Local Bus address space from the Resource Monitor;
(5) a Local Bus to Common Bus address decode means for receiving Local Bus signals including a Local Bus a -dress, comparing the received Local Bus address with a Common Bus address space, determining when the Local Bus address is within the Common bus address space and accordingly generating a signal indicating the information present on the connected Local Buses is to be transferred to the Common Bus, said decoding means including circuitry connected to receive the Common Bus address space from the Resource Monitor;
(6) Common Bus/Local Bus interface means for latching information for transfer from the Common Bus to the Buffered Local bus and for gating information from the buffered Local Bus to Common Bus in accordance with received control signals;
(7) a Local Bus requestor and arbiter for receiving signals indicating a request for access to the connected Local bus and for receiving signals from the Common Bus access unit Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Local Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit by indicating which one of the plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted Local Bus access;
(8) protocol signal control logic means for, (A) in response to information on the connected Local Bus;
(1) generating control signals to the Local Bus buffer means for receiving information onto the buffered Local Bus;
(2) receiving said indication from the Local Bus to Common bus address decode means and in accordance with such indication;
(3) transmitting a request for Common Bus access to the Common Bus requestor means;
(4) generating control signals to the Common Bus/Local Bus interface means for transferring information from the buffered Local Bus to the Internal Common Bus;
(5) generating a response on the buffered Local Bus and generating control signals to the Local Bus buffer for transfer of the response from the buffered Local Bus to the Local Bus;
(6) generating control signals to the Common bus buffer for gating the information on the Internal Common bus to the Common Bus in accordance with a grant signal from the Common bus requestor;
or, (B) in response to information on the Common Bus,
(1) generating control signals to the Common Bus buffer means for receiving information onto the Common Bus;
(2) receiving said indication from the Common Bus to Local Bus address decode means and in accordance with such indication;
(3) transmitting a request for Local Bus access to the Local bus requestor means;
(4) generating to the Common Bus/Local Bus interface means for latching information from the Internal Common bus to the buffered Local Bus;
(5) generating a response on the Internal Common Bus and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common Bus to the Common Bus;
(6) generating control signals to the Local Bus buffer for gating the information on the buffered Local Bus to the Local bus in accordance with a grant signal from the Local Bus requestor;
(9) the Common Bus access unit Resource Monitor including means for controlling and monitoring the Common Bus control unit circuitry and connected to the Test Bus;
(10) Common Bus control unit clock means for providing at least one timing signal to the Common Bus control unit circuitry;
(11) common lock interface means connected to the buffered Local Bus for responding to addresses specified by the Resource Monitor, providing status information of individual system addressable devices, and further connected to a Lock bus for transmitting requests for access to the individual system addressable devices and for receiving grants to such requests;
(12) an InterComputer interrupt interface means connected to the Common bus and the Local Bus for receiving a time division multiplexed interrupt signal, and including circuitry that receives inputs from the Resource Monitor, said circuitry for demultiplexing the interrupt signal and generating an InterComputer interrupt signal on the Local Bus in response thereto;
(13) a Common Bus memory circuit including:
(a) Common Bus memory address decode means for receiving Common bus signals including a Common Bus address, comparing the received Common Bus address with a Common Bus memory address space provided by the Resource Monitor, determining when the received Common Bus address is within the Common Bus memory address space, and accordingly, generating a signal indicating that the information on the Common Bus is to be transferred to the Common Bus memory;
(b) Common Bus memory interface logic means for receiving the indicating signal, generating access signals to the Common Bus memory for providing access to the Common Bus memory in accordance with the Common Bus address, data and control signals;
(c) Common Bus memory response logic means for generating a response on the Internal Common Bus to the Common Bus information and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common Bus to the Common Bus; and
H. a system monitor means including a first processor for transferring information via the Test Bus to the Resource Monitors of the computer units, Common Bus access units and Common Bus control unit and connected to at least one environmental sensor, a first address specification device, a real time clock, a power relay for controlling power to the data processing system, a mass memory for storing program information including the configuration information for each Common Bus control unit, Common Bus access unit, and computer unit, and a first processor memory means for storing a program of instructions for execution by the first processor for: (1) the transfer of the configuration information by the Test Bus to each Resource Monitor, (2) for monitoring the system operation from the Resource Monitors, (3) for receiving information from and providing information to an operator terminal, (4) for regulating power to the data processing system through the power relay in accordance with information received from the environmental sensor, said first processor connected to first and second data buffers, said data buffers further connected to a second processor, said first data buffer providing storage of data from said first processor to said second processor and said second data buffer providing storage of data from said second processor to said first processor, said second processor connected to a second address specification device, a network bus, and a second processor memory which includes instructions for execution by said second processor to provide: (1) transfer of information with said first processor via the first and second data buffers and (2) transfer of information via the network bus.
4. A data processing apparatus comprising:
a plurality of comptuer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;
said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;
said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and
said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;
said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means ina a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signal representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests;
said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means;
wherein the plurality of computer means protocols further include: means responsive to an access request for sending a wait signal when a response will take longer than one bus cycle, means responsive to a wait signal for entering a state wherein the computer means is accessible only by a device sending the received wait signal, means for sending a retry signal to any other device requesting access during the wait state, means responsive to receipt of a retry signal for identifying the retry sending device and means for reintiating an access request to the retry sending device; and
each protocol means of the intercomputer interrupt means including means for issuing an override signal to a local bus device sending an access signal while the common bus is attempting to access the local bus device for resolving bus contentions between the common bus and local bus device in favor or the one having the faster transfer rate.
5. A data processing apparatus comprising:
a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;
said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;
said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and
said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means and further includes a programmable decoder means for detecting when access to the common bus is required, said programmable decoder being programmable: for altering the address positions of the common bus, common bus devices, other local buses and other local bus devices; for allowing read only access to devices accessible via the common bus; and for preventing access to selected devices of the system;
said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests; and
said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means.
6. A data processing apparatus comprising:
a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;
said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;
said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and
said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;
said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests and further includes a plurality of common lock devices connected to the plurality of local buses of the plurality of local buses, said lock devices for providing status information of devices connected to the system and being addressable on each local bus for permitting devices resident on that local bus to request access to devices on the common bus or other local buses without having to access the common bus or other local buses to determine if these devices are available; and
said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means.
7. A data processing apparatus comprising:
a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;
said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;
said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and
said shared memory means including a memory having a plurality of segments corresponding to the addresses o the plurality of connector means;
said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding one of the linked plurality of interface means in arbitration of the access requests; and
said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means and wherein the intercomputer interrupt means is connected to the common bus or local bus and includes a register designated for each of the plurality of computer means, said intercomputer interrupt device for addressing by any device and providing an interrupt signal at the time information is written into the register and is cleared when the interrupted device reads its register.
8. A data processing apparatus comprising;
a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;
said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;
said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and
said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;
said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or decides resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests;
said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means; and
further including a plurality of resource monitors for the plurality of computer means, a system monitor connected to the plurality of resource monitors, and a mass storage device connected to the system monitor, each of said plurality of resource monitors including means for monitoring and controlling the operation of a corresponding computer means, and the system monitor including means for evaluating the system operation and detecting an error on the buses, and means for stopping operation of a failed computer means and replacing a failed computer means by another computer means by loading the information of the failed computer means into the other computer means.
9. A data processing apparatus comprising:
a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;
said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;
said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units including a plurality of peripheral device means, and a peripheral bus interconnecting the pluralities of computer means and peripheral device means for adding peripheral equipment to the system and providing an alternative interconnection between the computer cards selectable by an override signal of the common bus interface means protocol means for resolving contentions between the local bus devices and the peripheral bus devices, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and
said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;
said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or decides resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests; and
said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means.
Description
BACKGROUND OF THE INVENTION
I. Field of the Invention
This invention relates to data processing systems and specifically to multiple computers that communicate with one another via information buses.
II. Description of the Prior Art
Most existing computers in their different forms are sequential Von Neumann machines that perform only one step at a time. This leads to excessive delays in multi-user systems. Since the 1940s emphasis has been placed on increasing computer speeds with faster and denser circuit components. There are many computer experts and researchers trying to redesign the basics of computer structure to overcome heretofore sequential processing limitations. Conventional stored program computers are generally composed in three main parts - a Central Processing Unit (CPU), Common Memory and an Input/Output section. When such conventional computers were first introduced they could only run one program at a time. A Central Processing Unit (CPU) when operating in sequential fashion will execute only one instruction at a time. However, with the advent of semiconductors and later intergrated circuitry, CPUs have become fast enough to efficiently enable time sharing in their execution of instructions. This has lead to the development of multi-tasking operating systems allowing several programs to run in a time shared mode within one computer. Further development of these operating systems progressed from time-sharing memory to simulating large main memories by swapping data with rotating storage components and, thereby, providing a virtual memory operating system.
This has not been accomplished without its problems and that the added burden of simulation accomplished with such operating systems takes its toll in available memory and computing power. Inherently, as operating systems increase in capability, the host computer using such an operating system decreases in capability, a result certainly not desired. For this reason and many others there has been a continuing need for increasing more powerful and faster Central Processing Units. There are, however, practical factors of space, time and technology limiting the execution speed that a single CPU can attain.
In an approach to resolve some of these problems, CPUs have attained increased performance and speed not only as a result of advances in integrated circuit technology but also by adding processors together. In such a CPU with many processors, each processor accomplishes certain tasks but retains appearance of a single CPU architecture with greatly increased performance. Another approach providing more power of speed is the attachment of Auxiliary Processing Units to a Central Processor. This offers additional freedom of implementation and may allow processes to execute concurrently (at the same instant in time). Most attached processing systems, however, tie input/output and scheduling functions directly to the main CPU disallowing direct programmability of the attached processors.
In such a system the CPUs communicate via an Information Bus which is several signal lines connected in parallel to the CPUs. The Information Bus must include a signal protocol which defines what the different signals mean and the timing of the signals. Such an Information Bus is the VME Bus including the VME protocol definition. This Information Bus has been established as a standard and interfacing to the VME Bus has been made easier through products such as the XVME-080 Intelligent Prototyping Module by XYCOM that provides a means to interface a CPU to the VME Bus.
However, the VME Bus does include certain disadvantages. One disadvantage is the difficulty of passing a large amount of information traffic between a multiple of CPUs in a short time frame. While typing multiple VME buses together may seem to solve this difficulty, a contention problem results when a first CPU on a first VME Bus attempts to access a second CPU on a second VME Bus at the time the second CPU is attempting to access the first CPU. The present invention removes this difficulty while providing for high speed information transfer between several CPUs in a short time frame.
It is an object of the present invention to provide an arrangement that facilitates communication between a multiple of computer units.
It is also an object of the present invention to provide an arrangement that includes scalable units permitting system configurations of varying size and capabilities and further permitting ease of system reconfiguration by providing plugably connectable units such as computer cards, memory cards, and other cards that may be connected to or removed from an information transfer bus arrangement that provides fast and efficient communications between the connected units.
It is a further object of the invention to provide a monitor arrangement permitting a system unit to individually or collectively monitor and control the operation of the system.
SUMMARY OF THE INVENTION
In an embodiment of the present invention, the data processing system includes several Local Buses that provide the parallel transfer of information. Each of these Local Buses include several Local Bus connectors. Further, the system includes a Common Bus that is orthogonally positioned relative to the Local. Buses and contains Common Bus connectors that are positioned in line with the Local Bus connectors. In an embodiment, the Common Bus and Local Bus configuration is contained within a single housing. In a variation of this embodiment, several cabinets may be connected together by jumpering either the Local Buses of one cabinet to another cabinet or the Common Bus from one cabinet to another or both. The system further includes plugably connectable cards such as a Bus Interface Card that plugably connects a Local Bus to the Common Bus by connection to both the Common Bus connector and the Local Bus connector. This system further includes computer cards that are plugably connectable to the Local Bus along with memory cards and peripheral device cards which may also be plugably connectable to the Local Bus. The computer cards, memory cards and peripheral device cards connected to the Local Buses may communicate with each other via the Local Bus and to other Local Buses via the Common Bus. The bus interface cards connecting each Local Bus to the Common Bus provide a Common Bus protocol for the transfer of information between Local Buses over the Common Bus. Further these cards provide arbitration to determine which Local Bus gains access to the Common Bus for information transfers. In this embodiment, all devices connected to the buses may access one another by merely addressing one another since all devices are assigned addresses within one address space. Additionally, this system includes a shared memory device accessible to all devices connected to the Local Buses, an InterComputer Interrupt device also accessible by all devices and providing interrupts to the computer cards connected to the Local Buses, and a lock device that is capable of providing status information of all devices connected to the system and further receiving requests to access and providing grants of access to these devices. In one embodiment, the shared memory, common lock and InterComputer Interrupt devices are contained within the bus interface cards. However, the shared memory, InterComputer Interrupt device and lock device may physically be located anywhere within the data processing system since they are addressably accessible as all devices connected to the system.
The number and types of cards that are connected to the Common Bus and Local Buses are determined by the requirements of the application. Since the computer cards, memory cards and peripheral cards are plugably connectable to the Local Buses, the number and types of these cards may be changed by merely adding or removing cards to the Local Buses. Even the number of Local Buses may be increased or decreased by adding or removing the bus interface cards connecting these Local Buses to the Common Bus. Also in an embodiment, the computer cards include an interface to a Peripheral Bus which is connectable to peripheral devices external to the system cabinet. The Peripheral Bus connection can also serve to provide a further bus interconnection between two or more computer cards in the same cabinet. This may be advantageous when there is an excessive amount of traffic between these two cards. A Peripheral Bus connection between these two cards will relieve bus traffic over the Local Buses and Common Bus.
The bus interface cards provide arbitration between the Local Bus and the Common Bus in a unique manner. Firstly, since there is a single address space, access from the Local Bus to the Common Bus is obtained by merely addressing an address space of a device on another Local Bus or a device resident on the Common Bus. The arbitration within the bus interface card is provided by the address decode circuitry which detects when access to the Common Bus is required. The bus interface cards are linked together such that they will arbitrate requests for Common Bus access to provide orderly access to the Common Bus resource. One unique feature of the invention is that the address decode circuitry is programmable, therefore, the address of the Common Bus, Common Bus devices, other Local Buses and other Local Bus devices are programmable and thus alterable by the operator. The bus interface device further defines bus protocol and bus cycles. In the preferred embodiment, the arbitration for the next bus cycle is determined concurrently with the transfer of information of the current cycle. Further, the bus interface cards may be programmed to allow READ ONLY access to devices accessible via the Common Bus. Further, the bus interface cards may be programmed to prevent access to certain devices of the system.
The bus interface cards in defining the protocol, will define information transfers to be within a single Common Bus cycle. In order to provide for information transfers that require more than a single bus cycle, an interlock signal is defined by the protocol. In one embodiment, the shared memory is connected to and addressable from the Common Bus and includes several memory segments, each segment capable of being interlocked by a device. When interlocked, the shared memory segment will only respond to an access by that device. However, Common Bus information transfers are permitted with the remaining memory segments during these interlock periods. Therefore, the Common Bus will not be obstructed during a multiple of non-interruptable transfers of information to the shared memory segments.
Another aspect of the bus protocol is the WAIT and RETRY signals. The WAIT signal is used to respond to a requesting device when the responding device will take more than one bus cycle to complete the transaction. When the requesting device receives a WAIT signal, the requesting device enters a state wherein it only is accessible by the responding device that issued the WAIT signal. During this time, the requesting device responds to other attempted accesses by issuing a RETRY signal. When the responding device provides the information to the requesting device, the requesting device leaves the WAIT state and resumes normal operation. Concurrently with this WAIT state, information transfers over the Common Bus are maintained between the other devices. The device receiving a RETRY signal also enters into a state wherein it monitors the bus for the identifier of the device sending the RETRY signal. Once that identifier has been received then the device receiving the RETRY will reinitiate its bus transmission to the device that sent the RETRY signal. A further protocol signal that is provided is an OVERRIDE signal. The OVERRIDE signal is used to resolve bus contentions between the Common Bus and Local Bus and between the Local Bus and Peripheral Bus. In an embodiment, the Common Bus transfer rate is much faster than the Local Bus transfer rate and when the Common Bus is attempting to access a Local Bus and that Local Bus is attempting to access the Common Bus, the bus interface device will transmit an OVERRIDE signal to the device on the Local Bus attempting to access the Common Bus. Upon receiving the OVERRIDE signal, the device resident on the Local Bus will cease bus transmissions and surrender control of the Local Bus to the bus interface device permitting the transfer of information from the Common Bus. Since the Common Bus transaction will only last for a single Common Bus cycle, the control of the Local Bus is promptly returned to the Local Bus device. Likewise, when an OVERRIDE signal is issued from a Peripheral Bus device to a Local Bus device, the Local Bus device will surrender control of the Local Bus to permit the transfer of information from the Peripheral Bus to the Local Bus.
The implementation of this bus protocol and the arbitration scheme as described provides a contention avoidance system permitting a more efficient use of the information transfer bus resources.
The data processing system further includes a common lock device that provides the status information of devices connected to the system and further receives requests for access and grants access to these devices. In one embodiment, these common lock devices are located on each Local Bus and are addressable on the Local Bus permitting devices resident on that Local Bus to request access to devices on the Common Bus or other Local Buses without having to access the Common Bus or other Local Buses to determine if these devices are available. In one embodiment, the common lock devices resident on each Local Bus include registers dedicated to each computer card connected to the Local Bus. When a computer card requests access to any shared device, that request is arbitrated together with the other requests for that device and a grant of access is according transmitted. In one mode of operation, upon receiving a grant the computer card would be interrupted by the lock device relieving the computer card of the requirement to continually poll to determine when the device is available. Also, the computer card may access the register information of the lock device to determine the status, and poll the availability of other devices. The lock arrangement thus resolves contention problems relative to devices.
An InterComputer Interrupt device is also provided in one embodiment that, in an embodiment, is resident upon the Common Bus, but, may be connectable to any Local Bus and still be addressable by all devices. The InterComputer Interrupt device provides a means for generating an interrupt to any computer card connected to the system by the accessing of an InterComputer Interrupt register that has been designated for that computer card. In this embodiment, a device desiring to interrupt a computer card merely inputs data into that computer card designated register in the InterComputer Interrupt device. In this embodiment, the information that is being written into the register is actually ORed with the contents of this register. The InterComputer Interrupt device generates the interrupt at the time information is written into the register. The interrupt is cleared when the interrupted device reads its register. In one embodiment, the InterComputer Interrupt device provides a hardwired interrupt to the computer card. In another embodiment, the INTERRUPT signal is time division multiplexed and transmitted to the bus interface card for the Local Bus containing the computer card to be interrupted. The interface bus card then demultiplexes the INTERRUPT signal and provides the interrupt directly to the computer card.
In one embodiment of the present invention, the system includes cards that each have a Resource Monitor circuit interconnected to each other and further connected to a System Monitor by a Test Bus. The System Monitor and Resource Monitors on the cards provide a means to initialize the cards defining address spaces, arbitration schemes, identifiers, etc. in accordance with a predetermined configuration. In this embodiment, the System Monitor is connectable to a mass storage device which contains several different configurations. Upon initialization, and operator may specify a specific configuration or the System Monitor may poll the system to determine the existing cards and then determine the configuration in accordance with the available resources. The Resource Monitors on each card include circuitry to monitor and control the individual operations of the cards. The System Monitor connected to these Resource Monitors includes the means to perform an evaluation of the system operation while the system is active. Included in this capability is the ability to detect and correct errors on the buses, to detect failures on the cards, to intervene by stopping operation of the card, correcting the error and then restarting the card and effectively replacing a failed card by another available card in the system by loading the stayed information of the failed card into the new card, reconfiguring the new cards address and starting the card at the point where the failed card failed. In one embodiment, performance evaluation occurs in one of the computer cards located in the system communicating with the Resource Monitors via the System Monitor and Tes Bus.
In a further embodiment of the system, the Common Bus includes a Common Bus timing card that includes propogation lines for each bus interface card that are configured to provide the TIMING signals to each bus interface card at approximately the same time by providing on the timing card propogation lines that have similar characteristics to the propogation lines of the Common Bus but to provide the equivalent physical distances to all bus interface cards.
In a still further embodiment, the plugably connectable cards are provided in a configuration that permits insertion of the cards into the system while the system is operating. In one configuration the power pins of the bus connectors extend to a higher profile than the signal pins, thus permitting the power to be applied to the card being inserted before the signal pins are engaged. In a preferred embodiment, once the power pins are engaged, a power circuit permits regulated power distribution to the circuitry on the card and providing a first indication to one inserting the card that the power pins have engaged and a second indication of when the signal pins may be engaged. In another embodiment, the Common Bus is dual redundant and the Interface Buses are configured to provide for simultaneous transfers of information on the redundant buses.
In one embodiment, of the present invention, the data processing system includes the first information bus with a first protocol and connected to several second information buses by several interface units. In this configuration, a computer device connected to one of the second information buses may communicate via the first information bus to a computer device on a separate second information bus. In this embodiment, the first information bus is a high speed information transfer bus relative to the second information buses. In addition, in this embodiment, the interface units provide control of access to the first information bus by the second information buses, provide a memory accessible on the first information bus, and provide an interrupt device located on the first information bus. The first information bus memory is a fast access memory that may be accessed by any device connected on any of the second information buses. Since the first information bus is a fast transfer bus, the memory is limited to single transactions for access under ordinary conditions. However, a single accessing device may interlock a segment of the first bus memory to perform a READ-MODIFY-WRITE operation. The interrupt circuitry connected to the first information bus also provides for interrupt generation to the computational devices connected to the second buses. This interrupt circuitry includes interrupt registers for each of the devices connected. These registers may be written into by any of the other devices. If one computational device desires to transmit an interrupt to another computational device, the first computational device merely writes into the register of the interrupt circuitry for that second computational device. The writing into the register will generate the interrupt to the second computational device. This interrupt will be cleared when the second computational device reads its interrupt register. The combination of the interrupt circuitry and the first bus memory provide an efficient means to transfer information between devices connected on separate second buses by providing a means for one computational device to "mailbox" information into the memory and then signal the presence of that information by raising the interrupt for the intended device. Upon responding to the interrupt, the intended device can then read the interrupt register and determine who initiated the interrupt and can also read the memory location to obtain the information. The computational units connected to the second buses are provided with means to control peripheral devices external to the data processing system by interfacing to several third information buses. Additionally, in this embodiment, all the bus interfaces together with all the computational devices include individual unit monitoring circuits that are connected to a fourth bus which connects these monitoring units to a system monitor. The system monitor through these individual monitor units and the fourth bus provide means to configure the data processing system, and monitor and evaluate the performance of the system. Because of these features and other unique features of this invention, this data processing system has the flexibility to be configured to efficiently perform any different and varied applications.
In one embodiment, a data processing system is provided that includes a Common Bus which includes several signal lines with a transfer of power, address, data, control and interrupt information in accordance with a Common Bus protocol that defines the timing and formats of the transfer of address, data control and interrupt information and response formats to indicate the completion of these information transfers. Normally, these transfers occur between a requestor device and a responder device amongst a plurality of devices connected to the Common Bus. In accordance with the Common Bus protocol, some of the control information provided includes an INTERLOCK signal from the requestor to the responder defining an interlock period wherein the responder locks out all other information transferred to it except for the information transfers with the requestor until the requestor information transfer does not include the interlock control signal. This permits the requestor to perform a READ-MODIFY-WRITE operation without an intervening information transfer. During this interlock period the responder transmits a RETRY control signal to all devices attempting access. All these devices attempting access and receiving this RETRY control signal store the identifier code of the device sending the RETRY control signal (i.e. the responder). These other devices then lockout all other access attempts to them responding with RETRY signals and monitor all of the information transfers on the Common Bus to determine if the responders identifier code is contained in any of these control signals. Upon the occurrence of the responders identifier code, these units reinitiate their attempted information transfers to the responder device.
The Common Bus protocol also includes a WAIT control signal that is sent from the responder in response to an access from a requestor and defines a requestor WAIT period wherein the requestor locks out all attempted accesses by responding to these attempted accesses with a RETRY control signal and then monitors the control signals representing a source identifier code for the responders identifier code. The requestor then responds only to the accesses containing the responders source identifier code and remains in the WAIT period until the responder has transmitted a COMPLETE control signal indicating a completion of the information transaction.
The Common Bus protocol further includes an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal relinquishes control of the bus until the device issuing the OVERRIDE control signal has completed its bus transaction. At the completion of this intervening bus transaction, the device receiving the OVERRIDE is restored to control over the bus.
Also among the control signals is a TYPE control signal indicating that the device transmitting this TYPE signal will properly respond to the INTERLOCK, RETRY, WAIT, COMPLETE and OVERRIDE control signals. Since these protocol signals are essential for efficient operation of the Common Bus, only devices transmitting this TYPE signal will have access to the Common Bus. Additionally, this Common Bus includes several connectors connected in parallel to the signal lines of the Common Bus and in line with the Local Bus connectors.
In one embodiment, at least two Local Buses are provided that also include several signal lines for the transfer of power, address, data, control and interrupt information in accordance with a Local Bus protocol that defines the timing and formats for these information transfers and a response format to define an information transfer between a requestor and a responder device connected to the Local Buses. This Local Bus protocol also defines an interlock signal between a requestor and a responder that permits the requestor to perform an interlock operation such as the READ-MODIFY-WRITE operation as previously discussed. Also the Local Bus protocol includes the OVERRIDE control signal that permits a device not having control of this Local Bus to obtain control of the Local Bus by ending the OVERRIDE signal to the device having bus control. As before, the device having this control will relinquish this control until after the transaction of the device sending the OVERRIDE signal wherein the originally controlling device will then reestablish control over the Local Bus. Also included is a TYPE control signal. Additionally, each of the Local Buses includes several connectors coupled to the bus permitting parallel access to the signal lines of the Local Bus. In the preferred embodiment the signal lines of the Local Bus are positioned approximately orthogonally to the signal lines of the Common Bus.
In this embodiment, a Peripheral Bus is furthered included that contains several signal lines for the transfer of power, address, data control and interrupt information in accordance with a Peripheral Bus protocol that is similar to the Local Bus protocol.
Further, a Test Bus is provided that includes several lines for the serial transfer of information. The Test Bus is connected to a selected group of Local Bus connectors.
Each of these Local Bus connectors are positioned to receive a computer unit. This computer unit further includes a connection to a Peripheral Bus such that when connected the computer unit is connected to both a Peripheral Bus and the Local Bus. The computer units include a Resource Monitor circuit connected to the Test Bus through the Local Bus connector. The Resource Monitor is provided for controlling and monitoring the computer unit circuitry in a manner to be described. The computer unit further includes a processor for independently executing instructions on data. The processor is connected to the Resource Monitor (RM) and a computer unit Internal Bus and further includes a processor address decode circuit for receiving a processor address space from the Resource Monitor and providing a signal to the processor when an address on the Internal Bus is within this processor address space. A computer unit clock is also included for providing timing signals to the computer unit circuitry. A Peripheral Bus gate circuit is provided for controlling the transfer of information between the Peripheral Bus connected to the computer unit and a computer unit Internal Peripheral Bus. Also a Local Bus gate circuit is provided for controlling the transfer of information between the Local Bus and a computer unit Internal Local Bus. A Peripheral Bus address decoding circuit is provided for receiving Peripheral Bus signals including a Peripheral Bus address, comparing these address signals with a computer unit Peripheral Bus address space provided by the Resource Monitor and providing an indicating signal when the received address is within this address space. Likewise, a Local Bus address decoding circuit is provided that receives the Local Bus addresses and provides an indication when the received address is within a computer unit Local Bus address that has been provided by the Resource Monitor. A Peripheral Bus interface circuit is provided that is connected to the Internal Local Bus and the Internal Peripheral Bus and stores information representing address translation information that is provided by the Resource Monitor. When a Peripheral Bus address is received on the Internal Peripheral Bus, a translated address is then provided to the Internal Local Bus. An Internal Bus gate circuit is connected to the Internal Local Bus and through this Peripheral Bus address interface circuit to the Internal Peripheral Bus to provide the connection to the Internal Bus in order to control the information transfer between the Internal Peripheral Bus, the Internal Local Bus and the Internal Bus.
The computer unit further includes an interrupt handler that receives interrupt signals from either Peripheral Bus or the Local Bus and generates signals to the processor indicating the reception of the interrupt. Further, the interrupt handler generates response signals to indicate acknowledgement of the receipt of the interrupt.
A Local Bus requestor and arbiter circuit is provided for receiving signals from the processor or the Peripheral Bus indicating a request for access to the Local Bus and for receiving signals from the Resource Monitor to designate which one of several arbitration lines to transmit this request. An arbitration circuit receives the request and provides a grant on the same line on which the request is received. The Resource Monitor is also connected and controls the arbitration circuit such that one of several arbitration schemes may be implemented in order to determine which of the received request is granted access. Likewise, a Peripheral Bus requestor and arbiter circuit is provided that functions in a manner similar to that of the Local Bus requestor and arbiter circuit. As before the Resource Monitor controls the operation of the arbitration lines and also determines which of several arbitration schemes is implemented.
The computer unit further includes an access control circuit that provides several control signals to regulate the transfer of information between the processor, a memory within the computer unit, the Local Bus and the Peripheral Bus. Included is a Peripheral Bus control circuit that receives control signals from the processor representing a request for generating information transfer on the Peripheral Bus. This circuitry then transmits the request to the Peripheral Bus requestor and generates signals for the information transfer in accordance with the Peripheral Bus protocol. Upon receiving the Peripheral Bus grant from the requestor the Peripheral Bus control circuit will generate signals to the Peripheral Bus gate for transferring this information to the Peripheral Bus. Further, in response to information on the Peripheral Bus, this control circuitry will generate signals to the Peripheral Bus gate means and the Internal Bus gate means to receive the information from the Peripheral Bus and upon receiving an indication from the Peripheral Bus address decode circuit, generate several synchronization signals to the processor or the memory to receive the information from the Peripheral Bus. Additionally, this Peripheral Bus control circuitry generates control signals to initiate a Local Bus transfer and to the Local Bus gate circuitry for the transfer of information from the Peripheral Bus to the Local Bus when the Peripheral Bus address is contained within the Local Bus address space. The Peripheral Bus control circuitry further transmits a request for access to the Local Bus requestor and generates a response on the Peripheral Bus to respond to the received Peripheral Bus information. Upon receiving the grant to the Local Bus, the Peripheral Bus control circuitry then generates the appropriate control signals for the Local Bus transfer.
Additionally, a Local Bus controls circuit is included for receiving control signals from either the processor or the Local Bus representing a request for generation of an information transfer on the Local Bus. The control circuit then transmits the request to the Local Bus requestor and generates signals for the information transfer on the Local Bus in accordance with the Local Bus protocol. The Local Bus control circuit generates control signals to the Local Bus gate circuit for transferring the information to the Local Bus upon receiving the Local Bus grant from the Local Bus requestor and arbiter circuit. Additionally, in response to information on the Local Bus, the Local Bus control circuit generates control signals to the Local Bus gate circuit and internal gate circuit for receiving the information from the Local Bus. This information includes address information which is decoded by the Local Bus address decode circuit and in accordance with an indication from the address decode circuit, the Local Bus control circuit generates synchronization signals to either the processor or the memory to receive information from the Local Bus. Further, the Local Bus control circuit generates control signals to initiate a Peripheral Bus transfer by generating control signals to the Peripheral Bus gate circuit for transfer of information from the Local Bus to the Peripheral Bus, transmitting a request to the Peripheral Bus requestor, generating a response on the Local Bus to respond to the received Local Bus information and then generating control signals to the Peripheral Bus buffer for gating the information onto the Peripheral Bus in accordance with a grant from the Peripheral Bus requestor.
Also included is an Internal Bus control circuit for regulating the information flow on the Internal Bus by controlling the access to the Internal Bus by the processor, the memory, the Internal Peripheral Bus and the Internal Local Bus. The Internal Bus control circuit further includes an internal arbiter for arbitrating access to the Internal Bus by the processor, the Local Bus address decoder, the Peripheral Bus address decoder, the interrupt handler, the Local Bus requestor and the Peripheral Bus request