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United States Patent
4783739
Calder
November 8, 1988
Title
Input/output command processor
Abstract
An input/output command processor provides a sophisticated communication link between a central processor and peripheral digital apparatus. The command processor receives commands from the central processor, interprets them and transmits them to the peripheral digital apparatus. The command processor is comprised of a store/fetch circuit for directly accessing the memory of the central processor; a fetch and buffer circuit for causing a fetch and for temporarily storing the results of the fetch (commands) in a buffer register file; an interpret controller for interpreting the commands and routing them to the cognizant peripheral apparatus, according to their function.
Inventors:
Calder; Powell L.
(Georgetown,
TX
)
Assignee:
Geophysical Service Inc.
(Dallas,
TX
)
Appl. No.:
459333
Filed:
January 19, 1983
Current U.S. Class:
710/4
Current International Class:
G06F 13/12 (20060101)
Field of Search:
364/2MSFile,9MSFile
U.S. Patent Documents
4001783
January 1977
Monahan
4025905
May 1977
Gorgens
4032899
June 1977
Jenny
4063221
December 1977
Watson
4075691
February 1978
Davis
4104718
August 1978
Poublan
Primary Examiner:
Eng; David Y.
Attorney, Agent or Firm:
Walkowski; Joseph A.
Parent Case Text
This a continuation of application Ser. No. 091,861, filed Nov. 5, 1979 now abandoned.
Claims
I claim:
1. A command processor in an input/output controller for accepting commands from a central processor having a central memory, interpreting the commands and transmitting the interpreted commands to associated digital apparatus, comprising:
(a) store/fetch means connected to the central memory for directly accessing the central memory and for initiating all store and fetch cycles in the central memory;
(b) fetch and buffer means having:
(i) an activation controller operatively connected to receive the commands from the central memory for determining whether the commands may be sent directly to the associated digital apparatus or whether the central memory must be accessed for additional commands to be sent to the associated digital apparatus;
(ii) a list fetch controller, connected to the store/fetch means and to the activation controller for requesting from the central memory, through the store/fetch means, a plurality of commands when so indicated by the activation controller; and
(iii) a list buffer memory having an address register, for storing the plurality of commands received from the activation controller at desired addresses; and
(c) interpreting means, connected to interpret the commands in the list buffer memory to select the associated digital apparatus and to distribute the interpreted commands.
2. The controller of claim 1 wherein the interpreting means comprises a list interpret controller, connected to monitor the list buffer memory and the availability of the associated digital apparatus, and to take the plurality of commands from the list buffer memory, interpret them to select the associated digital apparatus and send the interpreted commands to the cognizant associated digital apparatus.
3. The processor of claim 1 wherein the activation controller comprises:
an activation microprocessor for determining whether a command may be sent directly to the associated digital apparatus or whether the central memory must be accessed by the store/fetch means for fetching the plurality of commands;
an activation read-only memory connected to control the activation microprocessor;
a left interface vector bus connected to the activation microprocessor for transmitting the commands from the central memory thereto;
a right interface vector bus, connected to the activation microprocessor for transmitting commands directly to the associated digital apparatus or the plurality of commands to the list fetch controller from the activation microprocessor.
4. The processor of claim 1 wherein the list fetch controller comprises:
a list fetch microprocessor;
a list fetch read-only memory, connected to control the list fetch microprocessor;
a left interface vector bus, connected to the list fetch microprocessor, for transmitting commands from the activation controller to the list fetch microprocessor;
a right interface vector bus connected to the list fetch microprocessor for transmitting addresses of the list buffer memory from the list fetch microprocessor; and
central memory addressing means, connected to the right interface vector bus and to the central memory, responsive to the list fetch microprocessor for requesting the store/fetch means to fetch a plurality of command addresses from the central memory.
5. The processor of claim 1 wherein the list buffer memory is a random access memory.
6. The processor of claim 1 wherein the interpreting means comprises:
a list interpret microprocessor for receiving and interpreting commands;
a list interpret read-only memory, connected to control the list interpret microprocessor;
a left interface vector bus, connected to the list interpret microprocessor, for transmitting commands from the list buffer memory to the list interpret microprocessor; and
a right interface vector bus, connected to the list interpret microprocessor, for transmitting interpreted commands to the associated digital apparatus from the list interpret microprocessor.
7. The processor of claim 3 wherein the list fetch controller comprises:
a list fetch microprocessor;
a list fetch read-only memory conencted to control the list fetch microprocessor;
a left interface vector bus, connected to the list fetch microprocessor, for transmitting commands from the activation controller to the list fetch microprocessor;
a right interface vector bus connected to the list fetch microprocessor for transmitting addresses to the list buffer memory from the list fetch microprocessor; and
central memory addressing means, connected to the right interface vector bus and to the central memory, responsive to the list fetch microprocessor for requesting the store/fetch means to fetch a plurality of command addresses from the central memory.
8. The processor of claim 7 wherein the list buffer memory is a random access memory.
9. The processor of claim 10 wherein the store/fetch means comprises:
(a)
(i) a store/fetch controller connected to the fetch and buffer means for initiating the storing into and fetching data from the central memory; and
(ii) direct memory access interface means, connected to the store/fetch controller, adapted to provide a central memory store/fetch cycle grant to the fetch and buffer means in response to initiating the storing into and fetching data from the central memory.
10. The processor of claim 9 wherein the interpreting means comprises:
a list interpret microprocessor for receiving and interpreting commands;
a list interpret read-only memory connected to control the list interpret microprocessor;
a left interface vector bus connected to the list interpret microprocessor for transmitting commands from the list buffer memory to the list interpret microprocessor; and
a right interface vector bus connected to the list interpret microprocessor for transmitting interpreted commands to the associated digital apparatus from the list interpret microprocessor.
Description
TABLE OF CONTENTS
Background of the Invention
Brief Summary of the Invention
Brief Description of the Drawings
Detailed Description of the Invention (General)
Store/Fetch Controller & DAMIF
Activation Controller
List Fetch Controller
List Interpret Controller
List Buffer and Address Register
System Read Controller
Data Read Controller
Write Sequence Controller
Formatter Selector Switch
Process Sequence Controller
Mode of Operation
Claims
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital peripheral equipment controllers and more specifically to command processors for relieving the central processor with which the peripheral equipment communicates, of certain housekeeping functions.
2. Description of the Prior Art
Most present date peripheral controllers are designed to control I/O data transfers. No data manipulation is performed on the data stream as it is transferred between the central processor and the peripheral digital device. The preferred embodiment of this invention is a major component of an intelligent controller, the subject of copending U.S. application Ser. No. 514,357, July 15, 1983, now abandoned, a continuation of Ser. No. 095,807 filed Nov. 19, 1979, now abandoned which involves seismic data processing. In prior art seismic data processors, data moving between the central processor and, for example, its tape sub-system, are transferred in a memory image form, in the same format as they were recorded in the field. Unfortunately, field recorded data is not optimized for manipulation by the typical office processing system. In the present state of the art, it is estimated that there are approximately 200 seismic field formats and with the present date peripheral controllers, the central processor is required to transform any of those field formats to a blocked demultiplexed format of a relatively short record and with numerical representations that are either 16 to 32-bit six point integers, or 32 to 40-bit floating point values.
A state of the art solution has been to increase the power of the central processor and the speed and size of its central memory. However, this solution tends to be expensive, requiring an extensive hardware and software effort. Also, in view of the fact that seismic data collection is increasing at an exponential rate, this solution is not long term.
This invention provides a viable alternative, reducing the burden placed on the central processor by shifting some of the processing burdens to a command processor. This relieves the central processor of the need to execute common housekeeping tasks.
BRIEF SUMMARY OF THE INVENTION
The command processor of this preferred embodiment comunicates with a Central Processing Unit (CPU) and, in this preferred embodiment, a maximum of 16 magnetic tape transports. The transport densities may be of the 800-bit per inch (BPI) variety, 1600 BPI or 6250 BPI in non-return to zero, phase encoding and group encoding, respectively. In the preferred embodiment, seismic data in any one of over 200 field formats is recorded on the magnetic tapes.
The intelligent processor is comprised of three sections: this command processor, the device interface controller, and the process sequence controller. The command processor interfaces with the CPU, receiving commands which are decoded and sent to the device interface controller and to the process sequence controller.
The command processor has an activation controller which monitors information from the CPU to determine whether a command has been issued. The activation controller, upon detecting a command, determines whether that command requires fetching a command list block (typically eight words) from the central memory of the CPU or whether it is a single command word that can be directly sent to the appropriate component of the intelligent controller. If a command list block is required, the activation controller causes the list fetch controller, another component of the command processor, to fetch the command list block which is then stored in the list buffer, in either the output or input section as determined by the list fetch controller. A list interpret controller takes a command list block from the list buffer, interprets it and sends it to the device interface section in the process sequence controller.
The device interface has a system read controller which accepts commands from the list interpret controller and controls a data read controller which in turn, through a formatter selector switch, controls a tape formatter. Also included in the device interface is a write sequence controller which responds to controls from the list interpret controller and a tape write controller which in turn, through the formatter selector switch, controls the writing on the tape through a formatter.
The process sequence controller responds to commands from the list interpret controller, and takes incoming data from the data read controller for processing and transmission to the central memory. Its function is to process data as commanded. For example, raw data coming from the data read controller may be changed to an IBM floating point block format and then sent to the central memory.
The device interface section is seen to have an input and output section which are capable of operating independently. That is, while information is being read in from tape, information can be written onto another tape.
The primary object of this invention is to process seismic data on the fly prior to storing in central memory of a CPU.
Another object of this invention is to provide an intelligent controller that can read and write simultaneously.
These and other objects will be made obvious in the detailed description that follows:
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a-1b is a block diagram of the intelligent controller;
FIG. 2 is a schematic diagram of the circuitry for providing various clock signals.
FIG. 3 is a timing diagram illustrating the clock signals.
FIGS. 4a and 4b are, together, a schematic of the store/fetch controller 12.
FIG. 5 is a flowchart illustrating the operation of store/fetch controller 12.
FIGS. 6a and 6b, together, are a block diagram of the DMA interface 11 of FIG. 1a.
FIGS. 7a, 7b and 7c schematically represent the cycle request/grant logic circuitry of the intelligent controller.
FIG. 8 is a synchronizing circuit for synchronizing the signal access granted, with the system clock.
FIG. 9 is a schematic diagram of the interrupt request/recognize circuitry.
FIGS. 10a and 10b illustrate the prioritizing circuit for the interrupt request.
FIGS. 11a-11c, together form a block diagram of ACT13 of FIG 1a.
FIGS. 12a-12b together are a map of ROM 202 of FIG. 11c.
FIG. 13 illustrates reset logic for the entire intelligent controller.
FIG. 14 is a schematic of the HALT logic.
FIG. 15 illustrates the ATI function output.
FIG. 16 illustrates the development of signals from the ACT.
FIGS. 17a and 17b schematically illustrate the development of control signals for the ACT.
FIG. 18 is the ACT status store register.
FIG. 19 is a schematic of the ATI BUSY signal development.
FIG. 20 is the circuit for storing ATI2.
FIG. 21 illustrates the circuitry for providing the PSC and WSC list limits.
FIG. 22 illustrates L pending and ATI flags.
FIGS. 23a-23d schematically illustrate the LFC14.
FIGS. 24a-24d, together, are the address circuity for LFC STORE/FETCH.
FIG. 25 is the PSC look-ahead limit counter and compare circuitry.
FIG. 26 is the WSC look-ahead limit counter and compare circuitry.
FIG. 27 is the circuitry for storing list word 1 back into the memory.
FIG. 28 illustrates circuitry for the development of certain control signals for the LFC.
FIGS. 29a-29b together are a map of the contents of ROM 302.
FIGS. 30a-30c are a schematic of LIC 15 of FIG. 1a.
FIG. 31 illustrates circuitry for the development of control signals for LIC.
FIG. 32 illustrates circuitry for writing status information.
FIG. 33 illustrates circuitry for the development of control signals for LIC.
FIGS. 34a-34c together form a map of ROM 402.
FIGS. 35a-35c illustrate the circuitry for the list buffer address register 16 of FIG. 1a.
FIG. 36 details RAM 465 of FIG. 35c.
FIGS. 37a-37c illustrate the circuitry of the system read controller 27.
FIGS. 38a and 38b illustrate circuitry for the development of control signals for the SRC.
FIGS. 39a and 39b illustrate the SRC memory address counter circuitry.
FIG. 40 illustrates the generation of PSC control signals.
FIG. 41 also illustrates the generation of a PSC control signal.
FIG. 42 illustrates the status FIFO's 22 and 23 of FIG. 1b.
FIGS. 43a and 43b, together, are a schematic of the bytes per scan counter.
FIGS. 44a and 44b form a schematic of the list word two counter.
FIGS. 45a and 45b are schematic of the list word six counter.
FIGS. 46a and 46b form a schematic of the level one files for PSC, SRC and WSC.
FIGS. 47a-47c together form a map of the contents of ROM 502.
FIGS. 48a-48c form a schematic of the data read controller 30 of FIG. 1b.
FIG. 49 is a schematic diagram of the tape read data parity counter.
FIGS. 50a-50c form a schematic diagram of the data read controller FIFO.
FIG. 51 is a schematic of the start of scan counter and limit.
FIGS. 52a and 52b form a schematic of the DRC data comparator.
FIGS. 53a-53d together form a map of the contents of ROM 602.
FIGS. 54a-54c schematically illustrate the write sequence controller 26 of FIG. 1b.
FIGS. 55a-55c are schematics of circuitry for development of control signals for the WSC.
FIG. 56 is the central memory addressing circuitry of WSC.
FIG. 57 is the byte counter of WSC.
FIGS. 58a and 58b are the 32 byte tape write FIFO.
FIG. 59 is a flow diagram of the tape write FIFO controller.
FIG. 60 is a schematic of the tape write FIFO controller.
FIGS. 61a-61c together form a map of the contents of ROM 702.
FIG. 62 schematically illustrates the prioritizing circuitry of formatter selector switch 31 of FIG. 1b.
FIGS. 63a-63c are schematics of a development of formatter commands from signals provided by WSC and SRC.
FIGS. 64a and 64b form a schematic of the generation of formatter status.
FIG. 65 schematically illustrates formatter to WSC select.
FIG. 66 schematically illustrates formatter status to WSC select.
FIG. 67 is a functional block diagram of the process sequence controller 28 of FIG. 1b.
FIG. 68 is a functional timing diagram of the PSC.
FIG. 69 is a schematic of the FIFO of the PSC
FIG. 70 is a schematic diagram of the FIFO controller of the PSC.
FIGS. 71a-71e are schematics illustrating the generation of various control signals for the PSC.
FIG. 72 is a flowchart illustrating the operation of the PSC.
FIGS. 73a-73d, together, are a detailed block diagram of the PSC.
FIG. 74 is a signal selection table.
FIG. 75 is a schematic of the development of PSC input signals.
FIGS. 76a-76b together form a map of the contents of the PSC ROM.
FIG. 77 illustrates words ATI1 and ATI2.
FIG. 78 illustrates the set list look-ahead limit register command.
FIGS. 79a-79f illustrate types A-F command lists.
FIG. 80 illustrates indicator status words for read and write.
FIG. 81 illustrates the loading of memory for unpacked SEG A.
FIG. 82 illustrates memory of a packed SEG A.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1a and 1b depict, in block form, the entire intelligent processor system 10. The system 10 communicates with the central memory of a computer such as the TI980B, in this preferred embodiment, by way of a direct memory access interface (DMAIF) 11 and Store/Fetch Controller 12. It will be evident that there are six users of the central memory requiring inputs "Cycle Requests" (CYREQ) and "Interrupt Requests" (INTREQ). The Process Sequence Controller (PSC) 28 has one input "Data Memory Access Go" (DMAGO) to and receives one output "Data Memory Access Requested" (DMAREQ) from Store Fetch Controller 12, the memory accessing for PSC 28 being different from the other memory users. The Store/Fetch Controller 12 provides outputs "Cycle Granted" (CYGRAN), "Interrupt Recognized" (INTRECOG) and "Data Available" (DATAV) to the memory users. Store/Fetch Controller 12 provides a Store/Fetch signal and an IREQ signal to DMAIF 11, receiving from the DMAIF 11 the DATAV signal, the IRECOG signal and an "Acknowledgment Granted" (AG) signal. Memory Read Data Bus (MRB) 35, Memory Write Data Bus (MWD) 37, and Memory Address Bus (MAD) 39 are connected to DMAlF 11.
Activation Controller (ACT) 13 is connected to receive ATI strobes (to be described later) from DMAlF11 and is also connected to receive words from the memory via MRD and to write words into memory via MWD at the proper address by selection through MAD. ACT 13 is connected bilaterally to List Fetch Controller (LFC) 14 which is connected to read and write into the central memory. ACT 13, depending upon instructions it receives, will cause LFC 14 to fetch a list of commands from the central memory or will directly communicate with the device interface section (described later) of the intelligent controller 10.
List Buffer Address Register 16 is addressed by LFC 14 and by List Interpret Controller (LIC 15). LFC 14 loads list Buffer 17 at the addresses specified in List Buffer Address Register 16 with command lists for use by the device interface section or by PSC 28 (described later). LFC 14 determines whether a particular command list is for use by the Device Interface Section or by PSC 28 and places such lists in List Buffer 17 in a section designated for use by the Device Interface or in a section designated for use by PSC 28.
LIC 15 continuously monitors the device interface section and PSC 28 to determine whether those sections are demanding action. LIC 15 also continuously monitors the contents of list buffer 17 to determine whether there are any command lists therein for either PSC 28 or the device interface section. LIC 15 is a user of central memory for purposes of reporting status as is described below.
ACT 13, LFC 14, LIC 15, List Buffer Address Register 16 and List Buffer 17 make up the command processor section of the intelligent controller 10. DMAlF 11 and Store/Fetch Controller 12 are, in this preferred embodiment, incorporated on the command processor circuit board.
The Write Sequence Controller (WSC) 26, the Tape Write Controller (TWC) 29, the System Read Controller (SRC) 27, the Data Read Controller (DRC) 30 and the Formatter Selector Switch 31 are the major, components of the data interface section and are all mounted on a common circuit board. System Read Controller Level 1 (SRC LVL 1) register 19 is connected to LIC 15 and to SRC 27 and functions as a very fast access storage register for command lists transferred from List Buffer 17 by LIC 15. Register 19, in this preferred embodiment, is a random access memory manufactured by Texas Instruments Incorporated, Type SN74S208 controlled as a first-in, first-out (FIFO) register. This random access memory could, of course, be accessed in any random fashion desired-other than as a FIFO.
In a similar manner, WSC LVL 1 register 18 is conncted between LIC 15 and WSC 26 and is identical to and performs the same function as register 19. Status FIFO's 22 and 23 are connected between LIC 15 and WSC 26 and SRC 27, respectively. Status is sent to LIC 15 so that there is no unnecessary interruption of the data flow either to or from the device interface section. Flip flop 21 is connected between LIC 15 and WSC 26 and indicates that register 18 is full or not full. Likewise, flip-flop
24, connected between LIC 15 and SRC 27 indicates whether register 19 is full or empty. If register 18 is full, then WSC 26 is able to have its contents transferred. In the same manner, if flip-flop 24 indicates that register 19 is full, then the SRC can accept the information from register 19. WSC 26 and SRC 27, as memory users, have connections to the MRD, MWD and MAD buses.
The Tape Write Controller (TWC) 29 is bilaterally connected to WSC 26 and is further connected to Formatter Selector Switch 31. The Data Read Controller (DRC) 30 is bilaterally connected to SRC 27 and is bilaterally connected to the Formatter Selector Switch 31. DRC 30 also is connected to PSC 28 to transmit data passing through Formatter Selector Switch 31 and through DRC 30. Formatter Selector Switch 31 has formatter A 32 and Formatter B 33 connected to it. These formatters are not part of the intelligent controller and in this preferred embodiment, as accessories, are supplied by the Telex Corporation and are series 6800. Each is capable of handling eight tape transports. The tape transports are not shown, but could be connected to each of the eight lines shown from Formatter A 32 and Formatter B 33.
WSC 26 communicates through Formatter Selector Switch 31 with Formatter A32 and Formatter B33 as determined by the command word from WSC LVL 1 register 18. When a particular write instruction is received, WSC 26 fetches data from the central memory, transfers it to TWC 29 which in turn transfers the data through Formatter Selector Switch 31 to the selected Formatter 32 or 33 for writing on tape. WSC 26, while such writing of data is occurring, continuously monitors the formatters for any status signals which are transmitted to status FIFO 22 which in turn transmits the status to LIC 15 which sends such status to the central memory. If necessary, the CPU can then take action.
SRC 27 operates in much the same fashion as WSC 26. That is, a command is taken in from register 19, SRC 27 through Formatter Selector Switch 31 selects a tape on Formatter 32 or Formatter 33 from which to read as determined by the instruction sent from register 19. Data is read from the tapes into DRC 30 (which can recognize scan codes) and then to PSC 28. While such reading operation is going on, SRC 27 monitors Formatter 32 and Formatter 33 for status, sending any such status to status FIFO 23, which then sends the status to LIC 15 which in turn transmits it to the central memory. If action is warranted, the CPU will take action.
PSC 28 is the third section of intelligent controller 10. Similar to SRC 27 and WSC 26, PSC 28 has a level 1 register known as "Process Sequence Controller Level 1" (PSCLVL 1) register 20 connected between itself and LIC 15 Register 20 receives commands from LIC 15 for action by PSC 28. Flip flop 25 operates in the same fashion as flip flops 21 and 24. Flip flop 25 is connected to LIC 15 and indicates whether register 20 is empty or full. If it is full, then the commands therein may be transferred to PSC 28. PSC 28 has connection to the central memory through buses MRD, MWD and MAD. Also, PSC 28 has a connection from the Store/Fetch Controller on the line DMAREQ and has a connection to controller 12 through line DMA GO.
Refer now to FIGS. 2 and 3. Circuitry for development of clock pulses and the developed pulses, respectively, are depicted. It should be noted that "inverse" or "not" functions are designated by a dash (-) following the identifier. Also, "Q" following the identifier generally indicates a flip flop output.
The input clock from the TI 980B computer is applied on terminal TO92, carried on line 55 and inverted through inverter 53, being applied as the clock input to flip flop 54. Voltage VCC is applied, through resistor R1, to line 55 which is connected through resistor R2 to ground. The voltage waveform A applied to the clock input of flip flop 54 is shown as waveform A (CLK4MHZ), with time t1-t4 being 167 nanoseconds and time t4-t6 being 83 nanoseconds in the preferred embodiment, providing a total period of 250 nanoseconds and therefore a frequency of 4 MHz. As connected, flip flop 54 triggers each time that waveform A goes positive. Therefore, the Q output of flip flop 54 is one half the frequency of waveform A and is shown in FIG. 3 as waveform B (CLK2MHZ). Waveform B is applied as one input to exclusive OR circuit 45 and also as an input to delay line 42. Delay line 42 provides an output waveform C (TAP60) which is waveform B delayed 62.5 nanoseconds. Waveform C serves as the otherinput to exclusive OR circuit 45 whose output is waveform F (CLKXORA). Note that waveform F results from the condition that waveform B equals "1" while waveform C equals "0" or that waveform B equals "0" while waveform C equals "1".
The last tap on delay line 42 is connected as an input to delay line 41 which has an output waveform D (TAP120) which is waveform B delayed approximately 125 nanoseconds, applied as an input to exclusive OR circuit 43. Delay line 41 has a second, later output waveform E (TAP180) which is waveform B delayed approximately 187.5 nanoseconds, applied as the other input to exclusive OR circuit 43 whose output is waveform G (CLKXORB). Note that waveform G is identical to waveform F, simply delayed. Also note that waveform G results from the condition that waveform D equals "1", while waveform E equals "0" or that waveform D equals "0" while waveform E equals "1". Waveforms F and G are applied as inputs to exclusive OR circuit 46 whose output is waveform H (CLK8MHZ). Waveform H is a result of the condition that waveform F equals "1" while waveform G equals "0" or that waveform F equals "0" while waveform G equals "1" . Waveform H is inverted through inverter 48 whose output is CLKTPCX2 and applied to terminal B45. Waveform H is also inverted through inverter 49 whose output is identified as CLK8X300 applied to output S11. Waveform F is amplified through amplifier 51 providing output signal CLKTPC applied to terminal B47. Waveform F is also inverted through inverter 52 providing signal CLKTPC- applied to terminal B48. These clocks are used as clock inputs for the various circuits to be described.
Store/Fetch Controller and DMAIF
FIGS. 4a and 4b schematically illustrate the store/fetch controller 12 which functions as a memory expander for the central memory. That is, it permits direct access to the central memory by components of this intelligent controller 10 as well as by the CPU.
In FIG. 4a, signal SFO, developed in this circuit, signal DMAREQ from DMA terminal B34, and signal DMAGO from the PSC 28 are inputs to AND circuit 59 whose output is the D input to flip flop 61. The Q output of flip flop 61 is connected to the D input of flip flop 64 which provides inputs to each of open collector NAND gates 71 and 72. The Q outputs of each of flip flops 61 and 64 provide inputs to NOR circuit 62 whose output is the SFO signal mentioned above. The SFO signal is passed through registor R3 where it becomes the ARDEV- signal (access request for the device). Signals SFO and SF2/Q are inputs to OR circuit 66 whose output, SFO-IN, is an input to AND circuit 67. GATEDCLK clock signal on terminal B50 (described later) is an input to AND circuit 67 and also to AND circuit 68. The Q- output of flip flop 61, signal SF1/Q-, is one input of NOR circuit 70 whose other input is the signal AG/Q- (access granted). The output of NOR circuit 70 provides the other input, signal SF1-AG, for AND circuit 68. AND circuits 67 and 68 are the inputs to NOR circuit 69 whose output is signal CLKSFC-, providing the clock input to flip flop 61 and one input to OR circuit 63. The other input to OR circuit 63 is the AG- (access granted-) signal. The output of OR circuit 63, signal SF2CLK- is the clock signal to flip flop 64. The Q- output of flip flop 64 is signal SF2/Q-. Open collector NAND gate 71 has its other input supplied by the signal STORE MUX and open collector NAND gate 72 has its other input provided by the FETCH MUX signal. The output of gate 71 is signal DEVSTORE- and is applied to terminal S63. The output of circuit 72 is signal DEVFETCH- and is applied to terminal S90. Gate 72 also provides its output on line 73 to the CKA and CKB inputs of first-in, first-out memory (FIFO) 74. FIFO 74 is a Texas Instruments Type SN74S 225, fully described in the Texas Instruments Publication "Bipolar Microcomputer Components Data Book" LCC 4270A, dated December 1977. The CK IN input to FIFO
74 is provided by signal RDSTB/Q- on terminal B53, the CLR-input is provided by signal CLRTPC- and the OR output is signal DATAVEN. Inputs supplied to the FIFO are signals FETCHACT/Q, FETCHSTC/Q, FETCHWSC/Q and FETCHLFC/Q. These inputs are output to NAND gates 75, 76, 77 and 78, respectively, whose other input, in each case is provided by signal RDSTB/Q on terminal B53. The output of NAND gate 75 is signal DATAVACT- provided on terminal B56, the output of NAND gate 76 is signal DATAVSRC- provided on terminal S53, the output from NAND gate 77 is signal DATAVWSC- provided on terminal S13 and the output of NAND gate 78 is signal DATAVLFC- provided on terminal B54.
FIG. 5 is a flowchart illustrating the operation of store/fetch controller 12 in conjunction with DMAIF 11. At state SFO, block 85 asks the question "Is there a direct memory access request?" If the answer is no, nothing happens. If the answer is yes, then the next question at block 86 is whether there is a signal from PSC28 that it has released memory by signal DMAGO. If the answer is no, nothing happens. If the answer is yes, then controller 12 moves into the SF1/Q state and at block 87, it is determined whether there has been access granted. If the answer is no, the controller waits, and if the answer is yes, it moves into state SF2/Q. At block 88, it is determined whether the FETCH MUX signal is present. If the answer is yes, a fetch cycle is started and if the answer is no, a store cycle is started. In either event, at block 89, it is determined whether there has been an access grant- signal. If the answer is no, the controller waits and if the answer is yes, it goes back to SFO as indicated at block 90.
The outputs of AND circuits 75-78 indicate data active or not active for the various controllers that have the facility for reading. These outputs tell those controllers that the reading is completed.
Referring now to FIG. 6A, input signals DEVMRD (device memory read data) 13, 14 and 15 are applied on terminals T71, T76 and T81, respectively. These three signals represent the three highest order bits in the ATI1 (automatic transfer instruction-) word from the CPU and select the intelligent controller. Signal DEVMED 13 is applied directly as an input to AND gate 94, while signals DEVMRD 14 and 15 are inverted through inverters 92 and 93, respectively, and then applied as inputs to AND gate 94. The output of AND gate 94 is applied to the D input of flip flop 95, whose Q output is applied as the D input to flip flop 96 whose Q- output is connected to the clear input of flip flop 95. Along with the three bits from word ATI 1 is sent a strobe signal on terminal T13 identified as DEVATI 1- providing a clock input to flip flop 95. The clock input to flip flop 96 is the signal CLKTPC- developed as shown in FIG. 3. The combination then of flip flops 95 and 96 is simply to synchronize the incoming information with the intelligent controller clock.
The Q output of flip flop 95 is applied as one input to NOR circuit 97 whose other input is supplied by the Q output of flip flop 96 and whose output is inverted through inverter 98 providing the signal THIS DEV (this device selected).
A synchronizer combination is also formed by the combination of flip flops 99 and 101 with the Q output of flip flop 99 being connected to the D input of flip flop 101 and the Q- output of flip flop 101 being connected to the clear input of flip flop 99. The clock input to flip flop 99 is a strobed pulse from the instruction word AT12 that follows ATIl. The strobe pulse DEVAT12- is applied to terminal TO90 and then to the clock input of flip flop 99. The Q- output of flip flop 99 is applied as an input to NAND circuit 106 which has another input applied from the Q- output of flip flop 95.
Still another synchronizer is provided by the combination of fiip flops 104 and 105. A signal DATAVEN on terminal B57 from FIFO 74 of FIG. 4B is inverted through inverter 102 and applied as the D input to flip flop 104. A strobe pulse DATAV- indicating that data is stable is applied from the CPU on terminal TO95, inverted through inverter 103 and applied as a clock input to flip flop 104. The Q- output of flip flop 104 is applied as the D input to flip flop 105 whose Q output provides the signal RDSTB/Q. The Q- output of flip flop 105 is applied as the preset input of flip flop 104. The Q output of flip flop 104 is applied as a third input to NAND circuit 106 whose output, on line 107, is identified as signal MRDCLK-.
Signal MRDCLK- on line 107 as seen in FIG. 6B is the clock input to memory read data register 109. Bus 110 from connector TOXX from the central memory supplies a 16 bit word to register 109 and provides a parity check bit to flip flop 111. The bus 110 is biased through resistor R4 by voltage VCC. Register 109 provides a 16 bit bus labeled MRD/Q and a bus containing the inverse bits labeled MRD/Q-. Signal MRDCLK- is applied as a clock input to flip flop 111 which has a Q output signal MRD16/Q applied to the odd input of parity generator 112 and a Q- output signal MRD16/Q- applied to the even input terminal of parity generator 112. The summation of even inputs of parity generator 112 is applied to the even input of parity generator 113 and the summation of odd inputs of parity generator 112 is applied as an input to the odd input of parity generator 113. Parity generators 112 and 113 are Texas Instruments types SN74180 9-bit odd/even parity generators described beginning at Page 7-269 of the TTL Data Book #LCC4112, Copyright 1976. The 16 bits carried by bus MRD/Q are connected to the inputs of parity generators 112 and 113. The summation of even inputs of parity generator 113 is signal MRD PERR (memory read data parity error) and is applied to the D inputs of flip flops 114 and 115. The summation of odd inputs of parity generator 113 is the signal MRDPERR-. Flip flop 114 is clocked by signal ATI1/Q- and flip flop 115 is clocked by signal AT12/Q- with the Q outputs providing signals AT11PARERR/Q and AT12PARERR/Q, respectively.
The CPU- supplied instruction words AT11 and AT12 have been mentioned above. Also mentioned were the words from the central memory read into memory read data register 109. These words will be dealt with in detail in the description of the operation of the intelligent controller that follows.
Please refer to FIG. 7C where inverter array 145 is shown having input signals CYREQACT, CYREQSRC, CYREQWSC, CYREQLFC and CYREQLIC applied to input terminals B35, SO7, S42, B36 and B37, respectively. These input signals all come from read-only memories (ROMs) from the various controllers in the intelligent controller. Each of the signals is inverted by an individual inverter of the assembly 145 and is applied inverted on terminals B8-B12. The signal on B13 is high because of its input being grounded.
Referring now to FIG. 7A, the inverted signals from the ROMs are shown applied to flip flop array 121 in reverse order, that is, signal CYREQ0- is applied to terminal D of flip flop 8 of array 121 while signal CYREQ5- is applied to the D terminal of flip flop 3 of array 121. Flip flop array 121 is clocked by the output from NAND circuit 122 which has one input signal SF1/Q- applied to terminal B24 and a second input signal, CPU clock, foom the central processor applied to terminal TO8 and inverted through inverter 123. The output of inverter 123 carries signal GATLDCLK which is available at terminal B26.
FIG. 7B indicates outputs 2Q-8Q of flip flop array 121 being applied to inputs 1-7 of 8-line-to-3-line priority encoder 130 which is a Texas Instruments Type SN74LS148 described beginning at Page 7-151 of the TTL Data Book. The EO output of encoder 130 provides signal DMAREQ which is applied to terminal B34 and inverted through inverter 133 being pplied to terminal S26 as signal DMAREQ-. Outputs A0, A1 and A2 provide signals CYGRANT20, CYGRANT21 and CYGRANT22 applied to input selects A, B and C of decoder 134 which is a Texas Instruments Type SN74LS138 described beginning at Page 134 of the TTL Data Book. The decoder is enabled by signal SFl/Q applied to terminal B28 and then to the enable input of decoder 134. Outputs Y0-Y4 of decoder
134 are applied to the inputs 1D-5D of flip flop array 144 of FIG. 7C. Flip flop outputs 1Q-5Q of flip flop array 144 provide output signals GRANTACT-, GRANTSRC-, GRANTWSC-, GRANTLFC- and GRANTLIC- provided on terminals B1-B5, respectively. The flip flop array 144 is clocked by signal SF1-AG applied to terminal B25 from FIG. 4A and then to the clock input.
Flip flop array 146 of FIG. 7c has inputs applied on terminals 1D-7D by signals FETCHACT applied to terminal B330, FETCHSRC applied to terminal S52, CYREQWSC applied to terminal S42, FETCHLFC applied to terminal B31, STOREACT applied to terminal B32, STORELFC applied to terminal B33 and CYREQlIC applied to terminal B37, respectively. Outputs 1Q-7Q of flip flop array 146 are applied to terminals B14-B20, respectively.
On FIG. 7B, terminals B14-B17 are shown connected to inputs 0-3 of data multiplexer 136, Texas Instruments Type SN74LS151 described beginning at Page 7157-157 of the TTL Data Book. The other inputs of multiplexer 136 are grounded and data select signals A, B and C are provided by outputs A2, A1 and A0 of encoder 130, respectively. A strobe input is supplied by the ACCESS GRANTED signal from the CPU, AG-. The output signal, FETCH MUX is supplied to terminal B6.
Multiplexer 138 is identical to multiplexer 136, having identical select inputs and strobe input. Data inputs are supplied by the signals on terminals B18, B19 and B20 which are applied to inputs 0, 3, and 4, with all other inputs grounded. The output signals STORE MUX is applied to terminal B7.
The operation of the apparatus described in FIGS. 7a-7c is straightforward. That is, a signal from the appropriate ROM provides, for example, the input CYREQACT on terminal B35 which is inverted through inverter 145, applied to terminal B8 and then to input 8D of flip flop 121. This signal is eventually applied to input 7 of decoder 130, providing an output signal on A0 which is applied to the C data select of multiplexers 136 and 138.
If it had been desired to read from memory, then a FETCHACT signal would also be applied to terminal B30 connected to flip flop array 146, providing an output on terminal B14. Terminal B14 is connected to the 0 input of multilexer 136 and with data select C active, the FETCH MUX signal on terminal B6 will then be high. Also, one of inputs Y0-Y4 of decoder 134 is activated, resulting in the signal from the 1Q output of flip flop array 144, GRANTACT- being high. Any other requests would be done in like manner. It should be pointed out that in the case of WSC26 and LIC15, only a FETCH cycle and a STORE cycle, respectively, is possible in this preferred embodiment and therefore each requires a simple cycle request.
FIG. 8 is a synchronizing circuit for synchronizing the signal AG- which is provided on terminal TO39 with the intelligent controller clock. Incombing signal AG- is delayed through delay circuit 124 and is applied as one input of NAND circuit
124. Supply voltage VCC is applied through resistor R5 to the output of delay circuit 124. The output of NAND circuit 125 sets flip flop 126 which is clocked by the signal GATEDCLK described above. the Q output of flip flop 126 is signal AG/Q which is the D input to flip flop 127 and also the output supplied on terminal 129. further, the Q output of flip flop 126 is one input to NAND circuit 128 whose other input, signal AGD/Q- is supplied from the Q- output of flip flop 127. The clock input to flip flop 127 is also supplied by the signal GATEDCLK. The output of NAND circuit 128 serves as the other input to NAND circuit 125.
FIG. 9 is a schematic diagram of the interrupt request/recognize circuitry for enabling the central memory to act. GRANTACT-, from terminal B1 of FIG. 7C, is applied to one input of NOR circuit 151. Signal GRANTSRC- from terminal B2, is applied to one input of OR circuit 153 and GRANTWSC- signal from terminal B3 is applied as one input to OR circuit 155. Grant LFC- signal from terminal B4 is applied as one input of NOR circuit 157. Signal GRANTLIC-, from terminal B5, is one input to OR circuit 159. Signal AG/Q- from terminal B38 of FIG. 8 is applied as the other input to NOR circuits 151 and 157, and OR circuits 153, 155 and 159.
The output of NOR circuit 151 is connected as one input of NAND circuits 152 and 154, with the other input to NAND circuit 152 being the FETCHACT/Q output from terminal B14 of FIG. 7C, and the other input to NAND circuit 154 being the STOREACT/Q signal from terminal B18. The outputs of NAND circuits 152 and 154 are signals FETCHACTEN- applied to terminal B40 and STOREACTEN-, applied to terminal B41, respectively. The output of OR circuit 153 is signal FETCHSRGEN-, applied to terminal S64. The output from OR circuit 155 is signal FETCHWSCEN- applied to terminal S65. The output from NOR circuit 157 is applied to the input of each of NAND circuits 156 and 158. the other input to NAND circuit 156 is the FETCHLFC/Q signal from terminal B17 and the other input to NAND circuit 158 is the STORELFC/Q signal from terminal B19. The output of NAND circuit 156 is the FETCHLFCEN- signal applied to terminal B42 and the output of NAND circuit 158 is the STORELFCEN- signal applied to terminal B43. The output of OR circuit 159 is signal STORELICEN-, applied to terminal B44.
In operation then, this circuit simply provides memory enable signals in response to certain combination of input request signals and grant signals. FIGS. 10a and 10b illustrate, in block form, the circuit for prioritizing the interrupt request from the separate controllers. While provision is made for a total of seven interrupts to be serviced, only two controllers in this preferred embodiment require interrupts. They are the list interrupt controller 15 having signal INTREQLIC from its ROM impressed on terminal B58, and the activation controller 13 having signal INTREQACT from its ROM impressed on terminal B59, each of which is inverted through inverter array 163. The other inputs to inverter array 163 are grounded. The inverted outputs are connected to the inputs of flip flop array 164 whose outputs are connected to the inputs of priority encoder 165. Output EO of encoder 165 is connected to line 168 and inverted through inverter 174, passed through resistor R8 to terminal S32 as the signal INTDEV-. Line 168 is also connected to line 160 which provides the EO output as an input to AND circuit 161 whose other input is the clear controller signal CLRTPC from terminal B67. The output of AND circuit 161 provides one input to OR circuit
162 whose other input is the signal CLKTPC- impressed on terminal B48. The output of OR circuit 162 provides the clock input signal for encoder 164.
The inputs to decoder 165 is provided from encoder 164. Decoder 165 is identical to decoder 134 of FIG. 7b. Decoder 178, capable of providing eight outputs from the three inputs provided on lines 170-172 from encoder 165, provides two outputs, one on its terminal Y0 which provides one input to OR circuit 177 and another on its terminal Y4, which provides one input to OR circuit 176. Signal IRECOGTPC-, which is an interrupt recognize from the CPU, is impressed on terminal S33 and inverted through inverter 184 whose output is applied to the J input of flip flop 166. The clock input to flip flop 166 is provided from terminal B48 and is the signal CLKTPC-. The Q output from flip flop 166 is impressed on line 182 which provides an input on terminal S/L of 4-bit parallel-access shift register, TI Type SN74LS195A, which is described in the TTL Data Book beginning on Page 7-324. The Q.sub.D - output is connected to the K input of flip flop 166. The clear input to flip flop 166 is provided by the signal CLRTPC-. The Q.sub.D output of shift register 180 is impressed on line 183 which provides the output control input to flip flop array 164. Outputs Q.sub.A and Q.sub.B are the inputs to NOR circuit 179 whose output serves as the other input to each of 0R circuits 176 and 177 which provide, respectively, output signals IRECLIC- on terminal B60 and IRECACT- on terminal B61.
This circuit, described in FIGS. 10a and 10b then simply selects one of two possible interrupts and provides an output signal for causing the desired interrupt.
Activation Controller
FIGS. 11a-c depict, in block form, ACT 13 of FIG. 1a.
The heart of the activation controller 13 is microprocessor 200 which, in this preferred embodiment, is a Signetics Type 8X300. It is a sequence controller as well as a process controller. Operatively connected to microprocessor 200 is read-only memory array 202, having instruction register (IR) section 203, interface vector left (IVL) section 204, interface vector right (IVR) section 205 and control (CTL) section 206. In this preferred embodiment, memory array 202 has 512 words, each word being 32 bits in length. The addressing is done on the 12 bit ACTAR bus connecting microprocessor 200 with ROM 202. Sixteen bits of the 32 bit word addressed in ROM 202 is the instruction register portion and is utilized by microcprocessor 200
which receives the 16 bit words over bus ACTIR connecting ROM 202 with microprocessor 200. In this preferred embodiment, the memory 202 is made up of TI Type 74S472 Programmable Read-only Memory with a three output. Four bits of each word is sent from section 204 to flip flop array 210 which provides the signals ACTIVL (03) Q. Four bits from section 205 are sent to flip flop array 209 which provides the signals at its output ACTIVR (03) Q. Eight bits from the section 206 are used for control functions and are described in FIG. 13. The contents of the ROM 202 is shown in accompanying FIG. 12.
The control section 206 provides output signals CLRBUSYEN, ATI2SAVE, CYREQACT, STOREACT, FETCHACT and INTREQACT.
Signal MCCLK from microprocessor 200 is inverted through inverter 207 and applied as the clock inputs to each of flip flop arrays 209 and 210. Signal CLKACT is applied to terminal B66, amplified through amplifier 222 and applied to terminal X1
of microprocessor 200, such terminal also being connected through resistor R10 to voltage VCC. Signal CLKACT is also inverted through inverter 221 and applied to terminal X2 of microprocessor 200, such terminal being connected through resistor Rll to voltage VCC. Output terminal SC of microprocessor 200 is inverted through inverter 208 and applied to terminal B62 as signal ACTSC-. Voltage regulator 201 is connected to the microprocessor 200 to supply voltages in accordance with the manufacturer's specifications. Signal CLRTPC- is applied to terminal B67 and also to the reset terminal of microprocessor 200.
In FIG. 11A, signals MRD01/Q, MRD02/Qand MRD03/Q are inputs to AND circuit 190 whose output is signal ILLTYPAFUN which indicates an illegal instruction. Buffer line drivers and arrays 191, 192 and 193, in this preferred embodiment, are Texas Instruments Type SN74LS240, having inverted three-state outputs. Array 191 is selectively activated by signal ACTLIVSELO-, which is one of the outputs from flip flop array 210. Array 191 has eight inputs for inversion, those inputs being the output from ANDcircuit 190, signal ATIBUSY/Q, signal LAL=F, signal MRDPERR, ATI1PARERR/Q, ATI2PARERR/Q, PATIPROG/Q and WATIPROG/Q.
Array 192 is selectively activated by signal ACTLIVSEL 1 which also is one of the outputs from flip flop array 210. The inputs to array 192 are signals MRD00/Q, MRD01/Q, MRD02/Q, MRD08/Q, MRD09/Q, MRD10/Q, MRD11/Q and MRD12/Q. These signals are all data from memory signals, while the signals applied to array 191 are test condition signals.
Array 193 is activated by signal ACTLIVSEL3-, also an-output from flip flop array 210. The input signals to array 193 are CYGRANTACT-, DATAVACT-, IRECACT-, PSCYBSY-, ATI2LATCH-, THISDEV- and REWPEND/Q. The inverted outputs from arrays 191-193
are all connected to ACTLIV bus 194. Bus 194 is connected to bus 195 which in turn is connected to microprocessor 200. Bus 194 is inverted through inverter array 196 which is identical to arrays 191-193. The output bus from inverter 196 is ACTRIV bus
199. Connected to bus 199 is bus 198 which is an input to flip flop array 197 whose output signals are REWINTEN, REWUNLOAD, REWFMTSELB, REWXPT22, REWXPT21, and REWXPT20, impressed on output terminals S55-S60, respectively. Flip flop array 197 is clocked by signal ACTLIVCLK4- impressed on terminal D80. The clear input is from signal CLRTPC-, impressed on terminal B67.
Bus 219 is connected to bus 199 and also to ACT status address register 218, which is clocked by signal ACTREVCLK6-, impressed on terminal B82. Register 218 is cleared by the signal STOREACTEN- impressed on terminal B41.
Signal STOREACTN-, impressed on terminal B41, is also connected to one input of AND circuit 220 whose other input is the signal STORELICEN- from terminal B44. The output of AND circuit 220 is used as the gating input for inverter array 217 which is identical to arrays 191 and 193, but shown as a single inverter. Eight inputs from voltage VCC are inverted by selective inverter 217 having eight output signals DEVADD0 through DEVADD7. The eight outputs from register 218 are signals DEVADD8
through DEVADD15.
FIG. 13 illustrates reset logic which is developed in the activation controller 13 section. Memory data signals MRD08/Q- through MRD11/Q- are applied as inputs to NOR circuit 230 whose output provides one input to NAND circuit 231. The other input to NAND circuit 231 is the signal THISDEV impressed on terminal B85. The output of NAND circuit 231 provides one input to NAND circuit 232 whose other input is signal CPURESET- from terminal S005 from the CPU. The output of NAND circuit 232 is inverted through inverter 233 and provides signal CLRTPC- which is impressed on terminals S012 and B67. The output from NAND circuit 232 is also connected as one input to OR circuit 237. The other input to OR circuit 237 is provided by OR circuit 236, whose two inputs are signals HALTPSC/Q and PSCTERM/Q, both from the list interpret controller 15. The output of OR circuit 237 is impressed on terminal S040 and is inverted through inverter 238, providing output signal CLRSPC-, impressed on terminal B86.
FIG. 14 is a schematic of the HALT logic which is developed in the activation controller 13. From the ACT controller right interface vector bus (ACTRIVBUS), lines 6 and 7 are provided as inputs to AND circuits 240 and 241, respectively, each of whose other input is signal ACTRIVCLK1 from terminal B77. The output of AND circuit 240 provides the J input to flip flop 242 and the output of AND circuit 241 provides the J input to flip flop 246. Flip flops 242 and 246 have their clock inputs provided by signal ACTMCCLKfrom terminal B87. The K- input of flip flop 242 comes from the output of NAND circuit 243 whose inputs are provided by signals LICHLTCLRPS, from the read-only memory of LIC15, signal LFCHLTCLRPS from the ROM of LFC14 and signal SRCHLTCLRPS on terminal S08 from system read controller.
The K input of flip flop 246 is provided by the output of NAND circuit 244 whose inputs are signals LICHLTCLRWS from the ROM of LIC15, signal LFCHLTCLRWS from the ROM of LFC14 and signals WSCHLTCLRWS on terminal S09 from WSC26. The clear input of flip flop 242 is signal CLRPSC- from terminal B86. The clear input to flip flop 246 is provided by signal CLRTPC- from terminal B67.
FIG. 15 illustrates the ATI function output from the ACT right interface vector bus (ACTRIVBUS) lines 4-7 which provide inputs to WSC function flip flop array 249 and to PSC function flip flop array 250. Array 249 is clocked by signal ACTRIVCLK2- from terminal B78 and array 250 is clocked by signal ACTRIVCLK3- from terminal B79. The output control for array 249 is provided by signal SELPSCFUN/Q from terminal B88, which signal is inverted through inverter 251 and provides the output control to array 250. The four outputs from each of arrays 249 and 250 are connected together and then connected to output terminal B90 which is connected to list buffer 17, carrying signals ATIFUN23, 22, 21 and 20. The signals are provided to the list fetch controller 14 and connector B89.
FIG. 16 illustrates circuitry for the development of more signals in the activation controller 13. Lines 0, 1, and 2 from ACTRIV bus 199 provide one input to each of AND circuits 211, 212 and 213, respectively, with line 0 also providing one input to AND circuit 214. The other input to each of AND circuits 211-213 is signal ACTRIVCLK5- from terminal B81. The output of each of AND circuits 211-214 provide the J inputs to flip flop array 216. The other input to AND circuit 214 is signal ACTRIVCLK4- from terminal B80, inverted through inverter 215. The clock input to array 216 is provided by signal ACTMCCLK- from terminal B87 and the reset input is provided by signal CLRTPC- from terminal B67. The Q output of section 1 of array provides signal ATIFUNF to terminals T83 and B63. The Q output of section 2 is signal PATIPPROG/Q provided on terminal B64. The Q output of section 3 is signal WATIPROG/Q. The Q output from section 4 is signal REWPEND/Q provided on terminal S61.
FIG. 17a shows the ACT controller left interface vector address logic. This logic is provided by a 3 to 8 line decoder 253 which is a Texas Instruments Type 74S138 described at page 7-134 of the TTL Data Book. Signal ACTLP- provides the G2A enable, and signal ACTLIVO/Q provides the G2B enable input, with voltage VCC being applied to enable input Gl. Signals ACTLIVl/Q through ACTLIV3/Q are applied as the select inputs, providing one of eight possible output signals, namely, ACTLIVSEL0- through ACTLIVSEL7- on output terminals B69-B76, respectively.
FIG. 17b depicts the address logic for the ACT CONTROLLER RIGHT INTERFACE VECTOR. Decoder 255 is identical to decoder 253 and has select inputs provided by signals ACTRIV1/Q through ACTRIVc/Q. AND circuit 254 has inputs provided by signals ACTRB- and ACTSC- with its output providing the G2A enable input to decoder 255. Signal ACTRIVO/Q provides the G2B enable signal. The G1 enable signal is provided by voltage VCC. The combination provides one of eight possible output signals on output lines which provide inputs to NOR gate 256, OR gates 257, 258 and 259, NOR gate 260, and OR gates 261 and 262, respectively. OR gate 263 has one input from inverter 264 whose input is provided by signal ACTRIV0/Q. The other input to each of these gates is provided by the signal ACTMCCLK-from terminal B87. The output from each of these gates is signals ACTRIVCLK1, ACTRIVCLK2-, ACTRIVCLK3-, ACTRIVCLK4-, ACTRIVCLK5, ACTRIVCLK6-, ACTRIVCLK7-, and ACTRIVCLK8-, applied to terminals B77-B84, respectively.
FIG. 18 shows ACT status store circuitry with input signals ASTRIV(0-7) from the ACT controller right interface vector bus 199 applied to each of flip flop arrays 265 and 266. Array 265 is clocked by signal ACTRIVCLK7- from terminal B83 and array 266 is clocked by signal ACTRIVCLK8- from terminal B84. Both of these devices have their output control provided by signal STOREACTEN- from terminal B41. The output signals from array 265 are DEVMWD(07) and from array 266 RDEVMWDWD(815).
FIG. 19 shows the development of the ATI BUSY signal. THISDEV signal from terminal B85 provides the J and Kinputs to flip flop 267 whose Q output is signal ATIBUSY/Q. Flip flop 268 has applied to its J input signal ATI2/Q and has the ROM signal CLRBUSYEN from section 206 of ROM 202 inverted through inverter 269 and applied to its K- input. The output of flip flop 268 provides the reset input to flip flop 267 and the Q-output provides signal ATI2LATCH-.
FIG. 20 illustrates the appropriate circuitry for saving and storing the ATI word 2.
Signals PSCSTA2EN/Q and WSCSTA2EN/Q from the list interpret controller 15 are applied as inputs to AND gates 272 and 273, respectively. Signal STORELICEN- from terminal B44 is inverted through inverter 274 and applied as the other input to each of NAND gates 272 and 273. Signal ACTRIVCLK1 from terminal B77 provides one input to each of NAND gates 277 and 278. Signal ACTRIVBUS4 provides the other inputs to NAND gate 277 and ACTRIVBS5 provides the other input to NAND gate 278. The output of NAND gate 277 provides the clock input to PSCATIWRD2 to flip flop array 275. The output from NAND gate 278 provides the clock input to WSCATIWRD2 flip flop array 276. Memory data signals MRD(015)/Q provide inputs to flip flop array 279 whose clock input is provided by signal ACTI2SAVE from control CTL section 206 of ROM 202. The output signals provide inputs to flip flop arrays 275 and 276. The output signals from array 279 also provide inputs to buffer array 280 whose gate inputs are provided by the signal FETCHACTEN- from terminal B40 and whose outputs provide the DEVADD(0015) bus 282. The outputs of arrays 275 and 276 are connected together and form DEVMWD(0015) bus 281.
In this preferred embodiment, the look ahead list (LAL) of instructions that may be placed in list buffer 17 is limited to 256 16-bit words. This is organized into 16 blocks of 8 words each for the write sequence controller 26 and 16 blocks of 8
words each for the process sequence controller 28. FIG. 21 illustrates the circuitry that is employed in the ACT controller to bring out from the central memory the number of lisrs desired. That number is determined by bits 12-15 from the central memory shown as MRD(12-15)/Q providing four inputs to each of flip flop arrays 286 and 287. Lines 3 and 2 of bus 199 provide one input to each of NAND gates 284 and 285, respectively, whose other input is provided by the signal ACTRIVCLK1 from terminal B77. The output from AND circuit 284 provides a clock input to flip flop array 287 and the output from NAND gate 285 provides a clock input to flip flop array 286. Signal HALTPSC/Q from terminal B90 provides one input to NOR gate 288 and signal HALTWSC/Q from terminal B91 provides one input to NOR gate 289. The other input to each of these NOR gates 288 and 289 is provided by the signal MASTERCLR from terminal B92. The output of NOR gate 288 provides the clear input to flip flop array 286 and the output from NOR gate 289 provides the clear input for flip flop array 287. The outputs from flip flop arrays 286 and 287 are signals PSCLIMIT(0-3)Q and WSCLIMIT ()-3)Q, respectively, providing inputs to AND gates 290 and 291, respectively. AND gates 290 and 291 provide the inputs to NOR gate 292, whose output is inverted through inverter 293 and provides the signal LAL=F. Signal LAL=F provides a control input to inverter array 191.
FIG. 22 illustrates the generation of certain flag signals. Lines 0 and 1 from bus 199 provide one input to each of AND circuits 294 and 297 whose other inputs are provided by the signal ACTRIVCLK1 from terminal B77. THe output from AND gate
294 provides the J input to flip flops 295 and 296. The clear inputs are provided by signal CLRPSC from terminal B86. The K- input to flip flop 95 is provided by signal PSCLPNDCLR- from the process sequence controller 28. The K- input of flip flop 296
is provided by signal PSCATICLR- from PSC28.
The output of AND gate 297 provides the J input to each of flip flops 298 and 299. The clear input to flip flops 298 and 299 is provided by the signal CLRTPC- from terminal B67. The K- input of flip flop 298 is the signal WSCLPNDCLR and the K- input of flip flop 299 is provided by signal WSCATICLR-, both of these signals coming from write sequence controller 26.
The Q output of flip flop 295 is signal PSCLPEND/Q; the Q output from flip flop 296 is signal PSCATIFLG/Q the Q output of flip flop 298 is signal WSCLPEND/Q; the Q output from flip flop 299 is WSCATIFLG/Q. These output signals are flags which are set by ACT13 and reset or cleared by list fetch controller 14 ROM bits.
LIST FETCH CONTROLLER
As indicated in FIG. 23a, LFC14 is designed around microprocessor 300 which, in this preferred embodiment, is a Signetics Type 8X300, identical to microprocessor 200 of ACT controller 13. ROM 302 is connected to microprocessor 300 in the same fashion as ROM 202 is connected to microprocessor 200 of ACT13. The ROM is divided into three sections, the LFCIR section 303 for instructions, the IVR, IVL section 304 and the control section 305. This latter section provides eight inputs to flip flop array 306 whose clear input is provided by the signal CLRTPC- and whose clocksignal is provided by signal LFCMCCLK- from terminal B99. Its output signals are PSCCHNLDEN, WSCCHNLDEN, LFCHLTCLRPS, LCHLTCLRWS, CYCREQLFC, STORELFC and FETCHLFC. Four outputs transmitting signals LFCIVR(0-3) and four outputs transmitting signals LFCIVL(0-3) are connected from section 304 to the inputs of flip flop arrays 308 and 309 respectively. Flip flop arrays 308 and 309 are clocked by a signal from terminal MCCLK of microprocessor 300 which is inverted through inverter 310 and designated signal LFCMCCLK-. Output signals LFCIVR(0-3)/Q and LFCIVL(0-3)/Q are provided from flip flop arrays 308 and 309, respectively. Address bus LFCAR is provided by the microprocessor 300 to the ROM 302 which responds with the instructions for microprocessor 300 in the form of a 16 bit word transmitted over bus LFCIR. Eight bits are transmitted as IVR, IVL signals and the remaining eight bits are control signals, the word being 32 bits long as indicated for the ACT controller 13. Voltage regulator 301 is attached to the microprocessor 300 as in the case of voltage regulator 201 with respect to microprocessor 200 of ACT13. The clock signal CLK8X300 from terminal B66
is inverted through inverter 330 and applied to terminal X2, the output of inverter 330 being biased through resistor R15 to voltage VCC. Signal CLK8X300 is also buffered through buffer 331 whose output is biased through resistor R14 to voltage VCC and which is applied as an input to terminal X1 of microprocessor 300.
Microprocessor 300 provides an output from its SC terminal, inverted through inverter 311 which provides the signal LFCSC-. The RB- terminal of microprocessor 300 provides signal LFCRB- and the LB terminal provides output signal LFCLB-. The signal CLRTPC- from terminal B67 is applied to the RST- terminal and voltage VCC is applied to the HALT- terminal of microprocessor 300. LFCLIVBUS(0-7)bus 312 is connected to microprocessor 300.
As in the case of ACT13, this bus 312 is for inputs which are applied through inverter arrays 316, 317, 318 and 319. Input signals are identified as DPEND#GTLMT and WPEND#GTLMT, from list fetch controller 14; PSCLPENDQQ, WSCLPEND/Q, PSCATIFLG/Q, WSCATIFLG/Q, ATIFUN23, ATIFUN22, and ATIFUN21 from ACT13; HALTPFC/Q-, HALTWSC/Q-, MRDPERR-, CYGRANTLFC-DATAVLFC- and LFCLBFGNT/Q- from LFC14. Bus 312 is also inverted through inverter array 320 whose output is LFCRIVBUS(0-7) of 321. Bus 321 provides inputs to flip flop array 326 which is clocked by signal LFCRIVCLK4- from terminal B96 to provide output signals ATI20E-, PSCCAROE-, WCSCCAROE- and LWIMWDOE-. Bus 321 is connected to the inputs of flip flop array 327 which is clocked by signal LFCRIVCLK3- from terminal B96 to provide output signals LFCPSCSEL/Q, SELPSCFUN/Q, PCLRTERM-, WCLRTERM-, PSCATICLR-, WSCATICLR-, PSCLPNDCLR-, and WSCLPNDCLR-. Bus 321 provides an input to list buffer 17, to be described later.
As shown in FIG. 23d, bus 321 provides one input, line 2, to AND gate 325 and another input , line 3, to AND gate 326' each of whose other input is provided by clock signal LFCRIVCLK2-from terminal B95. The output of AND gate 325 provides the D input to flip flop 327 which has a clear input provided by signal SRCCLRABORT- from terminal S49 and which provides a Q- output signal SRCABORT/Q to terminal S48. The output of AND gate 326 provides the D input to flip flop 328 which is cleared by signal WSCCLRABORT-from terminal S51 and which provides an output on its Q- terminal that is signal WSCABORT/Q- to terminal S50.
The circuitry for LFCSTORE/FETCH address is shown in FIGS. 24a-24d. Signal DATAVLFC- from terminal B54 is inverted through inverter 333 and applied as one input to each of NAND gates 330 and 331 whose other inputs are provided by signals PSCCHNLDEN and WSCCHNLDEN, respectively, outputs from flip flop array 306. The output of NAND gate 330 serves as the clock input to flip flop array 335 while the output of NAND gate 331 serves as the clock input of NAND gate 336. Central memory, bits
00-07 are applied as inputs to each of flip flop arrays 335 and 336. Flip flop arrays 335 and 336 form a part of a chain address register which is the address at which a new routine or program is started without referring back to the CPU. Bits 00-07 of word ATI2SAVE from flip flop 220, reflecting one output from the control section 206 of ROM 202 of ACT13, is applied through buffer array 334. Buffer array 334 is gated by signal ATI20E- from flip flop array 326 as shown on FIG. 23b.
Referring to FIG. 24b, signal WSCCARLDfrom NAND gate 331 clocks flip flop array 349 and signal PSCCARLD- from AND gate 330 clocks flip flop array 348. The other half of ATI2SAVE, namely bits 08-15 is applied to buffer- array 347 which also is gated by signal ATI202-. The inputs to flip flop arrays 348 and 349 are bits 08-15 from memory. Signal WSCCAROE- from flip flop array 326 is used to enable the output of flip flop arrays 336 and 349. Signal PSCCAROE- from flip flop array 326 is used to enable the output from flip flop arrays 335 and 348.
The output of buffer array 334 is tied together with the outputs from flip flop arrays 335 and 336 in bus 338 which provides inputs to counters 340 and 341 shown in FIG. 24C. The output from buffer array 347 is tied to the outputs from flip flop arrays 348 and 349 in bus 351 which is shown providing inputs, in FIG. 24d, to counters 352 and 353. Counters 340, 341, 352 and 353 are all clocked by signal LFCMCCLK- from terminal B99. In this preferred embodiment, these counters are Texas Instruments Type SN74LS163A Synchronous FourBit Counters, described beginning at page 7-190 of the TTL DAta Book. The load inputs for these counters is provided by the output from NAND gate 343. The inputs to NAND gate 343 are provided by line 6 of bus
321 and clock signal LFCRIVCLK2- from terminal B95. Potential VCC is applied to the one enable terminal so that when the other enable terminal has a potential provided by the output of AND gate 354, the counters are enabled. AND gate 354 has input signals from line 7 of bus 321 and clock signal LFCRIVCLK2- from terminal B95. This enable signal causes the counter combination of counters 340, 341, 352 and 353 to add one count.
The outputs of counters 340 and 341, as shown in FIG. 24c, are combined and buffered through buffer array 345 which is gated by the output of AND gate 344. The inputs to AND gate 344 are signals FETCHLFCEN- and STORELFCEN- from terminals B42 and B43, respectively. The outputs from counters 352 and 353 of FIG. 24d are combined and buffered through buffer array 355 which is enabled by the output of AND gate 344. The outputs of buffer arrays 345 and 355 are applied to MAD bus 39.
It can be seen then that the circuitry of FIGS. 24a-24d is designed to provide addresses dependent upon information from the central memory of the CPU. Specifically, an address for saving the ATI2 word is provided, as well as other addresses from the CPU central memory for fetching and storing.
The list buffer 17 of FIG. 1a, in this preferred embodiment, has the capability of storing a total of 256 16-bit words. This capacity is divided up by providing 16 blocks of eight words each for the WSC section and 16 blocks of eight words each for the PSC section. That is, output operations for WSC26 and input operations for PSC28 may be stored prior to their use in list buffer 17. To provide this feature of having such information available, it is necessary that the limit of the list buffer
17 not be exceeded. The circuitry for determining the limits is illustrated in FIGS. 25 and 26.
In FIG. 25, signals PSCLIMIT(0-3)/Q from terminal B100 of FIG. 21 provide four inputs to comparator 360. Four other input signals for comparison are provided from counter 362. Counter 362, in this preferred embodiment, is a Texas Instruments Type 74LS193 described beginning at page 7-306 of the TTL Data Book. Signal PPEND#Ml- from terminal S28, originated in the system read controller 27 is applied to the count down terminal. The output of NAND gate 368 is connected to the count up terminal of counter 362. The inputs to NAND gate 368 are line 0 from bus 321 and LFCRIVCLK2 from terminal B102. AND gate 370 provides the signal applied to the load terminal of counter 362. The inputs to AND gate 370 are signals SRCTERM/Q, inverted through inverter 372, signal CLRTPC- from terminal B67 and signal HALTPSC/Q- from flip flop 242 of FIG. 14. Counter 362 counts under control of these various signals and applies the result to comparator 360 which compares the information from counter
362 with the process sequence controller limit number. If the limit number is smaller than the number from the counter, an output signal PPEND#GTLMT is present, as indicated.
Counter 366 is identical to counter 362 except that its down count input is provided by signal PSCLIST#Ml-which is provided ultimately from the ROM of list interpret controller 15. The four outputs from counter 366 are inverted through inverter array 364 and applied to bus 374, identified as LICLIVBUS(0-7)-.
The circuit of FIG. 26 is identical to that of FIG. 25 except for the input signals. That is, comparator 361 (identical to comparator 360) receives input signals WSCLIMIT()-3)/Q from terminal B101. The output signal from comparator 361 is identified as WPEND#GTLMT. The count down input to counter 363 (identical to counter 362) is provided by signal WPEND#Ml- from terminal T85. The count up input is provided by NAND gate 389 whose inputs are signals LFCRIVBUSl from bus 321 and clock signal LFCRIVCLK2 from terminal B102. The load input is provided by the output of AND circuit 371 which has a clear input CLRTPC-from terminal B67, signal WSCTERM/Q inverted through inverter 373, and signal HALTWSC/Q- from flip flop 246 of FIG. 14. Counter 367 is identical to counter 366, having a count down input provided by the signal WSCLIST#M1- from the ROM of list interpret controller 15 with its count up and load inputs the same as those of counter 363. The output of counter 367 is buffered through buffer array 365 which is gated by line 6 of the left interface vector bus of LIC15, as is buffer array 364. The output from buffer array 365 is connected to bus 374 over line 375.
FIG. 27 simply illustrates the circuitry required to store list word 1 back in the memory. The signal LBUFDI(0115)/Q is provided from the list buffer 17 and is buffered through buffer array 377 whose output is enabled by the output from AND gate
378. The inputs to AND gate 378 are signals STORELFCEN- from terminal B43 and LWIMWDOE- from flip flop array 326. The output of buffer array 377 is applied to device memory write data bus 379.
FIG. 28 illustrates the development of certain clock pulse signals from bus 321. LFCRIVl-, 2-, 3-, 4-, and 5- are applied as one input to each of AND gates 381, 382, 383 and 384 and NOR gate 385, respectively. The above menioned gates are enabled by signal LFCMCCLK- from terminal B99. The output from AND gate 382 is applied to one input of NAND gate 380 whose other input is voltage VCC, providing an output signal LFCRIVCLK2 on terminal B102. AND gates 381-384 provide output signals LFCRIVCLK1-, 2-, 3- and 4- on terminals B94-B97, respectively. NOR gate 385 provides signal LFCRIVCLK5 on terminal B98.
FIG. 29 is a map of the contents of ROM 302.
LIST INTERPRET CONTROLLER
The List Interpret Controller 15 primarily provides the process sequence controller 28 with an interpreted command list block from the list buffer 17. LIC 15 also receives status information from status registers 22 and 23 and transmits that status to the central memory of the CPU. As shown in FIG. 30a-30c, LIC 15 has a microproessor 400 which is identical to the microprocessors 200 and 300 previously described. It has a voltage regulator 401 and a read-only memory 402 having section 403
which contains 16-bit words for the operation of the microprocessor 400, section IVR/IVL/404 and control section 405, all as described earlier with respect to microprocessors 200 and 300. The output of the control portion 405 inputs flip flop array 406
which provides signals PSCLIST#Ml-, WSCLIST#MI-, LICHLTCLRPS, LICHLTCLRWS, CRYEQLIC and INTREQLIC. Flip flop array 406 is clocked by the signal LICMCCLK- from terminal B102 and is cleared by the signal CLRTPC- from terminal B67. Addressing information comes over 12-bit bus LICAR and the instruction words for microprocessor 400 come back over 16-bit bus LICIR. Clock 8X300 from terminal B66 is applied through buffer 390 to terminal X1 of microprocessor 400 and is inverted through inverter 391 and applied to terminal X2 of microprocessor 400. Voltage VCC is applied through resistor R16 to terminal X1 and through resistor R17 to terminal X2. The output of terminal MCCLK is inverted through inverter 394 providing signal LICMCCLK- at terminal B102
and also as a clock input to flip flop arrays 392 and 393. Four bits from the IVR portion of section 404 provide inputs to flip flop 392 and four bits from the IVL portion of section 404 provide inputs to flip flop array 393. The outputs of flip flop array 392 are signals LICRIV(0-3)/Q and the outputs from flip flop array 393 are LICLIV(0-3)/Q. The output from the SC- terminal of microprocessor 400 is inverted through inverter 395 and provides one input to AND circuit 396 whose other input is provided by the signal LICRB-, from the RB- output of microprocessor 400. The output from AND gate 396 is signal LICRIVEN-. LICLIV bus 397 is connected to microprocessor 400 for receiving command inputs exterior to the processor.
Those inputs include, as shown in FIG. 30b, signal PSCLVL1FUL which is inverted through inverter 409 and applied to one input of inverter array 408. Signal WSCLVL1FUL is inverted through inverter 410 and applied to another input of inverter array 408. Signal SRCLVLlFUL is inverted through inverter 411 and also applied to array 408. These inputs indicate that registers 20, 18 and 19, respectvely, are full and therefore no further information can be entered.
Signal HALTPSC/Q- and signal HALTWSC/Q- are also inputs to inverter array 408. Signals are for halting the operation of the proces sequence controller 28 and the write sequence controller 26 and come from flip flops 242 and 246, respectively, as shown in FIG. 14.
Signals SRCSTATRDY from terminal S44 and signal WSCSTATRDY from terminal S45 are inputs to inverter array 412. These signals indicate that registers 23 and 22 respectively, as shown in FIG. 1b are ready. Signals LICLBFGNT/Q- which orders a fetching of data from the list buffer 17 is another input to array 412; signal IRECLIC-, an interrupt request, and signal CYGRANTLIC-, a cycle grant for the LIC15 are also inputs to array 412. Buses 548 and 549 are direct inputs to bus 397. The inverted outputs of inverter arrays 408 and 412 also are inputs to bus 397. The outputs of inverter arrays 408 and 412 are enabled by signals LICLIVSEL1- and LICLIVSEL7-, respectively, both signals coming from the decoder 444.
Inverter array 414 also provides inputs to bus 397, those inputs being enabled by signal LICLIVSEL6-from decoder 444. The inputs to array 414 are signals PSCLIST#0 through PSCLIST#3, and WSCLIST#0 through WSCLIST#3. These groups of signals are from counters 366 and 367 as shown in FIGS. 25 and 26, respectively.
Bus 397 having eight lines, connects to an inverter array 398, providing an eight line bus output LICRIV bus 415. Bus 415 is connected as an input to system read controller 27, described later.
Lines 0 of bus 415, as shown in FIG. 30c, provides one input to AND gate 415. Line 1 provides an input to AND gate 416 and to AND gate 418. Line 2 provides an input to AND gate 417 and to AND gate 419. Line 4 provides an input to AND gate 420, line 5 provides an input to AND gate 421 and line 6 provides an input to NAND gate 422. The other input to AND gates 415, 416, 420 and 421, and also to NAND gate 422 is provided by signal LICRIVCLK1 from NOR gate 430 of FIG. 31. The other input to NAND gates 417, 418 and 419 are provided by signal LICRIVCLK9 from NOR gate 439 of FIG. 31. The output of AND gate 415 provides the J input to two flip flops of flip flop array 423 with the K- inputs of those two flip flops provided by signals PSCLVLIK-from terminal S46 and signal SRCLVL1K- from terminal S37. The output of AND gate 416 provides the J input to the third flip flop of array 423 whose K- input is provided by signal WSCLVL1K- from terminal S41. The output of AND gate 417 provides the J input to the fourth flip flop of array 423 whose K- input is provided by signal PCLRTERM- from array 327 shown in FIG. 23b.
The output of AND gate 418 provides the J input to the first flip flop of array 424 whose K- input is signal WCLRTERM- from flip flop array 327. AND gate 419 provides both the J and K inputs to the second flip flop of array 424. AND gate 420
provides the J input to the third flip flop and AND gate 421 provides the J input to the fourth flip flop whose K- input is provided by NAND gate 422. Flip flop arrays 423 and 424 are clocked by signal LICMCLLK- from terminal B102 and are cleared by signal CLRTPC- from terminal B67.
The output from the first flip flop of array 423 is signal PSCLVL1FUL applied to terminal T87; the output of the second flip flop is signal SRCLVL1FUL/Q applied to terminal S36; the output of the fourth flip flop is signal WSCLVL1FUL/Q applied to terminal S38 and the Q output of the fourth flip flop is signal SRCTERM/Q.
The Q output of the first flip flop of array 424 is signal WSCTERM/Q; the Q output of the second flip flop is signal PSCTERM/Q; the Q output of the third flip flop is signal PSCSTA2EN/Q; the Q output of the fourth flip flop is signal WSCSTA2EN/Q.
Bus 415 also provides eight inputs to flip flop array 426 whose eight outputs are applied to MAD bus 39. Array 426 is clocked by signal LICRIVCLK3- from FIG. 31 and is cleared by signal STORELIC-, inverted from flip flop array 146 of FIG. 7C. The memory is thereby addressed by the eight lines of bus 415 for storing of status information.
FIG. 31 illustrates the development of clock signals from inputs signals shown in FIG. 33. That is, AND gates 432-438 have signals LICRIVSEL2- through LICRIVSEL8-, respectively. The other inputs to AND gates 432-438 is provided by signal LICMCCLK- from terminal B102. NOR gate 430 has one input provided by signal LICRIVSEL1- and NOR gate 439 has one input provided by signal LICRIVSEL9-. The output from NOR gate 430 is inverted through inverter 431, supplying signal LICRIVCLK1-. The output of AND gate 432 is signal LICRIVCLK2-; the output of AND gate 433 is signal LICRIVCLK3-; the output of AND gate 434 is signal LICRIVCLK4-; the output of AND gate 435 is signal LICRIVCLK5-; the output of AND gate 436 is signal LICRIVCLK6-; the output of AND gate 437 is signal LICRIVCLK7-; the output of AND gate 438 is signal LICRIVCLK8-; the output of NOR gate 439 is signal LICRIVCLK9.
FIG. 32 illustrates simple circuitry for the writing of status data in association with the addressing mentioned above. The eight conductors of bus 415 are applied to the inputs of flip flop arrays 441 and 442, respectively. Flip flop 441 is clocked by signal LICRIVCLK7- and flip flop array 442 is clocked by signal LICRIVCLK8-. Flip flop 441 provides output bits 0-7 for application to bus MWD37 and flip flop array 442 provides output bits 8-15 for application to bus 37.
FIG. 33 illustrates the development of control signals by decoders 444-447. The decoders are Texas Instruments Type SN74LS138 described earlier. Decoders 444 and 445 have their C, B and A select inputs provided by conductors 1, 2 and 3, respectively, of bus 397. The enable input of G2A of decoders 444 and 445 are connected to receive signal LICLB- from microprocessor 400. Enable input G2B of decoder 444 and G1 of decoder 445 have conductor 0 of bus 397 attached. Enable input G1 of decoder 444 has voltage VCC applied, and enable input G2B of decoder 445 is attached to ground.
decoders 446 and 447 have connected to their C, B and A select inputs, lines 1, 2 and 3 from bus 415. Line 0 of bus 415 is connected to enable input G2B of decoder 446 and enable input G1 of decoder 447. Signal LICRIVEN- from AND gate 396
provides the input signal for enable terminals G2A of decoders 446 and 447. Enable terminal G1 of decoder 446 is connected to voltage VCC and enable terminal G2B of decoder 447 is connected to ground. The decoders then, in a prescribed manner as set out beginning at page 7134 of the TTL Data Book, have one of eight outputs available. Decoder 444 provides signals LICLIVSEL(0-7)-; decoder 445 provides signals LICLIVSEL(8-15)-; decoder 446 provides signals LICRIVSEL(0-7)-; decoder 447 provides output signals LlCRIVSEL(8-15)-.
FIG. 34 is a map of the contents of ROM 402.
LIST BUFFER AND ADDRESS REGISTER
Referring to FIG. 35a, 35b and 35c, the circuitry for the list buffer address register 16 of FIG. 1a is described. Flip flop arrays 459 and 460 receive address input information from line 0 and lines 1-7 of each of LFCRIV bus 321 and LICRIV bus
415, respectively. Flip flop array 459 is clocked by signal LFCRIVCLKl- shown on FIG. 23b and flip flop array 460 is clocked by the signal LICRIVCLK-2 from FIG. 31. The Q output of array 459, that refers to the line 0 input, carries signal LFCREQLBUF. The Q output of array 460 that corresponds to line 0 input carries signal LICREQLBF. The seven other outputs from array 459 provides an input to data selector 461 which, in this preferred embodiment, is a Texas Instruments Type 74LS157, described beginning at Page 7-181 of the TTL Data Book. The other seven outputs from array 460 also provide inputs to data selector 461 which is made up of two of the above mentioned 74LS157's. Signal LFCPSCSEL/Q from FIG. 23b is an input along with the inputs from array 459. Signal LICPSCSEL/Q is an input to selector 461, along with the seven inputs from array 460.
The output from selector 461 is an eight line bus, LBUFADRS(0-7) which is connected to random access memory (RAM) 465 which is the memory in which the 16-bit words from memory are stored, together with four bits of the ATI instruction word. That is, RAM 465 has a capacity of 256 words that are 20 bits in length. As indicated, one half of those words are devoted to the write sequence controller 26, while the other 128 words are for the process sequence controller 28.
Control circuitry for list buffer 17 is shown in FIG. 35a. Signal LICREQLBUF from flip flop array 460 is applied as one input to AND circuit 450 whose output is inverted through inverter 449 and applied to one input of AND gate 451 which has another input provided by signal LFCREQLBUF from array 459. The output of AND gate 450 also provides the J input to flip flop 452 whose Q output provides signal LICLBUFGNT/Q, providing one input to NOR gate 454, and whose Q- output provides the signal LICLBFGNT/Q- which provides the other input to AND gate 451. AND gate 451 has an output for providing the J input to flip flop 453, whose Q output provides the other input to NOR gate 454 and also provides an input to NAND gate 455. The Qoutput of flip flop 453 provides signal LFCLBFGNT/Q- which is the second input to AND gate 450. Flip flops 452 and 453 are clocked by signal CLKTPC.
Shift register 457 is a Texas Instruments Type 74LS195, a 4-bit parallel-access shift register described beginning at page 7-324 of the TTL Data Book. Its serial inputs are provided by the output of ANDgate 455; its outputs QA, QB and QC all provide inputs to NOR gate 456. Output QC of shif register 457 provides the signal LBUFTIMEOUT on terminal B105, which is then inverted through inverter 458, providing the K- input to each of flip flops 452 and 453. Shift register 457 is clocked by the signal CLKTPC-. The output of OR gate 454 provides one input to AND gate 455, whose other input is provided by the output from NOR gate 456. The signal LBUFTIMEOUT from terminal B105 provides the other input to NAND gate 455 whose output is used as the clear input to flip flop array 459. Flip flop array 460 is cleared by the signal CLRTPC- from terminal B67.
Output terminal QA of shift register 457 is also connected to the one input of NAND gate 464 whose other input is the signal LCFLBFGNT/Q from the Q output of flip flop 453.
FIG. 35c shows the connection made to NAND gate 464 whose output provides the store input to RAM 465. The memory read data signals MRD(00-15)/Q are applied as inputs to flip flop array 463 which is clocked by the signal DATAVLFC- from terminal B54 of FIG. 4b. These 16-bits provide the input to the RAM 465 and also to LFC14 as shown in FIG. 27. The ATI function bits from FIG. 15 are seen as signals ATIFUN(23-20) for storage in RAM 465.
FIG. 36 provides more detail of RAM 465 illustrating five sections, 466-470 which make up the total ROM.
In this preferred embodiment, the RAM sections are Texas Instruments Type 74LS208 random-access memories each having- 256 4-bit words of storage and described fully in the Bipolar Microcomputer Components Data Book, LCC4270. The output enable signals to sections 466 and 467 are LICLIVSEL2from decoder 444 of FIG. 33. The output enable inputs to sections 468 and 469 are provided by signal LICLIVSEL3- from decoder 444. The output enable input to section 470 is provided by signal LICLIVSEL0-, also from ecoder 444. The input data from flip flop array 463 is divided into four groups of four bits each. The four bits 00-03 are stored in section 466; bits 04-07 are stored in section 467; bits 08-11 are stored in section 468 and the four bits
12--15 are stored in section 469; ATI function bits 23-20 are stored in section 470. The output signal from NAND gate 464 is BUFSTORE applied to input W of each of the sections. The four bit outputs from each of the sections 466-470 are connected to LICLIV bus 397 as shown in FIG. 30b.
The combination of list buffer 17 and list buffer address register 16 then provides a list buffer grant and address selection. The list buffer is used by the LFC14 and LIC15. LFC14 fetches a list from the central memory and stores it in the list buffer 17 at an address determined by the circuitry of FIG. 35b. The list interpret controller 15, on the other hand, causes the lists to be removed from storage in list buffer 17 and moved into the list interpret controller.
SYSTEM READ CONTROLLER
The system read controller 27 is a part of the device interface controller. The SRC 27 accepts commands from LIC15 through SRCLVL1 register 19. The details of SRC 27 and register 19 follow.
FIGS. 37a, 37b and 37c make up the block diagram of SRC 27.
FIG. 37 illustrates microprocessor 500, voltage regulator 501 and ROM 502, identical to the previously described microprocessors and their associated ROM's. ROM 502 has an instruction portion 503 for holding the instructions or microprocessor
500 which are addressed from the microprocessor 500 over bus SRCAR(0-11) with those instructions sent from section 503 over bus SRCIR(00-15) to microprocessor 500. Control section 504 provides eight outputs to flip flop array 478 which in turn provides the output signals SRCIVR4/Q, SRCLVLlK-, LW#LDEN, SRCHLTCLKPS, SRCCCL, CYREQSRC, and FETCHSRC. The inputs to microprocessor 500 include clock signal CLK8X300 from terminal B66, which is buffered through buffer 476 and applied to terminal X1 and which is inverted through inverter 477 and applied to terminal X2. Voltage VCC is applied through resistor R19 to terminal X1 and through resistor R18 to terminal X2 of microprocessor 500. Terminal MCCLK of microprocessor 500 provides the signal SRCMCCLK and terminal LB- provides output signal SRCLB-.
Microprocessor 500 has eight internal registers, but for its application in SRC27, it was found useful to add registers 484, 485 and 486, whose outputs are connected to
SRCLIV bus (0-7) 488a. Registers 484-486 are clocked by signals SRCRIVCLK20- through 22-, respectively. Registers 484-486 are cleared by signals SRCLIVSEL12- through 14-, respectively. AND gate 483 has inputs SRCLIVSEL12- through 14- and output signal SRCLIVSELEN- which is the enable signal for inverter 482 whose input accepts bus 488a and whose output is connected to bus 488 which is SRCLIVBUS(00-07).
Bus 488 is similar to the left interface vector buses described in connection with the other controllers. That is, it is connected to microprocessor 500 and has a number of inputs. Data from memory, namely MRD(00-15) is applied to flip flop arrays 472 and 473 with bits 00-07 being applied to flip flop 472 and bits 08-15 being applied to flip flop array 473. The arrays 472 and 473 are clocked by signal DATAVSRC- from terminal S53 of FIG. 4b. Array 472 is cleared by the signal SRCLVSEL6- and array 473 is cleared by signal SRCLIVSEL7-. Eight outputs from each of arrays 472 and 473 provide inputs to bus 488.
Inverters arrays 474 and 480 each have eight outputs connected to bus 488. Inverter array 474 has the following inputs: CYGRANTSRC-, DATAVSRC-, CMDTIM/Q, SCANERR/Q, TESTFLAG03. Array 474 has its outputs enabled by signal SRCLIVSEL0.
Array 480 has the following inputs: HALTPSC/Q, SRCLVLlFUL/Q,FATOWSC/Q, FBTOWSC/Q, REWLOOK/Q, DRCRATERR/Q, DRCXFRCOMP/Q and DMASTOD. Inverter array 480 has its outputs enabled by signal SRCLIVSEL2-.
Bus 490 carries the command word from SRCLVL1 register 19, the level 1 register, to bus 488 of the system read controller.
Buses 491-495 carry formatter status bytes from the SRC/WSC formatter, to be described later.
Still other inputs to bus 488 include buses 565 and 566 from the list word two counter of FIGS. 44a and 44b.
Still another set of inputs to bus 488 is the output set of inverter array 508 whose outputs are enabled by signal SRCLIVSEL3-and whose inputs are provided from the data read controller 30. The input signals to array 508 are the TRDPAR#(27-20) signal outputs from a tape read data parity error counter to be described later. The number of parity errors is counted and transferred to the memory by way of this circuit.
Bus 488 provides the inputs to inverter array 481 whose output is bus 496, the write interface vector bus, similar to those previously described in association with the other controllers. SRCRIVBUS(0-7) bus 496 provides outputs to the registers
484-486. It also provides outputs on buses 561 and 562 to the bytes/scan counter of FIGS. 43a and 43b. Bus 496 provides bus 497 to the SRC status FIFO of FIG. 42. Further provided are eight line buses 498 and 499 to the SRC memory address counter, FIGS. 39a and 39b. Also, eight-line bus 506 from bus 496 provides inputs to the formatter logic to be described later. Bus 507 from bus 496 goes to the data read controller 30 and is described later.
Line 1 of bus 496 provides one input to NAND gate 487 whose other input is provided by signal SRCRIVCLK3 and whose output is signal SRCCLRABORT-, applied to terminal S47. Bus assemblies 563(i a-d) and 564(a-d) go to the list word two counter of FIGS. 44a and 44b and to the list word six counter of FIGS. 45a and 45b respectively.
The eight lines of bus 496 provide an input to flip flop array 509 which is clocked by signal SRCRIVCLK19- which has four outputs corresponding to lines 0-3 of bus 496 that are used for test flags, one line used for GAPFLG/Q and one for signal DRCGO/Q.
Lines 0-4 from bus 496 provide the input to flip flop array 510 which is clocked by signal SRCRIVCLK9-and which has three outputs providing signals SRCTA(0-2)/Q and two outputs providing signals SRCDS(0-1)/Q.
Lines 3-7 of bus 496 provide inputs to flip flop array 511 whose outputs are signals SRCCMD(0-4)/Q.
Lines 1 and 2 of bus 496 provide inputs to flip flop array 512 whose outputs are signals SRCESC(0-1)/Q. Signal SRCRIVCLK10- provides the clock input to both flip flop arrays 511 and 512.
FIGS. 38a and 38b illustrate the SRCIV select circuitry. Decoders 515, 516, 521, 522 and 523 are all Texas Instruments Type 138 3-to-8 line decoders described beginning at page 7-134 of the TTL Data Book.
Signal SRCLB- from terminal LB- of microprocessor 500 provides the G2A enable input of decoder 515 and the G2A and G2B enable inputs of decoder 516. Voltage VCC is applied to the G1 enable input of decoder 515. Signal SRCIVLO/Q from flip flop array 518 is connected to the G2B enable input of decoder 515 and to the G1 enable input of decoder 516. Signals SRCIVL3/Q, SRCIVL2/Q and SRCIVL1/Q provide the A, B and C select inputs to each of decoders 515 and 516. Decoder 515 provides signals SRCLIVSEL(0-7) and decoder 516 provides outputs SRCLIVSEL(8-15)-.
Lines 3-11 of bus SRCAR from microprocessor 500 provide the inputs to flip flop array 517 whose output signals SRCLIVSEL(0-7) are applied to flip flop array 518 (0-3) and to flip flop array 520 (4-7). Signal SRCMCCLK from microprocessor 500 is inverted through inverter 519 and provides the clock input to each of flip flop arrays 518 and 520. The output signals of flip flop array 518 are SRCIVL(0-3)/Q and the output signals from flip flop array 520 are SRCIVR(0-3)/Q Signal SRCIVR1/Q from flip flop array 520 provides the G2B and G1 enable inputs of decoders 521 and 522, respectively. Voltage VCC is connected to the G1 enable input of decoder 521. Signal SRCMCCLK-, from the output of inverter 519, is applied to the G2A enable input of each of decoders 521, 522 and 523. The G2B enable inputs of decoders 522 and 523 are grounded. Signal SRCIVR0/Q, from flip flop array 520, provides the input signal to enable input G1 of decoder 523. Select input terminal B of each of decoders 521, 522 and
523 are activated by signals SRCIVR2/Q through 4/Q from flip flop array 520.
The output signals from flip flop 521 are SRCRIVCLK(0-7)-; the outputs from decoder 522 are signals SRCRIVCLK(8-15); the outputs from decoder 523 are signals SRCRIVCLK(16-23)-.
The circuitry of FIGS. 30a and 30b then provides the various select signals and clock signals that are used throughout the SRC27.
FIGS. 39a and 39b illustrate the SRC memory address counter circuitry. The addressing is done to effect reading from the central memory of various words that are to be compared in the circuitry of the data read controller 30, to be described later.
Counter assemblies 530-533 are Texas Instruments Type 74LS163, described beginning at page 7-190 of the TTL Data Book. Bits 0-3 from bus 498, connected to bus 496, provide the-input signals to counter 530. Bits 4-7 from bus 498 provide the inputs to counter 531. Bits 0-3 from bus 499, connected to bus 496, provide the inputs to counter 532 and bits 4-7 from bus 499 provide the inputs to counter 533.
Signal SRCRIVCLK3-, from decoder 521, is inverted through inverter 536 and provides one input to AND gate 535 whose other input is provided by line 0 of bus 496. The output of AND gate 535 provides the enable P input of counter 533 whose enable T input is connected to voltage VCC. Each of counters 530-533 is clocked by signal SRCMCCLK-. The ripple carry output of counter 533 provides both enable P and enable T signals for counter 532. The ripple carry output from counter 533 also provides the enable P input to each of counters 531 and 530. The ripple carry output of counter 532 provides the enable T connection to counter 531 whose ripple carry output is connected to the enable T terminal of counter 530.
Signal SRCRIVCLK8-, from decoder 522, is inverted through inverter 538 and again through inverter 537 and provides the load inputs to counters 533 and 532. Signal SRCRIVCLK7-, from decoder 521, is inverted through inverter 540 and then through inverter 539, providing the load inputs to each of counters 531 and 530. The clock input to each of counters 530-533 is provided by the signal SRCMCCLK-, mentioned above.
The outputs from counters 530 and 531 are inputs to buffer array 534 which provides eight inputs to the memory address bus 39. The outputs from counters 532 and 533 provide eight inputs to buffer array 541 whose eight outputs are inputted to memory address bus 39. Buffer arrays 534 and 541 are enabled by signal FETCHSRCEN-from terminal S64.
FIG. 40 is a schematic illustrating the generation of a control signal. Signal DMACST00, indicating that the PSC28 is inactive, provides a J input to flip flop 479. The output of inverter 477, signal SRCX2CLK-clocks flip flop 479. Signal CLRPSC is inverted through inverter 489 and provides the clear input to flip flop 479 with the Q output providing generated signal PSCSTO/Q.
FIG. 41 is another simple schematic illustrating the generation of a control signal. Line 0 of bus 496 provides one input to AND gate 543. Signal SRCRIVCLK10- from decoder 522 is inverted through inverter 542 and provides the other input to AND gate 543. The output of AND gate 543 provides the J input to flip flop 544 which is clocked by the signal SRCMCCLK- and whose Q- output is control signal PPEND#M1-, applied to terminal S28 and to the K- input of flip flop 544.
FIG. 42 illustrates, in more detail, the status FIFO's 22 and 23 of Figure 1b. These devices are Texas Instruments Type 74S225 asynchronous first-in first-out memories described in the Bipolar Microcomputer Components Data Book, LCC4270. Bus
550 from the right interface vector bus of write sequence controller 26 provides eight inputs to status FIFO 22 whose CK A and B inputs are provided by signal WSCRIVCLK5- . Its clear input is provided by the signal CLRTPC-; its OR input is provided by the signal WSCSTATRDY, its UNLOADCK input is provided by the signal LICLIVSEL4- from decoder 446 and its OE- input is provided by signal LICLIVSEL4-. Its outputs are provided on bus 548 to LIC bus 397.
Bus 497 from bus 496 provides eight inputs to status FIFO 523 which is clocked by signal SRCRIVCLK1-from decoder 521. It is cleared by signal CLRTPC-and its OR input is provided by signal SRCSTATRDY from terminal S44. Its OE-input and UNLOADCK input is provided by signal LICLIVSEL5- from decoder 444. Eight outputs from status FIFO 23 are combined in bus 549 and connected to bus 397 of LIC15.
A status word held in the status FIFO 23 contains first, an interrupt CPU bit to provide an interrupt capability. Also provided are status indicator, a terminate status, a store instruction bit and an abnormal termination bit. LIC15, by way of controlling the OE-terminal of each of status FIFO's 22 and 23, sends any status information received for storage into the central memory.
FIGS. 43a and 43b schematically represent the "bytes per scan counter". The counter is loaded by SRC27 and incremented by the data read controller 30. This particular counter is used for a tape read purpose to be described later.
Buse 561 and 562 from bus 496 provide inputs to flip flop arrays 555 and 558, respectively. These arrays are clocked by signals SRCRIVCLK15- and SRCRIVCLK16-, respectively, from decoders 522 and 523, respectively. Bits 00-03 from array 555 are input to counter 556 and bits 4-7 are input to counter 557. Counters 556, 557, 559 and 560 are Texas Instruments Type 74LS163 synchronous 4-bit counters described beginning at Page 7-190 of the TTL Data Book. The load input of all these counters is provided by signal DRCROM10/Q-, ultimately from the ROM of the data read controller.
Bits 8-11 from array 558 provide inputs to counter 559, bits and bits 12-15 provide inputs to counter 560. Signal DRCROM11/Q, ultimately from the ROM of DRC30, provides the P and T enable inputs to counter 560 whose ripple carry output provides the T and P enable inputs to counter 559 and the P enable inputs to counters 557 and 556. The ripple carry output of counter 559 provides the T enable input to counter 557 and the ripple carry output of counter 557 provides the T enable input to counter
556. The ripple carry output of counter 556 provides the J input to flip flop 545 which is clocked by signal DRC#CLK- from DRC30 and whose K- input is provided by signal DRCRUNEN from DRC30. The Q output of flip flop 545 provides the counter output signal BY/SCN#CO4/Q.
FIGS. 44a and 44b schematically illustrate another counter assembly made up of counters 572, 573, 574 and 575, all identical to the counters described in association with FIGS. 43a and 43b. Lines 0-3 from bus 46 provide inputs to counters 572
and 574 while lines 4-7 of bus 496 provide inputs to counters 573 and 575. The load input signals for counters 572 and 573 are provided by signal SRCRIVCLK11- from decoder 522, inverted through inverter 576 and again through 577. The load signal for counters 574 and 575 is provided by signal SRCRIVCLK12- from decoder 522, inverted through inverter 578 and again through inverter 579.
Signal LW#LDEN from flip flop array 478 provides one input to AND gate 569. Signal LW#LDN is inverted through inverter 568 and provides one input to AND gate 570. The other input to AND gate 569 is signal SRCMCCLK and the other input to AND gate 570 is signal DRCMCCLK, from DRC30. The outputs of AND gates 569 provide the inputs to NOR gate 571 whose output signal, DRC#CLK- provides the clock input to each of counters 572-575.
Signal DRCROM08/Q, ultimately from the DRC30 ROM provides the enable T and P inputs to counter 575 whose ripple carry output provides the enable T and P inputs to counter 574 and the enable P inputs of counters 573 and 572. The ripple carry output from counter 574 provides the enable T input to counter 573 whose ripple carry out provides the T input to the enable input of counter 572. The ripple carry output from counter 572 is connected to the J input of flip flop 582 which is clocked by the signal DRC#CLK-, from NOR circuit 571, and whose K- input is provided by the signal DRCRUNEN from inverter 568. The Q output of flip flop 582 is signal DRCXFRCOMP/Q. The outputs of counters 572 and 573 are inverted through inverter array 580 whose output is enabled by signal SRCLIVSEL4-. The output of inverter array 580 is connected through bus 565 to bus 488. The outputs from counters 574 and 575 are inverted through inverter 581 whose output is enabled by signal SRCLIVSEL5- from decoder 515, whose output is bus 566, connected to bus 488.
FIGS. 45a and 45b depict still another counter, this one for counting list word 6. The reasons for such counting will be provided in the Mode of Operation description that follows.
This general purpose counter assembly is made up of four counters assemblies, 590-593, identical to the counters of FIGS. 44a and 44b. Lines 0-3 from bus 496 provide the inputs to counters 590 and 592. Lines 4-7 of bus 496 provide the inputs to counters 591 and 593. The load signal for counters 590 and 591 is provided by signal SRCRIVCLK13- from decoder 522, inverted through inverter 584 and again through inverter 585. The load input for counters 592 and 593 is provided by signal SRCRIVCLK14- from decoder 522, inverted through inverters 586 and 587. Counters 590-593 are all clocked by the signal DRC#CLK- from NOR circuit 571.
Signal DRCROM09/Q, ultimately from the DRC ROM, provides the P and T enable inputs to counter 593 whose ripple carry output provides the T and P enable inputs to counter 592 and the P enable inputs to counters 591 and 590. The ripple carry output from counter 592 provides the T enable input to counter 591 whose ripple carry output provides the T enable input to counter 590. The ripple carry output from counter 590 provides the J input to flip flop 588 which is clocked by signal DRC#CLK-, whose K- input is provided by signal DRCRUNEN and whose output is signal WL6#CO4/Q.
None of the data outputs are used in this operation, but simply the last carry out of counter 590.
FIGS. 46a and 46b schematically illustrate the WSCLVL1 register 18, the SRCLVL1 register 19 and the PSCLVL1 register 20 shown in FIG. 1a. RAM's 596, 609 and 612, in this preferred embodiment, are Texas Instruments Type 74S208 random-access memories described in the Bipolar Microcomputer Components Data Book, LCC4270. Selectors 597, 599 and 611 select addresses for the RAM's 596, 609 and 612, respectively. Selectors 597, 599 and 611 are Texas Instruments Type 74LS157 Data Selectors/Multiplexers described beginning at page 7181 of the TTL Data Book. All of the three selectors have their B inputs provided by the outputs of flip flop array 598 whose inputs are provided from bus 496 over connecting bus 595. Flip flop array
598 is clocked by signal LICRIVCLK4-, from decoder 521. The A inputs to selector 597 are provided by signals XFR(10-15) from PSC28. Selector 599 receives its A inputs from flip flop array 607. The inputs to flip flop array 607 are provided by lines
2-7 of bus 496 and it is clocked by signals SRCRIVCLK6- from decoder 521. Th A inputs for the WSC selector 611 come from the output of of flip flop array 610 whose inputs are provided by lines 2-7 of the right interface vector bus of WSC26. Flip flop array 610 is clocked by signal WSCRIVCLK6- from WSC26. The inputs to PSC RAM 596 are provided from bus 595 while the inputs to SRC RAM 609 and WSC RAM 612 come from bus 594 which is the inverted output of inverter array 608. Array 608 receives bus 595
as an input. RAM's 596 and 609 are clocked by signal LICRIVCLK5- and RAM 612 is clocked by signal LICRIVCLK6-, both signals from decoder 521. The select input of selector 597 and the output enable input of RAM 596 are controlled by signal LICSEL0- from PSC 28. The select input of selector 599 and the output enable input of RAM 609 are controlled by signal SRCLIVSEL1- from decoder 515. A select input to selector 611 and the output enable input of RAM 612 is controlled by signal WSCLIVSEL4-, from WSC26.
The combination of selector 597 and RAM 596 comprises the PSCLVL1 register 20 of FIG. 1a and provides 8-bit word outputs to the PSC28. Selector 599 and RAM 609 comprise SRCLVL1 register 19 of FIG. 1a with RAM 609 providing 8-bit words to the bus
488. Selector 611 and RAM 612 comprise WSCLVL1 register 18 with RAM 612 providing an 8-bit word output to the left interface vector bus of WSC26.
It should be noted that the RAM's 596, 609 and 612 have addresses selected as though they were FIFO's. That is, the first word entered is the first word removed. However, since they are in fact RAM's, any desired sequencing could be accomplished.
FIG. 47 is a map of the contents of ROM 502.
DATA READ CONTROLLER
FIGS. 48a, b and c diagrmmatically illustrate DRC 30 that is designed around its microprocessor 600. Microprocessor 600 is identical to microprocessors 200-500 having voltage regulator 601 and ROM 602. ROM 602 has instruction register portion
603, and LIV/RIV address portion 604, and a control portion 605. Control portion 605 provides 8 bits to flip flop array 621 and the next higher order 8 bits to flip flop array 622. The outputs of array 621 are signals DRCROM(00-07)/Q and in the outputs from array 622 are signals DRCROM(08-15)/Q. Clock signal CLK8X300, as in the prior cases, is buffered through buffer 612 and applied to terminal X1. CLK8X300 is also inverted through inverter 614 and applied to terminal X2. Voltage VCC is applied, through resistor R18 to terminal X1 and through resistor 19 to terminal X2. Signal DRCMCCLK from terminal MCCLK of microprocessor 600 is inverted through inverter 618 and clocks flip flop arrays 616 and 617. Signal DRCSC- is provided from terminal SC of microprocessor 600. Four bits from the LIC/RIV portion 604 provide inputs to flip flop array 616, and another four bits from portion 604 provide inputs to flip flop array 617 Three outputs from array 616 are applied to the select input terminals A, B and C of decoder 620, a Texas Instruments Type 74LS138. Three outputs from array 617 provide the A, B and C select inputs for decoder 619, identical to decoder 620. Signal DRCLB- from microprocessor 600, terminal LB-, provides the G2B enable input signal of decoder 619 and signal DRCMCCLK- from the output of inverter 618 provides the input to enable terminal G2B of decoder 620. Enable inputs G2A and G1 of each of decoders 610 and 620 are grounded and connected to voltage VCC, respectively. The outputs of decoder 619 are signals DRCLIVSEL(0-7)- and the outputs of decoder 620 are signals DRCRIVCLK(0-7)-.
RCLIVBUS(0-7)-, which is bus 625, is connected to microprocessor 600 and has various inputs similar to such left interface vector buses described earlier. The tape read data FIFO signals, TRDFIFO(0-7) provide inputs to inverter array 626, whose outputs are enabled by signal DRCLIVSEL4-, from decoder 619 (providing eight outputs to bus 625). The start of scan counters 0, 1 and 2 provide input signals to inverter array 627 whose outputs are enabled by signal DRCLIVSEL3- from decoder 619. Signals DN=CUR and DN=A from the DRC data comparator shown in FIGS. 52a and 52b also provide inputs to array 627. Signals DN=B and DNMO=A are inputs to AND gate 632 which provides the last input to array 627. The outputs from array 627 are connected to bus 625. Bus 488 provides eight inputs to each of flip flop arrays 628 and 269, each providing eight inputs to bus 625. The output control terminal of array 625 is activated by signal DRCLIVSEL0- and the output control of array 629 is activated by signal DRCLIVSEL1-, both outputs of decoder 619. Flip flop array 628 is clocked by signal SRCRIVCLK17-, and array 629 is clocked by signal SRCRIVCLK18-, both signals being outputs from decoder 523.
Inverter array 631 whose outputs are connected to bus 625 has input signals CMDTIME/Q- from the Q- outut of flip flop 638; signal BYTETIME from SRC27; signal GAPFLG/Q from SRC27; signal BY/SCN#C04/Q from flip flop 545 of FIG. 43a; signal LW6#C04/Q from flip flop 588 of FIG. 45a and DRCXFRCOMP/Q. The outputs of array 631 are enabled by signal DRCLIVSEL2- from decoder 619.
Bus 625 provides inputs to inverter array 624 whose outputs make up the bus DRCRIVBUS(0-7) which is bus 630. Bus 630 provides inputs to flip flop array 634 which is blocked by signal DRCRIVCLK2- from decoder 620. Its outputs are signals EOD/Q, SCANDT/Q, SEGMENT0/Q, SEGMENT1/Q and FLE/Q, this last output providing the J input to flip flop 635. Signal GAPFLG/Q from flip flop array 509 is inverted through inverter 636 and provides the K- input to flip flop 635 whose Q output is signal SCANERR/Q.
FIG. 49 is a schematic diagram of the tape read data parity counter. This counter reports the number of parity errors detected during a record. Signals TRDFIFO(0-8) from the output of FIFO's 658 and 659 are applied to parity generator 640 which is a Texas Instruments Type 74180 9-bit odd/even parity generator/checker, described beginning at page 7-269 of the TTL Data Book. A detected parity error is transmitted to counter 642 which is combined with counter 641, both being Texas Instruments Type LS161A described beginning at page 7-190 of the TTL Data Book. The clear input of counters 641 and 6