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United States Patent4744084
Beck , ; et al.May 10, 1988
Title
Hardware modeling system and method for simulating portions of electrical circuits
Abstract
A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.
Inventors:Beck; Ronald R. (Banks, OR), Stanbro; Michael E.  (Tigard, OR), Thomsen; Eric J.  (Aloha, OR)
Assignee:Mentor Graphics Corporation (Beaverton, OR)
Appl. No.:070598
Filed:July 8, 1987
Current U.S. Class:714/33 324/73.1 703/14 703/2 
Current International Class:G06F 17/50 (20060101)
Field of Search:371/15,16,17,18,20,23 364/578,488,489,490,491,2MSFile,9MSFile,149,150,151 324/73R,73AT,73PC
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Primary Examiner: Smith; Jerry
Assistant Examiner: Beausoliel; Robert W.
Attorney, Agent or Firm:Klarquist, Sparkman, Campbell, Leigh & Whinston
Parent Case Text


CROSS REFERENCE TO CO-PENDING APPLICATION

This application is a continuation of application Ser. No. 832,838, filed Feb. 27, 1986, which in turn is a continuation-in-part of co-pending application Ser. No. 707,497, filed Mar. 1, 1985 and entitled HARDWARE MODELING SYSTEM AND METHOD FOR STIMULATING PORTIONS OF ELECTRICAL CIRCUITS, both now abandoned.
Claims

We claim as our invention all such modifications as come within the true spirit and scope of the following claims:
1. In a simulation system which includes plural workstations for independently and simultaneously simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of a plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising:
hardware modeling circuit means including input means for receiving input test data from the workstation, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; and
network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide concurrent access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transfering resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations for concurrent circuit simulations by the workstations.

2. A simulation system according to claim 1 including plural hardware modeling circuit means, said network interface means comprising means for interfacing the workstations to such plural hardware modeling circuit means so as to permit sharing of the plural hardware modeling circuit means among the plural workstations.

3. A system according to claim 1 in which the hardware modeling circuit means includes plural integrated circuit interface means and input/output port means for coupling to actual circuit elements, the integrated circuit interface means and input/output port means including the stimulus signal generation means coupled to the input means for receiving input test data and for generating evaluation stimuli corresponding to the input test data, the application means coupled to the stimulus signal generation means for applying evaluation stimuli to the actual circuit elements, and the retrieval means coupled to the actual circuit elements for receiving output signals from the actual circuit elements, the output signals being generated by the actual circuit elements in response to the evaluation stimuli.

4. The hardware modeling system of claim 1 in which the input means comprises:
a first semiconductor memory circuit capable of operating at a first rate for storing input test data for use in a plurality of simulations;
a second semiconductor memory circuit capable of operating at a second rate faster than the first rate for storing input test data for use in a single simulation;
means for transferring input test data for use in a single simulation from the first semiconductor memory circuit to the second semiconductor memory circuit; and
means for transferring input test data from the second semiconductor memory circuit to the stimulus signal generation means.

5. A hardware modeling system with a plurality of different plural pin hardware modeling elements used for performing simulations of the performance of electronic circuits in response to input test data, means for converting test data to evaluation stimuli and for applying the evaluation stimuli to selected input pins of the hardware modeling element, means for retrieving output signals from selected output pins of the hardware modeling element and for converting the output signals to resultant test data, timing analyzer circuit means for periodically sampling the resultant data from the output pins to provide a timing representation of the resultant data at the output pins over time, and means for selectively coupling the timing analyzer circuit means to the output pins to provide the timing representation.

6. A hardware modeling system according to claim 5 including:
user memory means for storing input test data for one or more simulations;
operating memory means for storing input test data for only one simulation;
means for applying input test data from the operating memory means to said means for converting test data during a simulation; and
means for transferring input test data for a single simulation from the user memory means to the operatin memory means following the application of input test data for a prior simulation from the operating memory means to the means for converting test data.

7. In a hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plurality of different plural pin hardware modeling elements used in circuit simulations so as to produce output signals from output pins of the hardware modeling elements and thereby simulation results;
gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element;
means for selecting any of the pin connections as input data pin connections;
means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element;
means for selecting any of the pin connections as clock pin connections;
means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element;
means for selecting any of the pin connections as output data connections; and
means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element.

8. A gating circuit according to claim 7 including means for selectively applying a variable logic 0, logic 1 or high impedance to any of the pin connections and thereby to the associated pins.

9. A gating circuit according to claim 7 including means for selectively applying a pull-up or a pull-down load to any of the pin connections and thereby to the associated pins.

10. A hardware modeling system according to claim 7 which includes means for selectively applying clock signals to any of the pins of the actual circuit element, and also includes means for adjusting the phase, duty cycle and frequency of the applied clock signals.

11. A hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plural pin hardware modeling element corresponding to a component in a circuit being simulated so as to produce output signals from output pins of the hardware modeling element for use in the circuit stimulation, the system including;
gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element;
means for selecting any of the pin connections as input data pin connections;
means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element;
means for selecting any of the pin connections as clock pin connections;
means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element;
means for selecting any of the pin connections as output data connections;
means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element;
the system further including bus contention detection means for indicating when any of such pin connections are driven by a signal from a hardware modeling element to one state while the same pin connection is driven by a signal from the gating circuit to an opposite state, and for disabling at least one of the drive signals applied to the pin connection under such conditions.

12. An apparatus according to claim 11 including timing analyzer means selectively coupled to the output pin connections for performing timing analysis on output signals received from the associated pins.

13. An apparatus according to claim 11 including clocking means for applying clocking signals to the clocking pin connections, such clocking means including means for varying the frequency, duty cycle and phase of clocking signals applied to each such clocking pin connection.

14. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
memory means for receiving and storing input test data from the workstation;
circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli;
the memory means comprising means coupled to the resultant test data retriveval means for receiving and storing the resultant test data;
control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; and
the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means.

15. A hardware modeling system according to claim 14 which the control circuit means comprises means for controlling the transfer of resultant test data from the resultant test data retrieval means to the first memory means.

16. The hardware modeling system of claim 14 in which the first and second memory means comprise semiconductor memory circuits.

17. The hardware modeling system of claim 16 in which the second semiconductor memory circuit can be accessed more quickly than the first.

18. A system according to claim 14 in which the first memory means operates at a first rate and the second memory means operates at a second rate greater than the first rate.

19. A hardware modeling system according to claim 14 in which the control cirucit means includes device clock means for generating device clock signals for clocking the actual circuit elements, the control circuit means also including means for selectively positioning the rising and falling edges of the device clock signals relative to the evaluation stimuli and thus relative to the input test data.

20. A system according to claim 14 in which the second memory means has a full pattern depth available to each circuit element during a simulation using the circuit element.

21. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
memory means for receiving and storing input test data from the workstation;
circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli;
the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data;
control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation;
the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means; and
the memory means including third supplemental disk memory means which acts as a virtual memory means, the hardware modeling system including means for swapping inputting test data from the first to third memory means and from the third to first memory means.

22. A hardware modeling system according to claim 16 including timing analyzer and memory circuit means coupled to the resultant test data retrieval means for selectively receiving resultant test data, the control circuit means comprising means for periodically transferring resultant test data to the timing analyzer and memory circuit means to provide a representation of such resultant test data over time.

23. A hardware modeling system according to claim 22 in which the control circuit means includes means for applying timing analysis clocking signals to the timing analyzer and memory circuit means to transfer resultant test data in response to the timing analysis clocking signals.

24. A hardware modeling system according to claim 21 including high impedance testing means for determining whether a pin of the actual circuit element is at a high impedance state, the high impedance testing means comprising means for applying a logic high signal and a logic low signal to the pin and evaluating whether the pin is pulled to the logic high and logic low states in response to the applied signals.

25. A system according to claim 21 in which the first memory means operates at a first rate and the second memory means operates at a second rate greater than the first rate.

26. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
memory means for receiving and storing input test data from the workstation;
circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli;
the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data;
control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation;
the control circuit means including first clock means for clocking a first set of input test data from the memory means to the circuit interface means, second clock means for clocking a second set of input test data from the memory means to the circuit interface means, master clock means for generating master clock signals for clocking the stimulus signal generation means following the transfers of the first and second sets of input test data, thereby controlling the generation of evaluation stimuli to correspond to both of the first and second sets of input test data, and device clock means for generating device clock signals for clocking the actual circuit elements.

27. The hardware modeling system according to claim 26 in which the control circuit means includes means for selectively positioning the rising and falling edges of the device clock signals relative to the master clock signals.

28. A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising:
memory means for receiving and storing input test data from the workstation;
circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli;
the memory means comprising means coupled to the resultant test data retreval means for receiving and storing the resultant test data;
control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation;
the system further including bus contention means for detcting bus contentions, a bus contention occurring upon the application of a drive signal by the application means to a pin of the actual circuit element simultaneously with the generation of an output drive signal at such pin by the actual circuit element in response to the applied evaluation stimuli.

29. A hardware modeling system according to claim 28 in which the bus contention means includes means for changing the drive signal which is applied to such pin by the application means to a high-impedance signal upon detection of a bus contention at such pin to thereby minimize the risk of damage from the bus contention.

30. An electronic circuit simulation method in which actual plural pin hardware circuit elements are used in the simulation comprising:
storing test data for plural simulations in a first memory;
transferring test data for a single simulation from the first memory to a second memory;
applying test data for the single simulation from the second memory to an actual hardware circuit element to provide resultant test data from the circuit element; and
transferring test data for successive single simulations from the first memory to the second memory following the application of test data for a prior single simulation to an actual hardware modeling element.

31. A method according to claim 30, including the step of sampling output signals from output pins of an actual circuit element as test data is applied to the actual circuit element during a simulation, thereby providing a representation of the output signals at the sampled output pins during the simulation.

32. A method according to claim 30 comprising the steps of transferring test data at a first rate from the first memory to the second memory and applying the test data at a second rate higher than the first rate from the second memory to the actual hardware circuit element.

33. In a simulation system which includes plural workstations for simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of at least one plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising:
hardware modeling circuit means including input means for receiving input test data from the workstations, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data;
network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transferring resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations; and
the hardware modeling circuit means including:
user memory means for storing input test data for one or more simulations;
operating memory means for storing input test data for only one simulation;
means for applying input test data from the operating memory means to said means for converting test data during a simulation; and
means for transferring input test data for a single simulation from the user memory means to the operating memory means following the application of input test data for a prior simulation from the operating memory means to the means for converting test data.

34. A system according to claim 33 in which the means for transferring input test data from the user memory means to the operating memory means comprises means for transferring such input test data at a first rate, and in which the means for applying input test data from the operating memory means comprises means for applying such test data at a second rate which is greater than the first rate.

35. A system according to claim 34 in which the operating memory means has a full pattern depth available to each circuit element during a simulation using the circuit element.

36. A system according to claim 33 including third supplemental disk memory means which acts as a virtual memory means, the hardware modeling circuit means including means for swapping input test data from the first to third memory means and from the third to first memory means as the first memory means fills with input test data.

37. A simulation system comprising:
plural workstations each capable of independently performing circuit evaluations of various circuit in which the evaluations involve at least in part a software simulation of the circuit being evaluated by each workstation;
hardware modeling circuit means coupled to the plural workstations and including at least one actual circuit element, the hardware modeling circuit means comprising means for providing shared access by the plural workstations to the actual circuit element, the hardware modeling circuit means comprsing means permitting the plural workstations to perform concurrent circuit evaluations using the actual hardware element in the evaluation when such element appears in the circuits being evaluated by the plural workstations.

38. A simulation system according to claim 37 in which the hardware modelling circuit means has plural actual circuit elements.
Description
BACKGROUND OF THE INVENTION

The present invention relates to a method and apparatus for simulating portions of electrical circuits by using actual hardware components, such as integrated circuits, printed circuit boards and electrical circuit subsystems, in the simulation.

Heretofore, software systems have been developed for modeling or simulating the performance of circuit components. Through the use of software models, the design and engineering of electrical circuits is facilitated. Although these devices have proven to be powerful tools in aiding circuit designers, drawbacks exist, especially in software modeling of large-scale integrated and very-large-scale integrated circuit devices, such as microprocessors. For these latter devices, it is time-consuming and expensive to create software models. In this regard, the length of time required to prepare such models makes it difficult to create models as rapidly as new circuit designs evolve. Furthermore, complex software models are difficult to test and sometimes suffer from less than optimal reliability. Moreover, proprietary circuit designs are typically not subject to modeling unless the owner of the design releases sufficient information to enable the creation of a software model. Owners of circuit designs are frequently reluctant to provide such information.

In an attempt which partially addresses these problems, Daisy Systems and Valid Logic Systems, have developed devices designated respectively as "PMX" and "Real Chip". In each of these devices, a circuit designer uses a workstation equipped with software models of a number of circuit components. Each workstation is also connected to its own dedicated hardware component modeling unit. These hardware component modeling units contain actual integrated circuit components for use in modeling. When a user at a workstation is evaluating a circuit design having components corresponding to one or more of the hardware components in the hardware component modeling unit, the corresponding hardware component in the hardware modeling unit is accessed and is used for modeling. That is, test data is fed from the workstation to the physical component in the hardware modeling unit. Test results are then returned from the hardware modeling unit to the workstation following the test. In this way, an actual hardware component is used in modeling in lieu of a software model.

These existing devices suffer from a number of limitations. In the first place, as explained above, each workstation is associated with its own dedicated separate hardware modeling unit. Therefore, for example, four such workstations require four hardware modeling units. Consequently, to provide each user with access to a given integrated circuit for modeling, one of these integrated circuits must be provided in each of the hardware modeling devices. This can be prohibitively expensive. Moreover, it may be difficult or impossible in the case of proprietary circuits, where only one or a few such circuits are in existence.

The "PMX" and "Real Chip" devices also suffer from a variety of technical deficiencies. For example, they are understood to lack the capacity to clock the hardware components at very high speeds, required by some components to maintain them in an active condition, and lack other features which are desirable in circuit modeling systems.

Therefore, a need exists for an improved hardware modeling circuit system and method which is directed toward solving and minimizing these and other problems of prior art devices.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, a hardware modeling circuit system provides users at plural workstations with access to a hardware modeling circuit means on a shared basis. The hardware modeling circuit means includes means for applying test data to pins of one or more hardware modeling elements, such as integrated circuits, printed circuit boards and circuit subsystems. In addition, the hardware modeling circuit means includes means for retrieving resultant data generated from the hardware modeling elements during an evaluation. Optional timing analyzer means provides time analysis of outputs from pins of the hardware modeling elements under test and permits observation and evaluation of asynchronous signal behavior in the resultant data.

As a further feature of the present invention, clocking means are provided for generating high frequency device clocking signals for clocking hardware modeling elements at frequencies required to maintain such elements in an operational state. Moreover, the frequencies and other characteristics of these signals are variable. For example, the clocking frequencies can be varied as required to clock the hardware modeling elements from 12.2 kilohertz to 16.67 megahertz in twenty nanosecond increments.

As a further feature of the present invention, the hardware modeling circuit means includes means for employing software-generated phase clocks, as required for complex hardware modeling elements.

As a still further feature of the present invention, a tri-state sensing means and technique is employed for detecting high impedance states on the output pins of the hardware modeling elements.

As still another feature of the invention, the hardware modeling circuit means includes means for detecting bus collisions between the hardware modeling circuit means and the pins of the hardware modeling elements and for limiting the current at such connections to prevent device burnup or overheating.

In addition to permitting timing analysis of actual test results, the apparatus of the invention also permits timing evaluation from software file data which specifies the minimum, maximum and typical ranges of timing parameters for the hardware modeling device used in the modeling.

As still another feature of the present invention, the hardware modeling circuit means includes means for providing clocking and control signals to the integrated circuit or printed circuit board subsystem modeling elements as required, thereby synchronizing the operation of these hardware modeling elements with the hardware modeling circuit means.

As still another feature of the present invention, unique gating circuit means are employed to access the pins of hardware modeling elements, such gating circuit means incorporating one or more of the above features.

As a further aspect of the present invention, means are provided to automatically partition the system memory to facilitate use by a plurality of users.

Therefore, it is an overall object of the present invention to provide an improved hardware modeling circuit system, improved hardware modeling circuit means, and improved gating circuit means for utilizing hardware modeling elements in electrical circuit simulations.

These and other features, objects and advantages of the present invention will become apparent with reference to the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an overall block diagram of a hardware modeling circuit and system in accordance with the present invention;

FIG. 2 is a block diagram of the control circuit utilized in the hardware modeling circuit of the system of FIG. 1;

FIG. 3 is a timing example of a two vector data stream processed by the system of FIG. 1;

FIG. 4 is a schematic block diagram of plural gate arrays utilized in the integrated circuit interfaces of the hardware modeling circuit of FIG. 1;

FIG. 5 is a block diagram of a single integrated circuit interface gate array assembly;

FIG. 6 is a flow chart of a program employed by the microprocessor of the control circuit of FIG. 2 to initialize an integrated circuit interface for processing data for a simulation evaluation;

FIG. 7 is an electrical circuit schematic diagram of a portion of the integrated circuit interface of FIG. 1;

FIG. 8 is an electrical circuit schematic diagram of another portion of the integrated circuit interface of FIG. 1;

FIG. 9 is an electrical circuit schematic diagram of still another portion of the integrated circuit interface of FIG. 1;

FIG. 10 is an electrical circuit schematic diagram of a further portion of the integrated circuit interface of FIG. 1;

FIG. 11 is a block diagram of a single gate array circuit utilized to deliver signals to and receive signals from a single pin of a hardware modeling element;

FIG. 12 is an electrical circuit schematic diagram of a gate array circuit which accesses one pin of a hardware modeling element;

FIG. 13 is a timing diagram of signals applied to the gate array circuit of FIG. 12 when this circuit is coupled to a clock pin of a hardware modeling element (any pin of a hardware modeling element may be treated in this manner as a clock pin);

FIG. 14 is a timing diagram of signals applied to the gate array circuit of FIG. 12 during streaming of data from the operating memory of the hardware modeling circuit of FIG. 1 to the gate array circuit of FIG. 12 during evaluation;

FIG. 15 is a timing diagram of signals applied to the gate array circuit of FIG. 12 during reading of resultant data from the pin accessed by this gate array circuit;

FIG. 16 is an electrical circuit schematic diagram of the bus contention portion of the gate array circuit of FIG. 12;

FIGS. 17a through 17e are flow charts describing the operation of the network interface of the system of FIG. 1;

FIG. 18 is a timing example of a four vector transfer to a 64-pin or to a 128-pin hardware modeling element during an elevation by the system of FIG. 1;

FIG. 19 is a timing example of a two double-vector transfer to a 256-pin hardware modeling element during an evaluation by the system of FIG. 1.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

With reference to FIG. 1, the hardware modeling circuit system of the present invention includes a hardware modeling circuit means 10 which is interfaced by a computer network interface means 12 with plural electrical circuit simulation workstations 14 on a shared network basis. Hardware modeling circuit 10 is adapted to receive plural integrated circuit components, some of which are indicated schematically at 16, as well as printed circuit boards or circuit subsystems, as indicated schematically at 18. These integrated circuits, printed circuit boards and circuit subsystems are collectively and individually designated as "hardware modeling elements" or "HMEs." As explained below, these hardware modeling elements are accessed and used in simulating components in circuits being designed at the workstations 14.

In general, workstations 14 are designed to perform computer simulation of circuits being designed and evaluated at such stations. The workstations typically include software models of components of circuits being analyzed. Through the use of such software models, circuit design and evaluation is facilitated. Such workstations are presently being produced by companies such as Mentor Graphics Corporation, Daisy Systems and Valid Logic Systems.

As previously explained, there are limitations in the use of software models for circuits. To overcome these limitations, the present invention provides the workstations 14 with access to actual physical hardware modeling elements 16, 18 as required. The physical hardware modeling elements are thus used in circuit simulation in place of software models of such elements.

In general, when a workstation 14 recognizes that a circuit component used in a design or evaluation corresponds to one of the hardware modeling elements 16, 18 in the hardware modeling circuit 10, that element is accessed by the workstation through the network interface 12. Insofar as the user is concerned, software models and hardware modeling elements co-exist and are available for use in the simulation. Stimulus vectors, or input test data, generated at the workstation in the same manner as such vectors are generated for a software-evaluated model, are transmitted to the hardware modeling circuit 10 and corresponding stimuli signals are are applied to the appropriate pins of the corresponding hardware modeling element. The resultant output signals from the hardware modeling element 16, 18 are converted into corresponding resultant test data and returned from the hardware modeling circuit 10, via network interface 12, to the appropriate workstation 14 upon completion of an evaluation. Thus, the network interface 12 functions as a means for receiving input test data from a workstation and as a means for receiving the resultant test data from the hardware modeling circuit.

Plural workstations are coupled to the network interface 12, and thus to the hardware modeling circuit 10, by a commercially available local area network, such as the Domain.TM. network from Apollo Computers, Inc. Network interface 12 also comprises a computer, such as an Apollo Model No. DSP-80(A), programmed as shown in the flow charts of FIGS. 17a through 17e. Not only does network interface 12 permit sharing of a single hardware modeling circuit 10 by plural workstations 14, it also permits sharing of additional hardware modeling circuits 10 which may be coupled to the interface, as indicated schematically by lines 22. In this manner, a substantial library of hardware modeling elements 16 and 18 are available, with each workstation having shared access to all of the hardware elements in the library. Duplicate hardware modeling elements 16, 18 are thus not needed in the hardware modeling circuits 10 because each of the workstations has access to all of the hardware modeling elements in the system.

The hardware modeling circuit 10 includes a control circuit 24, a user memory 26, an operating memory 28 and plural integrated circuit interfaces 30, which support the integrated circuit hardware modeling elements 16. User memory 26 may be augmented by additional memory such as an optional virtual disk file 27. In addition, an input/output port 32, which may be similar to the integrated circuit interfaces 30, is provided for coupling the hardware modeling circuit 10 to printed circuit boards and subsystems 18 when such elements are used in modeling. A timing analyzer 34 is also provided for performing timed analysis on resultant data generated from the hardware modeling elements during an evaluation. The control circuit 24, and thus the hardware modeling circuit 10, is connected to the network interface 12 by a coupler 36. One suitable coupler is a Multi-Channel.TM. coupler, such as a Multi-Bus.TM. circuit board Model 53C (Single Board Computer)-589, available from Intel Corporation. The interconnection of these components of the hardware modeling circuit 10 and their general functions will next be described.

As explained in greater detail below in connection with FIG. 2, the control circuit 24 is a microprocessor based circuit that performs a variety of functions. The control circuit generates the various clocking signals required for a circuit simulation; establishes the proper data flow paths through the various blocks of the hardware modeling circuit 10; starts and stops the application of stimulus data to the various hardware modeling elements and determines whether timing analysis is to be performed by the timing memory circuit 34; monitors the commands from a software server run on the network interface computer 12; and sets up and initializes direct memory access (DMA) transfers of data from the user memory 26 to the operating memory 28. Thus, the control circuit 24 coordinates the data movement between the various components of the hardware modeling circuit 10.

More specifically, the components of the hardware modeling circuit are interconnected as follows. A sixteen bit bidirectional data bus (SYS.sub.13 DAT) 38 interconnects the control circuit 24, the integrated circuit interfaces 30, the input/output port 32 and the timing analyzer 34. A twenty-four bit address bus (SYS.sub.-- ADD) 40 and a system control bus (SYS.sub.-- CTRL) 42 also interconnect these same elements. In addition, a STREAM CLOCKS bus 44 interconnects each of these elements except the user memory 26. A STREAMING ADDRESS bus 48 couples the control circuit to the operating memory 28. A two hundred fifty-six bit vector data (VEC.sub.-- DAT) bus 50 interconnects the user memory 26 to the operating memory 28, to integrated circuit interfaces 30 and to input/output port 32. Finally, a sixty-four bit unidirectional timing (TIM) bus 52 couples the integrated circuit interfaces 30 and input/output port 32 to the timing analyzer 34.

In general, data (i.e. stimulus data from a user's workstation 14 which is to be applied to a particular hardware modeling element 16, 18), as well as address and other information, is loaded into user memory 26. Server software in network interface 12 partitions the user memory 26 for reception of data from a user. This software also manages the virtual user memory disk file 27 discussed below. User memory 26 typically is from one to eight megabytes of dynamic MOS RAM. This memory is relatively slow, but is not used in applying stimulus vector data to the hardware modeling elements 16, 18. Instead, this memory temporarily stores data from one or more users prior to delivery of one user's data to the operating memory 28. The operating memory 28 and user memory 26 are independently operable such that data for simulation experiments from one or more users may be loaded into the user memory 26 while data vectors for one user's evaluation are being applied from the operating memory 28 to the selected hardware modeling element 16, 18.

Following the completion of a user's evaluation or experiment, information pertaining to the next user's evaluation is transferred from user memory 26 to the operating memory 28 under the direction of control circuit 24. Operating memory 28
provides storage of stimulation vectors for an evaluation by one user immediately before these vectors are transferred to a desired hardware modeling element 16, 18 for a simulation evaluation cycle.

The operating memory 28 comprises a high-speed static RAM memory. During an evaluation cycle, vector data stored in operating memory 28 is clocked by the STREAM CLOCKS 44 to the selected hardware modeling element 16, 18. As explained below, this clocking rate is variable to fit the requirements of the particular hardware modeling element being used in the evaluation. Moreover, in the illustrated embodiment of the present invention, a clocking rate of up to 16.67 megahertz is provided so that high speed hardware modeling elements can be clocked fast enough to maintain them in an operational state. Operating memory 28 typically comprises either two parallel circuit boards (each 16k by 128), for a total storage of 16k by 256, or alternatively two sets of such boards, for a total storage of 32k by 256. In the former case, the operating memory 28 is capable of storing 32k vectors (each vector being two hundred fifty-six bits) for each pin of a 64 pin device; 16k vectors for each pin of a 128 pin device; or 8k vectors for a 256 pin device. The above storage is doubled in the case where two sets of operating memory boards are utilized. Thus, the operating memory 28 is expandable to accommodate a large number of stimulus vectors for any one hardware modeling element 16, 18.

To conserve storage, as the pin count of a hardware modeling element exceeds 128, data is loaded into successive word block positions in the operating memory 28 and successively applied to a hardware modeling element 16, 18 under test. The resultant data from the hardware modeling element is then multiplexed and time aligned.

The data from the operating memory 28 is clocked to the appropriate hardware modeling element 16, 18 in response to a signal on the STREAM CLOCKS bus 44. That is, in response to the clock signal, data from the operating memory 28 is clocked into input registers of the appropriate integrated circuit interface 30 via the vector data (VEC.sub.-- DAT) bus 50. Address information is provided along STREAMING ADDRESS bus 48 for the data stored in the operating memory 28.

For each pin of the hardware modeling element, the VEC.sub.-- DAT bus 50 carries two bits of information. One is a control bit that indicates whether the hardware modeling system is to drive the pin or receive data from it. The other bit is a data bit. Consequently, VEC.sub.-- DAT bus 50 carries twice as many bits of data as there are pins in the hardware modeling element. Since VEC.sub.-- DAT bus is only 256 bits wide, it can normally only support a 128-pin device. Two support a 256-pin device, as explained below, two consecutive transfers to an ICIF 30, or to the Input-port 32, are made in the VEC.sub.-- DAT bus. The ICI.sub.-- CLK1 and ICI.sub.-- CLK2 busses are used for this purpose. The ICI.sub.-- CLK1 clocks the first 256 bits across the VEC.sub.-- DAT bus, while the ICI.sub.-- CLK2 clocks the second 256 bits. After all data has been transferred, the master clock, MAS.sub.-- CLK, then passes all of these data and control bits to the pins of the hardware modeling elements 16,
18 mounted to the ICIF or the input-output port.

Following an explanation, in response to a read signal on system control (SYS.sub.-- CTRL) bus 42, resultant data is transferred from IC interface board sample registers to the system data (SYS.sub.-- DAT) bus 38 when timing analysis is not used, or from the timing analyzer 34 when timing analysis is used. From the system data bus 38, the resultant information is fed to the user's workstation 14.

In a situation in which timing analysis is employed, a control signal on system control bus 42 enables the timing analysis portions of the hardware modeling circuit 10, as explained below. In general, during timing analysis, desired pins of the hardware modeling element 16, 18 are sampled at a periodic rate, for example at a 100 megahertz sampling rate. The sampled data from these pins permits a user to observe timing behavior, such as asynchronous behavior of a hardware modeling element. This provides a more accurate representation of the modeling element's timing characteristics.

An individual hardware modeling element has its own timing characteristics and does not model the range of minimum to maximum timing characteristics applicable to other elements of the same type. Where such information is needed, instead of, or in addition to, utilizing timing analysis, timing information can be software generated in the same manner as presently employed in existing software modeling systems. That is, timing data pertaining to a particular hardware modeling element 16, 18 may be stored in a software file that can be accessed by the workstation 14. For example, this timing data may comprise minimum, typical and maximum response times for the hardware modeling element 16, 18. Timing information can be computed from this data.

With reference to FIGS. 1, 2, 3 and 6, the control circuit 24 will be described in greater detail. In general, the control circuit includes a clock circuit portion 56, described in greater detail in the Clock Circuit description below, for generating the clocking signals on STREAM CLOCKS bus 44. These signals are indicated in FIG. 2 and defined below. More specifically, clock circuit 56 includes a clock parameter register 58, a high frequency clock generator 60, a reference clock generator 62, a device clock generator 64, a streaming control clock sequencer 66 and a streaming clock time alignment circuit 68. When establishing an evaluation, a user at a workstation 14 can select the desired clocking waveform type, clocking frequency and duty cycle. This information is fed to the clock parameter register 58, which in turn causes the reference clock generator 62 and the device clock generator 64 to produce device clocking signals for the hardware modeling elements 16, 18, corresponding to these parameters.

In the illustrated embodiment, the waveform generators 62 and 64 are used to create all clock signals for a hardware modeling element 16, 18. Typically, these waveforms include non return to zero signals, return to zero signals and return to one clocking signals. Moreoever, the clocking frequencies are controllable by the user from, in the preferred embodiment, 12.2 kilohertz (81.94 microseconds) to 16.67 megahertz (60 nanoseconds), in 20 nanosecond increments. In generating the required clocking signals, the high frequency clock generator 60 produces clocking signals at the maximum signal frequency rate, which in turn control and synchronize the reference clock generator 62 and device clock generator 64. Streaming control clock sequencer 66 and streaming clock time alignment circuit 68 sequence the clocking signals at the appropriate times to produce the required clocking signals for the hardware modeling circuit 10.

In addition to a clock circuit 56, control circuit 24 includes a microprocessor 70, such as an Intel 80186 microprocessor, which executes a software program stored in a local memory and program store 72. The programming of the microprocessor 70
will be apparent with reference to the description below and from the flow chart of FIG. 6. The control circuit 24 also includes an access and DMA control 74 for controlling the transfer of information to and from the user and operating memories 26, 28
and the network interface 12. A streaming address circuit 76 is provided for delivering address information to the operating memory 28 on streaming address bus 48. Microprocessor 70, local memory and program store 72, access and DMA control 74, and streaming address circuit 76 are interconnected by a SYSTEM BUS 77 which provides the system data, system address and system control outputs on busses 38, 40 and 42.

When the simulation software running on a workstation 14 needs to evaluate a hardware modeling element 16, 18, it passes a request to the server software running on the network interface computer 12. If this is the first request for a simulation, the server will examine its map of user memory 26 to allocate four areas of storage: (1) task control block; (2) vector data block; (3) linked-list; and (4) results area. The purpose of these four areas of storage is individually detailed below.

The task control block embodies setup and run-time configuration information for a simulation experiment. The following information is provided in a task control block: Address of the hardware modeling element 16, 18 on which the evaluation is to be performed (IC interface board number and the socket number on that interface board where the hardware modeling element is installed); clocking information (clock period, data/clock setup time, clock duty cycle); a flag to determine whether timing analysis is to be used; an address pointer to the location in which the results of the evaluation are to be placed; the transaction code to be returned in the results queue upon completion of the task; a list of clock, open-collector, tri-state, and input/output pins for the hardware modeling element; the number and location of unknowns; and an address pointer to the vector data linked-list.

The vector data block contains the stimulus data for the hardware modeling element 16, 18. This block expands with each new evaluation cycle. The newest vector is appended to the end of any existing vectors.

The linked-list contains linkage information for discontiguous blocks of vector data. As a simulation evolves over time, the size of the vector data block grows. The server software may need to break up the data block into two or more discontiguous pieces to fit it into available memory space. Being able to break the large block into several smaller ones facilitates operation of the hardware modeling system 10 during multiple, concurrent simulations. The linked-list provides a mechanism for the server software and control circuitry to maintain continuity between the discontiguous blocks. Each element in the linked-list contains three pieces of information pertaining to one data block: (1) size of the block (byte count); (2) address pointer to the location in user memory 26 of the block; and (3) address pointer to the next element in the linked-list. The linked-list block may potentially cause the same problem as the vector data block. That is, it may grow to be so large that it must be broken in two or more pieces for it to fit into available memory space. The address pointer to the next linked-list element provides a means by which the elements of the linked-list may be chained together.

Finally, the results area is provided for storage of the results data generated by the evaluation cycle. The control circuit 24 deposits the data in the results area and the server software recovers it.

In general, when the simulation software running on the workstation 14 requires an evaluation of a hardware modeling element 16, 18, it passes the request to the server software running on the network interface computer 12. The server builds a task control block, passes it to user memory 26 and deposits an address pointer to the task control block into a command queue in user memory.

Control circuit 24 continuously scans the command queue. When it sees any non-zero value, it assumes the value to be a valid address pointer to a task control block. The control circuit 24 decodes the information in the control block and performs the appropriate setup of the clock circuit 56, streaming address circuit 76, and IC interface 30 or input/output port 32.

The control circuit 24 reads the linked-list and uses the address pointers and block size information to locate each of the vector data blocks and to DMA transfer them one at a time from user memory 26 into operating memory 28. The control circuit employs the access and DMA control circuits 74 to perform the transfer operations. The first block for any given evaluation is loaded into operating memory 28 starting at address zero. Any additional blocks for the same evaluation are successively appended to the end of previously transferred blocks and thereby assembled into a contiguous block. Any "unknown" in the vector data are treated as a logical one or zero, as selected by the user.

Once all the vectors have been placed in the proper order in operating memory 28 and the total number of vectors has been determined, the control circuit 24 sets a "go" bit in a control register that starts the autonomous clock circuit 56 (The use of this "go" bit is shown in the STREAM-GO lines of FIGS. 18, 19). The clock circuit generates the control clocks that move the data from operating memory 28 to the hardware modeling element 16, 18 through the IC interface board 30 or through the input/output port 32. This is clarified with reference to the description of the control clocks below and with reference to the timing diagram of FIG. 3. Once an evaluation has been started, the control circuit 24 waits for a "finished" flag from a vector counter 75 to go true. When the "finished" flag is true, the entire vector stream for the evaluation has been applied from operating memory 28 to the appropriate hardware modeling element 16, 18. Vector counter 75 counts the number of stimulus vectors remaining to be clocked to the hardware modeling element. The "finished" flag goes true when the vector counter reaches zero. (FIGS. 18 and 19 show the use of the signal from vector counter 75).

Because each simulation evaluation contains only one new vector, the last one in the entire vector stream, the only response from the hardware modeling element 16, 18 that is of interest is the response to the last vector applied. This response can be recorded in the form of a single response vector if timing analysis is not used. Alternately, the response is recorded as many successive high speed samples made by the timing analysis circuit 34.

If timing analysis is not used, the results of the evaluation are recovered from sample registers in the gate arrays, explained below, located on the IC interface board 30 or the input/output port 32. If timing analysis is used, the results of the evaluation are recovered from the memory of timing analysis circuit 34 and transferred to the results area in user memory 26 specified by the results address pointer in the task control block.

The control circuit 24 then zeros the entry in the command queue and writes the transaction number obtained from the task control block into the results queue. This signifies the completion of the task for the hardware modeling control circuit
24.

While any task is awaiting completion by the control circuit 24, the server software continuously scans the results queue. When it sees any non-zero value, it assumes the value to be a valid transaction number. Since the server software originally assigned the transaction number to the evaluation task, it can use the number to determine the proper address in user memory 26 to obtain the results. The server software retrieves the results from user memory 26 through the Multibus adapter
36 and passes them to the simulation software running on the workstation 14.

This completes one evaluation cycle of a hardware modeling element 16, 18.

Virtual Memory Management

The memory manager is a part of the server software that runs on the network interface computer 12. It controls the allocation of storage space within user memory 26. At the bottom of user RAM is a fixed length block of memory used for message passing between the server and the hardware modeling system firmware. This area is not under the control of the memory manager. All the remaining user RAM is used for vector data, task control blocks, linked-lists, and results areas. The memory manager controls this area of memory.

The memory manager does not differentiate between memory allocation for any particular function. The "free list" is a link data structure. Each element of the list represents a block of memory (256 bytes). All allocations are from the "free list" and all deallocations are to the "free list." There is a similar structure for maintenance of the virtual disk file 27. This latter file is optional and used to store vector data in excess of user RAM as explained below.

Each record for each hardware modeling element 16, 18 contains two indicators. The first indicator indicates whether data for the hardware modeling element currently resides totally in user RAM (in.sub.-- memory). The second indicator indicates if an evaluation of that hardware modeling element is currently in process (in.sub.-- que). The in.sub.-- memory indicator is maintained by the memory manager. The in.sub.-- que indicator is maintained by the server and is used to determine if the data for the hardware modeling element can be safely swapped between user RAM 26 and the virtual desk file 27.

Under conditions of heavy use or limited user memory 26, there may be a shortage of space in user RAM. This occurs any time the total space taken by hardware modeling element data and system overhead exceeds the current amount of user memory 26
in the hardware modeling system. Should this happen, all of the vector data associated with one hardware modeling element 16, 18 will be swapped to the virtual disk file 27. That is, all vector data pertinent to that hardware modeling element is transferred to the network interface computer 12 and subsequently written to a file on a disk memory for storage. Once the data is transferred, all user RAM allocated to store that data is returned to the "free list" for reallocation.

The choice of which hardware modeling element data to swap is made by first checking for a hardware modeling element 16, 18 whose vector data has already been swapped. If none are found, then the hardware modeling element that was least recently used is choosen. If hardware modeling element is being evaluated, or has an evaluation pending (as a function of a command in the command que (in.sub.-- que)), it will not be swapped. If no hardware modeling element data can be found to swap, the current command being processed will be halted until a swappable set of data is found, or until user memory is freed for some other reason, such as by returning results upon the completion of an evaluation.

The disk file 27 used to store hardware modeling element vector data is a temporary file partitioned into 2 kbyte segments. These segments are managed in much the same way that user RAM blocks are managed. When the vectors of a swapped hardware modeling element are copied back into the hardware modeling system 10, the disk image is maintained until the channel associated with it is closed. By saving these vectors on disk, if another swap is needed, only those vectors generated after the last swap need be transferred.

When the data associated with a hardware modeling element 16, 18 is not in user RAM (as indicated by the in.sub.-- memory flag), it must be reloaded and rebuilt. The first step is to copy all vector data from the disk file 27 to a buffer in the server. Second, the server is instructed to reset the hardware modeling element. Third, the buffer is passed to the server and the server is instructed to rebuild the data blocks for the hardware modeling element. Finally the evaluation sequence is resumed.

Clock Circuit Description

With reference to FIGS. 1 and 2, the clock circuit 56 is that part of the control circuit 24 responsible for moving the hardware modeling element stimulus from operating memory 28 to the IC interface 30 or input/output port 32, and for capturing any resultant response. The clock circuit is connected to the IC interface 30, the input/output port 32, the operating memory 28 and the timing analyzer and memory 34 by means of the STREAM CLOCKS bus 44.

Additionally, the clock circuit 56 provides high frequency device clocking signals for clocking hardware modeling element devices at frequencies required to maintain such devices in a functional state. Clock circuit 56 also provides the means to supply software generated phase clocks at software variable rates of from 12.2 KHz (81.940 microseconds) to 16.67 MHz (60 nanoseconds) in 20 nanosecond increments. Other suitable clocking rates may also be provided as needed.

Clocking signals are applied directly to integrated circuit modeling element 16 through the appropriate I.C. pins. Some printed circuit boards or circuit subsystems 18, however, have their own on-board oscillator circuits to generate system clocks. These devices are synchronized with the hardware modeling circuit system by disabling the on-board clocks and using instead the software generated clocks provided by the present invention.

The clock circuit 56 includes a clock parameter register 58, high frequency clock generator 60, reference clock generator 62, device clock generator 64, streaming control clock sequencer 66 and streaming clock time alignment circuit 68. Eight clocks are produced by clock circuit 56 for IC interface 30, input/output port 32, operating memory 28, and timing analyzer and memory 34 (if used). These clocks are as follows:

1. DEV.sub.-- CLK provides means to supply a programmable hardware modeling element clock. This clock provides the signal that actually toggles the clock-pin(s) of the hardware modeling element being modeled.

2. MAS.sub.-- CLK provides means to time align stimulus from operating memory. This clock is used to present the stimulus from the operating memory to the hardware modeling element 16, 18.

3. ICI.sub.-- CLK1 provides means to time align stimulus from operating memory. This clock is discussed above with reference to the VEC.sub.-- DAT bus 50.

4. ICI.sub.-- CLK2 provides means to time align stimulus from operating memory. This clock is also discussed above with reference to the VEC.sub.-- DAT bus 50.

5. SAM.sub.-- CLK provides means to capture hardware modeling element stimulus response information. This clock provides signals after all stimuli have been applied to the hardware modeling element and controls the underwriting of the resultant hardware modeling element response.

6. OM.sub.-- CLK provides means to move stimulus from operating memory. One stimulus vector is applied to the hardware modeling element for each OM.sub.-- CLU pulse.

7. CLK25PH0 provides means to analyze timing of hardware modeling element components at the timing analyzed and memory circuit This clock provides signals used by the timing analyzer and memory circuit 34 to evaluate propagation delays among pins of the hardware modeling element with better granularity than would otherwise be available.

8. CLK25PH1 also provides means to analyze timing of hardware modeling element components at the timing analyzer and memory circuit. This clock is used in conjunction with CLU25PH0 above.

High Frequency Clock Generator

The high frequency clock generator 60 provides the fundamental operating frequency signals for the hardware modeling circuit system 10. To achieve a high degree of accuracy and provide required programmability of the device clocks, a 100
megahertz crystal oscillator is used. This provides 10 nanosecond timing states for the hardware modeling circuit system.

Additionally, the high frequency clock generator 60 provides two 25 megahertz timing memory clocks (CLK25PH0 and CLK25PH1), phase shifted 90 degrees, for the timing analyzer and memory 34. Clock generator 60 also provides a microprocessor clock on a line 71 for the control circuit microprocessor 70.

Clock Parameter Registers

The clock parameter registers 58 provide the means for programming the fundamental device frequency, duty cycle and time alignment parameters. There are four clock parameter registers as follows:

1. REF.sub.-- CLK frequency register.

2. DEV.sub.-- CLK setup delay register.

3. DEV.sub.-- CLK hold delay register.

4. Time Alignment register.

REF.sub.-- CLK frequency register

The REF.sub.-- CLK frequency register provides a programmable means for supplying variable frequencies to hardware modeling elements 16, 18 as required by these elements to maintain them in a functional state.

Loading of this register is accomplished with the microprocessor 70 supplying the register's address and data collected and calculated from the task control block in user memory 26. In the exemplary embodiment, the allowable frequency register values are one (1) through 4095 inclusive. A value of zero is not permitted.

Each increment of the frequency register value increases the REF.sub.-- CLK period by 20 nanoseconds. For example, a one (1) written to this register specifies to the reference clock generator 62 a device clocking period of 60 nanoseconds. A value of 4095 specifies a device clocking period of 81.94 microseconds.

DEV.sub.-- CLK setup delay register

The DEV.sub.-- CLK setup delay register provides a means for supplying variable device setup times to hardware modeling elements 16, 18 as required by these elements to maintain them properly stimulated. The DEV.sub.-- CLK setup delay register affects only DEV.sub.-- CLK generation.

Setup times are provided by varying the DEV.sub.-- CLK leading edge while holding the operating memory 28 stimulus application point, MAS.sub.-- CLK, fixed in time.

Each increment of the value in the setup register specifies the number of 10 nanosecond delay periods that will elapse from the positive going edge of a MAS.sub.-- CLK pulse before the occurrence of the positive edge of DEV.sub.-- CLK signals. This programmable delay is illustrated by several possible positions of the DEV.sub.-- CLK pulses relative to the MAS.sub.-- CLK pulses as shown in FIG. 3. Values for this register's contents must be less than the value of the hold delay register. In this specific illustrated embodiment, acceptable values are from one (1) to 4095 inclusive. A value of zero is not permitted.

DEV.sub.-- CLK hold delay register

The DEV.sub.-- CLK hold delay register provides a programmable means for supplying variable device hold times to hardware modeling elements 16, 18 as required by these elements to maintain them properly stimulated. The DEV.sub.-- CLK hold delay register affects only DEV.sub.-- CLK generation.

Hold times are provided by varying the DEV.sub.-- CLK trailing edge while holding the operating memory 28 stimulus application point, MAS.sub.-- CLK, fixed in time. This is also shown in FIG. 3.

Each increment of data in the hold register specifies the number of 10 nanosecond delay periods that will elapse before the deassertion of DEV.sub.-- CLK. Values for this register's contents must be greater than the value of the setup delay register since DEV.sub.-- CLK is not asserted until the setup delay period has elapsed. In the illustrated embodiment, acceptable values are from one (1) to 4095 inclusive. A value of zero is not permitted.

Time Alignment Register

The time alignment register provides a programmable means of compensating for standard component tolerances, for allowing variable amounts of settling time for device response capture, and for providing increased resolution and accuracy during timing analysis.

The time alignment register holds three fields of three bits each for providing the means to add delays to four of the eight streaming clocks, namely: OM.sub.-- CLK, SAM.sub.-- CLK and the two timing memory clocks CLK25PH0 and CLK25PH1. The three fields of programmable delay are listed below:

1. OM.sub.-- CLK delay.

2. Timing memory clocks delay.

3. SAM.sub.-- CLK delay.

For the case of OM.sub.-- CLK delay, the three bit field specifies increments of two nanoseconds for values from zero to seven. This provides a maximum delay of fourteen nanoseconds of the OM.sub.-- CLK with respect to MAS.sub.-- CLK, ICI.sub.-- CLK1 and ICI.sub.-- CLK2.

For the case of timing memory clocks delay, the three bit field specifies increments of two nanoseconds for values from zero to seven. This also provides a maximum delay of fourteen nanoseconds of the timing memory clocks with respect to MAS.sub.-- CLK, ICI.sub.-- CLK1 and ICI.sub.-- CLK2.

For the case of SAM.sub.-- CLK delay, the three bit field specifies increments of fifty nanoseconds for values from zero to seven. This provides a maximum delay of 350 nanoseconds of the SAM.sub.-- CLK with respect to MAS.sub.-- CLK, ICI.sub.-- CLK1 and ICI.sub.-- CLK2.

Reference Clock Generator

The reference clock generator 62 provides a means for generating fundamental operating frequency clock signals for the hardware modeling elements 16, 18. The generator produces a pulse train which specifies the operating frequency for the element at the streaming control clock sequencer 66 and device clock generator 64. Input for the reference clock generator is taken from the clock parameter registers 58 (namely, from a REF.sub.-- CLK frequency register).

The reference clock generator 62 is a twelve bit counter that decrements each ten nanosecond period until zero is reached. At this time, the counter is reloaded and the counting repeated. The reloading of the counter thus provides the programmable means for providing variable frequencies.

Device Clock Generator

The device clock generator 64 provides a means for generating the hardware modeling element setup and hold time signals. The generator produces a variable duty cycle output, at the reference clock generator frequency, from the contents of the clock parameter registers 58 (namely, from a DEV.sub.-- CLK setup delay register and a DEV.sub.-- CLK hold delay register).

The device clock generator 64 comprises a pair of twelve bit counters that decrement each ten nanosecond period after the start of each reference clock period. The setup delay passes first, delaying the leading edge of DEV.sub.-- CLK behind the reference clock. This is followed by the hold delay count, delaying the falling edge of DEV.sub.-- CLK. Both setup and hold delay counts expire within the reference clock generator period. This provides a means for varying the edge placement of the DEV.sub.-- CLK signals clock with reference to the stimulus being delivered to the device (See FIG. 3).

Streaming Control Clock Sequencer

The streaming control clock sequencer 66 comprises a means for moving the hardware modelling element stimulus from operating memory 28 to the IC interface circuit 30 and to the input/output port 32. In addition, sequencer 66 provides a means to enable the timing analysis to function and to provide for starting and stopping the streaming clocks.

The streaming control clock sequencer 66 generates the following streaming clocks:

1. OM.sub.-- CLK.

2. ICI.sub.-- CLK1.

3. ICI.sub.-- CLK2.

4. MAS.sub.-- CLK.

5. SAM.sub.-- CLK.

The specific sequence of the streaming clocks is affected by the hardware modeling element IC interface board type. The sequence is adjusted to perform the required time demultiplexing of stimulus packed in operating memory. This unpacking and alignment is accomplished with OM.sub.-- CLK, ICI.sub.-- CLK1, ICI.sub.-- CLK2 and MAS.sub.-- CLK.

IC interface boards 30 for hardware modeling elements having 64 and 128 pins may receive their stimulus at any one instant on the VEC.sub.-- DAT bus, since that bus is 256 bits wide. FIG. 18 shows an exemplary 64/128 pin four vector transfer. The REF.sub.-- CLK signal in FIG. 18 is the internal clock circuit signal, generated by reference clock generator 62, which drives the streaming clock sequencer circuit 66. STREAM.sub.-- GO is the assertion of the "go" bit, referenced in the discussion of the control circuit above, which starts the clock circuit 56. The vector counter signal is the signal from vector counter 75 which indicates the number of vectors that still need to be transferred from the operating memory 28. Vector counter 75 is decremented with each OM.sub.-- CLK pulse. When the vector counter signal reaches zero, the "finished" flag, described above in connection with the control circuit is set and the simulation is ended.

Operation of the interface board 30 for hardware modeling elements with more than 128 pins is somewhat more complex. In the case of a 256 pin device, the 512 bits of stimulus are supplied with two transfers on the VEC.sub.-- DAT bus. Therefore, two transfers are performed on VEC.sub.-- DAT using OM.sub.-- CLK for both. ICI.sub.-- CLK1 captures the first vector, ICI.sub.-- CLK2 captures the second and MAS.sub.-- CLK simultaneously applies the stimulus to the hardware modeling element device. See FIG. 19 for a 256 pin format four vector (two double vector) transfer.

The streaming control clock sequencer 66 also provides means for pipelining the stimulus. The pipes are required to provide the extremely short stimulus period of 60 nanoseconds. When moving stimulus from operating memory 28 to the hardware modeling element, a minimum of three pipe stages exist. They are:

1. Pass vector address to operating memory.

2. RAM access of the stimulus vector.

3. Pass vector stimulus data to IC interface circuit.

All three stages are totally overlapped to provide the minimum vector cycle time (60 nanoseconds).

In addition to providing stimulus movement control, the streaming control clock sequencer 66 also provides the stimulus response capture pulse SAM.sub.-- CLK. This timing pulse is generated after the application of all stimulus to the device.

The control clock sequencer 66 also provides start and stop information to timing analyzer and memory 34 for enabling its analysis of hardware modeling element timing behavior. This start and stop information is provided through an enable timing analysis line (not shown) connecting sequencer 66 and timing analyzer and memory 34.

Streaming Clock Time Alignment Circuit

Streaming clock time alignment circuit 68 provides a means for compensating for standard component tolerances, allowing variable amounts of settling time for device response capture, and for providing increased resolution and accuracy during timing analysis.

Time alignment is provided for four of the eight stream clocks described above: OM.sub.-- CLK, SAM.sub.-- CLK, CLK25PH0 and CLK25PH1.

For the case of component tolerance, operating memory clock (OM.sub.-- CLK) is aligned by adding delay with respect to the capturing of stimulus at the gate array (described below). Differences in component propagation time, from the operating memory board 28, to a gate array output register, can be compensated from system to system. Compensation insures reliability and system performance.

For the case of device settling time, sample clock (SAM.sub.-- CLK) is aligned by adding delay with respect to the last applied stimulus to the device. Doing so allows variable amounts of time, as required, for the device to drive or release its outputs. This process guarantees that hardware modeling element capacitive effects will not corrupt logical state readings.

For the case of timing analysis resolution and accuracy, timing memory clocks (CLK25PH0 and CLK25PH1) are delayed synchronously with respect to MAS.sub.-- CLK, ICI.sub.-- CLK1 and ICI.sub.-- CLK2. Doing so enables calculation or measurement of wavefront propagation delays among pins of the hardware modeling element device with better granularity than available at the operating frequency of control circuit 24. In addition, this provides a means for determining the delay added by a hardware modeling element.

Access and DMA Control

The Access and Direct Memory Access (DMA) control circuit 74 provides the control circuit 24 with a means for passing message and data between workstation 14 and user memory 26. In addition, it provides a means for directly transferring hardware modeling element stimulus between user memory 26 and operating memory 28.

The Access and DMA control