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United States Patent
4434459
Holland , ; et al.
February 28, 1984
Title
Data processing system having instruction responsive apparatus for both a basic and an extended instruction set
Abstract
A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The instruction responsive apparatus thereof responds to unique microinstructions which, for example, provide for the selection of one of a plurality of interrupt routines each corresponding to an interrupt request from a different external device, provide for the sequential loading of a plurality of segment identification registers each pointing to selected memory management tables associated with a segment storage region of main memory, provide for a program counter relative jump operation, provide for zero-extending or sign-extending 16-bit words to 32-bit words having the same value, and provide for the multiplication of the lower 16 bits of two 32-bit accumulators and the sign-extension of the 16-bit result to form a 32-bit word.
Inventors:
Holland; Charles J.
(Northboro,
MA
)
, Wallach; Steven
(Framingham,
MA
)
, Alsing; Carl J.
(Hopkington,
MA
)
Assignee:
Data General Corporation
(Westboro,
MA
)
Appl. No.:
143982
Filed:
April 25, 1980
Current U.S. Class:
712/210
Field of Search:
364/2MSFile,9MSFile
U.S. Patent Documents
3168723
February 1965
Foin et al.
4025904
May 1977
Adney et al.
4060849
November 1977
Bienvenu et al.
4090237
May 1978
Dimmick
4181933
January 1980
Benysek
Primary Examiner:
Zache; Raulfe B.
Attorney, Agent or Firm:
O'Connell; Robert F.
Claims
What is claimed is:
1. A data processing system having a processor unit which includes means for supplying instructions and a main memory containing a plurality of segment storage regions, said system including
a plurality of segment identification registers each associated with one of said segment storage regions and capable of storing a 32-bit double word which points to a memory management table related to said region, said segment identification registers being located externally of said main memory;
accumulator storage means for storing a starting address of a block of double words stored in main memory;
instruction decode means connected to said instruction supplying means and responsive to an instruction therefrom requiring the storage of said block of data words into said segment identification registers for providing selected control signals;
means connected to said instruction decode means, to said accumulator storage means, to said main memory and to said segment identification registers and responsive to said selected control signals for accessing the first word of said block of double words at said starting address in said main memory and for loading the double words in said block into said plurality of memory management registers, said double words being loaded sequentially into said registers in a preselected order.
2. A data processing system having a main memory containing a plurality of segment storage regions, said system including
an instruction processor unit comprising
a program counter register, said program counter register containing a 32-bit double word representing the current program count in a sequence of instruction operations being performed by said data processing system;
instruction decode means responsive to an instruction occurring in said sequence of instruction operations for requiring a program counter relative jump operation, said decode means providing a plurality of decoded bits, a selected number of which form a displacement value; and
means connected to said instruction decode means and to said program counter register for adding said displacement bits to the current double word in said program counter register and for placing the result into only the lower portion of said program counter register so that the result provides a reference to a specified location only in the currently used segment storage region of said main memory which is displaced relative to the location specified by the current program count.
3. A data processing system for handling first data words having thirty-two bits and second data words having sixteen bits;
a plurality of accumulator storage means capable of storing said first or said second data words;
means connected to said accumulator storage means and responsive to a second data word in a source accumulator storage means of said plurality of accumulator storage means for extending the number of bits thereof so that said extended second data word has thirty-two bits, said extended second data word having the same value as said second data word prior to its extension and being capable of storage in a destination accumulator storage means of said plurality of accumulator storage means;
instruction decode means responsive to an instruction requiring the extending of a second data word for providing first selected bits of an instruction word for identifying said source accumulator storage means and second selected bits of an instruction word for identifying said destination accumulator storage means and for providing control signals; and
means connected to said instruction decode means and responsive to said control signals for extending said second data word and for storing said extended second data word in said destination accumulator storage means.
4. A data processing system in accordance with claim 3 wherein said extending means includes means for zero-extending said second data word.
5. A data processing system in accordance with claim 4 wherein said extending means includes means for sign-extending said second data word.
6. A data processing system having means for supplying instructions and comprising
a destination accumulator storage means capable of storing thirty-two bits of which only a first word having sixteen bits is required for an arithmetic operation;
a source accumulator storage means capable of storing thirty-two bits of which only a second word having sixteen bits is required for said arithmetic operation;
instruction decode means connected to said instruction supplying means and to said destination and source accumulator storage means and responsive to an instruction requiring multiplication of said first and second words for providing control signals for multiplying the sixteen lower bits of said destination accumulator storage means and the sixteen lower bits of said source accumulator storage means to produce a result having sixteen bits, for sign-extending said result to form a double word having thirty-two bits, and storing said sign extended double word in said destination accumulator storage means without changing the contents of said source accumulator storage means.
7. A data processing system capable of use with one or more external devices, said system comprising memory means including
a first storage region containing a plurality of instruction routines, each routine for performing one of a plurality of selectable interrupt operations;
a second storage region containing a plurality of device control tables, each said table being associated with one of said external devices and including an interrupt routine address pointing to a selected one of said interrupt routines in said first storage region;
a third storage region containing a plurality of device control table addresses each of said addresses being associated with one of said external devices and pointing to a selected one of said device control tables in said second storage region;
a fourth storage region having a first selected location capable of storing information defining an instruction for transferring control of said system to a desired one of said plurality of interrupt routines associated with an external device and a second selected location containing an address pointing to a selected location in said third storage region;
means connected to said external device and to said memory means and responsive to an interrupt request from an external device for examining the first selected location of said fourth storage region to determine whether or not the information defining said transfer instruction is present therein and for supplying the address in said second selected location where said information is present and
means connected to said external device and to said memory means and responsive to coded information from said external device requesting said interrupt for providing to said third storage region an address offset from said selected location in said third storage region, the address at said offset location being the address pointing to said selected one of said device control tables in said second storage region.
8. A data processing system in accordance with claim 7 wherein the device control table in said second storage region includes coded masking information for preventing other external devices from requesting interrupts when an interrupt has already been requested by said external device and processor status information as to whether or not a fixed point overflow condition is to be enabled.
Description
INTRODUCTION
This invention relates generally to data processing systems and, more particularly, to such systems which can handle 32 bit logical addresses at a size and cost which is not significantly greater than that of systems which presently handle only
16 bit logical addresses.
RELATED APPLICATIONS
This application is one of the following groups of applications, all of which include the same text and drawings which describe an overall data processing system and each of which includes claims directed to a selected aspect of the overall data processing system, as indicated generally by the titles thereof as set forth below. All of such applications are being filed concurrently and, hence, all will have the same filing date.
(1) Data Processing System, Ser. No. 143,561, filed by E. Rasala, S. Wallach, C. Alsing, K. Holberger, C. Holland, T. West, J. Guyer, R. Coyle, M. Ziegler and M. Druke;
(2) Data Processing System Having A Unique Address Translation Unit, Ser. No. 143,681, filed by S. Wallach, K. Holberger, S. Staudener and C. Henry;
(3) Data Processing System Utilizing A Hierarchical Memory Storage System, Ser. No. 143,981, filed by S. Wallach, K. Holberger, D. Keating and S. Staudener;
(4) Data Processing System Having A Unique Memory System, Ser. No. 143,974, filed by M. Ziegler and M. Druke;
(5) Data Processing System Having A Unique Instruction Processor System, Ser. No. 143,651, filed by K. Holberger, J. Veres, M. Ziegler and C. Henry;
(6) Data Processing System Having A Unique Microsequencing System, Ser. No. 143,710, filed by C. Holland, K. Holberger, D. Epstein, P, Reilly and J. Rosen;
(7) Data Processing System Having Unique Instruction Responsive Means, Ser. No. 143,982, filed by C. Holland, S. Wallach and C. Alsing.
BACKGROUND OF THE INVENTION
Presently available data processing systems which are often referred to as belonging to the "mini-computer" class normally handle logical addresses and data words which are 16 bits in length. As used herein, the term "logical" address, sometimes referred to by those in the art as a "virtual" address, is used to denote an address that is programmer visible, an address which the programmer can manipulate. In contrast, a "physical" address is the address of a datum location in the main memory of a data processing system. Operating data processing systems utilize appropriate translation tables for converting logical addresses to physical addresses.
Such mini-computers have been successfully used in many applications and provide a high degree of data processing capability at reasonable cost. Examples of such systems which have found favor in the marketplace are those known as the "Nova" and the "Eclipse" systems designed and developed by Data General Corporation of Westboro, Mass. The Nova and Eclipse family of mini-computers are described in the publications available from Data General Corporation which are listed in Appendix A incorporated as part of this specification.
The Nova system provides a logical address space of 64 kilobytes (the prefix "kilo" more accurately represents 1024, or 2.sup.10) and the Eclipse system also provides a logical address space of 64 kilobytes, both being proven systems for handling many applications at reasonable cost. It is desirable in the development of improved systems to provide for an orderly growth to an even larger logical address space than presently available in Nova and Eclipse systems. Such an extended logical address base permits a larger set of instructions to be utilized by the system, the enlarged instruction set being capable of including substantially all of the basic instructions now presently available in the prior Nova and Eclipse systems as well as a large number of additional, or extended, instructions which take advantage of the increased or expanded logical address space.
Accordingly, such an improved system should be designed to be responsive to software which has been previously designed for use in Nova and Eclipse systems so that those presently having a library of Nova and Eclipse software, representing a substantial investment, can still use such software in the improved, expanded address system. The improved system also would provide for a greater flexibility in performance at a reasonable cost so as to permit more on-line users at a larger number of on-line terminals to utilize the system. The expanded address space would further permit the system to support more extensive and sophisticated programs devised specifically therefor, as well as to support all of the previous programs supported by the unextended Nova or Eclipse systems.
BRIEF SUMMARY OF THE INVENTION
The system of the invention utilizes a unique combination of central processor and memory units, the processor comprising an address translation unit, an instruction processor unit, an arithmetic logic unit and a microsequencing unit, while the memory unit includes a system cache unit, a main memory unit and a bank controller unit for controlling data transfers therebetween. The system handles thirty-two bit logical addresses which can be derived from either sixteen bit or thirty-two bit addresses. Unique means are provided for translating the thirty-two bit logical addresses. The system uses hierarchical memory storage, wherein information is stored in different segment storage regions (rings), access to the rings being controlled in a privileged manner so that access to different rings are governed by different levels of privilege.
The memory system uses a main memory comprising a plurality of memory modules each having a plurality of memory planes. The main memory normally interfaces with the remainder of the system via a dual port system cache memory unit, block data transfers between the main memory and the system cache are controlled by a bank controller unit.
Macro-instructions are decoded using a unique programmable read-only-memory means which is capable of decoding instructions of two types, i.e., instructions from a first basic instruction set or instructions from a second extended instruction set, the instruction which is being decoded containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded.
The decoded instructions provide the starting address of one or more microinstructions, which starting address is supplied to a unique microinstruction sequencing unit which appropriately decodes a selected field of each microinstruction for determining the address of the next successive microinstruction, such address being suitably selected from a plurality of microaddress sources.
The overall system includes means responding to certain macro-instructions which perform unique operations indigenous to the overall system.
DESCRIPTION OF THE INVENTION
The invention can be described in more detail with the help of the drawings wherein:
FIG. 1 shows a block diagram of the overall data processing system of the invention as described therein;
FIG. 2 shows a block diagram of the system cache unit of the system of FIG. 1;
FIG. 3 shows a block diagram of the bank controller unit of the system of FIG. 1;
FIG. 4 shows a block diagram of a module of the main memory unit of the system of FIG. 1;
FIGS. 5-44 show specific logic circuitry for implementing the system cache of FIG. 2;
FIGS. 45-63 show specific logic circuitry for implementing the bank controller of FIG. 3;
FIGS. 64-78 show specific logic circuitry for implementing the main memory modules of FIG. 4;
FIGS. 79-81 show block diagrams which represent the address translation unit of the system of FIG. 1;
FIGS. 82-100 show specific logic circuitry for implementing the address translation unit of FIGS. 79-81;
FIGS. 101-106 show block diagrams which represent the instruction processor unit of the system of FIG. 1;
FIGS. 107-136 show specific logic circuitry for implementing the instruction processor unit of FIGS. 101-106;
FIGS. 137 and 138 show block diagrams of the microsequencer unit of the system of FIG. 1;
FIGS. 139-153 show specific logic circuitry for implementing the microsequencer unit of FIGS. 137 and 138; FIG. 154 shows a block diagram of a representative arithmetic logic unit of the system of FIG. 1;
FIG. 155 shows a diagrammatic representation of certain memory locations used to explain the operation of a particular macro-instruction used in the system of FIG. 1; and
FIG. 156 shows a diagrammatic representation of certain operations performed in the macro-instruction discussed with reference to FIG. 155.
FIG. 157 depicts a one-level page table traversal in a long address translation.
FIG. 158 depicts a two-level page table traversal in a long address translation.
In connection with the above figures, where a particular figure requires more than one sheet of drawings, each subsequent sheet is designated by the same figure number with sequential letters appended thereto (e.g., FIG. 5 (for sheet 1); FIG. 5A (for sheet 2); FIG. 5B (for sheet 3) . . . etc.). With respect to FIG. 146 in particular, which depicts the microcontrol store 170, fifty-six sheets of drawing are used. The sheets are numbered 146, 146A, 146B, 146C, 146D, 146E, 146F; 146.1, 146.1A, 146.1B 146.1C, 146.1D, 146.1E, 146.1F; 146.2, 146.2A, 146.2B . . . etc. to 146.8, 146.8A, 146.8B . . . 146.8F.
GENERAL DESCRIPTION
Before describing a specific implementation of the system of the invention, it is helpful to discuss the overall concept thereof in more general terms so that the characteristics that are desired can be described and the description of a particular implementation can be better understood.
A significant aspect of the system of the invention, as discussed above, is the size of the logical address space which is available. For purposes of convenience in distinguishing between the previous NOVA and Eclipse systems, the extended system as discussed herein will sometimes be referred to as the "Eagle" system. In the Eagle system, for example, the logical address space can be as high as 4 gigabytes (more accurately the prefix "giga" is 1,073,741,824, or 2.sup.30, so that 4
gigabytes is, more accurately, 4,294,967,296) where a byte is defined as having 8 bits of precision. As used hereinafter, a "word" is defined as having 16 bits of precision (i.e., equivalent to 2 bytes) and a "double-word" as having 32 bits of precision (equal to two words, or four bytes). Because of the increased logical address space the overall system is able to support an instruction set which is larger than that supported by a Nova system or an Eclipse system having, for example, a much smaller logical address space. The overall capability of the system can be best understood by those in the art by examination of the set of the extended instructions which are capable of being performed by the system. Such an instruction set in accordance with the invention is set forth in Appendix B incorporated as a part of this specification. Such instruction set includes the extended instruction set (which can be referred to as the Eagle instruction set) and the Eclipse C-350 instruction set, as well as the Nova instruction set, all of which are capable of being handled by the system, the latter two instruction sets being already disclosed as part of the above publications. All Nova and Eclipse instructions are executed according to the principles and specifications presented in the above-referenced publications.
The binary encodings of the extended instructions which are supported by the system of the invention are shown in Appendix B. A significant difference exists between the systems having extended instructions in accordance with the invention and systems having extending instructions which have been suggested by others. In any system in which an extended instruction set effectively represents a "super" set of a previous, or original, set of instructions, all of the instruction must be suitably decoded for machine operations. Normally, such systems utilize a decoding sub-system for decoding both the original instruction set and for decoding the extended instruction set. The decoder operates so as to permit the decoding of only one of the instruction sets at a time, the original instruction set and the extended instruction set being in effect, mutually exclusive. In order to determine which instruction is to be decoded, a unique instruction must be used to set a "mode bit", i.e., a single bit which in one state indicates that the original instruction set is to be decoded and in the other state indicates that the extended instruction set is to be decoded. However, in neither case can the decoding subsystem be made available to decode either of the both sets simultaneously. Such approach inserts a limitation on the overall machine operation since it is never possible to simultaneously decode instructions from different instruction sets of an overall super set thereof.
The system of the invention, however, avoids such mutual exclusivity and is arranged to be capable of decoding instructions from either set or both sets at any one time. A decoder PROM (programmable read-only-memory) system is utilized for decoding both the extended Eagle instruction set and the original or basic instruction sets as, for example, the original Nova and Eclipse instruction set. Each instruction to be decoded includes the information which determines which decoder is to be utilized, such determination thereby being inherently carried in each instruction word which is to be decoded. As seen in Appendix B, for example, the information is contained in bits .0. and 12-15.
Thus, in the extended Eagle instruction set, bit .0. is always a "1" while bits 12-15 are always "1001" for all instructions of the extended instruction set except for those extended instructions which use a "1" in bit .0. and the encoding "011000" in bits 10-15 and a "1" in bit "0", a "0" in bit 5, and the encoding "111000" in bits 10-15. On the other hand, the original Eclipse instructions are such that bit .0. is 0 and bits 12-15 are "1000". Further, in cases where the instruction does not carry either the Eagle coded bits or the Eclipse coded bits, such instruction is interpreted as a NOVA instruction.
Because each instruction carries with it an identification as to which instruction set the instruction belongs, the system operates to decode instructions on a non-mutually exclusive basis.
In order to support the extended operations of the system, the configuration thereof requires an augmentation of the registers which were previously available in the original system of which the new system is an extension. The following registers are utilized in the system and are discussed in more detail later with respect to the particular implementation described in connection with specific figures below.
The register set includes fixed point registers, floating point registers, stack management registers and memory management registers.
Fixed Point Registers
The system includes four fixed point accumulators (ACC .0.-3), one program counter (PC) and one processor status register (PSR). Each of the accumulators has 32 bit precision which can accomodate (1) a 16 bit operand which can be sign extended to 32 bits; (2) a 15 bit address which can be zero extended to 28 bits, the higher order 3 bits of the program counter being appended thereto together with a zero bit, all of which can be appended for storage in the accumulator; or (3) an 8 bit byte which can be zero extended to 32 bits before storage in the accumulator.
The program counter has 31 bits of precision, bits 1-3 identifying one of 8 current memory rings (discussed in more detail below) and bits 4-31 of which accomodate an address offset for instruction addresses. For Eclipse operation, for example, which normally requires only a 15 bit program counter, the bits 1-3 identify the current memory ring as in a 31 bit extended operation while the 15 least significant bits 17-31 represent the 15 bit Eclipse program counter and bits 4-16 are all zeros.
The processor status register is a 16 bit register which provides an overflow mask bit which if set will result in a fixed point overflow. Additionally the register includes a fixed point overflow indicator bit and a bit which indicates that a micro interrupt has occurred. Other bits in the register are reserved and are thus available for potential future use.
Floating Point Registers
The system includes four floating point accumulators (FPAC .0.-3) and one floating point status register (FPSR). Each of the floating point accumulators contains 64 bits of precision which is sufficient to wholly contain a double precision floating point value. The floating point registers of the extended system are identical to the Eclipse floating point accumulators (FPAC) which are discussed in the aforementioned publications.
The floating point status register also has 64 bits of precision, 32 bits of which act as the floating point program counter. In the event of a floating point fault the floating point program counter bits define the address of the floating point instruction that caused the fault. Four other bits are utilized, respectively, to indicate an exponent overflow condition, an exponent underflow condition, a divide-by-zero condition and a mantissa overflow condition. Another counter bit will result in a floating point fault if any of the above latter four bits are also set. The floating point counter also includes a zero vit and negative bit, as are generally used in status registers, as well as bits for indicating a floating point rounding mode of operation and an interrupt resume operations.
Stack Management Registers
The system of the invention utilizes four 32 bit registers to manage the memory stack, which registers include a stack pointer, a stack limit, a stack base, and a frame pointer. The stack pointer register references the double word entry at the top of the stack. When a "push" operation occurs, all the bits of the stack pointer are incremented by 2 and the "pushed" object is placed in the double word addressed by the new pulse of the stack pointer. In a "pop" operation the double word addressed by the current value of the stack pointer is placed in a designated register and all 32 bits of the stack pointer are then decremented by 2.
The frame pointer register references the first available double word minus two in the current frame. The stack limit contains an address that is used to determine stack overflow. After any stack operation pushes objects onto the stack, the stack pointer is compared to the stack limit. If the stack pointer is greater than the stack limit a stack fault is signaled. The stack base contains an address that is used to determine the stack underflow. After any stack operation that pops objects from the stack, the stack pointer is compared to the stack base. If the stack pointer is less than the stack base a stack fault is signaled.
Memory Management Registers
Eight registers are used to manage memory, such registers each being designated as a segment base register (SBR) having 32 bits of precision, the memory being divided into eight segments, or rings, thereof. The SBR's in the system described herein are formed as part of scratch pad registers on an address translation unit (ATU) of the system, as discussed in more detail below. One bit of each SBR indicates whether or not the segment associated therewith can be referenced (i.e. is there a valid or an invalid reference to such segment). Another bit indicates the maximum length of the segment offset field i.e. whether or not the reference is a one level page table or a two level page table, as explained in more detail below. A third bit of each segment base register indicates whether a Nova/Eclipse instruction for loading an effective address of a Nova/Eclipse I/O instruction is being executed. Another bit represents a "protection" bit which indicates whether or not an I/O instruction can be executed or whether the execution thereof would be a violation of the protection granted to such segment. Nineteen of the bits contain a physical address which identifies the physical address in the memory of the indicated page table. Discussions of the addressing of page tables in the memory are presented in more detail below including a discussion of the memory locations in each segment.
Overall System
A block diagram of a preferred embodiment of the invention is shown in FIG. 1. The central processor portion of the system comprises an arithmetic logic unit (ALU) 11, an instruction processor unit 12, a micro-sequencer unit 13 and an address translation unit (ATU) 14. The memory system includes a main memory unit 16, an auxiliary cache memory unit 17 and a memory control unit identified as bank controller unit 18. A central processor address bus 19 permits the transfer of addresses among the instruction processor unit 12, the address translation unit 14 and the memory system. A control processor, memmory (CPM) bus 20 permits the transfer of instructions and operands among arithmetic logic unit 11, instruction processor unit 12, address translation unit 14 and the memory system 15.
I/O address bus 21 and I/O memory/data bus 22 permit the transfers of addresses and data respectively with respect to I/O devices via I/O channel unit 23, as well as the transfers thereof between the memory system and a console control processor unit 24. Suitable control buses for the transfer of control signals among the various units of the overall system are provided as buses 25-31 described in more detail below. Appropriate teletype and floppy disc systems 33 and 34, respectively, can be utilized with the system, particularly in the diagnostics mode of operation via console control processor unit 24 by way of a suitable micro processor computer 35.
The inventive aspects of the system to be described herein require a more detailed discussion of the memory system, the address translation unit, the instruction processor unit and the micro sequencer unit. The arithmetic logic unit, the console control processor unit and the I/O channel unit with their associated controls need not be described in detail.
Memory System
In accordance with a preferred embodiment of the invention the memory system comprises up to two megabytes of main memory 16 and, if desired, the system can be expanded even further as, for example, to 4 megabytes. It should be noted that sufficient bits are reserved in the physical address fields so as to allow for system expansion to one billion bytes of memory. The interface between the main memory unit 16 and the remainder of the system is via the dual port cache memory unit 17, data being transferred between the main memory and the cache memory unit in blocks of 16 bytes. The cache memory unit herein will usually be referred to as the "system cache" (SYS CACHE) to distinguish it from a separate cache memory in the instruction processor unit which latter memory will normally be referred to as the "instruction cache" (I CACHE) unit. The system cache unit 17 services CPU requests for data transfers on port 17A of its two ports and services requests from the I/O system at port
17B thereof. CPU data transfers can include "byte-aligned-byte" transfers, "word-aligned-word" transfers, and double word transfers. I/O data transfers can include "word-aligned-word" transfers, "double word-aligned-double word" transfers and 16 byte block transfers.
The main memory unit 16 can include from one to eight 256-kilobyte memory modules, as shown in FIG. 4. Each memory module contains a memory array of 156 16K dynamic random access memories (RAMs), organized at each module in the form of four planes .0.-3 of 16K 39-bit words each. Each word comprises 32 bits of data and 7 error correction bits, as discussed in more detail below. Memory timing and control for the RAMs of each memory module is accomplished on the memory bank controller board
18. The control signals from the memory bank controller are clocked into a register on each memory module, the outputs thereof driving the "plane-.0." RAMs. The outputs from such reigister are clocked a fixed time later into another register which drives the "plane-1" RAMs. Such pipe line operation continues through "plane-2" RAMs and "plane-3" RAMs so that all four planes receive the same control signals at fixed intervals (e.g. 110 nanosecond intervals), resulting in the transfer of a block of four consecutive 39-bit words.
Memory bank controller 18 has three main functions. First of all, it provides an interface between the system cache 17 and the memory modules of the main memory unit 16. Secondly, it performs necessary error checking and correction operation and, thirdly, it controls the refresh operation of the dynamic RAMs on each of the memory modules. The details of the interface between the system cache and the bank controller are discussed in more detail below.
The error checking and correction logic on the bank controller performs single-bit error correction and double-bit error detection using a 7 bit error correction Hamming code as is well known in the art. The 7 check bits generated for each 32
bit data word are stored with such word in the main memory modules. When the word is subsequently read from memory, all 39 bits are decoded to produce a 7 bit pattern of syndrome bits which pattern identifies which, if any, single bit is in error and indicates when more than one bit is in error. When a correctable single-bit occurs, the console control processor 24 is provided with the address and the syndrome bit pattern of the failing bit. The data is thereupon corrected and sent to the system cache after a fixed time delay equal to a system clock period, e.g. 110 nanoseconds in a particular embodiment, in accordance with well-known error correcting operation, the remaining words in the pipe line operation being prevented from transfer until the corrected signal is made available by the use of a suitable inhibit signal identified as the BC ERROR signal.
Substantially immediate correction of single bit errors is desirable so that such errors do not grow into multiple bit errors. A conventional technique can be used in which the corrected data is written back into memory only when it has been read and found to be in error. Two problems arise with such a technique. First of all, the memory locations which are not often read are not often corrected and, secondly, significant time can be wasted in trying to correct a failure if it occurs in a frequently accessed memory location. The system of the invention can avoid such problems by utilizing a separate process for monitoring all of the main memory locations so that each location therein is checked and corrected, if necessary, once every two seconds. Such checking is performed during the memory refresh cycle and does not reduce the availability of the memory to the system. A detailed description of such a technique is disclosed in U.S. Pat. No. 4,380,812, issued Apr. 19, 1983, filed concurrently by M. Ziegler, M. Druke, W. Baxter and J. VanRoeckle, which application is incorporated by reference herein.
The system cache unit 17 represents the sole connection between the main memory unit 16 and the remainder of the system and consists of a memory system port 38 for connection to the main memory and two requestor ports 17A and 17B, as discussed above, one intended primarily for handling CPU requests and one intended primarily for handling I/O requests. The system cache board also provides a direct access path 39 between the I/O port and the memory system port providing for direct block transfers therebetween. Cache board 17 also includes a 16-kilobyte, direct mapped high speed cache data store 40 having a block size of 16 bytes which can be accessed from either the I/O or the CPU requestor port. Block diagrams of the logic utilized in the system cache unit 17, the bank controller unit 18 and a typical memory module of the main memory unit 16 are shown in FIGS. 2,3, and 4.
As can be seen in FIG. 2, the system cache data store 40 receives all requests for data from the memory other than block transfer request from the I/O port which are serviced by the main memory directly. In the particular embodiment described, the cache data store receives the data address at the address input of either CPORT 17A or IPORT 17B which address is placed in either CPORT address register 41 or IPORT address register 42. The incoming address includes a Tag portion, an Index portion and a word pointer portion as follows:
______________________________________ ##STR1##
______________________________________
The three least significant bits 29-31 of the cache data store address specify the word pointer, which identifies the desired word within a block of the 16 byte 8 word block of the data store. The remaining bits 9-28 identify the block address which corresponds exactly to the address which would be used to fetch the desired block from the main memory. The latter bits are divided into Tag bits 9-18 and Index bits 19-28 as shown.
The system cache as depicted in FIG. 2 includes a "Tag" Store Unit 43. Data store 40 is a high speed memory array of 4K.times.32 bit words (i.e. 1K 16-byte blocks) and holds a copy of a block of words from main memory. The data store is addressed by the index and word pointer bits of the cache data store address word, the index being a 10-bit address of a block within the data store 40 and the three word pointer bits pointing to the desired word within the selected block, as mentioned above. A data store block may be used to buffer any data block of main memory which shares the same index.
The function of the Tag store 43 is to identify which of the many possible blocks from the main memory is buffered in each 16 byte block of the data store 40. Tag store 43 is a high speed array of 1K 12-bit words and is addressed by the 10-bit index portion of the memory address. Each 12-bit word contains ten bits which identify the block from the main memory which is buffered in data store 40. When the main memory is 4 megabytes or less, the first two bits of this tag are needed only for future expansion of the main memory capacity and can be zero. Bits 10 and 11 are flags to indicate the status of the data. Thus a "valid" flag V indicates that the identifiable data store block contains valid data. For example, if an I/O port operation were to request a block "write" to main memory which modifies the contents of a block which has already been buffered in the data store 40, the valid flag of that block would be reset to indicate that its data is no longer valid.
A "modify" flag M indicates that the contents of the data store block have been modified. Thus, if a data block is removed from the data store 40 to make room for a new data block from main memory, the removed data block is written back to main memory if the modified data flag is set.
A second tag store unit 44 is shown on the system cache board, which latter tag store is a replica of the instruction cache (ICACHE) tag store which is described later. The ICACHE tag store is used on the system cache board to determine when a write to memory would affect the contents of the instruction cache at the instruction processor. When such an effect would occur, as indicated by a comparison at comparator 45 of the incoming address and the ICACHE address, the system cache alerts the instruction processor by asserting an "instruction cache write" signal, as indicated in FIG. 2, to inform the instruction cache (ICACHE) at the instruction processor board of the location of the block which has been so modified.
In the operation of the system cache all requests are initially assumed to be "read" requests, since even when a "write" request occurs it is possible that the data to be written will need to be read and modified (a "read-modify-write" operation) before the write operation is to be performed. If the system cache is not busy when a request is received at an input port, the data store 40 and the tag store 43 are accessed simultaneously, using the appropriate portions of the received input address as discussed above. The data from the location in the data store 40 which has been addressed is loaded into the cache write data register 46 via multiplexer 48 if the data transfer is a write into memory operation so that in the next cycle the contents of the write data register 46 can be enabled onto the bus via multiplexer 47 and bus driver unit 49. If the data is a read operation the data output from data store 40 is supplied at the CPORT or IPORT, as required, via multiplexer 48 and driver units
50 and 51, respectively.
The data from the tag store 43 is first examined to determine if the requested data, is, in fact, in the data store 40. The tag portion of the word which is read from the tag store is compared at comparator 52 with the tag portion requestor and the valid flag checked to see that it is set. If such comparison is successful (a system cache "hit") the data from data store 40 is the desired data and the requestor is permitted to receive it or to write it into memory. If the comparison fails (a system cache "miss") the data block which has been requested is not in the cache data store 40 and must be brought in from the main memory. Such an occurrence is termed a "cache fault" condition and, when such fault occurs, the requestor is prevented from loading in data until after the fault is resolved.
Once the data is available for the requestor the requestor must signal that it wishes to accept the data and, if the requestor does not do so when the data first becomes available, the read operation will be repeated until the requestor indicates its willingness to accept the data.
Because access to the data in data store 40 requires two system clock cycles to complete, the cache addresses as received from requestors can be "pipe-lined" in a manner such that two accesses can be in progress at any one time. Advantage is taken of this ability to pipe-line access requests by intertwining the accessors of one of the input ports with those of the other input ports. An appropriate clocking signal, which has a frequency one-half that of the basic system clock, is used to indicate which requestor port is allowed to access the cache data store at any given time. As a result there is no interference between CPU and I/O port accesses except during a cache fault. The only exception is that both I/O and CPU ports are not allowed to be in the process of accessing the same data store block at the same time. An example of the intertwining operation between the ports for a read operation is discussed below. In the particular example described the CPU port requestor does not choose to take the data at the first opportunity so that a read repeat occurs.
__________________________________________________________________________ t0 t1 t2 t3 t4 t5 __________________________________________________________________________ CPU Address and Tag and Data ready. Data Store Data Ready. PORT START Data Stores Requestor read Requestor READ Signal on read. does not again. asserts RT bus. assert RT Signal and Signal. loads data. IO Idle cycle Address and Tag and Data ready. Idle cycle PORT or end of START Data Stores Requestor or start of READ last Signal on read. asserts RT next access. bus. Signal and access. loads data. __________________________________________________________________________
For a cache write operation, the cache, at the time the memory write access is initiated, assumes that a read-modify-write operation will be performed and accordingly does a read as described above. However, even if the transfer is to be a simple write operation, the tag store information must be read to determine the location at which the incoming data will be written so that in actuality no time is lost in performing a superfluous data store read operation. For a simple write operation, or for the write portion of a read-modify-write operation, the requestor asserts a write transfer (WT) signal to indicate completion of the transfer. Instead of driving the data from the output register onto the memory port 38 the system cache loads an input register 53 with the data which is to be written from the data bus at the end of the cycle and writes it into the data store 40 during the next cycle. If a cache fault results from such a write request, the system cache accepts the data to be written into the input register but does not write it into the data store 40 until after the fault is resolved. An example of a CPU port write request in a manner similar to that discussed above for a read request is shown below.
__________________________________________________________________________ t0 t1 t2 t3 t4 t5 __________________________________________________________________________ CPU Address and Tag and Data ready. Data Store Idle cycle. PORT START and Data Stores Requestor written. WRITE WRITE read. asserts WT Signal on Signal and bus. sends data. IO Idle cycle Address and Tag and Data ready. Idle cycle PORT or end of START Data Stores Requestor or start of READ last Signal on read. asserts RT next access. bus. Signal and access. loads data. __________________________________________________________________________
The examples discussed above show single read or single write operations. It is also possible for a requestor to submit a new address and a START signal along with the read transfer (RT) and/or write transfer (WT) signal, so that consecutive read operations or consecutive write operations from a single port can be performed every two cache cycles (a CPU cycle, for example, is equivalent to two cache cycles) unless a cache fault occurs. However, if a read access is initiated at the same time that a write transfer is performed, the data store 40 cannot be read on the next cycle because it is being written into at that time. When this condition happens, the read operation requires an additional two cache cycles for completion. If the requestor is aware that a read operation is following a write transfer and wishes to avoid a wasted cycle, the requestor can either delay starting the read request until the next cycle or it may start the read request to wait an extra cycle before requesting the data transfer. In either case useful work could be done in the otherwise wasted cycle, although initiation of a read followed by a wait for an extra cycle is usually more desirable because it allows a cache fault to be detected at an earlier point in time.
A read-modify-write operation can be accomplished by asserting a START signal and WRITE signal along with the address, followed by a read transfer at a later cycle and a write transfer at a still later cycle. When a WRITE signal is signaled at the start of an access, the system cache will not consider that the access has been completed until a write transfer is performed. During such operation all other requestors are prohibited from accessing the same data. Thus, requestors utilizing the same input port are prevented from access by the fact that the first requestor controls the bus during the entire read-modify-write operation. Requestors on the other port are prevented from access by the fact that both ports are prohibited from accessing the same data store block at the same time. Such prohibition also prevents requestors at another port from removing a block of data from the cache data store when the system cache is in the middle of an operation.
If the system cache board receives a write transfer request when a write operation has not been previously indicated or, if it receives a read transfer and a write transfer request simultaneously, access to the system cache data store is aborted without the transfer of any data. If such simultaneous read and write transfer requests are asserted at the beginning of the next cycle after the START request, the access may be avoided without even initiating an unnecessary cache fault indication.
In addition to the above transfers, the system cache board has the capability of performing direct write transfers between the input ports and the main memory, the bulk of such data traffic being capable of being handled without affecting the contents of the cache data store 40. If the requested transfer is a block write transfer, the data is written directly into the main memory via data write register 40A, MUX 48 and write data register 46. Data transfers at the I/O port are not allowed when the CPU port is in the process of accessing data which has the same Index as the I/O block which is to be transferred. Data read-modify-write transfers are also not permitted by the system.
In the overall system cache block diagram shown in FIG. 2, the input registers for the CPU request port and the I/O request port are shown as data registers 54 and 55. Addresses associated with the data at such registers are supplied to the CPU address register 41 and the I/O address register 42, each address comprising the Index, Tag and Word Pointer as discussed above.
Specific logic diagrams of the system cache board 17 depicted in FIG. 2 are shown in FIGS. 5-44, which latter figures are appropriately labeled as follows to show more specifically a particular embodiment of the various portions of the system cache 17 depicted therein.
FIG. 5 shows the cache data store 40; FIG. 6 the Tag store 43; FIG. 7 the ICACHE tag store copy unit 44; FIG. 8 the tag store comparator 52; FIG. 9 the ICACHE tag store comparator 45; FIG. 10 the CPORT and IPORT registers 41 and 42 and the write back tag unit; FIGS. 11 and 12 the INDEX SV WP SV unit of FIG. 2; FIG. 13 the INDEX and WP multiplexer units; FIG. 14 data write register 40A; FIG. 15 the multiplexer unit 48 and the index driver unit 48' which supplies an input to multiplexer 48; FIG.
16 the write data register 46; FIG. 17 the multiplexer unit 47; FIG. 18 the driver units 50 and 51 and driver logic associated therewith; FIG. 19 the INDEX/INDEX SV comparator unit; FIG. 20 the CPU buffer data register 54, the I/O buffer data register
55, and the CRD IN register 53. The specific system cache parity logic is shown in FIGS. 21-25. The main memory and other interface control logic is shown in FIGS. 26-28. As in any data processing system board, adequate control signals for the various units thereon must be provided and control logic for the particular embodiments of the system cache board depicted in FIGS. 5-27 are shown in FIGS. 29-43.
FIG. 3 depicts an overall block diagram of the bank controller 18 which interfaces between the system cache at the left hand side of the drawing and the memory modules at the right hand side thereof. Words which are read from the memory modules, identified as RD .0.-38, including 7 parity bits, are supplied to the bank controller for transfer to the system cache, such words being identified as CRD .0.-31 in FIG. 3, via the error correction logic 70 which also supplies four parity bits, idenified as CRD PAR .0.-3. Address and data words which are to be written into the main memory modules are supplied from the system cache such words being identified as CA/WD .0.-31, together with the parity bits therefor, identified as CA/WD PAR .0.-3, the data being supplied to the write data bus for the memory modules as WD .0.-31 and parity bits WD 32-38 via error correction logic 70. The addresses therefor are supplied in the form of information which is required to select the desired memory module (MODSEL .0.-3) (to identify up to 16 modules) and to select the desired RAM within the selected module (ADDR.0.-7)
Further, the bank controller supplies the following control signals to the main memory which responds thereto as required. The RAS and CAS signals represent the row address and column address strobe signals for the RAM's of the main memory. The LDOUT signal causes the selected module to load its output register at the end of the current cycle and to enable the register to place the contents of the output register on the read data bus during the next cycle. The LDIN signal causes the selected module to accept data from the write bus during the next cycle and to write such data into the RAMs during the following cycle. The REFRESH signal overrides the module selection for the row address strobe (RAS) signal only. During a refresh operation one module is read normally and all others perform an RAS refresh only.
The bank controller also interfaces the system cache to supply 32-bit words (CRD .0.-31) to the cache along with 4 parity bits (CRD PAR .0.-3) for byte parity and to receive 32 bit address and data words (CA/WD .0.-31) from the cache along with byte parity bits (CA/WD PAR .0.-3). The bank controller also supplies the following control signals to the cache. The BC BUSY signal indicates that the bank controller is not able to accept a BC START (see below) request. The BC ERROR signal indicates that the data word placed on the read data bus during the last cycle contained a correctable error and must be replaced with the corrected word for the data which is on the bus during the current cycle. Once a BC ERROR signal has been asserted all subsequent words of the same block transfer are also passed through the error correction logic. Accordingly, BC ERROR need be asserted only once for each block transfer.
The BC DATABACK signal indicates that the first word of the four word block to be transferred will be at the read data bus in the next cycle. The BC REJECT signal indicates that the bank controller cannot accept the contents of the write data bus at the end of the current cycle. The BC START indicates that a bank controller transfer operation is to commence.
Specific logic diagrams for the particular units of the bank controller board 18 of FIG. 3 are shown in FIGS. 44-63, which latter figures are appropriately labelled as follows to show more specifically a particular embodiment of the various portions of the bank controller 18 depicted therein.
The error correction logic 70 is shown in FIGS. 44-63 and includes the multiplexer store unit shown in FIG. 44; the C-bit generator unit 45; the (32 bits) register and (8 bits) register shown in FIG. 46; the drivers for the write data bus shown in FIG. 47; the S-bit generator shown in FIG. 48. The read save register shown in FIG. 49; the S save register shown in FIG. 50; the read parity save register and parity logic shown in FIG. 51 and the correction logic shown in FIG. 52. The direct read driver unit is shown in FIG. 53.
With reference to the control units at the lower part of FIG. 3, the R/W module selection unit and the RADDR and CADDR units are shown in FIG. 54; the MODSEL unit and drivers therefor are shown in FIG. 55; and the ADDRESS unit and driver therefor are shown in FIG. 56.
Appropriate timing and control logic both for address and data transfer and for memory refresh operation is shown in FIGS. 57-59, the drivers for the principal control signals supplied to the memory module being shown in FIG. 60; and various bus interface logic as shown in FIGS. 61-63.
FIG. 4 depicts the overall block diagram for a typical memory module of the main memory system of the invention and shows the memory array 60 of dynamic NMOS random access memories (RAM's) organized as four planes of 16K 39-bit words each and identifiable as planes .0.-3. A word which is to be written into the memory array is received from the bank controller as WD.0.-38 via buffer 62. Words being stored in even planes .0. and 2 are stored in even plane data register 63 while words to be stored in odd planes 1 and 3 are stored in odd plane data register 64. The control signals are supplied from the bank controller to control logic 65. The module select code bits MOD SEL.0.-3 are supplied to a comparator 66 to provide a MODSEL signal if the particular module has been selected. Control signals from control logic 65 are supplied to appropriate latching circuitry 67 to provide appropriate signals for controlling the operation of the memory array via drivers 61. The control signals from the memory bank controllers are first clocked into the plane .0. latching registers 67A and the outputs thereof drive the plane .0. RAMs vis drivers 61A. The outputs of the first latch register are those clocked at a fixed time period later into the next latch register set 67B which drives the plane 1 RAMs. Such pipeline operation continues in order to drive the plane 2 and plane 3 RAMs such that all four RAM planes receive the same control signals at fixed intervals, resulting in the transfer of a block of four consecutive 39-bit words. While the RAM address from the bank controller includes eight bits, only seven bits of address are used for the 16K RAMs discussed above, the extra bit allowing for possible future expansion. Thus, addressed bits ADR .0.-5 are clocked at fixed intervals to each of the latches 67A-67D of the planes .0.-3 at fixed intervals. ADR 6 is supplied to RAM selection logic 68 together with the plane .0. latch signal RPL .0. RAS to provide the JADR 6 signal for the plane .0. latch register 67A. The RAS and CAS signals provide the necessary control signals via the control logic 65 and latch registers 67 for driving the row address strobe (RAS) and the column address strobe (CAS) signals for the RAMs.
The LDOUT signal to the input of control logic 65 causes the module to load its output register at the end of the current cycle and enable it onto the read data bus during the next cycle via the data out register and multiplexer logic 69 and read bus driver 69A. The LDIN signal at the input to control logic 65 causes the module to accept data from the write data bus via registers 63 and 64 for writing into the RAM during the following cycle. The following timing diagrams show the status of the various signals for block read and block write operations at each fixed time interval (in the particular embodiment described, for example, each cycle can be 110 ns). As can be seen, the plane .0.-3 data is provided in the read operation in sequence and the input data is written into such planes in sequence.
__________________________________________________________________________ Block Read t0 t1 t2 t3 t4 t5 t6 t7 __________________________________________________________________________ Control RAS RAS,CAS RAS,CAS LDOUT <pre- <next Signals MODSELS MODSELS MODSELS MODSELS charge> access> Address ROW COLUMN COLUMN Lines ADDRESS ADDRESS ADDRESS Read PLANE PLANE <etc.> Data bus DATA DATA. <etc.> Write Data Bus __________________________________________________________________________
__________________________________________________________________________ Block Write t0 t1 t2 t3 t4 t5 t6 t7 __________________________________________________________________________ Control RAS,LDN RAS,CAS RAS,CAS <next Signals MODSELS MODSELS MODSELS access> Address ROW COLUMN COLUMN Lines ADDRESS ADDRESS ADDRESS Read Data Bus Write PLANE 0 PLANE 1 PLANE 2 PLANE 3 Data Bus DATA DATA DATA DATA __________________________________________________________________________
More specific detailed logic circuitry for implementing the units shown in the block diagram of FIG. 4 to achieve the desired operation as described above are shown in FIGS. 64-78. Data in registers 63 and 64 are shown in FIGS. 64 and 65, respectively. The memory array 60 is shown in FIGS. 66-73 wherein plane .0. RAMs and the control input circuitry therefor are shown in FIGS. 66 and 67; plane 1 RAMs and the control input circuitry therefor are shown in FIGS. 68 and 69, plane 2 RAMs and the control input circuitry therefor are shown in FIGS. 70 and 71, and plane 3 RAMs and the control input circuitry therefor are shown in FIGS. 72 and 73. The data out register and multiplexer unit 69 are shown in FIG. 74. Latching and driver logic is shown in 75. The RAM select logic unit (RAMSEL LOGIC) is shown in FIG. 76, while the MODSEL comparator unit 66 and the various control logic units and latching circuitry associated therewith and with the input control signals from bank controller unit
18 are shown in FIG. 77. Memory module timing logic is shown in FIG. 78.
ADDRESS TRANSLATION UNIT
The address translation unit (ATU) 14 is shown broadly in FIGS. 79-81, the primary function of such unit being to translate a user's logical address (LA) into a corresponding physical address (PA) in the physical address space of the processor's memory modules discussed above. Such translation is effectively performed in two ways, one, by accessing a page from the system cache or from main memory at the particular page table entry specified in a field of the logical address and placing the accessed page in a translation store unit for use in performing the address translation, a sequence of operations normally designated as a Long Address Translation (LAT) and, the other, by accessing additional references to a page that has already been selected for access after an LAT has been performed and the page selected by the LAT is already present in the translation store. The latter translation provides an accelerated address reference and can be accomplished by saving, at the end of every Long Address Translation, the address of the physical page which has been accessed. As mentioned, the physical page involved is stored in a high speed random access memory (RAM) file designated in FIG. 79 at ATU translation store 100.
Translations of addresses on the physical page which is stored in the ATU translation store 100 are available to the processor within one operating time cycle of the CPU, while normally the Long Address Translation will take a plurality of such cycles for a reference which requires a single level page table reference (e.g. 3 cycles) or a two-level page table reference (e.g. 5 cycles), where the page in question is available in the system cache memory. Even longer times may be required if the page involved can not be found in the system cache memory and must be accessed from main memory.
A secondary function of the ATU is to emulate all operations of the previous system of which the present system is an extension, e.g., in the system described, to perform all Eclipse memory management processor unit (MMPU1) address translation operations, as described in the above referenced publication for such systems, in an efficient and compatible way, such emulated operations being described in more detail later.
In order to understand more clearly the translation of a logical word address (a byte address when shifted right by one position produces a word address), the logical word address can be defined as shown below:
______________________________________ ##STR2## ##STR3## ##STR4## ______________________________________
As seen therein, the segment and logical page address is 21 bits long, the segment and logical page address being divided into two fields, the Tag field and the Index field. The Tag field is defined as bits LA 2-14 while the Index field is defined as bit LA 1 plus bits LA 15-21.
As seen in FIG. 79, when a logical word address LA.0.-31 is received from the arithmetic logic unit (ALU) on the logical address bus 26 it is latched into a logical address register (LAR) 101. The Index bits LA 15-21 are taken directly from the logical address bus to address four RAM stores, the first being a Tag store 102, which retains the tag portions of the logical addresses corresponding to the physical addresses saved in the ATU physical address (PA) translation store 100. The Index bits LA 15-21 are also supplied to a validity store RAM unit 103 and to a protection store RAM unit 104, as discussed below.
If the physical address translation store 100 contains valid address translations, when a memory access is started the logical address is loaded into the logical address register 101 and the Index (bits LA 15-21) is used to select a location in the store.
In the particular system described, even though there is a valid address translation at such location in translation store 100, it may not be the correct one. Corresponding with each index of the logical address (and each address location in the translation store) there are a selected number of possible "tags", each tag corresponding to a unique physical page address. Only one of such tags and its corresponding physical page address can be saved in the translation store 100 at the location selected by the Index. Therefore the "tag" (TAG 2-14) that corresponds to the Index in question and is currently stored in the tag store 102 is compared at comparator 105 to the "tag" in the logical address register (LA 2-14). If the "tags" correspond, the address translation contained in the translation store 100 is the correct one and can be used to supply the desired physical address (signified by an ATU HIT signal at the output of comparator 105). If they do not match, a Long Address Translation operation must be performed to obtain the desired physical page address from the system cache or main memory. The physical page address which is thereby accessed by such LAT procedure to replace the physical page address previously contained in the ATU translation store 100 is placed on the appropriate transfer bus (CPM bus 20). At the completion of the long address translation, the "tag" taken from the logical address register (LAR 2-14) is written into the tag store 102 at the location selected by the index and the physical page address from the memory data register 106 (MD 18-31) is written into the translation store 100 at the location specified by the index.
The ATU configuration shown in FIG. 79 also contains further components which are used to place the translated physical address of a desired physical page table on the physical page address (PA) bus 27. There are three other possible sources of physical page table addresses, the first of which is bits SBR 18-31 of a segment base register which segment base register can also be located in scratch pad units of the address translation unit. This address is used to reference either a high order page table (HOPT) of a two-level page table or the low order page table (LOPT) of a one-level page table. Since the segment base registers are located at the ATU, such address can be obtained from the logical address bus 26 as LA 18-31.
FIGS. 157 and 158 depict the results of the control actions initiated by the arithmetic translation unit (ATU) to perform a long address translation in which a physical address is derived from a logical address by traversing the one- and two-level page tables in the main memory. FIG. 157 depicts a one-level page table traversal, while FIG. 158 depicts a two-level page table traversal, the physical address bits 3-21 of the final physical address (i.e., the desired memory allocation data) being placed in the translation store 100 so that when the corresponding logical address is subsequently requires a translation, the physical address is available (an ATU HIT occurs) and there is no need for subsequent long address translation.
The logical word address to be translated for a one-level page table translation has the format shown in FIG. 157. Bits 1-3 of the word address specify one of the eight segment base registers (SBRs). The ATU uses the contents of this valid SBR to form the physical address of a page table entry (PTE), as shown at point 1 of the FIG. 157.
The selected SBR contains a bit (bit 1) which specifies whether the page table traversal is a one-level (bit 1 is zero) or a two-level (bit 1 is a one) page table. In FIG. 157 a page table entry address comprising the starting address of a selected page table and page table entry offset specifying a page address therein.
To form this physical page address, the ATU begins with the physical address as shown at 2 of the FIG. 157. This address becomes bits 3-21 of the PTE address. Bits 13-21 of the logical word address become bits 22-30 of the PTE address. The ATU appends a zero to the right of the PTE address, making a 29-bit word address.
Bits 3-21 of the PTE address (unchanged in the step above) specify the starting address of a page table. Bits 22-31 of the PTE address specify an offset from the start of the table to some PTE (labelled PTEn in FIG. 157). This PTE specifies the starting address of a page of memory, as shown at 3 of the FIG. 157.
PTEn bits 13-31, the page address, become bits 3-21 of the physical address, as shown at 4 of FIG. 157. The page offset field specified in bits 22-31 of the logical word address becomes bits 22-31 of the physical address. This is the physical word address translated from the original word address. The physical address bits 3-21 are placed in the translation store as the memory allocation data for subsequent use if the same logical word address requires subsequent translation. It should be noted that when using a one-level page table, bits 4-12 of the logical word address must be zero. If they are not zero and bit 1 of the SBR indicates a one-level page table is required, a page fault occurs.
Just as in the one-level page table translation process, in the two-level page table translation depicted in FIG. 158, the processor produces a physical address. The logical word address to be translated has the format shown in the diagram, the steps (1) through (4) being substantially the same as in FIG. 157 except that bits 4-12 of the logical word address become bits 22-30 of the PTE address. The ATU appends a zero to the right of the PTE address, making a 29-bit word address. Bits 1-3 of the word address specify one of the eight segment base registers (SBRs).
Bits 3-21 of the PTE address specify the starting address of a page table. Bits 22-31 of the PTE address specify an offset from the start of the table to some PTE (labelled PTEn). The PTE specifies the starting address of a page table. Thus, the ATU now constructs the address of a second PTE from the address at 4 . The physical address specified in bits 13-31 of the first (PTEn) becomes bits 3-21 of the address of the second PTEm. Bits 13-21 of the logical word address become bits 22-30 of the second PTE's address. The ATU appends a zero to the right of the second PTE address to make a 29-bit word address.
Bits 3-21 of the second PTE address specify the starting address of a second page table. Bits 22-31 of the second PTE address specify an offset from the start of the second table to some PTE (labelled PTEm in FIG. 158). The second PTE specifies the starting address of a page, as shown at 5 in FIG. 158.
The second PTEm's bits 13-31, the page address, become bits 3-21 of the physical address and the page offset specified in bits 22-31 of the logical word address becomes bits 22-31 of the physical address, as shown at 6 in FIG. 158. This last value is the final physical word address.
The physical page table address for the low order page table of a two-level page table is in bits 18-31 of the high order page table entry (HOPTE) which must be fetched from the main memory. Thus, the second possible source of the physical page table address is the memory data register (MD) 105 which holds the data that arrives on the physical memory data (CPM) bus 20 as MD 18-31. A suitable page table multiplexer 107 is used to select which of the two sources will drive the physical address bus when its outputs are enabled.
The third and final source is to drive the physical page address bus 27 directly through a physical mode buffer 108, such buffer being used to address physical memory directly (PHY 8-21) from buts LA 8-21 of the logical address bus. Such buffer is enabled while the ATU unit is turned off (i.e., no address translation is required) since the physical address in that mode is the same as the logical address and no translation is necessary.
Bits PHY 22-31 of the physical address are offset by displacement bits, there being three possible origins for the offset. The first source of such offset is from bits LA 22-31 of the logical address bus which bits are used while in physical mode (no address translation is necessary) as well as the offset in the object page. The second source of the offset is bits LAR 4-12 (referred to as two-level page table bits in FIG. 158 above) of the logical address register which is used as an offset within the high order page table during a long address translation. Since this source is only nine bits long and page table entries are double words aligned on even word boundaries, a ten bit offset (to form PHY 22-31) is constructed by appending a zero bit to the least significant bit. The final source for the offset is bits LAR 13-21 (referred to as one-level page table bits in FIG. 158 above) of the logical address register which is used as an offset within the low order page table during a long address translation. A zero bit is appended to the least significant bit of this source also. Offset multiplexer 109 is used to select the desired one of such three offset sources.
The following discussion summarizes the address bit sources for forming a low order or high order page table entry address in main memory in making a long address translation. The address of the page table entry is formed from address fields in a segment base register (SBR) and from address fields in the logical address register. The address fields of a segment base register can be depicted as follows:
______________________________________ ##STR5## SEGMENT BASE REGISTER ______________________________________
Depending on whether a one-level (low order) or a two-level (high order) page table entry is called for, the SBR address field comprising bits 4-12 or the SBR address field comprising bits 13-21 is transferred to the memory data register 105 to form the higher order bits of the page table entry. As mentioned above, the eight SBR registers are located in 8 of the 256 locations of scratch pad registers on the ATU. This use of such scratch pad locations for the segment base registers can be contrasted with prior known systems wherein the segment base register (or registers comparable thereto) in a segment, or ring, protection memory system are all located at specified locations in the main memory. By placing them in a scratch-pad memory located in a processing unit of the system, as in the ATU unit here, the higher order page table entry bits are acquired more rapidly than they would be if it were necessary to fetch them from main memory and, hence, the speed at which page table entries can be made is improved considerably.
One of the bits of an SBR (identified above as "V" bit) is examined to determine whether the SBR contents are valid. Another bit (identified above as "L" bit) is examined to determine whether a 1-level or a 2-level page table entry is required so that the correct field is supplied to the memory data register.
Other bit fields of the SBR are used to determine whether a Load Effective Address (LEF) instruction (such LEF instruction is part of the Eclipse instruction set as explained more fully in the above cited publications therein) or I/O instruction is required. Thus in a selected state the LEF Enable bit will enable an LEF instruction while a selected state of the I/O Protect bit will determine whether an I/O instruction can be permitted. The remaining field of the SBR contains the address offset bits.
As is also seen in FIG. 79 a variety of protection checks are made for each reference to memory, which protection checks are made by the use of protection store unit 104, protection logic unit 110 and ring protection logic unit 111 for providing appropriate fault code bits (FLTCD .0.-3) which are supplied to the micro-sequencer (described below) via driver 112 on to the CPD bus 25 for initiating appropriate fault micro-code routines depending on which fault has occured.
The following six protection checks can be made:
1. Validity storage protection
2. Read protection
3. Write protection
4. Execute protection
5. Defer protection
6. Ring maximization protection
A validity storage protection check determines whether the corresponding block of memory to which a memory reference is made has been allocated and is accessible to the current user of the system. The validity storage field is a one-bit field which is located, for example, at bit zero of each of the segment base registers (located on an ATU board as discussed above) or at bit zero in each of the high order page table entry addresses and low order page table entry addresses. In a particular embodiment, for example, a "1" indicates that the corresponding block has been so allocated and is accessible whereas a "0" indicates that the user cannot use such a memory block.
Generally when a new user enters the system all pages and segments in the logical address space which are allocated to that user, except those containing the operating system, are marked invalid. Validity bits are then set valid as the system begins allocating logical memory to such new user. If a user makes a memory reference to an invalid page, an invalid page table, or an invalid segment, the memory reference is aborted and validity storage protection error is then signaled by the fault code bits on the CPD bus.
The read protection field is a one-bit field normally located at a selected bit (bit 2, for example) in each of the lower order page table entry addresses and a check thereof determines whether the corresponding object page can or cannot be read by the current user. If the page cannot be read, a read error is signaled by the fault code bits on the CPD bus. In a similar manner a check of the write protection error field determines whether the corresponding object page can be written into by the current user, an appropriate write error being signaled by the fault code bits if the user attempts to write into a page to which he is not allowed.
The execute protection field is a one-bit field which is located at a selected bit (e.g. bit 4) in each of the low order page table entry addresses and a check thereof determines whether instructions from a corresponding object page can or cannot be executed by the current user. If such an instruction fetch is not allowed, an execute error is signaled by the fault code bits on the CPD bus. Execute protection is normally checked only during the first fetch within a page and any additional instruction fetches are performed using the physical page address from the first fetch, which for such purpose is retained by the instruction processor.
When a user is attempting to reference a location in memory and is utilizing a chain of indirect addresses to do so, the system will abort the operation if a chain of more than a selected number of said indirect addresses is encountered. For example, in the system under discussion if a chain of more than sixteen indirect addresses is encountered the operation is appropriately aborted and a defer error is signaled by the fault code bits on the CPD bus. Such protection is utilized, for example, normally when the system has performed a loop operation and the system, because of a fault in the operation thereof, continues to repeat the indirect loop addressing process without being able to break free from the loop operation.
Ring maximization protection is utilized when the user is attempting to reference a logical location in memory in a lower ring (segment) than the current ring of execution (CRE 1-3). Since such operation is not permitted by the system, the operation must be aborted if the user attempts to reference a lower ring than currently being used and a ring maximization error is signaled on the CPD bus. Since the logical address space is divided into eight rings, or segments, a ring which the user desires to reference can be indicated by bits 1-3, for example, of the logical address.
The specific logic circuitry utilized for such protection checks (i.e., the protection store 104 and the protection logic 110 and the protection logic 111 associated therewith) is shown in FIGS. 80 and 81. Thus, logic for the generation of the read error, write error, execution error and validity error signals is shown in FIG. 80 and logic for generating the defer error and ring maximization error signals being shown in FIG. 81.
With respect to the protection system, since logical address space is partitioned into eight hierarchical regions (i.e. the "rings" or "segments") the partitioning can be delineated by the segment field of the logical address. Thus, segment number 0 is always assigned to ring 0 (ring 0 being the ring in which only priviledged instructions can be executed), segment 1 is always assigned to ring 1, and so forth. Such approach differs from previous systems using a segmented hierarchical address space in that the ring number is not independent of the logical address space. In contrast, in the system discussed here, each ring is directly bound in the space so that segment 0 is always allocated to ring 0, segment 1 to ring 1, and so forth.
The access field in a page table entry comprises three bits (MD 2-4) is shown in FIG. 79 and indicates the capabilities of the referenced data item in the logical address space, i.e. as to whether the reference data item is to be a read access, a write access, or an execute access, the protection store 104 responding to such bits to produce either a read enable signal (RD ENB), or a write enable (WR ENB) or an execute enable (EX ENB). The ring protection governs the proper interpretation of the access privileges of the user to a particular ring, a user being permitted access only to selected, consecutively numbered rings. Thus, access can only be made to a bracket of rings (an access bracket) if the effective source for such reference is within the appropriate access bracket. For example, the read bracket of a data reference in any ring is the ring number. That is, a data address reference to segment 5 (ring 5), for example, can never legitimately originate from an effective source which is greater than 5. In other words an effective source in segment 5 can never reference a ring lower than ring 5 and, therefore, if a reference from an effective source greater than 5 attempts to access ring 5 a ring maximum error (MAX ERR) will be signaled as shown by the logic in FIG. 13. A table showing such ring protection operation is shown below:
______________________________________ Effective Source Target Space Space RING 0 RING 1 Ring 2 . . . RING 7 ______________________________________ RING 0 Val-R0 Val-R1 Val-R2 . . . Val-R7 RING 1 Fault Val-R1 Val-R2 . . . Val-R7 RING 2
Fault Fault Val-R2 . . . Val-R7 . . . . . . . . . . . . . . . RING 7 Fault Fault Fault . . . Val-R7 ______________________________________
In summary, in order to make a ring access, the ring maximization function is used to determine whether or not the reference is a valid ring reference and, if it is, the page table entry that reference the address datum is examined to see if the page is a valid one. Then, if the read protection bit indicates that such valid page can be read, the read can be performed. If any one of the examinations shows a protection error (i.e., ring maximization error, validity error, or read error) the read is aborted and an appropriate fault code routine is called. Similarly, appropriate examination for protection errors for write access and execute access situations can also be performed.
In an hierachical address space such as discussed above, it is desirable to mediate and authenticate any attempt to switch rings, i.e., to obtain access to a ring (segment) other than the ring which is currently being used (a "ring crossing" operation). The performing of a ring crossing operation is authenticated as follows.
Any ring crossing attempts occur only as a result of an explicit attempt to do so by a program control instruction, and such explicit attempt can occur only if the following conditions are satisfied.
(1) The program control instruction is of the form of a subroutine "call", i.e., where access is desired to a subroutine in another ring (LCALL-see Appendix B), or a subroutine "return", i.e., where a subroutine in another ring has been accessed and it is desired to return to the original ring (WRTN and WPOPB--see Appendix B). All other program control instructions (e.g., JUMP) ignore the ring field of the effective address required for the instruction and such instructions can only transfer to locations within the correct segment. (2) The direction of a subroutine call crossing must be to a lower ring number (i.e., inwardly toward ring 0) wherein the lower ring has a higher order of protection and the current ring of execution and the direction of a subroutine return crossing must be to a higher ring number (i.e., outwardly away from ring 0) wherein the higher ring has a lower order of protection than the called ring containing the subroutine. Outward calls and inward returns are trapped as protection faults.
(3) The target segment of the effective branch address is not in the segment identified by bits 1-3 of the program counter.
In the above conditions are met the return address for outward returns is merely interpreted as a normal word address. However, if the above conditions are met for an inward call, the branch address is interpreted as follows:
______________________________________ ##STR6## Inward Call Branch Address ______________________________________
Bits 16-31 are interpreted as a "gate" into the specified segment (SBR of bits 1-3) in the target space. The gate number is used to verify that the specified gate is in the called segment and, upon verfication, to associate on instruction address with the specified gate via a "gate array" in the called segment, as discussed below.
The location of the gate array in any called segment is indicated by a pointer contained in particular locations of the called segment (e.g., in a particular embodiment the pointer locations may be specified as locations 34 and 35 in each segment. The structure of the gate array is as follows:
______________________________________ ##STR7## Gate Array ______________________________________
The gate number of the pointer which referenced the target segment is compared with bits 16-31 of the first 32 bits of the gate array. If the gate number is greater than or equal to the maximum number of gates in the gate array, the ring crossing cell is not permitted and a protection fault occurs (if the maximum number of gares is 0, the segment involved cannot be a valid target of an inward ring crossing call operation).
If the gate number is less than the maximum number of gates, the gate number is then used to index into one of the gates of the gate array which follows the first 32 bits thereof. The contents of the indexed gate are read and are used to control two actions. First, the effective source is compared to the gate bracket bits 1-3 of the indexed gate. The effective source must be less than or equal to the referenced gate bits and, if so, the PC offset bits 4-31 become the least significant 28 bits of the program counter and bits 1-3 of the program counter are set to the segment containing the gate array.
If the gate in a ring crossing operation, as described above, is a permitted entry point to the ring to which the crossing is made, a new stack is constructed. In order to do so a stack switching operation must occur since there is only one stack per ring. Thus, before the new stack can be created, the contents of the current stack management registers must be saved at specified memory locations of the caller's ring. The callee's stack can then be created, the arguments from the caller's stack being coupled onto the newly created callee's stack, the number of such arguments being specified by the X or the LCALL instruction (see Appendix B). An appropriate check is first made to determine whether copying of all of the arguments would created a stack overflow condition. If so, a stack fault is signalled, the ring crossing being permitted and the fault being processed in the called ring.
In order to emulate operation of ECLIPSE address translation operations appropriate emulation control signals for placing the ATU in the ECLIPSE operating mode are required as shown by emulation control logic unit 115 which, in response to coded instructions generated by the microsequencer board 13 produces such signals to permit operation for 16-bit addresses equivalent to the memory management protection unit (MMPU) of ECLIPSE comparators as described in the aforesaid publications thereon.
Specific logic circuitry for implementing the various blocks of the address translation unit shown in FIGS. 79-81 are shown in FIGS. 82-100. FIG. 82 depicts the translation store unit 100 supplied with bits MD 18-31 from the memory data register
105 and in turn supplying the translated physical address bits 8-21 which have resulted from a translation of the logical address bits LA 15-21. FIG. 82 also shows the page table address multiplexer unit 107 and physical mode buffer unit 108. In addition, such figure includes the "last block" register unit 116 which during an ECLIPSE MMPU emulation operation provides the physical address bits PHY 8-21. FIG. 82 also shows the LMP Data Register. FIG. 83 shows Tag Store 102 and Protection Store
104. Tag comparator unit 105 is depicted in FIG. 84. FIG. 85 shows the logical address register 101, while physical address offset multiplexer 109 and the logical address register CPD bus driver unit are shown in FIGS. 86 and 87, respectively. The physical address bus driver units for filing the appropriate physical address bit PHY 8-21 are shown in FIG. 88.
Protection logic including fault detection and cache block crossing trap logic is depicted in FIGS. 89-92, protection logic identification encoder unit 110 being shown in FIG. 89, the fault code bit drive unit 112 being shown in FIG. 90, ring protection logic circuit 111 being shown in FIG. 91 and the fault detection and cache block crossing logic being shown in FIGS. 92 and 93.
Validity store unit 103 is shown in FIG. 94 together with translation purge logic and the multiplexer associated therewith. The translation register of FIG. 79 is depicted in detail in FIG. 95. The reference/modify storage and control logic unit is shown in FIG. 96, the state save drive unit associated therewith being depicted in FIGS. 97. The 16 bit MMPU emulation control logic is shown in FIG. 98.
ATU timing logic is shown in FIG. 99 and suitable system code interface logic is shown in FIG. 100.
INSTRUCTION PROCESSOR
The instruction processor (IP) 12 is utilized to handle the fetching and decoding of macro-instructions for the data processing system of the invention. The instruction processor operates both at and ahead of the program counter and its primary function is to provide a starting microaddress (ST.mu.AD) for each micro-instruction, which starting microaddress is supplied to the microsequencer unit 13. Subsidiary functions of the instruction processor (1) to provide the source and destination accumulator designations, (2) to provide the effective address calculation parameters for the arithmetic logic unit and (3) to provide sign or zero extended displacements for making memory references or for in-line literals (immediates) to the arithmetic logic unit (ALU).
As seen in FIG. 101, the instruction processor includes instruction cache logic 120 (ICACHE), macro-instruction decoding logic 121 (which includes an instruction decode register as shown in FIG. 103) and program counter/displacement logic 122 as described below. The ICACHE logic functions as a pre-fetcher unit, i.e., the instruction cache (ICACHE) thereof obtains a block of subsequent macro-instructions for decoding, which block has been accessed from memory while the previous macro-instructions are being executed. The ICACHE stores the subsequent block of macro-instructions even if such macro-instructions are not immediately going to be used by the microsequencer. The decoding logic 121 of the instruction processor responds to a macro-instruction from ICACHE, decodes the operational code thereof (opcode) to provide the opcode description information for control and status logic 123 and to supply the information needed therefrom to the starting micro-address (ST.mu.AD) register 124 (and thence to the micro-sequencer) to identify the starting micro-address of the required micro-instructions.
The displacement logic 122 supplies the displacement data to the ALU if the index for such displacement is on the ALU board. If the index for the displacement is the IP program counter, the displacement logic combines the displacement information with the program counter information available at the instruction processor to form the logical address for supply to the LA bus.
Thus, in an overall IP operating sequence, a macro-instruction is read from an ICACHE storage unit of the ICACHE logic 120 into the decode logic 121 which thereupon decodes the instruction opcode and generates the starting micro-address for the micro-sequencer. During the decoding and starting micro-address generation process, the instruction processor simultaneously reads the next macro-instruction from the ICACHE into the decode logic. While the micro-sequencer is reading the first micro-instruction, the decode logic is decoding the next macro-instruction for generating the next starting micro-address. When the micro-instruction at the starting micro-address is being executed, the micro-sequencer reads the next micro-instruction from the next starting micro-address. Accordingly, a pipeline decoding and execution process occurs.
As seen in the more detailed FIG. 102, the ICACHE logic 120 includes an ICACHE data store unit 130, a tag store unit 131 and a validity store unit 132. As discussed with reference to the system cache 17 of the memory system, the operation of the ICACHE is substantially similar in that the tag portion (PHY ICP 8-21) of the address of each desired word of the macro-instruction is compared at comparator 133 with the tag portions of the addresses stored in the TAG store 131 of those words which are stored in the ICACHE data store 130. In addition, the validity store unit demonstrates whether the desired address is a valid one. If the address is valid and if a tag "match" occurs, the 32-bit double word at such address is then supplied from the ICACHE data store 130 to the decode logic 121.
If the required macro-instructions in the appropriate ICACHE block are not present on the current physical page (i.e., the physical page corresponding to the logical page value of the current value of the program counter) which is stored in the ICACHE data store 130 (i.e., a Tag match does not occur) or if the validity bit is not set, an ICACHE "miss" occurs and the cache block containing the macro-instructions must be referenced from memory. Such ICACHE block memory reference may be to the system cache (SYS CACHE) or to the main memory, if the system cache access also misses. When the accessed ICACHE block is fetched, the desired macro instructions thereof are written into the ICACHE data store 130 from CPM register 134 and the block is simultaneously routed directly into the decoding logic through bypass path 135. The ICACHE logic can then continue to prefetch the rest of the macro-instructions from the fetched page as an instruction block thereof, placing each one into the ICACHE data store 130 as they are accessed. The control logic for the ICACHE logic 120 is ICACHE/ICP control logic unit 136.
The decode logic, shown in more detail in FIG. 103, includes instruction decode units 140 and 141 for decoding the opcode portion of the macro-instructions. Decode unit 140 is used for decoding the opcodes of the original basic instructions for the system of which the present system is an extension. Thus, in a specific embodiment as discussed above, such basic instructions may be the NOVA and ECLIPSE instructions for Data General Corporation's previous NOVA and ECLIPSE system. Decode unit 141
is used for decoding the opcodes of the extended instruction set, e.g. the "Eagle" macro-instructions mentioned above.
The opcodes are supplied from an instruction decode register (IDR) 142 having three storage register sections, each capable of storing a word and identified as IDR A, IDR B and IDR C. The opcode of each macro-instruction is stored in the IDR A section while displacements are stored in the IDR B and C sections. An IDR shifter unit 143 is used to shift the desired opcode portion of the instruction accessed from the ICACHE data store 130 into the IDR A section of IDR 142 and to shift the appropriate displacement words of the instruction, if any, to the IDR B and IDR C sections thereof. The control logic for the IDR and the IDR shifter units is IDR/shifter control unit 137, shown in FIG. 102.
When the macro-instruction has been routed to the decode logic, the decode units 140 or 141, as required, decode the opcode portion thereof to provide opcode description (OPCD DSCR) information, including the length of the instruction (i.e., whether the instruction comprises a single, or double or triple word). When the entire instruction has been supplied to the decode logic (from ICACHE data store 130) a SET IDR VLD signal is generated to produce an IDR VLD signal at IDR/shifter control
137 (FIG. 102). Following the decoding process, the starting micro-address is loaded into the ST.mu.AD register 144 from either decode PROM 140 or 141 depending on whether the macro-instruction is a basic or an extended instruction. Control of the loading of ST.mu.AD register 64 resides in ST.mu.AD load control unit 145.
The displacement word or words, if any, are generally present in IDR B or C (for certain NOVA instructions a byte displacement may be extracted from IDRA, although generally for almost all other instructions displacements are extracted from IDRB and IDR), being extracted from the displacement logic 146, as shown in FIG. 104. The displacements are sign or zero extended, as necessary, and are clocked into a displacement register thereof so as to be made available either directly to the logical address (LA) bus or to the CPD bus for use at the ALU unit, as discussed below.
When the starting micro-address has been clocked into ST.mu.AD register 144, an UPDATE signal is issued by the IP status logic unit 138 (FIG. 102) to inform the IDR/shifter control 143 that the decoded information has been used and can be shifted out of IDR 140/141. The decoding of subsequent macro-instructions continues until a discontinuity in the straight-line decoding operation occurs. When a jump in the straight-line operation occurs the micro-sequencer issues an IPSTRT signal to the program counter register 147 of the instruction processor (FIG. 20) so that a new program counter address (LA 4-31) can be placed in the program counter register from the logical address bus. The starting micro-address register 144 is reset and the starting micro-address of an appropriate wait routine, for example, is placed therein until the decoding process for the instruction associated with the new program counter can begin.
In some situations the sequence of macro-instructions which are being decoded are present on more than one physical page. Under such conditions when the ICACHE control detects the end of the page which is stored in the ICACHE data store 130, a special routine must be invoked in order to fetch the next page into the ICACHE store 130 so as to continue the prefetching operation on the new page. Thus, when the last instruction of a particular page has been decoded and the decode pipeline is effectively empty, the starting micro-address register is loaded with the starting micro-address of a suitable page control routine which accesses the required new page and permits the next page to be loaded into ICACHE store 130 via physical page register 134 so that the instruction processor can continue with the decoding of the macro-instructions thereon.
If a macro-instruction is not on the page contained on the ICACHE store 130, the correct page must be accessed from either the system cache or main memory because of an ICACHE "miss" in the instruction processor. Access to the system cache is provided at the same system cache input port as that used by the address translation unit (ATU). In the system of the invention, however, the ICACHE is given a lower priority than the ATU so that if the ATU wishes to access the system cache the instruction processor must hold its access request until the ATU has completed its access.
The use of ICACHE logic as described herein becomes extremely advantageous in programs which utilize a short branch backwards. If a macro-instruction branch displacement is less than the number of words in the ICACHE data store there is a good chance that the required macro-instructions will still be stored locally in the ICACHE data store and no additional system cache or main memory references are required.
In a particular embodiment, for example, the overall ICACHE logic 120 may comprise a single set, direct mapped array of 256 double words in data store 130 plus Tag and Validity bits in Tag Store 131 and Validity Store 132. Data is entered into the data store as aligned double words and the ICACHE data store is addressed with the eight bits which include bits ICP 23-27 from the instruction cache pointer (ICP) unit 150 shown in FIG. 105 and bits ADR 28, 29, 30 from unit 139.
A copy of the Tag store 131 of the instructor processor's ICACHE unit is also kept in the system cache, the latter cache needing such information so that it can inform the instruction processor when data has been written into the ICACHE.
The validity store 132 is arranged, for example, in a particular embodiment, as 64 double words by four validity bits in order to indicate the validity of each double word in the ICACHE data store. Each initial fetch into a new block of instruction words will set the corresponding validity bit for the double words and reset the remaining three validity bits. During a prefetch operation into the same block, the corresponding validity bit for the prefetch double word is set while the remaining three validity bits remain the same. The prefetching operation stops when the last double word in the block has been prefetched in order to avoid unnecessary system cache faults.
If the ICACHE operation is such that the end of a physical page is reached and it is necessary to obtain the next physical page address for the next logical page of the program counter (PC bits 4-21), the ICACHE control logic unit 136 (FIG. 102) asserts a signal (identified as the ICAT signal) which is supplied to the ST.mu.AD load control logic 145 (FIG. 103). When the last macro-instruction at the end of the current page has been decoded, the ST.mu.AD control logic 145 supplies the starting micro-address for the ICAT micro-code routine which thereupon performs the necessary address translation operation for a transfer of the next physical page address for the ICACHE data store 130.
The instruction processor utilizes two pointers to the instruction stream. The first pointer is the program counter register 147 (FIG. 104) which holds the logical address of the instruction which is being executed, and the second pointer is the instruction cache pointer (ICP) 150 (FIG. 106) which holds the logical address of the next macro-instruction which is needed for the decode logic. A separate register PICP 152 (physical instruction cache pointer) holds the physical page address of the logical page referred to by bits 4-21 of the instruction cache pointer (ICP). Thus the ICP 150 functions as the prefetch logical address pointer and the PICP functions as the prefetch physical address pointer. The program counter 147 and the ICP 150
are loaded from the logical address bus at the start of an instruction processor operation. The ICP is incremented ahead of the program counter as the decoding pipeline operation is filled. On an ICACHE fault, or miss, the PICP physical address is used to reference the memory and the ICP address is used as a pointer to the next logical page address for address translations when the end of the correct page has been reached.
In accordance with the instruction processor operation the optimum performance is achieved when the instructions are locally available in the ICACHE, such instructions thereby becoming substantially immediately available when the micro-sequencer requests them. Instructions which are not locally available in the ICACHE take an amount of time which is dependent on system cache access operation and page fault routine operations.
The macro-instruction decoding logic utilizes three 16-bit fields identified as the IDR A, IDR B, and IDR C fields, as mentioned above. The "A" field contains the opcode while the "B" and "C" contain either the displacement(s) for the instruction in the "A" field or one or more fields of the macro-instruction which follows in the instruction stream. The instruction decode register, IDR 142, is arranged to keep all three fields full, if possible, by sending word requests to the ICACHE (ICP control unit 136) when any of the three IDR fields is empty. As mentioned above, if the ICACHE word request results in an ICACHE "miss" a system cache fetch is initiated.
The "A" field of the instruction decode register 142 is used by the decode logic PROMs 140 or 141 to decode the opcode of the macro-instruction and, also to provide the starting address of the macro-instruction which is required. The "B" and "C" fields determine the displacements, if any, that are required. Each field is one word in length and therefore the longest instruction that the instruction processor can decode and canonicalize the displacement for has a maximum length of three words.
When the A field of the instruction decode register is full, the decode PROMs 140 or 141 decode the opcode of the instruction. If the entire instruction, including opcode plus displacement, is in the instruction decode register, a signal IDR VLD is asserted by the IDR shifter control logic 137 to inform the IP status logic 138 that an entire instruction is ready to be decoded so as to provide a starting micro-address for ST.mu.AD register 144. The displacement logic 146 which extracts the displacement, either sign or zero extends it, as necessary, and then loads it into a displacement register. If the displacement index is on the ALU board the displacement is latched onto the CPD bus via latch unit 153 for supply thereto. If the displacement index is the PC register 147, the displacement is added to the PC bits at adder 148 and supplied to the logical address bus via latches 149, as shown in FIG. 104.
During the above loading processes the instruction decode register 142 is shifted by the length of the instruction that has been decoded so as to be ready to receive the next instruction, i.e., a shift of one, two or three words. The IDR shifter unit 143 serves to provide such shift of the contents of the instruction decode register 142. A shift of three words, for example, completely empties the instruction decode register which is then ready to receive the next instruction from the ICACHE (or directly from memory on an ICACHE "miss"). The shifter, for example, allows either word in a double-word instruction which has been accessed from the ICACHE to be directly loaded anywhere into the instruction decode register. The placement in IDR 142
is determined by examination of the validity bits in the IDR. Thus if the "A" field is invalid, the incoming instruction data would be loaded into the "A" field. Whenever any of the three fields in the instruction decode register 142 are empty, a word request is made of the ICACHE via ICACHE control logic 136 for accessing the next instruction as determined by the ICACHE pointer (ICP) 150, bits 23-27 of which uniquely determine which double-word in the ICACHE is to be accessed. If the instruction is a single word instruction, the ICP bits 28-30 and the ICPX bits 28-30 obtained from the fetch request control logic 151 (FIG. 105) uniquely determine which word of the double word is to be used as the instruction as shown at word pointer logic 139 (FIG.
102).
If the instruction decode register 142 has at least two fields empty and a word pointer points to an even double word, then the double word would be loaded into two empty fields of the IDR. After loading, the ICACHE pointer 150 would be incremented so that it points to the next double word. If the IDR has only one empty field and a word pointer points to an even double word, then the first word would be loaded into the IDR and the word pointer would be sent to point to the second word of the double word and the ICACHE pointer remains the same. When the word pointer points to the second word, only one word can be accessed from the ICACHE and loaded into the instruction decode register.
The decode logic utilizes predecode logic 154 (FIG. 103) which is used to select the location in one of the two sets of decode PROMs 140 and 141. As mentioned above, one set of PROMs 140 holds a basic set of instructions (e.g., NOVA/ECLIPSE instructions) while the second set of PROMs 141 holds the extended instructions (e.g., EAGLE instructions). The decoding process for the basic set of decode PROMs 140 is performed in two stages, the first level being performed in the predecode logic 154
at the output of the shifter which is used to place the basic macro-instructions into the correct form so that the decode logic 140 can decode the opcode and be ready with the displacement information in the correct form and sequence. Such logic is shown in more detail in FIG. 122. The instructions for the extended set are already in the desired form and need not be predecoded before being supplied to the decode PROMs 141. In either case each incoming macro-instruction maps into at least one location of a selected one of the decode PROMs 140 or 141 to produce the required opcode descriptors and the required starting micro-address for supply to the micro-sequencer.
The decision to select the output of decode PROM 140 (e.g., NOVA/ECLIPSE) or decode PROM 141 (e.g., EAGLE) is determined by examining selected bits (e.g., bits .0., 12-15 as discussed above) of IDR A. As described above, the selection of the decode PROM is not determined by a separately designated "mode" bit as in previous systems, which prior process causes the decode operation to be mutually exclusive. In contrast, the present system in selecting the appropriate decode operation performs such operation on an instruction by instruction basis since each instruction inherently carries with it the information required to determine such decode selection.
Specific logic circuitry for implementing the block diagram of the instruction processor to provide the operation discussed above with reference to FIGS. 101-106 is shown in FIGS. 107-136. ICACHE data store 130 and the ICACHE data store address input logic are shown in FIGS. 107 and 108, respectively, while CPM register 134 supplying cache block words from memory being shown in FIGS. 109 and 109A. ICACHE tag store 131 is also depicted in FIGS. 109B and 109C and ICACHE validity store 132, together with the validity store address input is shown in FIGS. 110 and 111, respectively. Comparator 133 and logic for providing the SET IDR VLD signal are shown in FIG. 112.
FIG. 113 shows IDR shifter 143, the IDR shifter control logic 137 being shown in FIG. 114. The instruction decode register (IDR) unit 142 is depicted in FIG. 115 and include IDR sections A, B and C as shown.
With reference to the ICACHE logic circuitry the ICACHE pointer (ICP) logic 150 and the ICP logical address driver logic of FIG. 106 is shown in more detail in FIGS. 116 and 117, respectively. The ICACHE pointer pre-fetch request control logic
151 and the physical ICP translation register 152 of FIG. 105 is depicted in more detail in FIGS. 118 and 119, respectively. Other general ICACHE control logic is further depicted in FIG. 120.
The driver logic which provides inputs FASA.0.-15 from the CPD bus to IDR A as shown in FIG. 103 is depicted in FIG. 121, while the instruction pre-decode logic and control therefor is shown in FIG. 122. Decode PROMS 140 and 141 which effectively include the ST.mu.AD register 144, together with the IP status logic 138 are shown in FIG. 123. The starting microaddress control logic 145 is depicted in detail in FIG. 124.
With reference to the displacement and program counter portion of the instruction processor, the displacement logic 146 is shown in FIG. 125, the displacement multiplexer associated therewith being depicted in FIG. 126. The sign extend (SEX) logic is shown in FIG. 127, while the zero/ones extend logic is shown in FIG. 128. FIG. 129 shows the displacement increment buffer of FIG. 104 while the displacement latch and drivers 153 are depicted in FIG. 130. FIG. 131 shows program counter register 147 and the CPD bus driver of FIG. 104, while adder 148 and the PC+DISP latch and driver units 149 are shown in FIGS. 132 and 133, respectively. Program counter clock log