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United States Patent4409656
Andersen , ; et al.October 11, 1983
Title
Serial data bus communication system
Abstract
A node device for use in a digital data processing and communications system of the type utilizing a bus organization for facilitating the interconnection of a large plurality of digital data processing devices (user devices) in which redundant cables are employed. The node devices are interposed between the user devices and the redundant cables to permit automatic reconfiguration of the interconnection of the user devices in the event of malfunctioning or severing of one or more of the cable sets within a minimum period of time. The node devices provide the user devices with the structure needed to detect and diagnose system problems and to effect recovery procedures. In accordance with the invention, one of the plurality of nodes functions as the Bus Controller and by sampling the remaining nodes in the system, it determines the priority with which user devices may transmit or receive data over the bus. Each of the nodes employed is substantially identical and any one may be selected to function as the Bus Controller. Each includes a Microprogrammed Controller and necessary firmware to permit the controller to function in conjunction with special purpose hardware including a Programmable Logic Array (PLA) configured to perform a pre-processing function on control line inputs so that poll/response traffic on the active cables can continue with a minimum of delay.
Inventors:Andersen; Steven C. (Prior Lake, MN), Penkauskas; Thomas P.  (Eagan, MN), Kassel; James W.  (St. Paul, MN), Newcomer; Stephen O.  (Apple Valley, MN)
Assignee:Her Majesty the Queen, in right of Canada as represented by the Minister (Ottawa, CA)
Appl. No.:333068
Filed:December 21, 1981
Current U.S. Class:709/250 
Field of Search:364/200,900
U.S. Patent Documents
3771134November 1973Huettner et al.
4086627April 1978Bennett et al.
4106091August 1978Hepworth et al.
4208714July 1980Eklund et al.
4237534December 1980Felix
4257100March 1981Syrbe et al.
4262357April 1981Shima
Primary Examiner: Springborn; Harvey E.
Attorney, Agent or Firm:Haugen; Orrin M. Nikolai; Thomas J.
Parent Case Text


This is a continuation of application Ser. No. 130,125 filed Mar. 13, 1980 and now abandoned.
Claims

What is claimed is:
1. In a serial data bus transmission system of the type used to interconnect a plurality of user devices for message intercommunication over transmission cables, said system including a plurality of cables, one of which acts as an active control cable and one of which acts as an active message cable at a given time, with at least one bus access module coupled to each of said plurality of cables, a plurality of node devices for coupling said user devices to said bus access modules, each of said node devices comprising in combination:
(a) bus input/output means including data format conversion means coupled to said bus access modules for selecting said active ones of said control cable and said message cable and for transmitting or receiving digital messages and control signals therethrough;
(b) a control bus coupled to said bus input/output means;
(c) a message bus coupled to said bus input/output means;
(d) control line sequencer means coupled to said control bus for receiving control signals therefrom and including logic means for performing preprocessing functions relative to said control signals for determining whether said control signals are intended to affect that node device and are of a proper format;
(e) controller means adapted to receive preprocessed data signals from said control line sequencer and to develop command signals in accordance with said preprocessed data signals, and further status indicators;
(f) means including said control bus and said bus input/output means for sending said command signals on said active control cables to other of said plurality of nodes coupled to said active control cable; and
(g) means responsive to said command signals for controlling the flow of messages over said message bus and between said plurality of user devices.

2. Apparatus as in claim 1 wherein said data format conversion means comprises a serial-to-parallel and a parallel-to-serial converter coupled between said bus access module and said control bus or said message bus.

3. The system as in claim 1 wherein each of said nodes further includes:
(a) a storage unit associated with said controller means, a source bus coupling plural register means to said controller storage unit, a destination bus coupling said controller storage unit to further plural storage means associated with said control bus, and a user connection, said user connection being coupled to receive control and message words from a user device;
(b) means coupling said user connection to said source bus; and
(c) means coupling said message bus to said user connection for two-way data transmission therebetween.

4. The serial data bus transmission system of claim 3 wherein said controller means comprises a microprogrammable controller.

5. The serial data bus transmission system of claim 3 wherein said user connection comprises a user bus.

6. Apparatus as in claim 1 wherein said bus input/output means includes:
(a) multiplexer means coupled between said control bus and message bus and said plurality of cables;
(b) an active bus number register having an input and an output, said output being connected to said multiplexer means; and
(c) means coupling said controller means to said input of said active bus number register whereby said active control and message cables are definable by digital data originated by said controller means.

7. The serial data bus transmission system of claim 6 wherein said controller means comprises a microprogrammable controller.

8. Apparatus as in claim 6 and further including means in said node for causing new information to be loaded from said controller means into said active bus number register upon detection of a fault on the one of said plurality of cables previously acting as said control cable or said message cable, such that a different one of said plurality of cables is substituted for the one on which the fault was detected.

9. Apparatus as in claim 8 wherein said bus input/output means further includes:
(a) activity monitoring means coupled to each of said plurality of cables for detecting the time relationships of signal patterns detected on said plurality of cables and thereby determining whether a cable is carrying control or message type information;
(b) means in said activity monitoring means for developing a control flag indicative of control type activity;
(c) masking means connected to receive said control flag and further control signals from said controller means for selectively causing one or more of said control flags to be ignored; and
(d) means coupling the output of said masking means to said controller means for causing it to enter a new word into said active bus number register.

10. The serial bus transmission system of claim 9 wherein said controller means comprises a microprogrammable controller.

11. The serial data bus transmission system of claim 8 wherein said controller means comprises a microprogrammable controller.

12. Apparatus as in claim 1 wherein said control line sequencer comprises:
(a) register means connected to said control bus for at least temporarily storing control words carried by said control bus and applying said control words to said logic means; and
(b) buffer means coupled to the output of said logic means for receiving and at least temporarily holding one or more logic output control codes from said logic means and for transmitting said logic control codes sequentially to said control bus or to said controller means.

13. Apparatus as in claim 12 wherein the sequential transmission of said logic control codes is controlled by said controller means.

14. The serial data bus transmission system of claim 12 wherein said logic output control codes are stored in said logic array.

15. The serial data bus transmission system of claim 14 wherein said logic output control codes are stored in said logic means.

16. The serial data bus transmission system as in claim 1 wherein one of said plurality of nodes is a bus controller node and wherein said command signals from said bus controller node include poll and select commands directed to other nodes in said system.

17. Apparatus as in claim 16 and further including a first list and a second list in said bus controller node, each of said lists connected for control by said controller means and storing the address of all predetermined nodes in the system with the address of those nodes having a priority stored in said first list and with the addresses of those nodes having no priority stored in said second list; means for sequentially applying poll commands to those nodes pointed to by the address in said first list; and means for subsequently sequentially applying poll commands to those nodes pointed to by the addresses in said second list.

18. The apparatus as in claim 17 and further including sub-cycle counter means adapted to receive an initial value from said controller means; means for incrementing said sub-cycle counter at a fixed rate in synchronism with the addressing of said second list; comparator means for detecting when the count in said sub-cycle counter reaches a predetermined limit; and means coupled to said comparator means to reinitiate addressing of said first list upon the generation of an output by said comparator means.

19. The apparatus as in claim 17 wherein at least one of said first and second lists comprises a register stack.

20. Apparatus as in claim 16 and responsive to the receipt of a poll command signal from said bus controller node for initiating the return of a predetermined response control word over said control cable to said bus controller node.

21. Apparatus as in claim 20 and further including means in said bus controller node for sensing the time delay between the sending of a poll command by said bus controller and the subsequent receipt of said response control code by said bus controller; and means for signaling the particular user device associated with said bus controller node when said sensing means indicates a time delay greater than a predetermined value.

22. Apparatus as in claim 21 and further including:
(a) a control line input queue device coupled to said control bus for storing the node addresses of those node devices responding to a poll control word from said bus controller node;
(b) a select queue device connected to said control line input queue device and controlled by said control line sequencer for applying select codes to said control cable; and
(c) means responsive to the receipt of a select control code by an addressed node for entering or receiving data messages from said active message cable by way of said bus input/output means.

23. Apparatus as in claim 22 wherein said last-mentioned means operates simultaneously with transmission of said poll control words, said response control codes and said select control codes on said active one of said control cables.

24. The serial data bus transmission system of claim 1 wherein said logic means comprises a programmable logic array.

25. Apparatus for coupling a plurality of digital data processing and handling user devices through a communications bus, certain of said user devices having a first priority status and other of said user devices being of a non-priority status, such that said user devices may communicate on a non-contentious basis, comprising in combination:
(a) a plurality of node devices associated with said user devices, one of which being assigned bus controller responsibility, said bus controller node device having means for issuing polling control words to said plurality of node devices over control lines contained in said communication bus on a predetermined frequency basis, the nodes associated with said user devices having priority status receiving polling control words more frequently than said node devices associated with user devices having non-priority status;
(b) priority response queuing means and non-priority response queuing means in said bus controller node device, said priority and non-priority queuing means adapted to store response-type control words return from said plurality of node devices in response to the receipt of said poll control words from said bus controller node;
(c) control means for said queuing means for generating select control words for transmission from said bus controller node to selected ones of said node devices previously sending predetermined response control words to said bus controller node, said select means honoring node devices associated with said priority users in preference to said node devices associated with non-priority users; and
(d) means including data lines contained in said communications bus for transmitting messages of predetermined differing lengths from said priority and non-priority node devices in response to its receipt of said select control words from said bus controller.
Description
BACKGROUND OF THE INVENTION

This invention relates generally to a serial data bus for interconnecting large numbers of computers or other digital data processing equipment in a local area and more specifically to the design of the nodes used in such a system for coupling the user devices to the serial data bus whereby the throughput of the system is enhanced.

DISCUSSION OF THE PRIOR ART

The interconnection of large numbers of computers in a local area is a need which is quite different from computer interconnection requirements perceived in the past. Prior art approaches at local processing networks involved the so-called star configurations wherein peripheral equipments and computers were connected directly to a computer having centralized control over the resources comprising the network. It has been found that the rapid increase in the use of digital processing in all areas of a network in the form of microcomputers embedded in a process, mini computers for specialized front-end processing and large computers for large-scale operations has created at need for a flexible and extensible method of interconnecting processing elements. Interconnecting large numbers of processing elements for complete intercommunication can be accomplished, of course, by direct transmissions to all elements connected to a data bus or by indirect transmissions relayed by point-to-point interconnections. It is found, however, that the use of only point-to-point connections to establish a local processing network composed of a large number of computers is quite complex and cumbersome and does not easily satisfy the need for flexibility and extensibility.

The serial data bus in which the present invention finds application provides the medium for the complete interconnection of processing elements in a local processing network. The term "local" is intended to mean that the user devices are physically located within a well defined area such as a building, a ship or an aircraft as distinguished from remote communication systems which may be spread over many miles.

To be effective, a serial data bus network interconnection scheme should take into account the throughput requirements and bottlenecks due to a saturated transmission system or non-uniform flow of data are to be avoided. In accordance with the present invention, the control of information flow on the serial data bus is programmable and thereby allows the fitting of the bus to a specific application.

A drawback of prior art local porcessing networks and especially the interconnection scheme used therewith relates to the fact that they tended not to be particularly fault tolerant. Fault tolerance is the attribute of the local processing network to continue its operation after the occurrence of faults. The system of the present invention overcomes that drawback through the judicious use of redundancy and a built-in self-monitoring capability for detecting and isolating faults. The nodal structure comprising the present invention enhances the overall fault tolerance of the serial data bus system with which they are used by allowing redundant cables, isolated connections to the cables and programmable time-out interrupts for calling into play fault recovery software.

Closely associated with the need for fault tolerance is the requirement that the interconnection system be able to accommodate incremental change without deleteriously impacting other parts of the network. Stated otherwise, the occurrence of faults represents a change in the system configuration and corrective action by way of removal of system parts from the network must be tolerated while still maintaining a continuous information flow to suit particular modes of operation or system applications.

The node structure of the present invention permits user programs to change the organization of information flow which is controlled through a polling operation. Also, user software can be employed to inhibit specific messages from flowing to a particular user device.

Another attribute of local data processing network and its interconnect shceme, especially where military and other highly critical real-time operations must continue even upon the occurrence of catastrophic events is that it exhibits survivability. For example, it is essential that the user devices be able to communicate even when one or more interconnect cables is severed or when one of the system modules is destroyed. The local communication system in which the present invention finds use exhibits this property, primarily due to the fact that redundant cables are employed which cables are physically distributed throughout the local area along different paths and because the nodes of the present invention are modularly arranged and function such that any one may assume the role of Bus Controller in the event of a catastrophic failure of the type indicated.

The node device of the present invention which is used to interface a user device to the serial data bus employs a system monitor to control the initialization and reconfiguration and the system monitor function is assigned to one of the user processors with backup as required. During initialization, the Bus Controller node and the active primary bus cables are selected, message screens are loaded into each node, and each node is checked through a built-in test routine. During operation, the node hardware monitors the system for invalid formats, parity, missing responses/polls, and other fault indicators. On detection of a fault, a reconfiguration mode is initiated through the user processor which contains the system monitor function. For redundancy, other user processors can assume the system monitor function and perform the reconfiguration process. Using this technique, the level of reconfiguration becomes a function of the type or types of fault(s) detected which may include the following:

Switching a node to an alternate Bus Access Module stub in the event of a failure in this transmission path;

Switching all nodes to a backup primary bus cable in the event of breakage of this cable; and

Assigning the Bus Controller functions of a user/node to an alternate user/node in the event of failure including the user/node that contains the System Monitor/Bus Controller function.

To facilitate the configuration process, each node continuously monitors data on the alternate stub cables and if data is detected on a previously inactive cable, it will, under certain conditions, interpret such data as commands for initiating reconfiguration.

SUMMARY OF THE INVENTION

The preferred embodiment being described herein permits a local data processing network to involve up to 256 separate users (computers) each being associated with a node device having a plurality of ports for connection to the primary bus cables, thereby accommodating the desired redundancy requirements. That is, a plurality of primary bus cables are provided for redundancy purposes and at all times, two of the plurality are designated the control cable which carries control type data words and a message cable for carrying message data. The system is configured such that if one or the other of the active control or message cables is interrupted, the user devices are automatically reconfigured to cooperate with a different (previously inactive) one of the plural primary bus cables. Communications within the data bus system are implemented by assigning control of the active bus to one of the node devices, which then controls transmission of messages on the data cable. Contention between bus users is resolved by selectively polling the users and then granting bus access to the highest priority user. Addressing within the data bus system uses both physical and logical addresses with each node having a manually selectable address register.

One of the nodes in the data bus system has the responsibility for bus control. Users with time-critical communication requirements are polled more frequently than other non-priority users. The priority structure is controlled by user defined parameters so that it can be modified to adapt to the particular application in process.

When a particular node is polled, a response is transmitted to the Bus Controller, Indicating the needs of the node as well as the current status. As such, a bus malfunction can be detected within the time required for a full system polling cycle. Poll commands, responses, and other types of system commands are arranged to be transmitted on a control cable of the bus. The data cable is reserved for information messages only. The traffic on both cables is asynchronous, enabling polling and queuing of user devices concurrently with information messages being transmitted on the data cable.

OBJECTS

It is accordingly the principal object of the present invention to provide means for interconnecting a large plurality of digital data processing devices to one another via a serial transmission data bus.

Another object of the invention is to provide an improved node device for coupling a digital data processor to one of a plurality of data channels.

Still another object of the invention is to provide a node for coupling a digital data processor such as a user computer to a two cable system wherein one cable is arranged to carry polling/command signals and the second cable carries data messages.

A further and related object of the invention is to provide a node device for coupling a user computer to transmission cables such that concurrent polling and data transmission can be performed so as to minimize access time.

A yet further object of the invention is to provide a node system in which message traffic on a serial bus to which the node is coupled is controlled by one of a plurality of nodes which has been designated as the Bus Controller.

A still further object of the invention is to provide in a serial data bus transmission system a plurality of node devices, any one of which can function as the Bus Controller at any given time.

A still further object of the invention is to provide in a serial data bus communication system a plurality of distributed cables, each capable of carrying serial binary data between nodes and which allows for switching of all nodes to a backup primary bus cable in the event of breakage of the bus cable over which data and control signals had previously been conveyed.

Still another object of the invention is to provide in a node device hardware and firmware whereby each node in the system can continuously monitor data on alternate stub cables such that if data is detected on a previously inactive cable, the node may interpret such data as calling for bus reconfiguration.

Another object of the invention is to provide a node structure for a serial data bus system which includes special purpose hardware and firmware in a general purpose microprogram controller for maximizing the polling rate.

A yet still further object of the invention is to provide a node for a serial data bus transmission system employing a dynamic reconfiguration method whereby one of the nodes in the system, namely, the Bus Controller node, sends commands to the remaining nodes in the system so that those remaining nodes reconfigure automatically to a new cable.

Yet another object of the invention is to provide a node for use in a serial data bus transmission system whereby real-time reassignment of the so-called Bus Control function can be attained.

A still further and related object is to provide a node design for use in a serial data bus communication system whereby real-time channel change can be accomplished to facilitate recovery from faults in the transmission system.

Yet another object of the invention is to provide a high speed resource allocation mechanism which achieves a maximum bus access time of less than 1/2 millisecond for up to 16 different nodes on a serial data bus communication system.

These and other objects and advantages of the invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiment, especially when considered in conjunction with the accompanying drawings.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system block diagram of a serial data bus in which the node structure of the present invention finds use;

FIG. 2a through 2d, when arranged as shown in FIG. 2, depict a block diagram of the node portion of the system shown in FIG. 1;

FIGS. 3a and 3b, when arranged as shown in FIG. 3 depict by means of a block diagram the organization of the Microprogrammable Controller employed in the node;

FIG. 4 illustrates by means of a logic diagram the Mapping PLA used in the node;

FIGS. 5a and 5b, when arranged as shown in FIG. 5, illustrate the logic for implementing the Time for Select Flag Circuitry;

FIGS. 6a and 6b, when arranged as shown in FIG. 6, depict the control line output circuitry portion of the node;

FIGS. 7a and 7b when arranged as shown in FIG. 7, depict further portions of the control line output circuitry;

FIG. 8 illustrates by means of a logic diagram the command registers forming a portion of the Control Line Output Circuitry;

FIG. 9 illustrates the circuitry for implementing the Select Multiplexer/Register and Comparator portions of the Control Line Output Circuitry;

FIGS. 10a and 10b, when arranged as shown in FIG. 10, depict by means of a logic diagram the Priority Poll Lists portion of the node;

FIG. 11 depicts by a logic diagram the Non-priority Poll Lists;

FIG. 12 illustrates the logic for implementing the Non-Priority Sub-cycle Control;

FIGS. 13a and 13b, when arranged as shown in FIG. 13, illustrate the logic for implementing the Priority Poll List Control Circuitry of the node;

FIG. 14 shows the logic for implementing the Last Poll Address Register and the Own Node Poll Comparator;

FIGS. 15a and 15b, when arranged as shown in FIG. 15, depict the logic comprising a portion of the Control Line Input Circuitry;

FIG. 16 depicts the logic for implementing the comparator portion of the Control Line Input Circuitry;

FIG. 17 depicts by means of a logic diagram the Control Line Input FIFO buffer employed in the Control Line Input Circuitry;

FIGS. 18a and 18b, when arranged as shown in FIG. 18, depict the Processor Control Line Input Register portion of the Control Line Input Circuitry;

FIGS. 19a and 19b, when arranged as shown in FIG. 19, depict the logic for implementing the Control Line Sequencer PLA;

FIGS. 20a and 20b when arranged as shown in FIG. 20 illustrate further logic circuitry used in the implementation of the Control Line Sequencer PLA;

FIG. 21 shows the implementation of the Dispatch Queue Input Multiplexer portion of the Control Line Input Queue;

FIG. 22a and 22b, when arranged as shown in FIG. 22, depict the Priority and Non-Priority Dispatch FIFO buffers comprising a portion of the Control Line Input Queue;

FIG. 23 depicts the logic for implementing the Destination Bus Holding Register and the Activity Mask Register portions of the node;

FIGS. 24a and 24b, when arranged as shown in FIG. 24, depict by means of a block diagram the Control Line Decoder portion of the node,

FIG. 25 illustrated by means of a block diagram the Control Line Encoder portion of the node;

FIGS. 26, 27 and 28 together illustrate the control circuitry for the Control Line Encoder/Decoder apparatus of FIGS. 24 and 25;

FIGS. 29a and 29b, when arranged as shown in FIG. 29, and 30, together illustrate by a logic diagram the stub vectoring logic portion of the node;

FIGS. 31a and 31b, when arranged as shown in FIG. 31, illustrate the Control Line Activity Detector Circuitry of the node;

FIGS. 32a and 32b, when arranged as shown in FIG. 32, are flow diagrams illustrating the bus arbitration methodology;

FIGS. 33a, 33b and 33c when arranged as shown in FIG. 33, comprises a firmware flow diagram depicting the bus arbitration methodology; and

FIG. 34 is a further flow diagram helpful in understanding the bus reconfiguration process.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Before explaining the overall construction and mode of operation of the node devices comprising the present invention, it is deemed expedient to explain in summary fashion the overall system configuration in which the node devices find application. In this regard, reference is made to the general block diagram of FIG. 1 which depicts graphically the serial data bus architecture. User devices such as the user computers 40, 42 and 44 are but three of a large plurality of user devices which are adapted to communicate, one with the other, on the bus system. In a system actually constructed, up to 256 user devices were allowed for. Associated with each user device is a so-called node, node 34 being associated with user computer 40, node 36 with user computer 42 and node 38 with user computer 44. The serial data bus system functions to permit two-way, point-to-point communication between any pair of user computers or, alternatively, to permit any one user computer to broadcast simultaneously to all other users in the system. Interuser communication is accomplished via the main bus channels, here shown as including six such channels labeled 46-56, respectively. By utilizing plural channels, the desired redundancy is provided in that any two of the six are sufficient to support communication between all user devices.

Each of the channels 46-56 may comprise a triaxial cable capable of supporting Manchester encoded serial data at a 10 megabit per second rate. The six cables 46-56 will hereinafter be referred to as the primary bus system.

As is illustrated in the drawing of FIG. 1, each node 34, 36, etc., communicates with the primary bus system via stub cables 58, 60 and 62. The stub cables associated with each node correspond in number to the number of main bus channels employed in the data bus system. The interconnection between a node stub cable and one of the main bus channels is via a so-called Bus Access Module or BAM. Those desiring an explanation of the construction and operation of the BAM devices used herein are referred to a paper entitled "A Triaxial Bus Transmission System" by R. O. Starkson which was published on Oct. 23, 1979 in the IEEE Proceedings, 4th Conference on Local Computer Networks, pp. 82-85, which subject matter is incorporated herein by reference.

As is explained in the aforereferenced article, the BAM provides a zero length stub connection to the primary bus system and provides local signal regeneration to drive the stub cables. In a practical system that has been put into use, up to 64
BAM's can be accommodated on each of the primary bus cables 46, 48 . . . 56 without degrading the electrical performance of the system. Further, each BAM is capable of driving up to four stub cables such that it can serve a maximum of four separate nodes. The BAM may be positioned anywhere along the length of the primary bus cables which may, for example, each be approximately 300 meters in length. The stub cables 58, 60, etc., may typically be up to 30 meters in length, but no limitation to this particular dimension is intended. However, it is readily understandable, then, that these typical dimensions allow a system designer considerable flexibility in choosing the physical location of the channels of the primary bus system and the associated Bus Access Modules. Maximum fault tolerance is achieved by providing a significant number of redundant communications paths which may be physically disbursed. It is to be noted, for example, that nodes 34 and 36 gain access to the primary bus cable 46
by way of common BAM 10 while they gain access to the primary bus cable 54 via BAM's 26 and 28, respectively.

It is generally intended that each node 34, 36, etc., will communicate with all six of the main bus channels 46-56, although it is to be understood that some of these redundant cables can be eliminated in the interests of ecomony and only two cables are essential for operation. That is to say, the serial data depicted schematically in FIG. 1 requires two channels to be available in the bus transmission system at any given time. One of the two channels, called the "Control Channel", is used solely for the purpose of system control and reconfiguration. Bus arbitration is carried out on this channel with the net result being a controlled allocation of the other channel for the purpose of sending data messages. The second of the two active channels is called the "Data Channel" and is reserved entirely for message traffic. This feature makes it possible for the serial data bus to sample the requirements of the nodes in the system asynchronously and in parallel with the data transfers taking place.

High bus performance (low access time and high message throughput) is achieved through the use of a 10 megabit/second transmission rate. The two cable system, with one cable for bus polling/command signals and the second cable for data transmission also enhances the performance. It allows concurrent polling and data transmission on the bus system and minimizes access time. While data is being transmitted on one cable, the queue for the next user may be established. The two cable system also facilitates recovery from casualty or system failures in that at least one active alternate cable is available for reconfiguring the system in the event of cable breakage.

Message traffic is controlled through a single node which performs the polling cycle. Messages are transmitted sequentially on the data cable based on a priority algorithm of the poll cycle. In this manner, positive control and status of the bus system is maintained. This attribute is essential to those operations, such as military systems, where positive and timely transmission of critical messages must be guaranteed.

As was pointed out in the introductory portion of this specification, to guarantee reliable operation, both commercial and military bus systems must strive to eliminate or at least minimize single points of failure. The use of passive rather than active taps on the primary bus is the key to achieving this desired requirement. In addition, alternate cables are provided as backup in case of cable breakage or casualty. As is shown in FIG. 1, it is also important, especially in military systems, that the cable system, i.e., cables 46-56, be disbursed and that stubs 58-62 which physically separate the primary bus from the node/user by employed. In the system depicted in the block diagram of FIG. 1, each node 34, 36, etc. may be connected up to six primary bus cables, any two of which provide a full system capability.

In that the bus control function is duplicated in several nodes, failure of the particular node which happens to be in command at any given time, i.e., the Bus Controller, does not disable the bus. Rather, the bus control function is handed off to one of the other nodes based on a predetermined sequence. In this manner, single points of failure are virtually eliminated in the overall system. The manner in which this is accomplished will be set forth in considerably more detail hereinbelow when the overall design and operation of the node, per se, is set out.

NODE CONSTRUCTION

FIGS. 2a through 2d, when arranged as shown in FIG. 2, illustrates by means of a block diagram the basic organization and implementation of any one of the nodes 34, 36, etc., illustrated in the block diagram of FIG. 1. A node contains the circuitry to:

(1) support the serial data communication protocol;

(2) to communicate with the user computer; and

(3) to detect and report errors and hardware failures.

The failures mentioned may be within the node itself, they may be detected and reported from other nodes, or they may be failures or errors detected in one of the cables. Overall control of the node is accomplished by a Microprogrammable Controller which in the preferred embodiment is based upon the so-called 2900 family of integrated circuits manufactured and sold by Advanced Micro Devices, Inc. However, limitation to this particular Microprogrammer Controller is not to be implied. As will be explained in still greater detail hereinbelow, these devices are employed in the Microsequencer 160 (FIG. 2b) and the Arithmetic Logic Unit or ALU 180 (FIG. 2d). During each so-called microcycle, the Microsequencer 160 generates an address for the Microprogram Memory 162, the contents of which are then loaded into a Microinstruction Registr 164 in a conventional and well known fashion. Certain bits of the Microinstruction are translated by Decoder 166 and the outputs of this decoder, along with the remaining bits of the Microinstruction itself comprise the control signals appearing on the Control Bus 168 internal to the node itself. These control signals are distributed to every control point throughout the node, both within and external to the Microprogrammable Controller.

The condition of the node is sensed by the Node Status circuitry 154. This information is presented to the Condition Test Multiplexer 156 and to the Mapping PLA (Programmable Logic Array) 158. The Mapping PLA 158 causes the microprogram to be vectored to a specific task as required by a given node condition, while the Condition Test Multiplexer 156 permits the program to branch on any selected status condition.

The features thus far described with respect to FIG. 2 permit the so-called firmware running in the Microprogrammable Controller including the Microsequencer 160, the Microprogram Memory 162 and the Microinstruction Register 164 to exercise supervisory control over the remainder of the node hardware. Communication from the Microprogrammable Controller to various registers throughout the node is via the 8-bit Destination Bus 172, while communication from any of the various node registers to the Microprogrammable controller is via the 8-bit Source Bus 170.

Located at the top of the composite node block diagram of FIGS. 2a and 2b are a plurality of Stub Transceivers 100-110 which are coupled to communicate with the primary bus system (see FIG. 1) via their respective BAM's. These transceivers are designed to convert the received low level Manchester encoded serial data signal to a logic level Manchester signal. During transmission, they convert the logic level Manchester encoded serial data to the low level signal required to conform to existing electrical communications standards such as NATO STANAG 4153.

Lines 112-122 are presented to the Channel Selection Network 124 via serial data and control lines. Channel selection is primarily determined by the contents of the Active Bus Number Register 150. This register is arranged to be loaded by the Microprogrammable Controller previously described. If, for example, line 114 is selected to be the control line, two-way communication will be established from the Control Line Encoder 130 by way of the Serial Control line 126, through line 114 and Stub Transceiver 102 to its respective primary bus. Similarly, any of the remaining five lines could be selected to be the Data Line and thus provide a two-way communication path through the Serial Data line 128 to the Data Line Encoder/Decoder 186. The details of how this selection is made will be discussed later under the heading "Reconfiguration". For now, however, it is sufficient to understand that a selection is required such that all nodes have one common control line and another common data line.

The Control Line Encoder/Decoder 130 permits two-way conversion between the serial Manchester encoded data on line 126 and the 16-bit parallel interface on the Control Input/Output (CIO) bus 132. All control line transmissions are 16-bit words in which the first bit is always a "1", and is referred to as the "sync bit", and the last bit is a parity bit for error detection purposes. When a Control Word is received on line 126, the bi-phase Manchester code is decoded to recover the clock and data signals. The recovered Manchester clock is used to shift the 16-bit data word into a 16-bit register within the Control Line Encoder/Decoder 130 which is then presented to the CIO bus 132. The control word is then captured in a Control Line Input Register 146.

In the case of a transmitted word, the 16-bit parallel word is first developed in a Controll Line Output Multiplexer 134 and presented to the CIO bus 132. This data is captured in a 16-bit shift register within the Control Line Encoder/Decoder
130. It is shifted out serially into the Manchester Encoder section (not shown) of device 130 which converts it to Manchester bi-phase data at the Serial Control Line 126. The timed gating signals used to load and unload data from the CIO bus 132 and to initiate the serial transmission are derived from the programmable logic array based Control Line Sequencer 144. In all other respects, the Control Line Encoder/Decoder 130 operates asynchronously with the rest of the nodes. In a related manner, the Data Line Encoder/Decoder 186 (FIG. 2b) performs the serial-to-parallel and parallel-to-serial data conversion between the Serial Data line 128 and a so-called Message Input/Output bus (MIO bus) 187, the only difference being that in this case, the message length can be a multiple of 32-bit words.

Both Control Line and Data Line transmissions are checked for parity and format errors. In the event an error is detected, the Microprogrammable Controller is notified via the Node Status circuitry 154.

Each node has the capability to generate four types of control transmissions, namely:

(1) Poll;

(2) Response;

(3) Select; and

(4) Command.

These control words are generated by the Poll List 140, the Response Register 138, the Select Queues 142 and a Command Output Register 136, respectively. The poll, select and command transmissions are employed only by the particular node which has been selected to function as the system's Bus Controller. All other nodes employ only the response form of transmission.

In the Bus Controller mode, the Control Line Sequencer 144 controls the Control Line Output Multiplexer 134 to select the appropriate type of transmission. A pool is an interrogation addressed to another node asking it to respond as to its status. In this regard, each node maintains a status word in its respective Response Register 138 which is indicative of the node status or an indication whether that node requires access to transmit on the data line. The poll is broadcast by the Bus Controller to all nodes.

However, only the particular node addressed will generate a "Response". All Responses are loaded into the Control Line Input Queue 148 and the Microprogrammable Controller is notified of this via the Mapping PLA. The Control Line Sqeuencer is now in a condition to continue polling while the Microprogrammable Controller concurrently processes the Response. Polling proceeds sequentially on the basis of two ordered poll lists contained in Poll List 140, one for up to 16 so-called priority nodes and the other list for remaining (up to 256) non-priority nodes. If the Microprogrammable Controller determines that a node requires service, the address of that node is transferred from the Control Line Input Queue 148 to the Select Queue 142. This "Select" is the means by which the Bus Controller grants a node the use of the data Bus. The Microprogrammable Controller may also determine that a Command should be sent. In this event, the Command Register 136 is loaded via the Destination bus.

Once the Microprogrammable Controller has loaded either Register 136 or Select Queue 142, the Control Line Sequencer proceeds automatically to generate the correct sequence of Polls, Selects and Commands.

In the Non-Bus Controller mode, the operation of the Control Line Sequencer 144 is similar, except that now the Microprogrammable Controller tests the Control Channel inputs to determine if the node has received a Poll or a Command. Also, instead of transmitting Commands, Polls or Selects a node which is not functioning as a Bus Controller will only transmit a Response via Response Register 138.

A novel aspect of the present invention lies in the ability of the Control Line Sequencer to automatically process all Control Line transmissions in either mode without incurring any nominal delay due to processing by the Microprogrammable Controller. These features will be discussed in greater detail hereinbelow when the flow charts of FIGS. 33 and 34 are considered.

MESSAGE HANDLING AND USER INTERFACE

Because the remaining node functions do not relate directly to the invention, only a brief description thereof will be presented at this point so as to provide the reader with a more complete understanding of the overall system construction and operation.

The User Interface may consist of 32 input lines designed to carry digital signals which are arranged to be latched into Input Register 196 and 32 output lines which are driven by Output Register 197. Communication is via the 32-bit User Bus
195. Communication from the Microprogrammable Controller to the User is by way of a Bus Output Register 176. A 32-bit output word is assembled from four 8-bit bytes coming from the Destination Bus 172. Communication from the User to the Microprogrammable Controller is via the Bus Input Register 174. A 32-bit User word is latched into this register 174 and then disassembled into four 8-bit bytes which are sent sequentially to the Source Bus 170. The Microprogrammable Controller supports all of the User protocol, but does not become directly involved in the transmission of data. In a first instance where the User is the originator of a message, the User computer in question places a 32-bit header word on the User Bus 195. The header Format circuit 194 converts this word into the header required for serial data transmission. This involves the insertion of a sync bit and a node address. This word also is used to load a Buffer Control circuit 190 with a message word count. The reformatted header is loaded into the first word of a 128-word by 32-bit Data Output Buffer 192.

Next, 32-bit message words are sequentially loaded into the Buffer 192 until the word count specified by the contents of the Buffer Control 190 has been reached. The complete message is now resident in the Output Buffer, ready for serial transmission. If the message to be sent exceeds the 128-word limit, it must be divided into packets by the user and then treated as a single message. With the Output Buffer 192 now loaded, the node requests service from the Bus Controller which is the node then acting as the "master" at the particular time. When a "select" is received, the output data is loaded in 16-bit bytes onto the Message Input/Output bus (the MIO bus) 187 and is transmitted via the Serial Data Line 128 out to the associated main bus channel in an uninterrupted serial data stream. All data transfers proceed automatically to support a 10 MHz serial data rate.

Next to be considered is the case where a User Computer is to be the recipient of a message. All serial data is converted by the Data Line Encoder/Decoder 186 and presented to the MIO bus 187. A Message Screening circuit 188 coupled to this bus functions to examine the header of each message and ignores all messages which are not addressed physically or logically to this particular node. If the message is intended for the node's User, the Buffer Control circuit 190 is initiated to cause the message to be captured in a Data Input Buffer 191 which, too, many comprise a 256-word by 32-bit storage device. When the complete message has been loaded into buffer 191, the node hardware informs the User that it has a message waiting and this message is then read out from the Input Data Buffer 191 and sent to the associated User via the User Bus 195 and the output register 197. The Header Format circuit 193 converts the first 32-bit word of a message from the serial data format to the User Bus format. Because it is possible that a second message can arrive before the first message has been emptied from the Data Input Buffer 191, this buffer is organized as an exchange memory which permits simultaneous loading and unloading of messages. In designing the node of the present invention, the buffer 191 is sized such that two complete messages of the maximum length, e.g., 128 words, can be held without over-running it. Any abnormal message conditions are reported by the Buffer Control circuit
190 to the Node Status circuit 154.

SYSTEM TIMING

All timing for the node is derived from a stable crystal oscillator which may, for example, produce 20 MHz square waves. The output of this oscillator is used to form five critically lapped clock pulses designated Phase I through Phase V. Each clock pulse may typically be 50 nanoseconds wide and may occur every 250 nanoseconds. The resulting pulse-to-pulse interval defines the cycle during which an instruction is executed by the Microprogrammable Controller and also determines the execute cycle for the Controller Line Sequencer 144. The 20 MHz oscillator is also used in the encoding of the 10 MHz bi-phase Manchester serial data stream. The Phase III clock pulse is used to clock a 16-bit binary divider which generates 16 square wave outputs ranging from a 0.5 microsecond period to a 16,384 millisecond period. Certain of these output signals are employed in the various time-out checking performed by various modules within the node.

Now that the overall organization of a typical node has been explained with the aid of the system block diagram of FIG. 2, consideration will now be given to various modules set forth in that general block diagram.

MICROPROGRAMMABLE CONTROLLER

FIGS. 3a and 3b together illustrate by means of a more detailed block diagram the organization of the Microprogrammable Controller employed. The Microsequencer 160 of FIG. 2 is represented in FIG. 3 by a block identified by numeral 814 and provides an 11-bit address to a programmable read-only memory (PROM) 816 which may, typically, comprise 2048 words, each 56 bits in length. At the beginning of each cycle, a new word is fetched from the PROM 816 and loaded into a 56-bit Microinstruction Register 818. The 56 separate output from this register are used to control both the internal operation of the Microprogrammable Controller and to provide the hardware control signals for the remainder of the node. Selected bits of the register 818 are thus connect to each function of the Microprogrammable Controller.

Two instruction formats are utilized. When one format is involved, branching and program control can be effected. A second format dictates that data transfers and data manipulations are to occur. Referring to FIG. 3a, the particular format in use is defined by the state of bit 34 which causes the bits 0 through 33 to be interpreted differently. As is illustrated in FIG. 3a, bit 34 is received by the Format Control circuit 820 which selects the appropriate functions for a given format. The interpretation of the upper portion of the instruction bits, i.e., bits 35 through 55 is identical for both formats.

Consider first the interpretation of the lower order bits when bit 34 is a binary "0". As mentioned above, this defines the branch or program control format. Bits 0 through 3 of the Microinstruction word provide the command instruction for the Microprogram Sequencer 814. These bits are decoded to select one of 16 possible operations as defined for the Advanced Micro Devices series 2910 type integrated circuit. This instruction determines the source of the next address which will be used to fetch the next Microinstruction. If the program does not branch, the address count is simply incremented by 1. If a branch is required, the output of Branch Address Multiplexer 810 provides the source for the new address. As might be expected, branching can be either conditional or unconditional. For the conditional case, the decision to branch is decided by the output of Test Condition Multiplexer 812. Bits 4 through 17 of the Microinstruction are provided to the Test Condition Multiplexer
812 to select one of 83 possible test signals which will be used for conditional branching. These signals are comprised of 32 firmware flags which become available at the output of the Firmware Flag Decoder 824 and the various Test Condition Flags identified in Table I below.

TABLE I ______________________________________ TEST CONDITION FLAGS Active State Function ______________________________________ H INTER MESSAGE TIMEOUT H DATA LINE DATA STREAMING TIMEOUT H DATA LINE PARITY ERROR H IMMEDIATE REQUEST H MESSAGE TO SEND FLAG H CONTROL LINE SYNC ERROR H CONTROL LINE PARITY ERROR H SEQUENCER WAIT FLAG H FORCED COMMAND ENABLE H POLL/RESPONSE H SELECT ENABLE H COMMAND ENABLE H PREVIOUS POLL PRIORITY/NON- PRIORITY INDICATE L NON-PRIORITY LIST ENABLE H SELECT TIME FLAG L OWN NODE SELECT FLAG L OWN NODE POLL FLAG L NON-PRIORITY QUEUE EMPTY L PRIORITY QUEUE EMPTY H NON-PRIORITY QUEUE FULL H PRIORITY QUEUE FULL H CONTROL LINE ACTIVITY TIMEOUT H POLL/RESPONSE TIMEOUT H AUTO LOOP ERROR FLAG H PROCESSOR CONTROL LINE INPUT QUEUE FULL H CONTROL LINE INPUT WORD INDICATOR H PROCESSOR CONTROL LINE INPUT REGISTER BIT 6 H PROCESSOR CONTROL LINE INPUT REGISTER BIT 5 H PROCESSOR CONTROL LINE INPUT REGISTER BIT 4 H PROCESSOR CONTROL LINE INPUT REGISTER BIT 3 H PROCESSOR CONTROL LINE INPUT REGISTER BIT 2 H LATCHED MCU INTERRUPT FLAG H FORCED EXTERNAL FUNCTION FLAG H LATCHED INPUT DATA ACKNOWLEDGE FLAG H LATCHED USER DATA INPUT FLAG H LATCHED EXTERNAL FUNCTION INPUT FLAG H LATCHED DATA & HEADER LOST H LATCHED ERROR ACTIVITY INDICATOR L ALU SIGN FLAG H EXTERNAL INTERRUPT/DATA SWITCH H ALU SIGN FLAG H ALU CARRY FLAG H ALU = ZERO FLAG H ALU OVERFLOW FLAG H NODE POWER FAULT H BREAKPOINT FLAG H LATCHED DISPLAY MODE H PROC CONTROL LINE IN REG 0/ (AUTO LOOP) ERROR IND) H LATCHED INCOMPLETE MESSAGE H LATCHED DATA LINE DATA LOST (HEADER COMPLETE) H LATCHED CONTROL LINE ACTIVITY INDICATOR FLAG ______________________________________

It can be seen, then, that the state of any flag can be ascertained by the microprogram by executing the appropriate conditional branch instruction. Bit 19 of microinstruction contained in register 818 determines the source of the branch address via the Branch Address Multiplexer 810. If this bit is a 0, the branch address is determined by bits 20 through 31 of the microinstruction. If, however, bit 19 is a binary "1" signal, the branch address is determined by the output of the Mapping PLA
158 of FIG. 2b. By executing a branch instruction with bit 19 set to a 1, the program can be vectored to the starting address of one of a number of processing tasks as defined by the Mapping PLA. Bits 32 and 33 are not used in this format.

Next to be considered is the case where bit 34 of the Microinstruction is a binary "1", thus defining the data transfer and manipulation format. Bits 0 through 4 are presented to the Destination Field Decoder 828 to generate the 29 destination field decode signals identified in Table II below. Each of these signals has a unique code which, if programmed, causes the data on the 8-bit destination bus 846 to be latched into the corresponding register.

TABLE II __________________________________________________________________________ DESTINATION FIELD DECODER __________________________________________________________________________ SCREEN RAM ADDRESS REGISTER LOAD ENABLE CONTROL LINE INPUT REGISTER BYTE 2 LOAD ENABLE CONTROL LINE INPUT REGISTER BYTE 1 LOAD ENABLE ACTIVITY MASK REGISTER LOAD ENABLE DEST BUS HOLD REGISTER LOAD ENABLE COMMAND REGISTER BYTE 2 LOAD ENABLE COMMAND REGISTER BYTE 1 LOAD ENABLE SELECT REGISTER LOAD ENABLE NUMBER NON-PRIORITY USERS/SUBCYCLE REGISTER LOAD ENABLE END NON-PRIORITY LIST REGISTER LOAD ENABLE END PRIORITY LIST REGISTER LOAD ENABLE RESPONSE REGISTER LOAD ENABLE CONTROL LINE ACTIVITY TIMEOUT REGISTER LOAD ENABLE CABLE SELECTION REGISTER LOAD ENABLE INPUT RAM ACCUMULATOR LOAD ENABLE SCREEN RAM CONTENTS LOAD ENABLE OUTPUT DATA RAM ADDRESS LOAD ENABLE INPUT DATA RAM UNLOAD ADDRESS LOAD ENABLE DATA RAM CONTROL REGISTER LOAD ENABLE INPUT DATA RAM LOAD ADDRESS LOAD ENABLE MICROPROCESSOR CONTROLLER EXTERNAL INTERRUPT FORMING REGISTER BYTE 1 LOAD ENABLE MICROPROCESSOR CONTROLLER EXTERNAL INTERRUPT FORMING REGISTER BYTE 2 LOAD ENABLE MICROPROCESSOR CONTROLLER EXTERNAL INTERRUPT FORMING REGISTER BYTE 3 LOAD ENABLE MICROPROCESSOR CONTROLLER EXTERNAL INTERRUPT FORMING REGISTER BYTE 4 LOAD ENABLE __________________________________________________________________________

Data thus flows from the 8-bit Arithmetic Logic Unit 838, through the Destination Bus Driver 836 to the selected register. When in this format, bit 5 of the microinstruction controls the write enable (WR EN) input of a Word Register File 844. Typically, the file 844 may comprise 16-word registers each 8 bits in length. If bit 5 of the microinstruction is a binary "1", the destination for the data becomes the word of the Register File 844 specified by bits 0 through 3 of the Microinstruction, which is selected by the Multiplexer 842. Bits 6 through 14 of the microinstruction determine the source of the data to be put on the 8-bit Source Bus 848. When bit 14 is a "0", the Microinstruction Constant Driver 834 is enabled via inverter 835, causing bits 6 through 13 of the Microinstruction to be used directly as the source data applied to the bus 848. When bit 14 is a binary "1", the output of Multiplexer 832 is enabled such that it becomes the data source. Bits 6 through 13 of the instruction word are decoded by the Source Field Decoder 830, the output of which is used to select one of 19 possible source inputs for a source Multiplexer 832.

The various source Registers from which data can be accessed are identified in the following Table III.

TABLE III ______________________________________ SOURCE FIELD DECODE ______________________________________ SELECT REGISTER NUMBER NON-PRIORITY USERS/SUBCYCLE END NON-PRIORITY LIST REGISTER END PRIORITY LIST REGISTER LAST POLL ADDRESS POLL LIST OUTPUT CABLE SELECTION REGISTER NODE ADDRESS CONTROL LINE ACTIVITY INDICATORS CONTROL LINE INPUT LOWER BYTE CONTROL LINE INPUT UPPER BYTE INPUT DATA RAM ACCUMULATOR INPUT DATA RAM CONTROL REGISTER OUTPUT DATA RAM WORD COUNT OUTPUT DATA RAM ADDRESS INPUT DATA RAM UNLOAD ADDRESS INPUT DATA RAM WORD COUNT INPUT DATA RAM LOAD ADDRESS MICROINSTRUCTION CONSTANT SCREEN RAM CONTENTS REGISTER NODE STATUS REGISTER BYTE 1 NODE STATUS REGISTER BYTE 2 NODE STATUS REGISTER BYTE 3 EXTERNAL FUNCTION HOLDING REGISTER BYTE 1 EXTERNAL FUNCTION HOLDING REGISTER BYTE 2 EXTERNAL FUNCTION HOLDING REGISTER BYTE 3 EXTERNAL FUNCTION HOLDING REGISTER BYTE 4 ______________________________________

One of the outputs of the Source Field Decoder 830 comprises the file source enable signal which, when activated, enables the output of the 16-Word Register File 844. In this case, the data source is the register file word specified by bits 6
through 9 of the microinstruction, these being selected by the Multiplexer 842.

Bits 15 and 16 of the microinstruction control the operation of the Arithmetic Logic Unit Shift Control and Status Latch 840. During shift operations, these bits select one of four shift types; namely, 0 Fill, 1 Fill, Single Length Rotate, or Double Length Rotate. The Advanced Micro Devices 2901A Arithmetic Logic Unit integrated circuit employs two 4-bit address fields used in the manipulation of the 16 internal registers of the ALU itself. Microinstruction bits 17-20 provide the B-address field, while bits 21-24 provide the A-address field. The ALU 838 also employs two 3-bit fields to define the internal destination and source for arithmetic operations. These fields are provided by microinstruction bits 25-27 and 28-30, respectively. Bits 31-33 determine the type of arithmetic function to be executed by the ALU. Microinstruction bit 52 is used for carry control.

A Firmware Flag Decoder 824 which may comprise a 32-bit addressable latch is adapted to receive bits 35 through 39 of the microinstruction and functions to select one of these 32 flags while microinstruction bit 40 defines whether the flag is to be set or cleared. As will be explained in greater detail, these firmware flags are available to both of the control points of the node as well as for internal test by the Microprogram sequencer 814 by way of the Test Condition Multiplexer 812.

A Hardware Control Field Decoder 826 functions to translate microinstruction bits 41 through 50 to thereby develop 52 possible Hardware Control signals, these signals being set out in Table IV below.

TABLE IV ______________________________________ CONTROL SIGNALS Active State Function ______________________________________ H LOAD SCREEN RAM H CLEAR BREAKPOINT FLAG H CLEAR CONTROL LINE INPUT INDICATOR H FORCE PRIORITY POLL H ENABLE SEQUENCER H LOAD SELECT REGISTER H CLEAR POWER FAULT FLAG H CLEAR ACTIVITY MONITOR FLAGS L CLEAR DATA LINE INTERMESSAGE TIMEOUT L CLEAR PROCESSOR FLAGS L CLEAR MESSAGE TO SEND FLAG L CLEAR CONTROL LINE PARITY ERROR L CLEAR POLL/RESPONSE TIMEOUT H CLEAR SEQUENCER WAIT FLAG H SET SEQUENCER WAIT FLAG H SET FORCED COMMAND ENABLE H SET COMMAND ENABLE H SET SELECT ENABLE H SET POLL/RESPONSE ENABLE H CLEAR AUTO LOOP ERROR FLAG H POLL LIST WRITE ENABLE H ADVANCE POLL LIST H UNLOAD REQUEST QUEUE H LOAD REQUEST QUEUE WITH CONTROL LINE REG H LOAD REQUEST QUEUE WITH DESTINATION BUS H LOAD REQUEST QUEUE WITH NODE ADDRESS H RESET POLL LIST H TRANSMIT ENABLES L CLEAR USER INTERFACE L DELETE OUTPUT MESSAGE H CLEAR CONTROL LINE SYNC ERROR L CLEAR SELECT TIME FLAG L SET NODE POLLED INDICATOR L CLEAR SELECT QUEUES L CLEAR CONTROL LINE IN QUEUE L CLEAR ENCODER INTERFACE H DISABLE SEQUENCER L CLEAR CONTROL LINE ACTIVITY TIMEOUT L CLEAR INPUT DATA ACKNOWLEDGE L SET USER OUTPUT DATA REQUEST L CLEAR USER EXTERNAL FUNCTION LOCKOUT L CLEAR USER OUTPUT DATA ACKNOWLEDGE FLAG L CLEAR USER EXTERNAL FUNCTION ACKNOWLEDGE FLAG L SET MICROPROCESSOR CONTROLLER MESSAGE COMPLETE L SET USER INPUT DATA ENABLE L SET USER EXTERNAL INTERRUPT ENABLE L ENABLE DATA LINE MESSAGE TRANSMISSION L CLEAR DATA LINE PARITY ERROR L CLEAR INCOMPLETE MESSAGE LOCKOUT L CLEAR INCOMPLETE MESSAGE ERROR FLAG L CLEAR DATA LOST HEADER OK ERROR L CLEAR DATA LOST ALL ERROR ______________________________________

These signals are active only for the instruction cycle during which they are selected. Microinstruction bit 51 is used directly to form the Priority Queue Enable signal on line 827 which specifies the particular select queue to be referenced or operated upon during a current machine cycle. Continuing, microinstruction bit 55 is set to a state which establishes odd parity for the Microinstruction word. Parity is checked by the Parity Check Circuit 822 which functions to disable the node clock in the event a parity error is detected.

TABLE V A __________________________________________________________________________ MAPPING PLA TRUTH TABLE A-Inputs Term 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 __________________________________________________________________________
0 X 1 X 0 0 X X X X X X X X X X X 1 X 0 1 0 0 X X X 0 0 0 0 X X X X 2 X 0 1 0 0 X X X 0 0 0 1 X X X X 3 X 0 1 0 0 X X 0 0 0 1 0 X X X X 4 X 0 1 0 0 X X 1 0 0 1 0 X X X X 5 X 0 1 0 0 X X 0 0 0 1 1 X X X X 6 X 0 1 0 0 X X 1 0 0 1 1 X X X X 7 X 0 1 0
0 X X 0 0 1 0 0 X X 0 X 8 X 0 1 0 0 X X 0 0 1 0 0 X X 1 X 9 X 0 1 0 0 X X 1 0 1 0 0 X X 0 X 10 X 0 1 0 0 X X 1 0 1 0 0 X X 1 X 11 X 0 1 0 0 X X X 0 1 0 1 X X X X 12 X 0 1 0 0 X X X 0 1 1 0 X X X X 13 X 0 1 0 0 X X 0 0 1 1 1 X X X X 14 X 0 1 0 0 X X 1 0 1 1 1 X X X X 15 X 0 1 0 0 X X 0 1 0 0 0 X X X X 16 X 0 1 0 0 X X 1 1 0 0 0 X X X X 17 X 0 1 0 0 X X X 1 0 0 1 X X X X 18 X 0 1 0 0 X X X 1 0 0 X X X X X 19 X 0 1 0 0 X X 0 1 1 1 X X 1 X X 20 X 0 1 0 0 X X 0 1 1 1 X 0 0 X X 21 X 0 1 0 0 X X
0 1 1 1 X 1 0 0 X 22 X 0 1 0 0 X X 0 1 1 1 0 1 0 1 X 23 X 0 1 0 0 X X 0 1 1 1 1 1 0 1 X 24 X 0 1 0 0 X X 0 1 1 1 0 1 0 1 X 25 X 0 1 0 0 X X 0 1 1 1 1 1 0 1 X 26 X 0 1 0 0 X X 1 1 1 0 X X 1 X X 27 X 0 1 0 0 X X 1 1 1 0 X 1 0 X X 28 X 0 1 0 0 X X 1
1 1 0 X 0 0 0 X 29 X 0 1 0 0 X X 1 1 1 0 0 0 0 1 X 30 X 0 1 0 0 X X 1 1 1 0 1 0 0 1 X 31 X 0 1 0 0 X X 1 1 1 1 X X X X X 32 X X X 1 0 X X X X X X X X X X X 33 X X X X 1 X X X X X X X X X X X 34 X 0 0 0 0 1 X X X X X X X X X 0 35 X 0 0 0 0 1 X X X X X X X X X 1 36 X 0 0 0 0 0 1 X X X X X X X X X 37 X 0 0 0 0 0 0 X X X X X X X X X __________________________________________________________________________

TABLE V B __________________________________________________________________________ MAPPING PLA STATE DESCRIPTIONS TERM DESCRIPTION __________________________________________________________________________ 0 FAULT/ERROR DETECTED 1 CONTROL LINE INPUT - DISABLE 2 CONTROL LINE INPUT - START 3 CONTROL LINE INPUT - ASSIGN BUS CONTROL 4 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 2 ADDRESSING MODE BIT = 1 5 CONTROL LINE INPUT - CHANNEL CONTROL 6 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 3 ADDRESSING MODE BIT = 1 7 CONTROL LINE INPUT - STATUS REPLY - NOT WAITING 8 CONTROL LINE INPUT - STATUS REPLY - WAITING => IGNORE 9 CONTROL LINE INPUT - STATUS REQUEST - NOT WAITING 10 CONTROL LINE INPUT - STATUS REQUEST - WAITING 11 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 5 12 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 6 13 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 7 ADDRESSING MODE BIT = 0 14 CONTROL LINE INPUT - BIT #1 15
CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 8 ADDRESSING MODE BIT = 0 16 CONTROL LINE INPUT - BIT #2 17 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 9 18 CONTROL LINE INPUT - ILLEGAL COMMAND FUNCTION CODE = 10, 11 19 CONTROL LINE INPUT - RESPONSE - DISABLED => IGNORE 20 ##STR1## INTERNAL HARDWARE ERROR 21 CONTROL LINE INPUT - RESPONSE - BUS CONTROLLER - NOT WAITING => UNEXPECTED POLL RESPONSE 22 CONTROL LINE INPUT - NODE FAULT RESPONSE - BUS CONTROLLER - WAITING 23
CONTROL LINE INPUT - NO REQUEST RESPONSE - BUS CONTROLLER - WAITING 24 CONTROL LINE INPUT - NORMAL BUS REQUEST - BUS CONTROLLER - WAITING 25 CONTROL LINE INPUT - IMMEDIATE BUS REQUEST - BUS CONTROLLER - WAITING 26 CONTROL LINE INPUT - POLL OR SELECT - DISABLED => IGNORE 27 CONTROL LINE INPUT - POLL OR SELECT - BUS CONTROLLER - ##STR2## 28 ##STR3## ##STR4## 29 ##STR5## ##STR6## 30 ##STR7## ##STR8## 31 CONTROL LINE INPUT - ILLEGAL COMMANDS FUNCTION CODE = 14, 15 ADDRESSING MODE BIT = 1 32 USER ACTIVITY DETECTED 33 MICROPROCESSOR CONTROLLER ACTIVITY DETECTED 34 NORMAL MESSAGE TO SEND 35 IMMEDIATE MESSAGE TO SEND 36 DEFERRED TASK TO EXECUTE 37 NO TASKS REQUIRE SERVICE __________________________________________________________________________

TABLE V C ______________________________________ MAPPING PLA INPUTS ______________________________________ A15 NOT USED A14 ERROR FLAG A13 CONTROL LINE INPUT FLAG A12 USER ACTIVITY FLAG A11 MICROPROCESSOR CONTROLLER INTERRUPT FLAG A10
MESSAGE TO SEND FLAG A9 DEFERRED TASK FLAG (FIRMWARE FLAG 3) A8 PROCESSOR CONTROL LINE INPUT QUEUE BIT 2 (ADDRESSING MODE BIT) A7 PROCESSOR CONTROL LINE INPUT QUEUE BIT 6 (FUNCTION CODE 3) A6 PROCESSOR CONTROL LINE INPUT QUEUE BIT 6 (FUNCTION CODE
2) A5 PROCESSOR CONTROL LINE INPUT QUEUE BIT 4 (FUNCTION CODE 1) A4 PROCESSOR CONTROL LINE INPUT QUEUE BIT 3 (FUNCTION CODE 0) A3 BUS CONTROLLER (FIRMWARE FLAG 2) A2 DISABLE (FIRMWARE FLAG 1) A1 WAITING FOR POLL/RESPONSE FLAG A0 NORMAL (0)/IMMEDIATE (1) MESSAGE ______________________________________

Reviewing momentarily, it can be seen from an analysis of the Microinstruction and the manner in which its individual bits are assigned to different functions that the Microprogrammable Controller possesses the following capabilities:

(1) It executes a general purpose stored program;

(2) It can be directed to specific processing tasks via the Mapping PLA;

(3) It can interchange data with various node registers via the source and destination buses;

(4) It can issue control signals to the node; and

(5) It can sense the status of various node parameters.

MAPPING PLA

All firmware tasks executed by the Microprogrammable Controller are initiated via the Mapping Programmable Logic Array (PLA) 158 in FIG. 2b. When the performance of a specific task is required, the PLA generates an output which corresponds to the starting address of that task. As is shown in FIG. 4, the Mapping PLA 224 is driven by the output of octal latches 220 and 222. Each clock phase 5 timing signal latches the data on their respective input lines to generate a specific PLA output. If, on the next cycle, the Microprogrammable Controller executes a branch instruction with bit 19 of the Microinstruction Register set, it will branch to any one of 38 possible addresses determined by the various combinations of the inputs to latches 220
and 222. The so-called truth table for the Mapping PLA 224 is shown in Table VA below. Any combination of inputs A0 through A15 results in one of 38 PLA terms, each one corresponding to a unique output address labeled Z0 through Z7. Table VB is indicative of the task to be performed for each term while Table VC indicates the interpretation of inputs A0 through A15.

Inputs A9 through A14 can be considered to be the activity group. When all of these inputs are binary 0's and the Microprogrammable Controller has completed its previous task, it will go into an idle loop corresponding to Term 37 in Table VB. The PLA is programmed such that when any one of these lines goes high the appropriate task is initiated and, in the event that more than one line in this group goes high in a given cycle, a priority scheme is invoked to resolve the order in which the tasks will be executed. The highest priority activity is an interrupt from the Maintenance Control Unit (MCU) on input A-11. It will unconditionally generate output Term 33. The next highest priority is "user activity" on input A-12. It will generate output Term 32 conditional only on a 0 on input A-11. The next priority activity is the so-called "Error Flag" associated with input A-14 which will generate as its output Term 0 whenever inputs A-11 and A-12 are 0. This error flag will be generated by a 1 at any input of NOR gates 200,202,204,206 or 208.

The next highest priority is associated with the "control line input flag"-input A-13. This will cause one of the output Terms from 1 to 31 in Table VB to be generated where the specific term is determined by the states of the inputs A-1 through A-8 in Table VA. Inputs A-4 through A-8 are from the Control Word received from another transmitting node in the system. Inputs A-4 through A-7 represent the 4-bit control line function code while input A-8 is the so-called "addressing mode bit". When input A7 is a "0", the function code is a command resulting in output states defined by Terms 1 through 14 in Table VB. If inputs A-7 and A-6 are 1's, however, the function code is either a poll, a select or a response corresponding to the output states defined by Terms 19 through 31. Note that output terms are generated for both valid and invalid input codes.

Inputs A-0 through A-3 are driven by firmware flags and define the state that the node is in. For example, if input A-3 is a "0", the node is not functioning as the Bus Controller and therefore tasks will be initiated upon receipt of a poll or other bus commands. However, if input A-3 is a "1", the particular node is functioning as the Bus Controller and a task will be initiated upon receipt of a response during normal operation. Next in order of priority activity is the Message-to-Send flag input A-10 which results in either the output state defined by Term 34 or Term 35, depending on the binary value of input A-0. Finally, the lowest priority activity is associated with the Deferred Task Flag input A9 which results in output Term 36. The use of a PLA to analyze these inputs greatly improves the response to the Microprogrammable Controller to either polls or responses, since no firmware overhead is required to test for abnormal conditions. This feature is essential to achieving the high polling rate inherent in the preferred embodiment described herein.

TIME FOR SELECT FLAG

Referring next to FIGS. 5a and 5b, there is shown by means of a logic diagram the circuitry employed to generate the so-called Time-for-Select flag. It is this flag which is interpreted by the Microprogrammable Controller to indicate that, acting as the Bus Controller, it can now authorize another node to use the data channel. Toward this end, the Data Channel State Register shown enclosed by dashed line box 267 is comprised of two D-type flip-flops 268 and 270 which, together, may exist in four separate states, to wit:

(1) State 0--No activity currently exists on the data channel and no node has been authorized to use the channel.

(2) State 1--A select has been issued to a node and that node is currently using the data channel.

(3) State 2--A select has been issued to a node but that node has not begun to use the data channel.

(4) State 3--A select has been issued to a second node during the transmission sequence of the previously selected node.

The foregoing states are controlled by the signals on the Select Issued line 261 which connects to a "select" input of a dual 4 to 1 multiplexer 264 and by the "data line activity indicators" which control the setting of flip-flops 260 and 262
(FIG. 5a). When a message is transmitted by another node, it is detected at the bus input causing the Data Line Envelope Detect (Message Receive Envelope) line 255 to go high, such that the output from inverter 258 also goes high. If the node under consideration itself initiates a message transmission, the Data Line Output Transfer line 257 goes high and when the TB (Register B) line 253 also goes high, AND gate 250 is enabled. Thus, on clock phase 5, flip-flop 254 is set, causing the output from inverter 258 to go high. This condition prevails until the Data Line Output Transfer line 257 again goes low, indicating the end of the message transmission, after which the flip-flop 254 is clocked to its reset state. It can be seen, then, that the output from inverter 258 is high whenever the data line is active. The output from inverter 258 is passed through a 2-bit shift register comprised of the flip-flops 260 and 262 which are clocked by the phase 1 clock pulse. On the leading edge of the message, the flip-flop 260 will be set while flip-flop 262 remains reset, thereby causing the output of the Exclusive OR circuit 263 to be a binary "1" for a single clock pulse interval in that on the next clock pulse, both flip-flops 260 and 262 will be set. Similarly, on the trailing edge of the message, flip-flop 260 resets while flip-flop 262 remains set, such that the output from the Exclusive OR gate will again go positive for a single cycle. The output from the Exclusive OR circuit 263 can thus be considered as a form of edge detection for the message. It forms the lower order bit selection for the dual four-to-one multiplexer 264. The higher order bit selection of this multiplexer is governed by the Select Issued line 261 which goes positive for one clock period each time a select-type control transmission is issued.

The inputs to multiplexer 264 are hard wired to generate a unique 2-bit output for all four possible combinations of the selection inputs. This output is presented to the B-inputs of a 4-bit adder network 266. The A-inputs of this adder come from the outputs of the Data Channel State Register 267 and the outputs of the adder 266 are, in turn, applied as inputs to that same register. Thus, on the leading edge of each phase 1 clock pulse, the output of the multiplexer 264 is added to the contents of the Data Channel State Register and the resulting sum is stored back in that register. If these has been no "Select Issued" signal on line 261 and no message edge (leading or trailing) detected, the output from multiplexer 264 will be 0,0
and the Data Channel State Register 267 will have its contents remaining unchanged. If there is a "Select Issued" generated, but no edge detected, the output from multiplexer 264 will be 1,0 and the Data Channel State Register will thus be incremented by 2. When a message edge is detected, but a "select" has not been issued, the output of multiplexer 264 will be 1,1 which will have the effect of decrementing the Data Channel State Register by 1. If a "select" is issued simultaneously with a message edge detection, the output of multiplexer 264 will be 0,1, thus incrementing the Data Channel State Register 267.

If Firmware Flag #5 is set, or if either the Priority or Nonpriority queues are not empty, the NOR gate 272 will output a low signal indicating that a select is required as soon as the message line becomes available. The output of NOR gate 272
is used to partially enable the negative NAND gate 274 so that whenever the flip-flop 268 is reset indicating a data channel state of 1 or 0, it will be fully enabled. Thus, on the next phase 1 clock pulses, flip-flop 276 will output a high signal at its Q output, thus indicating the Latched Time for Select signal. This method of data line selection minimizes the firmware response time required to generate the next "select" transmission when the data line activity of the current select has been sensed. As such, in most cases, the next node to be selected will have received the Select command and will be ready to transmit its message at the end of the current message. Hence, intermessage dead time, which reduces channel capacity, is effectively avoided.

CONTROL LINE OUTPUT

Referring again to the overall system block diagram of FIG. 2 and particularly to FIG. 2a, there are four sources of Control Line output words, namely, the Command Register 136, the Response Register 138, the Poll List 140 and the Select Queue Register 142. Selection of the Control Word source is determined by Control Line Output Multiplexer 400 in FIG. 6a. These selections correspond to the states of 0,0; 0,1; 1,0; and 1,1 of Control Line Mux select lines 401 and 403. The Control Line Output Multiplexer outputs Z2 through Z14 to the corresponding inputs of the Control Word Latch 442 (FIG. 7b). Inputs A0 and A1 of latch 442 (FIG. 7b) are forced to the 1 state by virtue of being connected to a +5 V source. A0 provides the"sync" bit while A1 identifies the transmission as a control word. Input A15 of latch 442 is the parity bit generated by a Parity Generator 402 and 404.

Control word transmission is initiated by the "Send Word" signal which is initiated on clock phase 1 by the Control Line Sequencer PLA 144. On clock phase 3, NAND gate 440 is enabled causing the output of NAND 424 to go low and to latch in that condition via cross-coupled NAND gate 426. This enables the tri-state outputs of the Control Word Latch 442. On the trailing edge of clock phase 3, the output of NAND gate 440 goes positive, clocking latch 442 and putting the output of the Control Line Multiplexer on the CIO bus 132. Subsequently, clock phase 5 enables NAND gate 438 which causes the output of NAND gate 432 to go low and latch via cross-coupled NAND gate 434. This generates the "Control RC" signal at the output of inverter 436 which initiates the Control Line Encoder 130. At the end of the control word transmission, the "Control TC" signal resets the "Control RC" signal via inverter 406 and NAND gate 432. When the Control word has been latched in the Control Line Encoder, the "CONTROl CT" signal causes the output of NAND gate 432 to go high and latch via NAND gate 434, thereby clearing the "Control RC" signal. During initialization or after a fault condition, this function is accomplished by the "CLEAR ENCODER INTERFACE" signal. (See Table IV.)

Flip-flops 472 and 474 (FIG. 8) comprise the 2-bit Response Register 138 of FIG. 2a. The Response Register provides the code from the responding node to inform the Bus Controller or polling node of its status. The four possible responses, i.e., a "Node Fault" response, a "No Request" response, a "Normal Bus Request" and an "Immediate Bus Request", are encoded 0,0; 0,1; 1,0 and 1,1, respectively. These codes will be interpreted by inputs A4 and A5 of the Mapping PLA of the controlling node. The Response Register is not used by the Bus Controller node. The Response Register is loaded from the Microprogrammable Controller via the two least significant bits carried by the Destination Bus. When the Response Register Load Enable Line 463 is selected, a phase 5 clock pulse will load the data off bits 0 and 1 of the Destination Bus into the Response Register (See FIG. 8). Immediately after the response word has been loaded into the Control Word Latch 442, a phase 4 clock pulse will complete the enable of NAND gate 462, thus clearing the Response Register comprised of flip-flops 472 and 474. This action leaves the value 0,1 stored in the Response Register, corresponding to the "No Request" response. Thus, if no action is taken by the Microprogrammable Controller to reload the register before the next poll, the "No Request" response will be issued.

The format for the response word requires that bit 2 thereof be a 0, that bits 5 and 6 be 1's and, further, that bits 7 through 14 contain the address of the responding node. As can be seen from FIG. 6b, B2 is forced to 0 (ground) while the inputs B5 and B6 are forced to 1's (+5 V). Inputs B3 and B4 to the Control Line Output Multiplexer 400 are the 2-bit response code from flip-flops 472 and 474. Inputs B7 through B14 are node address bits 0 through 7, respectively.

Registers 468 and 470 constitute the upper and lower bytes of the 16-bit Command Register 136 in FIG. 2a. The register is loaded, one byte at a time, from the Microprogrammable Controller via the Destination Bus. When Command Register Byte 2
Load Enable line 457 is selected, a subsequent clock phase 5 pulse enables NAND gate 456 to load the upper byte. Similarly, a Command Register Byte 1 Load Enable on line 459 will cause the lower byte to be loaded. The format for a command word requires that bit 6 be a 1. Bits 3, 4 and 5 are the command code, while bit 2 indicates the addressing mode. If bit 2 is a 0, the command will be broadcast to all nodes. If it is a 1, the command will be broadcast to the addressed node where this address is contained in bits 7 through 14 of the command word. The Command Register outputs correspond to the A inputs of Control Line Output Multiplexer 400 of FIGS. 6a and 6b. The Select Multiplexer/Register 480 of FIG. 9 is a digital storage device which can be loaded from two sources via its A and B inputs. If the Select Register Destination Decode line 475 carries a 0 and the Load Select Register line 477 is selected, the next phase 5 clock pulse will enable negative AND gate 478 to thereby clock register
480. In this case, the outputs of the Select Register Queue corresponding to the A inputs of the multiplexer 480 will be loaded into the register. This is the condition for a "Normal" bus request. If the Microprogrammable Controller is processing an "Immediate" bus request, the Select Register Destination Decode line 475 will be set high, thus causing the contents of the Destination Bus (corresponding to the B inputs of the multiplexer) to be loaded into register 480, thus allowing the immediate bus request to gain precedence over previously queued selects.

The contents of register 480 can be sensed by the Microprogrammable Controller via the Source Multiplexer 832 of FIG. 3b. The control word format for a "select" requires that bits 2, 3, 5 and 6 each be a 1 and that bits 7 through 14 contain the address of node to be selected. Referring to multiplexer 400 in FIGS. 6a and 6b, it is to be noted that the D-inputs thereto correspond to the select mode. Inputs D2, D5 and D6 are forced to 1's while inputs D7 through D14 are connected to the output of the Select Register 480. The format for the poll control word also requires that bits 2, 5 and 6 be set. It is distinguished from the select word only by the different response code as previously mentioned. The poll word corresponds to the C inputs of multiplexer 400. Inputs C2, C5 and C6 are all forced to 1's. Inputs C7 through C14 are connected to the outputs of the Poll List, which provides the address of the node to be polled. This method of generating control word outputs is significant in maintaining a high degree of control line bus utilization. Whenever a control word is transmitted, the next control word of that type is computed and loaded into the corresponding register. Thus, it can be automatically sent, as required, under control of the Control Line Sequencer PLA 144 in FIG. 2a. This eliminates any dead time that would otherwise be required for processing overhead. One of the features of the present system is that the Bus Controller's responsibility is assignable to various nodes. This requires that each node, when in the Bus Controller role, be able to sense when it is itself being selected. This is the function of comparator 482 which compares the output of the Select Queue FIFO's 811 and 819 in FIGS. 22a and 22b to the node address, thus generating the "Own Node Select Flag". When this condition is detected, the Microprogrammable Controller suppresses the transmission of the select word and handles the select internally in its own firmware.

POLL LISTS

It is the Poll Lists which determine the order in which the Bus Controller polls all nodes, including itself. The polling order is contained in the user computer and is loaded into various registers and memories of the Poll Lists via the Microprogrammable Controller. Once this information has been entered into the poll lists, polling proceeds as previously described. The Priority Poll List contains the node addresses of up to 16 priority nodes, while the Non-priority Poll List contains the node addresses of all other nodes utilized in the system. The polling process proceeds as follows:

(1) Priority nodes are sequentially polled until the end of the Priority Poll List is reached;

(2) Starting at the top of the Non-priority Poll List, a specified number of non-priority nodes are polled where this number is referred to as the sub-cycle count;

(3) All priority nodes are again polled;

(4) Polling of non-priority nodes resumes at the point after the last non-priority poll and continues until the sub-cycle count is reached;

(5) Polling alternates between priority and non-priority polls until the end of the Non-priority List is reached; and

(6) Non-priority polling starts at the top of the Non-priority List.

It can be seen then that the information required to initialize the poll lists consists of:

(a) The poll addresses;

(b) The number of priority polls;

(c) The number of non-priority polls; and

(d) The sub-cycle count.

Referring to FIG. 10b, there is identified by numeral 518 the 16-word Priority Poll List Memory which is arranged to store the node addresses of the priority nodes. The memory 518 is arranged to be addressed by the output of a 4-bit Priority Counter 506 which has its Q.sub.0 through Q.sub.3 outputs coupled to the select inputs of the Priority Poll List Memory 518. When a low signal is applied to line 505 labeled CLR PRIORITY CTR, the 4-bit Priority Counter 506 will be reset, thus pointing to the top of the Priority Poll List stored in the RAM device 518. The outputs from the Priority Poll List Memory 518 are normally in a high state. If the Priority List Memory Enable line 517 goes low, it causes the contents of memory address 0 to be put on the Poll List Output Bus which bus is shared by the Non-priority Poll List Memory 530 (FIG. 11). This data is also available to the Microprogrammable Controller via the Source Multiplexer 832 (FIG. 3), thereby allowing polling order verification. When the Advance Priority List line 507 goes high, it causes the Priority Counter 506 to be incremented to thereby point to the next poll stored in the Priority Poll List Memory 518. To enter a poll address into the Priority Poll List, the Non-Priority List Memory Enable line 529 must be high and the Poll List Write Enable line 509 must also be high. Hence, when on the leading edge of clock phase 4, the output from NAND gate 508 goes low, generating a Priority List Write Enable, the data from the Destination Bus Holding Register 856 (FIG. 23) is loaded into the memory 518 at the particular address which is specified by the then-contents of the Priority Counter 506.

A further register termed the End Priority List Register 502 is provided and is utilized to hold the address of the last entry contained in the Priority List. The register 502 is adapted to be loaded from the Microprogrammable Controller by way of the Destination Bus when the End Priority List Register Load Enable line 501 is activated on the leading edge of a phase 5 clock pulse. The output from the End Priority List Register 502 is applied to a first set of inputs of a 4-bit comparator 510, while the second set of inputs to the comparator arrive from the Priority Counter 506. Wen the first and second set of inputs become equal, the comparator 510 outputs a "1". It is to be noted at this point that the flip-flop 504 is cleared at the same time that the Priority Counter 506 is cleared. If the count in register 502 is less than sixteen, its output Q4 will be low, and, hence, the output of Exclusive OR gate 512 will also be low such that inverter 514 outputs a high signal to a first input of AND gate 516. When the count in the counter 506 becomes equal to the count in the End Priority List Register 502, AND gate 516 will be fully enabled to thereby generate the command Priority List End Compare which is used to shift operation from priority polling to non-priority polling. If the count contained within the register 502 is sixteen, its Q4 output will be a binary "1" signal and the outputs Q.sub.3 through Q.sub.0 will be 0's. Now, when the counter 506 is cleared, there will be a match detected by the comparator 510 causing its output to go high. However, AND gate 516 is disabled at this time because the output from the Exclusive OR gate 512 will be a "1" under the assumed circumstances. When polling has progressed through all sixteen addresses, the Priority Counter 506 overflows, causing flip-flop 504 to be clocked to its set state. Now, the output of Exclusive OR 512 goes low, enabling the generation of the Priority List End Compare command.

The addresses of the non-priority nodes are contained in a 256-word Non-priority Poll List Memory 530. Its operation is quite similar to the above-described operation of the Priority Poll List Memory 518. That is, the memory address is derived from an 8-bit Non-priority Counter 520. As before, when this counter is cleared by a low signal on line 519, it addresses or points to the top entry in the Non-priority Poll List Memory 530.

When the Advance Non-Priority List line 521 goes high, it increments the counter 520 to access the next succeeding non-priority poll entry. The address of the node to be polled is put out on the Poll List Output Bus whenever the Non-priority List Memory Enable line 529 (FIG. 11) goes low.

Writing into the Non-priority Poll List Memory 530 is under control of a flip-flop comprised of cross-coupled NAND gates 526 and 528. Whenever the Poll List Write Enable line 525 and the Priority List Memory Enable line 527 are simultaneously high, the leading edge of a clock phase 4 pulse will enable NAND gate 524, causing the output of NAND gate 528 to go low, thus transferring the contents of the Destination Bus Holding Register 856 (FIG. 23) into the address location in memory 530
specified by the then-contents of the Non-priority Counter 520. The leading edge of clock phase 1 terminates the Memory Write Enable command.

Shown in FIG. 12 is an 8-bit counter 536, referred to as the Sub-cycle Counter, which controls the non-priority sub-cycle interval. The counter 536 is cleared when the Clear Non-priority Sub-cycle Counter line 535 goes low and is incremented each time the Advance Non-priority List line 537 goes high. The Sub-cycle Count Register 534 is adapted to be loaded by the Microprogrammable Controller via the Destination Bus on the leading edge of a clock phase 5 pulse whenever the line 531 labeled "Number of Non-priority Users Per Sub-cycle Load Enable" is selected and goes high. The output from the Sub-cycle Count Register 534 is available to the Microprogrammable Controller for verification via the Source Multiplexer 832 of FIG. 3.

As was earlier true with the priority list accessing circuitry, in the case of the non-priority accessing circuitry the contents of register 534 and the counter 536 are compared in an 8-bit comparator 538 such that when equality is detected, the output from the comparator 538 goes low, thus generating the End of Non-priority Sub-cycle Compare signal on line 539.

With reference to FIG. 13a, the End Non-priority List Register 540 is loaded from the Microprogrammable Controller via the Destination Bus on the leading edge of a clock phase 5 signal whenever the End Non-priority List Register Load Enable line
577 is selected. The output from the register 540 is compared with the output of counter 520 in an 8-bit comparator 542. Hence, when these two counts become equal, the output of inverter 576 goes high. Again, the output from the register 540 becomes available to the Microprogrammable Controller for verification by way of the Source Multiplexer on FIG. 3.

The polling mode is determined by the state of the flip-flop comprised of the cross-coupled NAND gates 548 and 550. When the output of NAND gate 548 is low, the priority polling mode is enabled and when the output of NAND gate 550 is low, the non-priority polling mode is enabled. When the polling operation is first initiated, the Force Priority Poll line 543 is selected. Thus, on clock phase 4, NAND gate 544 is enabled and NAND gate 550 is disabled. This establishes the priority polling mode. Next, the Reset Poll List line 553 is selected. Hence, on clock phase 4, the AND gate 554 is fully enabled, causing the Non-priority Counter 520 to clear via the output from NOR gate 570, the Non-priority Sub-cycle Counter 536 to clear due to the control signal applied thereto from the output of NOR gate 572 and the Priority Counter 506 to clear due to the control signal emanating from NOR gate 574. The foregoing events cause the first poll to be accessed from address 0 of the Priority Poll List Memory 518. When that poll is complete, the Advance Poll List line 563 is selected. Because the output of NAND gate 550 is high at this time, a clock phase 4 signal will enable AND gate 566, thus generating an Advance Priority List pulse which, when applied to the Priority List Counter 506, causes it to be incremented. The flip-flop 580 is clocked at the beginning of each cycle of the phase 1 clock pulse. Thus, its output reflects the polling mode of the previous cycle. For the priority mode, the output of flip-flop 580 is low and thus the output of inverter 560 is high. Polling proceeds sequentially to the end of the priority polling list stored in the random access memory device 518 at which time the output from AND gate 516 (FIG. 10a) generates the Priority List End Compare signal which is applied as a first input to AND gate 562. Hence, on clock phase 2 AND gate 562 will be fully enabled, causing NOR gate 574 to output the command "Cir Priority Counter" which, in turn, is applied by way of line 505 to the appropriate terminal of the Priority Counter 506 causing it to be set to all zero's. Also, NAND gate 548 will be disabled by way of the output from the inverter 546 causing the flip-flop comprised of NAND gates 548 and 550 to change to the non-priority polling mode condition.

The next poll will thus be accessed from address 0 of the Non-priority Poll List Memory 530. The output from NAND gate 548 is now high, Thus, when the Advance Poll List line 563 is selected, the phase 4 clock pulse will enable AND gate 564, thus incrementing the Non-priority Counter 520 and the 8-bit Sub-cycle Counter 536. Because the output of flip-flop 580 will now be high, AND gate 558 will be partially enabled. Then, when the Sub-cycle Counter 536 reaches its count limit, the output from comparator 538 will cause inverter 556 to output a high signal. On the next phase 2 clock pulse, AND gate 558 will be fully enabled and will cause the NOR gate 572 to output a signal for clearing the Non-priority Sub-cycle Counter 563 while simultaneously causing NAND gate 550 to be disabled via the output from inverter 552. This latter action causes the mode control flip-flop (548-550) to revert to the priority polling mode condition.

It is to be noted that the state of the Non-priority Counter 520 remains unchanged by this action. Polling proceeds alternating between the priority and non-priority mode until the end of the non-priority list is reached at which time the output from comparator 542 causes the output of inverter 576 to go high. When this happens, on the next phase 2 clock pulse, AND gate 568 will be enabled causing the counter 520 to be cleared via the output from NOR gate 570. When the Clear Poll/Response Enable line 585 (FIG. 14) goes high, the current output of the poll list is latched into a holding register 586 and the state of the Non-priority List Memory Enable line coming from the output of NAND gate 548 is latched into a D-type flip-flop 582. The output of this flip-flop is, in turn, latched into flip-flop 584 on the next subsequent phase 1 clock pulse to thereby yield a signal at its Q output indicative of whether the previous poll was a priority-type or a non-priority-type transaction.

The output from the holding register 586 is used to compare the address of the response to the address of the poll. The holding register is required since the next polling cycle is being set up while the response to the previous poll is being compared. The output from register 586 is also available to the Microprogrammable Controller by way of the Source Multiplexer 832 of FIG. 3.

The outputs from the Poll List Memories 518 and 530 are compared to the node address by a further 8-bit comparator 588. When equality is detected, the output from comparator 588 goes low thereby indicating that the node in question is polling itself. This polling technique maintains a very high polling rate by minimizing the processing overhead in the Microprogrammable Controller. Only a single microinstruction is required to generate the Advance Poll List signal for each poll. The high polling rate, coupled with the ability to distinguish priority from non-priority nodes, assures that the priority nodes will gain access to the bus in the minimum time.

CONTROL LINE INPUT

The Control Line Multiplexer/Register consists of the upper byte 628 and the lower byte 630 (FIGS. 15a and 15b). Data is entered into these registers, either from the Control Line Decoder 130 via the CIO bus 132 or from the Microprogrammable Controller via the Destination Bus 172, the former being the more normal mode of operation. When the Control Line Encoder has assembled a control word, the Control Line Input Present signal goes low, causing the output of NAND gate 603 to go high and latch via NAND gate 601. This occurs on clock phase 3. With the output from NAND gate 601 low, the output of inverter 610 is high, partially enabling NAND gate 618. Then, on the next phase 5 clock pulse, NAND gate 618 is enabled, causing clock pulses to be generated via negative OR gates 620 and 622. Since at this time both the byte 1 and byte 2 Control Line Input Register Load Enable lines 611 and 612 are low, the output of NOR gate 624 will be high. Thus, the output of inverter 626 will be low, selecting the A-inputs to the multiplexer 628 - 630. This causes the control word on the CIO bus to be latched simultaneously into both the upper and lower bytes of the Control Line Input Multiplexer/Register. At this time, NAND gate 608 is also partially enabled via NAND gate 601 and negative OR gate 606 so that on the next phase 1 clock pulse, flip-flop 612 is clocked to the set condition, indicating that a valid word is now loaded into the Control Line Input Register. Finally, the Phase 2
clock pulse causes the output of NAND gate 601 to go high and latch via NAND gate 603, thus resetting the system for the next control word transfer. Either a Clear Valid Word signal or a Clear Encoder Interface signal will propagate through negative OR gate 600 and inverter 602 to clear flip-flop 612.

To load the Control Line Input Register 628-630 from the Microprogrammable Controller, the Control Line Input Register Byte 1 Load Enable signal on line 611 is selected, thus partially enabling NAND gate 616 and causing the B-inputs to the multiplexer to be selected via NOR gate 624 and inverter 626. The next phase 5 clock pulse will enable NAND gate 616 and negative OR gate 622 to generate a clock pulse which loads the contents of the Destination Bus into the lower byte register 630. Similarly, on a subsequent cycle, the Control Line Input Register Byte 2 Load Enable signal on line 613 is selected to cause the contents of the Destination Bus to be loaded into the upper byte register 628. This action also sets the flip-flop formed by cross-coupled NAND gates 604 and 605, thus enabling the next phase 1 clock pulse to set flip-flop 612 to indicate a valid word. This flip-flop is reset on the next Phase 2 clock pulse.

With reference to FIG. 16, the Node Address Selector Switches 631 are set to define an 8-bit code identifying the node address. The node address is compared to output bits 7 through 14 of the Control Line Input Register by the 8-bit comparator
632. If the node has received a poll, select or a command in which the address field of the control word matches the node address, the output of comparator 632 generates the "Node Address Match" signal. This signal is used by the Sequencer PLA when the node in question is not that designated as the Bus Controller to allow it to ignore all point-to-point transmissions which are addressed to other nodes. The address field of the Control Line Input Register is also compared to the last poll address by an
8-bit comparator 634 to generate the "Response Address Match" signal. This signal is used by the Sequencer PLA when the node in question is the Bus Controller to verify that the responding node was, in fact, the node which had been previously polled.

Since it is possible that control line inputs occur more rapidly than the Microprogrammable Controller can process them on an instantaneous basis, an elastic buffer is required. This is the function of the 16 word control line input FIFO buffer
636 of FIG. 17. The FIFO buffer is initialized by selecting the Clear Control Line Input Queue line 635 which resets both the input and output pointers in the FIFO 636. The Output Ready signal (OR) of FIFO 636 will thus be low indicating that the queue is empty. The FIFO buffer is loaded by the positive transition of the Clock B input and is unloaded by the positive transition of the Clock In input.

With reference also to FIG. 18a, consider first the case where the queue is empty and the flip-flop formed by NAND gates 670 and 672 is reset, such that the Control Line Input Word Indicator line 675 is low. When the Control Line Sequencer PLA detects a control word which is relevant to the node, it generates a Load Processor Queue signal which functions to partially enable NAND gate 664. Since inverter 662 and NAND gate 670 are both high at this time, the next phase 3 clock pulse will fully enable NAND gate 664, thus disabling Negative OR gate 668. On the leading edge of the phase 3 clock pulse, the contents of the Control Line Input Register 628-630 are loaded into Register 676. Since the Processor Control Line Input Queue is empty, the selection of inputs for the Processor Control Line Input Multiplexer/Register 676 will be its A-inputs.

The output of Negative OR gate 668 also causes the output of NAND gate 672 to go high and latch via NAND gate 670. This indicates to the Mapping PLA that there is a new control word present and the Microprogrammable Controller is vectored to the appropriate processing task to deal with this control word. When the Microprogrammable Controller has completed branching to the specified processing task, it initiates the Clear Control Line Input Indicator signal on line 659 which is AND'ed with a phase 4 clock signal to reset the CONTROL Line Input Word Indicator flip-flop 674. If the Microprogrammable Controller completes this response before the next Load Processor Queue command appears on line 663, it effectively keeps up and the queue is completely by-passed with the data flowing directly from the Control Line Input Register 628-630 to the Processor Control Line Input Mux/Register 676. Note that outputs Q2 through Q6 of register 676 provide the control line inputs to the Mapping PLA and also that all outputs of register 676 are available to the Microprogrammable Controller via the source multiplexer.

With continued reference to FIG. 18a, consider next the case where a Load Processor Queue Command on line 663 occurs before the flip-flop comprised of cross-coupled NAND gates 670 and 672 can be reset. In this case, the output of NAND gate 670
is low, thus disabling NAND gates 664 and 666. Since the output of NAND gate 672 is high, NAND gate 644 (FIG. 17) is partially enabled via inverter 642 and NOR gate 640. Thus, on the phase 2 clock pulse, the NAND gate 644 is fully enabled generating a Load FIFO signal via inverter 646. This causes the Processor Control Line Input Queue Empty line 637 to go high. At this time, the output of FIFO 636 corresponds to the output of the Control Line Input Register 628-630 of FIGS. 15a and 15b. Once there is a word in the queue, subsequent control line input words will continue to be directed into the queue since the FIFO output enables NAND gate 644 via inverter 642 and NOR gate 640. It is to be noted that, now, NAND gate 664 is disabled via inverter
662 and that NAND gate 666 is partially enabled. Hence, when the Control Line Input Word Indicator flip-flop 670-672 is reset, the next phase 3 clock pulse will enable NAND gate 666 which disables Negative OR gate 668 so that on the leading edge of this clock pulse register 676 is loaded. Since the Select line 677 is now high, the data is taken from the B-inputs, which correspond to the output of FIFO 636, thus loading the first control word queued into the register. At the same time, the Control Line Input Word Indicator flip-flop is again set. The output of NAND gate 666 also sets the flip-flop formed by NAND gates 648 and 650 (FIG. 17) thus partially enabling NAND gate 652 so that on the next phase 4 clock pulse a FIFO Unload clock pulse is generated, advancing the pointer in the FIFO such that the output now corresponds to the next queued control word. This flip-flop is then reset on the next phase 1 clock pulse. This process of sequentially unloading the queue continues until the Microprogrammable Controller catches up, at which time the circuit reverts to the queue by-pass mode.

CONTROL LINE SEQUENCER

The Control Line Sequencer 144 in FIG. 2 is set out in greater detail in FIGS. 19a, 19b and 20 and serves to control the node's interface with the data bus system control line. It performs a pre-processing function on all control line inputs and sorts out all words that are irrelevant to this node. Only the control line words of importance to this particular node will be passed on to the node's Microprogrammable Controller for further processing. This pre-processing function provides the prompt response necessary to maintain a high polling rate. The Control Line Sequencer can initiate the next appropriate transmission on the control line generally within less than 1.5 microseconds after receipt of the previous transmission. If all of the necessary processing were to be performed solely within the Microprogrammable Controller, it would take significantly longer and would thus reduce the efficiency of the bus control system. The key to the high speed operation of the Control Line Sequencer is the fact that it can do many operations in parallel. For example, in a single 250 nanosecond machine cycle, it can recognize that a control line input has occurred, decode the function code, check the address field to see if it is relevant to this node and check to see if a word should be sent out in response. Another significant feature of the Control Line Sequencer is its ability to handle all types of control line transmissions, either as a Bus Controller or as a non-bus controller.

The central element of the Control Line Sequencer is the Programmable Logic Array 748 (FIG. 19a). The Truth Table for the PLA is shown in Table VIA below. A description of the 36 possible output terms generated is shown in Table VIB and a description of the A-inputs and Z outputs is shown in Table VIC.

TABLE VI A __________________________________________________________________________ CONTROL LINE SEQUENCER PLA TRUTH TABLE A-Inputs Z-Outputs Term 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 __________________________________________________________________________ 0 1 1 X X X X X X X X X X X X X X 0 0 1 0 1 0 0 0 1 0 0 X X 0 X X X X X X 1 0 1 X X 0 0 0 0 0 1 0 0 2 0 0 X X 0 0 X X X X X 1 0 0 0 1 0 1 0 0 0 1 0 0 3 0 0 X X 0 1 X X X X X 1 0 0 1 X 1 1 0 0 0 1 0 0 4 0 0 X X 0 1 X X X X X 1 0 0 0 1 1 0 0 0 0 1 0 0 5 0 1 X X 0 X 0 0 1 0 0 X X X X X 0 0 1 0 1 0 0 0 6 0 1 X X 0 X 1 X X X X X X X X X 0 0 1 0 1 0 1 0 7 0 1 X X 0 X 0 1 X X X X X X X X 0 0 1 0 1 0 1 0 8 0
1 X X 0 X 0 X 0 X X X X X X X 0 0 1 0 1 0 1 0 9 0 1 X X 0 X 0 X X 1 X X X X X X 0 0 1 0 1 0 1 0 10 0 1 X X 0 X 0 X X X 1 X X X X X 0 0 1 0 1 0 1 0 11 0 0 X X X X X X X X X 1 1 X X X 0 0 0 0 0 1 0 0 12 0 1 X X 1 0 0 1 1 X X X X X X X 0 0 1 0 0 0 0 0 13 0 1 1 X 1 0 1 X X X X X X X X X 0 0 1 0 0 0 0 0 14 0 1 X X 1 0 0 0 X X X X X X X X 0 0 1 0 1 0 0 0 15 0 1 X X 1 0 0 X 0 X X X X X X X 0 0 1 0 1 0 0 0 16 0 1 0 X 1 0 1 0 X X X X X X X X 0 0 1 0 1 0 0 0 17 0 1 0 X 1 0 1 X 0
X X X X X X X 0 0 1 0 1 0 0 0 18 0 1 0 X 1 0 1 X X 1 X X X X X X 0 0 1 0 1 0 0 0 19 0 1 0 X 1 0 1 X X X 1 X X X 0 X 0 0 1 0 1 0 0 0 20 0 1 0 X 1 0 1 1 1 0 0 X X X 1 X 0 0 1 0 0 0 0 0 21 0 1 0 X 1 0 1 1 1 0 1 X X X 1 X 0 0 1 0 0 0 0 0
22 0 1 0 X 1 0 1 1 1 0 0 1 X 1 0 X 0 0 1 1 1 1 0 0 23 0 1 0 X 1 0 1 1 1 0 0 1 X 0 0 X 0 1 1 0 1 1 0 0 24 0 1 0 X 1 0 1 1 1 0 0 0 X X X X 0 0 1 0 1 0 1 0 25 0 1 X X 1 1 0 0 X X X X X X X X 0 0 1 0 1 0 0 0 26 0 1 X X 1 1 0 X 0 X X X X X X X
0 0 1 0 1 0 0 0 27 0 1 1 X 1 1 1 X X X X X X X X X 0 0 1 0 0 0 0 0 28 0 1 0 X 1 1 1 X X X X X X X X X 0 0 1 0 1 0 0 0 29 0 1 X 0 1 1 0 1 1 X X 0 X X X X 0 0 1 1 1 0 0 1 30 0 1 X 0 1 1 0 1 1 X X 1 X 0 0 0 0 0 1 1 1 0 0 1 31 0 1 X 0 1 1
0 1 1 X X 1 X 1 X X 0 0 1 1 1 1 0 1 32 0 1 X 0 1 1 0 1 1 X X 1 X 0 1 X 1 1 1 1 1 1 0 1 33 0 1 X 0 1 1 0 1 1 X X 1 X 0 0 1 1 0 1 0 1 1 0 1 34 0 1 X 0 1 1 0 1 1 X X X X X X X 0 0 1 0 1 0 1 1 35 All Other Input Conditions 0 0 0 0 0 0 0 0 __________________________________________________________________________

TABLE II B __________________________________________________________________________ CONTROL LINE SEQUENCER PLA STATE DESCRIPTIONS TERM DESCRIPTION __________________________________________________________________________ 0 AUTO LOOP ERROR SET .multidot. CONTROL LINE INPUT 1 ##STR9## 2 ##STR10## ##STR11## 3 ##STR12## ##STR13## 4 ##STR14## ##STR15## 5 ##STR16## 6 ##STR17## 7 ##STR18## 8 ##STR19## 9 ##STR20## 10 ##STR21## 11 FORCED COMMAND .multidot. CLEAR-TO-SEND 12 ##STR22## 13 ##STR23## ##STR24## 14 ##STR25## ##STR26## 15 ##STR27## ##STR28## 16 ##STR29## ##STR30## 17 ##STR31## ##STR32## 18 ##STR33## ##STR34## 19 ##STR35## ##STR36## 20 ##STR37## COMMAND .multidot. POLL .multidot. NODE ADDRESS MATCH .multidot. DISABLED 21 ##STR38## COMMAND .multidot. SELECT .multidot. NODE ADDRESS MATCH .multidot. DISABLED 22 ##STR39## COMMAND .multidot. POLL .multidot. NODE ADDRESS MATCH .multidot. COMMAND QUEUED .multidot. ENABLED .multidot. CLEAR-TO-SEND