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United States Patent
4339796
Brereton , ; et al.
July 13, 1982
Title
System for generating a plurality of different addresses for a working memory of a microcontroller during execution of certain instructions
Abstract
A system is disclosed for a microcontroller which permits the interruption of a sequence of instructions, each of which are executable in a fixed machine cycle in response to one of a plurality of interrupt/trap signals. The microcontroller is interrupted for one fixed period machine cycle, during which period one of a plurality of instructions are read out from an instruction storage location of a memory determined by the active interrupt/trap signal concurrently as data stored in separate registers, which define the condition of the microcontroller at the point of interruption, are transferred to one group of locations in a storage device which is different than the memory which stores the instruction. After the transfer, another group of storage locations also determined by the active trap request signal is available to instructions which executed in subsequent machine cycles. The system further responds to a set machine level instruction of the microcontroller which functions to transfer the data defining the previous condition of the microcontroller at the point of interruption which has been stored in the storage device back to the plurality of registers. The system allows the microprogrammer a choice between treating the interrupt/trap signal as either a true interrupt to the program, which must be continued from the point of interruption, or a fast trap in the program where there is a need to take some immediate action and, in certain circumstances, no need or desire to return to the point of interruption.
Inventors:
Brereton; David A.
(San Jose,
CA
)
, Stansbury; Buddy F.
(San Jose,
CA
)
Assignee:
International Business Machines Corporation
(Armonk,
NY
)
Appl. No.:
133993
Filed:
March 26, 1980
Current U.S. Class:
712/228
712/244
710/264
Field of Search:
364/2MSFile,9MSFile
U.S. Patent Documents
4074353
February 1978
Woods et al.
Primary Examiner:
Zache; Raulfe B.
Attorney, Agent or Firm:
Cummins; R. E.
Parent Case Text
This is a division, of application Ser. No. 921,147 filed June 30, 1978.
Claims
Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:
1. In a microcontroller having memory means for storing different types of instructions at individually addressable storage locations, memory addressing means connected to said memory means, a plurality of registers for storing first data which define the condition of said microcontroller at the conclusion of each instruction, means connected to the output of said memory for executing in an ordered manner each of said instructions in a fixed period machine cycle, and a multi-level trap system connected to said memory addressing means and said means for executing for interrupting said ordered manner at the end of an instruction for one fixed period machine cycle selectively in response to one of a plurality of trap request signals, the improvement comprising:
storage means for storing data employed in the execution of said instructions at individual storage locations;
means for addressing said storage means comprising first and second groups of partial address generators and means for selectively combining the partial addresses generated by one generator from each said first and second groups to address one of said storage locations;
said first group of partial address generators including a level register having an input connected to said trap system for defining first groups of storage locations each having a common partial address determined by the contents of said level register;
said second group of partial address generators including a counter for defining storage locations in each of said first groups which have a common partial address determined by the contents of said counter; and
control means connected to said storage addressing means for controlling said storage addressing means during the next fixed period machine cycle following the interruption of said microcontroller to permit the transfer of said first data from said plurality of registers to a like plurality of storage locations, said control means further including means for converting each of said plurality of trap signals to a different unique memory address, means for supplying said unique memory address to said memory addressing means at the start of said next fixed period machine cycle to cause during said next fixed machine cycle the readout of the next instruction to be executed from said unique memory address to said control means concurrently with said transfer of said first data to said storage means, and encoding means associated with said trap system and connected to said level register for supplying to said level register at the end of said next fixed length machine cycle a unique partial storage address determined by said trap signal to permit subsequently executed instructions to address another of said first groups of storage locations in said storage means.
2. The microcontroller recited in claim 1 in which said plurality of registers includes a program counter register, a status register and a mask register, and said microcontroller further includes:
means for selectively connecting said program counter register to said memory address means and to the input of said storage means;
means for selectively connecting said status register to said input of said storage means;
means for selectively connecting said mask register to the input of said storage means; and
means connecting said control means to each of said means for selectively connecting, to provide data transfer control signals thereto at different preselected times during said next fixed period machine cycle.
3. The microcontroller recited in claim 2 in which said trap system includes:
means for assigning a different priority level to each of said trap request signals;
means for determining said trap request signal having the highest priority; and
means connecting said determining means to said encoding means and said converting means whereby the condition of said microcontroller at the time of interruption, as represented by the contents of said plurality of registers, is stored in the group of storage locations determined by the partial address supplied from said level register at the time of interruption and another group of storage locations determined by said encoded trap request signal having the highest priority is addressable by subsequently executed instructions.
4. The microcontroller recited in claim 3 in which said memory addressing means includes a memory address register and further including means selectively connecting the output of said storage means to said memory address register and said control means further includes means operable in response to a set machine level (SML) instruction to:
(1) transfer the contents of a predefined field of said SML instruction which corresponds to one of said unique partial storage addresses to said level register at the start of said fixed period machine cycle;
(2) control said counter to address storage locations containing said data which defines the condition of said microcontroller at the point of a previous interruption; and
(3) causes transfer of said data from said addressed locations to said memory address register, said mask register and said status register at preselected times during the execution of said SML instruction.
5. The microcontroller recited in claim 4 in which said program counter register comprises a Program Couner Low section and a Program Counter High section, said memory address register comprises a Memory Address Low section and a Memory Address High section, and said control means provides a different data transfer control signal to each said section at different preselected times.
6. The microcontroller recited in claim 5 further including clocking means connected to said control means, said memory means, and said storage means for establishing said fixed period machine cycle including first clocking means for establishing a predetermined number of equal sub-periods of said fixed period machine cycle and second clocking means for establishing read and write transfer cycles for transfer of said data to and from said storage means, each said transfer cycle being a predetermined fraction of one of said subperiods.
7. The microcontroller recited in claim 6 in which said predetermined fraction is 3/4.
Description
DESCRIPTION
1. Techinical Field
This invention relates in general to microcontrollers and specifically to microcontrollers for controlling the transfer of data between a control unit connected to a central processing unit of the data processing system and a plurality of storage units.
2. Related Applications
The following applications are related to the present application:
1. Ser. No. 921,146, filed June 39, 1978, directed to a system for controlling a serial read-write channel which employs the microcontroller of the present inventin.
2. Ser. No. 921,150, filed June 30, 1978, directed to a system for calculating the propagation delay of interface cables interconnecting a control unit and a controller.
3. U.S. Pat. No. 4,185,269, issued Jan. 22, 1980, directed to a system for generating error correcting check bytes under the control of the microcontroller of the present invention for data to be recorded on one of the devices being controlled by the microcontroller.
BACKGROUND ART
The throughput of a data processing system is to a large extent dependent on the system's ability to transfer data between peripheral storage devices and the central processing unit (CPU). The transfer path between a given storage device and the CPU usually involves a channel, a control unit and a controller. The control unit is generally a separate unit which is connected to a channel via a standard interface. The storage devices, i.e., disk files are generally arranged in a string consisting of a disk file controller and a group, usually 6 or 8, of disk files which are connected to the controller via a control interface. The controller in turn is connected to the control unit through another interface. An example of one such arrangement is the IBM 3830 Mod II control unit which connects to a System/360 or 370 central procssing unit through a block multiplexor channel. The 3830 Mod II is used to connect one or more strings of disk storage devices, such as the Models 3330, 3340 or 3350 disk files, to the system.
The string consists of an A box comprising a controller and a disk drive. The controller is connected to the control unit by a standard IBM interface referred to as CTL interface and to the drives by another standard interface referred to as the file control interface or simply FCI.
The overall function of the controller is to interpret and execute orders or commands issued by the storage control unit. Execution of these orders involves controlling both interfaces, controlling the track format, clocking and serializing the data during a transfer of data to the file and deserializing the data during a transfer of data from the file, checking the integrity of the transferred data through appropriate error correcting hardware, furnishing to the control unit the status of the controller and each of the attached devices when requested and diagnostic evaluation of the system when an error occurs.
File controllers have been implemented using large scale integration circuit technology and on a cost basis appear very favorable provided there are never any changes or additions to the initial functions. It has been recognized however, that each time a change such as the addition of a new function, has to be made, one or more of the large scale integrated modules has to be redesigned. This process is expensive in both time and money and, therefore, increases the overall cost.
The obvious solution to the problem of inflexibility of LSI combinatorial logic is a microprocessor. The microprocessor, once it is designed, can be readily and rapidly changed to accommodate new functions by merely changing the microprogram and thus avoid the constraints of the LSI process.
However, when it becomes necessary to maintain a high data transfer rate between the controlled device and the unit issuing the commands, it becomes readily apparent that any microprocessor cannot be used. At data transfer rates in the range of
1.75 megabytes/second, commands must be decoded and responses generated by the controller within nanoseconds. Prior art microprocessors are either too expensive or too slow relative to combinatorial logic to cope effectively with these increased data transfer rates.
There is, therefore, a need for an improved lower cost controller which can interpret macro orders from the control unit at a speed which matches the data transfer rate, and control both interfaces such that a minimum of time is lost in establishing a connection between a selected file and the control unit, has the flexibility to work with a number of devices attached to the interfaces and can be rapidly synchronized with a disk file having a high data transfer rate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a data processing system illustrating the overall function of the controller.
FIG. 1A shows the details of the Control Interface of FIG. 1.
FIG. 1B shows the details of the File Interface of FIG. 1.
FIGS. 2A and 2B are block diagrams showing the overall data flow of the controller of the present invention.
FIG. 2C is a diagram showing the trap section of FIG. 2A in detail.
FIG. 2D shows how FIGS. 2A and 2B are interrelated.
FIG. 2E shows the input port of FIG. 2A in more detail.
FIG. 3 illustrates the controller shown in FIGS. 2A and 2B as three interrelated subsystems.
FIG. 4 is a table illustrating the instruction set of the microcontroller.
FIGS. 5A-5C is a timing diagram of various signals used by the microcontroller.
FIGS. 6A-6HH each illustrate the logic circuitry for generating a gate funnel control signal. FIG. 7A illustrates the various gated drivers and their connection to busses.
FIGS. 7B-7E illustrate the logic circuitry for generating the gated driver control signals.
FIGS. 8A-8K illustrate the logic circuitry for generating the various load register signals.
FIG. 9 illustrates the details of one of the subsystems during the input phase of the machine.
FIG. 10 illustrates the details of the other subsystem during the input phase of the machine.
FIG. 11 illustrates the details of the machine during the output phase.
FIG. 12 is a flow chart illustrating an example of how the controller is returned to the point of interruption by use of selected instructions.
FIG. 13 is a chart illustrating the timings of interface lines for a select operation.
Briefly, the microcontroller shown in FIG. 1 brings together the flexibility, speed, data storage, responsiveness, I/O capability, and synchronization required to control a group of high performance files.
The flexibility is provided in the 30 instructions shown in FIG. 4 which execute in one machine cycle. This instruction set has been selected to provide those functions most often used in a controller application as well as special instructions to provide a given function within a minimum of controller time (one machine cycle). A brief summary of these instructions is as follows:
______________________________________ A 4 Branch Instructions including Bit or Condition testing and subrouting branching (BOB, BOC, BR, BAL) B 4 Local Storage Instructions with direct and indirect addressing (with auto incrementing) (FIM, SIM, FID, SID) C 6 Register Immediate Instructions half byte ALU ops internal or external (RIM) D 7 Register to Register Instructions full byte ALU ops internal or external (RR) E 1 Load Register Immediate Instruction (LRI) F 2 Execute Instructions immediate and indirect (EXI, EXID) G 3 Branch on Register Instructions immediate, indirect and link (BOR, BORI, BORL) H 1 Set Mask Instruction (STM) I 1 Restore Instruction from link 1, 2 or stack registers (RAR) J 1 Set Machine Level Instruction ______________________________________
The speed is demonstrated in the fast execution cycle which is in the range of 500 nanoseconds when used with low cost read only storage.
The overall efficiency and throughout are achieved over many instructions, because each instruction requires only one cycle, and through extensive use or direct addressing of both internal and external interfaces.
The microcontroller responsiveness is provided by the trap system which includes a full priority encoder and trap cycle hardware as well as a mask register which can selectively enable/disable any or all of the eight traps. This allows the microcontroller to respond within one machine cycle to external trap signals. The trap interrupt levels provide the microcode with the capability to dedicate a large group of registers to specific functions and interfaces without losing time in selecting different registers, i.e., no address paging. The trap levels correspond to the eight levels that the controller operates on.
The large local store of 256 bytes provides more than sufficient internal registers for each machine level as well as a temporary data buffer. In addition, a program "stack" area is provided which holds eight registers for each level. Two registers are reserved for the status and mask registers, four registers are for a push-pop stack for neste link functions, and two registers are for storing ROS address storage when a trap is taken. A significant function of the controller instruction set and direct addressing architecture is that all of these registers, program stacks, and data buffer areas are immediately available to all external I/O interfaces.
This means that the controller still has direct addressing to all external I/O interfaces while operating on any machine level. One instruction is provided which allows the microcode to force any machine level at any time.
The I/O link between all external interfaces and the microcontroller is provided by the input and output ports. The input port includes a plurality of input units such as "funnels" or bus multiplexers where output signals from the control unit and drives are brought into the controller. The output port includes a plurality of output units for the controller to supply input signals to the control unit and to the drive. Each of the units of the ports are addressable by one or more of the instructions.
To maximize the number of unique units which are directly addressable, input units and output units are given the same address and that address is utilized for two different units. The microcontroller distinguishes them by the fact that all inputs to the controller are "gated in" during the input phase of the machine cycle, and all external registers are loaded during the output phase of the machine cycle.
Another significant feature of the input port architecture is that input "and or" gates (funnels) require less hardware than the normal "bidirectional I/O register" used in other arrangements and therfore the input port is less expensive.
The external address structure provides for 16 different external addresses, 0 through 15. This allows for 16 input unit and 16 output unit registers for a total of 32.times.8 (256 lines) unique interface lines.
The synchronization capability is a major contributor to the overall efficiency and data throughput of the microcontroller. Because it is designed to function at a variable speed, the machine cycle can be synchronized with the file data byte rate. This eliminates all deskewing between the data and therefore minimizes any time that is normally lost in deskewing the data and control signals. It is not necessary to "pad" functions and timing to allow for the wide tolerances normally encountered between different devices.
DISCLOSURE OF INVENTON
As shown in FIG. 1, the microcontroller 10 functions to control the transfer of information between control unit 11 and a string 12 of disk drives 13. Control unit 11 is connected to the controller through a control interface CTL 16. String 12
is connected to the controller 10 through a file control interface FCI 17.
As shown in FIG. 1A, the control interface is a set of lines used to connect the storage control unit 11 to one or more controllers. The signal lines from the storage control unit to the input port of the controller comprise the following:
CTL Bus Out--The CTL bus out consists of nine lines for one byte of data and parity. Bus out transmits command information and tag modifiers when Tag Gate is present and information to be recorded on a disk drive when "Sync Out" is present.
CTL Tag Bus--The CTL Tab Bus consists of six lines for five bits and a parity bit of control information.
CTL Tag Gate--CTL Tag Gat is a single line employed to gate Bus Out and Tag Bus.
CTL Select Hold--CTL Select Hold is a single line which is made active and remains active when a drive is selected. It remains active until an End Signal is received from a drive after the last operaton on the drive is performed and the End Signal is acknowledged.
Sync Out--Sync Out is a single line which validates and gates data on Bus Out during a data transfer operation.
End Response--End Response is a single line used by the Control Unit to acknowledge to the controller the receipt of a Normal End or Check End from the controller.
The signal lines from the controller output port to the Storage Control Unit are as follows:
CTL Bus In--The CTL Bus In consists of nine lines for one byte of data and parity. Bus In transmits data from a disk to the Storage Control Unit during read operations with the use of Sync In for gating. Bus In is also used to transfer information to the Storage Control Unit when Normal End, Check In, or Tag Valid are active.
CTL Sync In--Sync In is a single line which is used during transfer of data of the Control Unit to validate and gate Bus In. Sync In is used to request a byte of data from the Control Unit.
Select Active--Select Active is a single line which becomes active after a successful selection sequence and remains active to indicate proper selection as long as Select Hold is active.
CTL Tag Valid--CTL Tag Valid is a single line which rises in response to Tag Gate from the Control Unit to indicae reception of the Tag Decode by the Controller.
Normal End--Normal End is a single line used to indicate to the Control Unit that the normal ending point of an operation has been reached.
Check End--Check End is a single line used to indicate that an abnormal ending condition exists. The abnormal condition is defined by the byte of data that exists on Bus In.
Alert Lines--Alert Lines is a series of three lines, two selected and one unselected. Select Alert 1 is used to indicate an error condition in the selected controller or drive. Select Alert 2 is used to indicate a busy condition. Unselected Alert 1 is used to indicate to the Control Unit that a polling sequence is required by the Control Unit.
The FCI interface 12 as shown in FIG. 1B consists of five control busses and four miscellaneous control and data lines. The FCI interface 12 can accommodate eight separate drives. All interface lines to and from a drive are multiplexed so that all signals issued by the controller are received by all drives. Similarly, like signals from different drives are "OR'd" together for transmission to the controller on a common line. All gating signals on the interface are under the control of the microcontroller. Reference pulses from the drives and read/write data are carried on a balanced bidirectional read/write data cable.
The FCI interface consists of the following busses and lines:
Select Bus--Select Bus consists of eight lines each of which is used to select a different drive, plus two unique lines for the operator to select a given drive or drives manually. Only one of these lines can be active at any given time. Select Bus is connected to a unit of the output port.
Device Tag Bus--Device Tag Bus consists of five signal lines plus parity. The data on the five lines are used to perform a specific function in the selected drive, such as sense a given register, set a given register, initiate a seek operation or set a given trigger, depending on the data on the Drive Bus Out. Device Tag Bus is connected to a unit of the output port.
Device Bus Out--Device Bus Out consists of nine lines for one byte of data and parity. The interpretation of the one byte is controlled by the Device Tag Bus, as mentioned above. Device Bus Out is connected to a unit of the output port.
Attention/Select Response Bus--This bus consists of nine lines for carrying attention or select information from the drive to the input port of the controller. The attention signals are presented according to the drive address. The select/response signal represents the address of the drive which has been selected.
Device Bus In--Device Bus In consists of eight data lines and one line for parity which carries sense and status information from the selected drive to a unit of the input port of the controller.
Tag Gate--This is a single line from the output port of the controller to the selected drive to gate both the Tag Bus and Device Bus Out.
Select Hold--Select Hold is a single line from the output port of the controller to the drive whose function is to maintain selection once it is established.
Tag Valid--Tag Valid is a single line from the selected drive to the input port of the controller to indicate that a Tag Gate signal has been received and that the Device Tag Bus and Bus Out parity are correct.
The overall function of the microcontroller as shown in FIG. 1, is basically to control the transfer of data to and from the files by taking the sequence of commands which have been generated by the control unit in response to receiving a series of Channel Command Words (CCW's) from the CPU channel and convert these to a series of orders for the drives. In addition, the controller receives status and control data from the drive and converts this data when necessary to suitable data to be supplied to the control unit.
The read/write channel between the drives and the controller and on to the control unit has the capability of transferring data at the rate of about 1.85 megabytes per second. The microcontroller must, therefore, be fast, flexible and quite responsive to both the orders from the control unit and status information from the drives so as not to interfere with the potential overall system performance obtainable by a 1.85 megabyte data transfer rate. A system for controlling the serial read/write channel is disclosed in copending application Ser. No. 921,146, filed June 30, 1978.
FIGS. 2A and 2B show the overall data flow of the controller. The details of the trap system are shown in FIG. 2C.
The microcontroller shown in FIGS. 2A and 2B comprises three major subsystems which are interrelated as shown in FIG. 3 so that the instruction stored in a storage unit can be read out and executed to achieve the overall function of the control of the data transfer between control unit 11 and the string 12 of disk drives on a dynamic basis.
The architecture of the microcontroller will first be described in relation to FIG. 3 which shows the major subsystems B, C and D, and a storage device A.
The function of device A is to store a plurality of microinstructions at individually addressable storage locations. Three different types of instructions are stored in device A, unconditional branch type of instructions, conditinal branch type of instructions, and non-branch type of instructions. Each type includes a predefined plurality of different instructions. Device A is shown as a read only storage device, but other devices known in the art may be employed. The first subsystem B is referred to as the Instruction execution subsystem, and the second subsystem C is referred to as the Next Instruction Fetch subsystem. As shown in FIG. 3, subsystem C includes means AR for addressing storage device A and a plurality of next address generators NAG 1 through NAG n. Subsystems B and C are controlled by a third subsystem D which includes the instruction register decoder IRD and control means CM. Subsystem D is referred to as the Control usbsystem and is responsive to one current instruction transferred from device A by subsystem C during the previous machine cycle to the instruction register decoder for generating the appropriate control signals to control the operation and interaction of the subsystems B and C to execute the current instruction and fetch the next instruction from source A during the current machine cycle. Control subsystem D also includes the trap system which is discussed in detail later in this specification.
The various components of the controller will now be described in connection with FIG. 2A and 2B and related to the FIG. 3 subsystems. This divisional application is directed to the interactions of the trap system 71 shown in detail in FIGS. 2
and 3, the level register 87 and the addressing of ROS 52 by ARL 58 through funnel 55C by the priority encoder 86 of the trap system 71. Additional features of this invention involve the control for selecting RAM addresses and the data path and control of the status register 100, the mask register 88, the program counter register 51, and the address registers 50A and 50B which permit transfer between these registers and the predetermined storage locations of RAM during the trap cycle and the operation of the Set Machine Level (SML) and the trap system. The operation of the system in converting a trap/interrupt signal to either a fast trap or a full interrupt shown in FIG. 12.
Input Port 8
The input port 8 comprises a plurality of input funnels or bus multiplexers which function to selectively transfer the data on an input bus from one or more of the files or the control unit to the microdata input bus 15 connected to one input of the ALU. FIG. 2E shows a pair of input funnels and the gated drives for connecting the output funnel to bus 15.
A funnel consists basically of a plurality of input OR gates 200, one for each line of the busses to be multiplexed. As shown in FIG. 2E, eight plural input OR gates 200 are used to connect DCI Bus Out lines 0-7 corresponding lines of the bus
15, one line being associated with each OR gate 200. Each line is connected to the OR gate 200 through a two-input AND gate 201. The other input being a single address line labelled "Select 0". A second group of similar AND gates 201 are used to connect the lines 0-7 of a second interface bus to each OR gate 200. The second input to each of these AND gates is a different address line, "Select 1". The input port 8 has sixteen groups of eight AND gates, each group of eight being individually selectable by the external address decoder 26. The output of the eight OR gates 200 are transferred to bus 15 by eight similar gate drivers 203. Each gated driver 203 consists of an AND gate 204, a binary stage 205, a second AND gate 206, an amplifier
207, and a diode 208 for isolating all the loads from the bus 15. The function of the amplifier and the diode can be combined in one transistor amplifier circuit, as is well known in the art. The second input to AND gates 204 and 206 is a gate funnel signal supplied from the control subsystem D. The input port, as described, can handle 128 external input lines and transfer the data on an addressed group of eight of these lines selectively to bus 15 at times selected by the control subsystem. As shown in FIG. 2, gated driver 110 is connected to bus 15 as is the output port 9, making bus 15 a bidirectional data bus. Gated driver 110 and the input port drivers can, therefore, never be on during the same period of a machine cycle.
Output Port 9
The output port 9 is not shown in detail but consists of sixteen registers, each with eight stages. The output of each register is adapted to be connected to an external interface which might include one of the input funnels. Each register input is provided with a three input AND gate for each stage, one input being connected to the corresponding line of bus 15, the second input to each AND gate being a select or address line, and the third input to each AND gate of each register being a load external register signal from the control subsystem. Since the registers and funnels are operated at different times, one select line addresses a funnel-register pair.
As will be explained later, the control subsystem can change external addresses during a machine cycle.
ROS 52
As shown in FIG. 2B, the ROS unit 52 corresponds to device A of FIG. 3 and consists of 16,384 individually addressable 16 bit (plus two parity bits, not shown) storage locations, each of which stores one of the 30 16 bit microinstructions which are discussed in detail later. The output of the ROS unit is applied to the instruction register bus 58 which consists of sixteen lines. Lines 3-7 and 11-15 of this bus are connected to external address decoder 26, and lines 0 through 15 to the instruction register decoder (IRD) 53.
A storage location in ROS is selected by a 14 bit address which is supplied to ROS from addressing means AR of subsystem C.
Address Register 50
As shown in FIG. 2A, A, the addressing means AR of subsystem C is instruction address register 50, comprising two units, Address Register Low (ARL) 50A and Address Register High (ARH) 50B. Address register low is an eight-stage register and supplies the eight low order bits 6-13 of the 14 bit address to the ROS unit 52. Address register high is a six-stage register and supplies the six high order bits 0-5 of the 14 bit address to ROS unit 52.
The inputs to ARL 50A are supplied from the output funnel 55 while inputs to ARH 50B are supplied from the output of funnel 54.
Funnel 55
Funnel 55 comprises four separate AND/OR logical units 55A-D. Unit 55A is an eight-stage unit which is connected to the ALU out bus 73 and functions to transfer partial addresses generated by subsystem B to subsystem C. Unit 55B is an eight-stage unit for receiving one byte of data directly from RAM 38 and is part of one of the NAG units of subsystem C. Unit 55C is a three-stage unit for receiving bits 0-2 from the ALU B bus 82 and is associated with the trap NAG unit. Unit 55D is an eight-stage unit for receiving an eight bit byte from the program counter low 51A which is part of the NAG unit 1.
The output of units 55A-D are connected to the appropriate inputs of ARL 50A.
Funnel 54
Funnel 54 comprises three separate AND/OR logical units 54A-C. Unit 54A consists of six stages for receiving six bits (2-7) directly from the RAM 38 and with unit 55B, forms part of the NAG unit. Unit 54B is a five-stage unit whose inputs are connected to the control means CM to receive bits 3-7 from instruction decoder 53. Unit 54C comprises a six-stage unit whose inputs are connected to the output of the program counter high 51B which is part of NAG unit 2 of subsystem C.
Program Counter 51
The program Counter (PC) 51 comprises a Program Countr Low (PCL) section 51A and a Program Counter High (PCH) section 51B. The program counter comprises a fourteen-stage settable counter whose function is to generate the next sequential address to be transferred to the address register 50. The PCL section 51A consists of eight stages whose inputs are connected to the output of ARL 50A so that PCL can be updated by ARL when signalled by the control subsystem at T6. PCL 51A has an increment input line 57 for advancing the counter one unit at T2 time. The PCH high section 51B consists of six stages whose inputs are connected to the output of the address register high section 50B so that PCH can also be updated at T6. The outputs of the program counter 51 are connected to the address register 50 through funnels 54 and 55 as previously mentioned and to the ALU out bus through funnels 56A and B and gated driver 112.
Funnel 56A
Funnel 56A comprises eight AND/OR units for connecting PCL 51A to the ALU output bus 73.
Funnel 56B
Funnel 56B consists of six AND/OR units for connecting PCH 51B to ALU output bus lines 2-7.
Gated Driver 112
Gated driver 112 drives the ALU output bus 73 to transfer the address of the instruction currently being executed to subsystem B. The portion of the ALU output bus 73 connected to funnel 77A is active when driver 112 is gated. This occurs during an output phase of a machine cycle when a link type instruction is being executed. Funnel 56A, 56B and gated driver 112 are part of subsystem B.
Instruction Register Decoder 53
The instruction register decoder 53 comprises a 16 bit register for receiving an instruction readout from ROS unit 52, and suitable decoding circuitry to provide the appropriate control signals such as an op decode, an ALU operation decode, a given bit line decode, or an address signal. It is part of control subsystem D of FIG. 3.
RAM 38
Random Access Memory (RAM) 38 is provided with 256 individually addressable storage locations each of which stores an eight bit byte. RAM 38 is provided with suitable addressing circuitry 60 to be discussed in detail later, and suitable read/write control circuitry 61 to permit an eight byte of data to be stored in an addressed location or to be read from an addressed location. Input data is supplied to RAM 38 on RAM input data bus 62 which is connected to the ALU out bus 73. Output data from RAM 38 appears on RAM output data bus 63 which is fed to several funnels.
The address of a RAM location is eight bits and is supplied from the outputs of funnels 64 and 65. Funnel 64 provides the four RAM address low order bits 4-7 (RAL) while funnel 65 provides the four RAM address high order bits 0-3 (RAH). Funnel
64 consists of five separate AND/OR logical units 64A-E. Units 65B and C and units 64A, B and C are connected to the control subsystem and are supplied selectively with signals from the IRD unit 53, as shown.
Funnel 64
Unit 64A is connected to lines 12-15 of the instruction register (IR) bus 58 and to RAM address lines 4-7. Units 64B is connected to lines 4-7 of the IR bus 58. Funnel 64C connects lines 9, 13-15 of the IR bus to RAM address lines 4-7. Funnel
64D is connected to lines 4-7 of the auxiliary register 66. Unit 64E connects the RAL counter 89B lines 0-2, to RAL lines 5-7 with address line 4 being forced always to a 1 through funnel 64E.
Funnel 65
Funnel 65 is for the RAM high order portion of the address. Funnel 65A connects lines 1-3 of the level register 87 to RAM address lines 1, 2 and 3. RAM address line 0 is maintained at a zero value except during the execution of specific instructions. Funnel 65B supplies IR signals 10, 11 and 12 to RAH lines 1, 2, and 3 while bit 0 is forced to a 1 by 65B. Funnel 65C supplies IR signals 11, 12, and 13 to RAH lines 1, 2 and 3 with RAH line 0 being forced to a 1.
Funnel 65D connects the output lines 0-3 of the auxiliary register 66 to RAH lines 0-3.
The 256 individually addressable storage locations of the RAM 38 are logically divided into three separate sections. The data buffer section 38A consists of 64 bytes or 64 general purpose registers. The program stack section 38B consists of 64
bytes or 64 registers. These latter 64 registers are logically grouped into eight levels with eight registers per level. Each of the eight registers of a level are assigned a specific function as follows:
______________________________________ Register 0 PCH Trap 1 PCL Trap 2 PCH Link 1 3 PCL Link 1 4 PCH Link 2 5 PCL Link 2 6 Status Register 7 Mask Register ______________________________________
The general function of these registers are indicated by their respective titles and is to temporarily store the value of certain other registers, e.g., the program counter, mask register and status register, when certain instructions are being executed.
Section 38C of RAM 38 consists of 128 addressable storage locations. Section 38C storage locations are divided into levels 0-7 corresponding to the eight levels of machine operation 42. Each of the eight levels, therefore, consist of 16 eight bit registers. The 16 registers at a given level are general purpose registers which are directly addressable by a subset of the instructions shown in FIG. 4. All of the above units associated with RAM addressing are part of subsystem B.
RAM Read-Write
The storing of data into RAM 38 from bus 73 (writing) and the retrieval of data from RAM 38 (reading) are discussed in connection with the 3/4 clock and the various instructions.
ALU 70
The ALU 70 is conventional and is, therefore, shown in block form. The unit 70 has two 8 bit inputs--the A input 74 and the B input 75, each of which is eight lines. The output 80 of unit 70 is connected to the input of the ALU register 71 by the eight line output 80. Carry out line 81 is also provided from unit 70.
The ALU is capable of performing the following logical operations: AND, OR, XOR, ADD+CARRY, COMPARE, ADD WITHOUT CARRY and MOVE. The particular operations to be performed are under the control of the ALU control bus 80C which is supplied with signals from the control subsystem D of FIG. 3.
ALU Reg. 71
The ALU register 71 is an eight-stage register whose inputs are connected to ALU output 80 and whose outputs are connected to funnel 72. ALU register 71 is provided with a load input line connected to subsystem D.
Funnel 72
Funnel 72 comprises two separate AND/OR logical units 72A and 72B. The output of ALU register 71 is connected to the ALU out bus 73 through funnel 72A and gated driver 111. Funnel 72B connects the output data bus 63 of RAM 38 to the ALU out bus
73 through gated driver 111 as was described earlier. The contents of the ALU register 71 can be transferred to the addressing means AR of subsystem C through funnel 72A gated driver 111 and funnel 55A.
Funnel 77
Funnel 77 comprises three separate AND/OR logical units, 77A-C. Unit 77A connects the ALU output bus 73 to the ALU A input 74, unit 77B connects the input port data bus 15 to the ALU A input 74 and unit 77C connects the RAM output data bus 63 to the ALU A input 74.
Funnel 78
Funnel 78 comprises two separate AND/OR logical units, 78A and 78B. Unit 78A connects the RAM output data bus 63 to the ALU B input 75 while unit 78B connects the output of another funnel 79 to the ALU B input 75.
Funnel 79
Funnel 79 comprises seven separate AND/OR logical units, 79A-G. Unit 79A connects the 8 bit output of the auxiliary register 66 to ALU B bus 82. Unit 79B connects the 8 bit output of the mask register 88 of the trap system to ALU B bus 82. Unit
79C connects the three line output of the priority encoder of the trap system to lines 0-2 of the ALU B bus 82, while units 79D-G connect selected lines from instruction register decoder 52 to selected lines of the ALU B bus 82.
Funnel 79D connects lines 3-6 of the IR bus 58 to lines 4-7 of the ALU B bus 82. The other four inputs to funnel 79D, which connect to lines 0-3 of the ALU B bus 82, are supplied from a common line which supplies an all 0's input or an all 1's input depending on the particular logic function being performed by the ALU. This signal is referred to as ALU OP constant, and is shown by XXXX in FIG. 2A. Funnel 79D is used during half byte ALU operations. Depending on the ALU operation, the ALU OP constant is selected so that the remaining half byte being supplied to the B input to the ALU appears unchanged at the output.
Funnel 79E connects lines 3-6 of the IR bus 58 to lines 0-3 of the ALU B bus 82. The other four inputs represented by XXXX to funnel 79E are again an ALU OP constant which is supplied to lines 4-7 of the ALU B bus 82. The pattern is selected by the control subsystem so as not to change bits 4-7 of the A input during the logic operation being performed in the ALU on bits 0-3. A simple latch (not shown) may be used to supply the appropriate all "1's" or all "0's" pattern for funnels 79D and 79E.
Funnel 79F connects lines 5-7 of the IR bus 58 to lines 5-7 of the ALU B bus 82.
Funnel 79G connects lines 8-15 of the IR bus 58 to lines 0-7 of the ALU B bus 82.
Status Register 100
Status register 100 is a four-stage register, each stage of which is associated with the status of a different condition. The stages are assigned as follows:
______________________________________ Stage 0 CC1 Condition Code 1 1 CC2 Condition Code 2 2 CC3 Condition Code 3 7 Stack Pointer ______________________________________
The inputs to the status register 100 is from funnel 106 which comprises two AND/OR logical units, 106A and 106B. Funnel 106A is a four stage unit which has one line connected to the output of the stack pointer logic 101 and three lines connected to condition decoder 102. Funnel 106B is a four-stage unit whose input is connected to lines 0-2 and 7 of the ALU out bus 73.
The output of the status register 100 is connected to the ALU out bus 73 through gated driver 114 and to the condition test logic unit 103.
Condition Decoder 102
The Condition Decode logic unit 102 has its input connected to the ALU output bus 73. In addition, the carry signal from the ALU 70 is supplied to the decoder unit 102. The decoder unit 102 functions to provide three separate output signals:
______________________________________ Line 0 ALU Bus = all zeros Line 1 ALU Bus .noteq. to all zeros Line 2 A carry signal. ______________________________________
The first two signals are a result of a sampling of all eight bits of the ALU bus 73. The last signal is supplied to the condition decoder 102 from the ALU carry line 81 of ALU 70.
Condition Test Logic Unit 103
The condition test logic unit 103 receives its input from the status register 100 and the output from the BOB logic unit 104. The output of 103 is used to select the correct address for the conditional branch instructions.
BOB Unit 104
The branch on bit logic unit 104, as shown in FIG. 2A, is supplied from funnel 105 which comprises two AND/OR logic units 105A and 105B. The input to funnel 105A is from input data bus 15, while the input to funnel 105B is from the RAM output bus 63. The BOB logic unit samples the data on either the input data bus 15 or the RAM data bus 63 when a branch on bit instruction is being executed.
Level Register 87
Level register 87 is a three-stage register whose output is connected to funnel 65A to provide the high order portion of the RAM address. Level register 87 is set from either the priority encoder of the trap system or from the instruction register decoder during execution of the SML instruction.
Trap System
The last part of the control system is shown in FIG. 2C and is referred to as the trap system. The function of the trap system is to interrupt the normal processing of instructions and direct the controller to a new predetermined sequence in response to some event occurring in the devices between which data is being transferred or the occurrence of some event in the microcontroller.
These events are each assigned a priority, and events with like priorities are OR'd together so as to generate a trap request signal. As shown in FIG. 2C, the trap system is arranged to accept up to eight levels of priorities.
The trap system interrupts the microcontroller at the end of an instruction cycle. If a trap request signal is provided which has a priority higher than the current level at which the machine is operating, the trap system then causes subsystems B and C to perform certain functions during the trap cycle which has a period corresponding to the normal machine cycle. The first function is to generate the address of the next instruction so that the next instruction can be read out of ROS into IRD
52 and processed during the next machine cycle.
The second function is to transfer the contents of certain registers which define the condition of the microcontroller at the point of interruption into RAM in the event that it is necessary to return to the point of interruption and this return can be achieved through programming the return rather than returning to the beginning of the subroutine and executing all the instructions over again up to the point of interruption. The microprogrammer is, therefore, given the option of converting the trap request to a full interrupt, depending on what instruction or series of instructions are placed at the location in ROS which is addressed by the trap request signal. In the present arrangement, the address in ROS for the eight different priorities are assigned so it is possible to execute a series of four instructions sequentially before running into the next level. This permits the control system to operate in two modes. The first is to place only instructions at these addresses which execute quick trap type of instructions; the second is to place at these addresses a series of instructions which set up an audit trail in the event the trap is going to be converted to an interrupt. If desired, the microprogrammer may use the second mode immediately following the first mode at each level.
The last function of the trap system during the trap cycle is to update the level register of subsystem B to the corresponding priority of the trap request being honored. The trap system must be rearmed before it will honor another trap request signal.
With reference to FIG. 2C, the trap system comprises a mask register 88, the trap register 85, the trap logic unit 92, the cycle controls 90, and the priority encoder logic 86.
Mask Register 88
The mask register 88 is an eight-stage unit whose input is connected to the ALU output bus 73 of subsystem B and whose output is connected to the trap logic unit 92. Mask register 88 also has a load signal input to which the load mask register LMR load signal is applied to transfer the contents of the ALU output bus 73 into the register.
Trap Logic Unit 92
The trap logic unit 92 comprises a group of logic circuits for receiving the trap request signals 0-7 representing the occurrence of predefined events and the output of the mask register. The logic unit 92 provides an input to the trap register
85 for all active trap request signals which match the corresponding bit in the mask register.
Priority Encoder 86
The priority encoder 86 functions to select the trap request signal having the highest priority from all trap request signals allowed by mask register 88 and convert that signal to a three bit binary pattern on its output which is supplied to the input of level register 87 at the end of the hardware cycle and to the ROS addressing means through funnel 79C at the beginning of the trap cycle, as previously described.
Trap Cycle Controls 90
The last portion of the trap system includes the trap cycle controls which provide a time sequence of control signals to the portion of the control subsystem and the other subsystems B and C to initiate the trap cycle.
The foregoing description of the controller shown in FIGS. 2A, 2B and 2C has been directed primarily to an explanation of the functional units, the interconnection of these units within each section and the interaction of the units in different sections in order to provide a general understanding of the various potential data flow paths which exist between these various units. It should be understood that various control lines and timing signals have not been shown in FIG. 2 in order to simplify the description. These will be described in connection with a description of the control subsystem D of FIG. 3.
Table I below summarizes the functions of all the internal funnels and lists the figures which illustrate the logic circuitry for generating the gate signals. The logic circuitry is part of the control subsystem.
TABLE I ______________________________________ Funnel Units Input Output FIG. 6 ______________________________________ 54A 6 RAM Output Bus ARH A 54B 5 IR Bus 3-7 ARH B 54C 6 PCH ARH C 55A 8 ALU Output Bus ARL D 55B 8 RAM Output Bus ARL E 55C 3 ALU B Bus 0-2 ARL F 55D 8 PCL ARL G 56A 8 PCL ALU Output Bus H 56B 6 PCH ALU Output Bus H 64A 4 IR Bus 12-15 RAL 4-7 I-J 64B 4 IR Bus 4-7 RAL 4-7 K 64C 4 IR Bus 9,13-15 RAL 4-7 L-M 64D 4 Aux. Reg. 4-7 RAL 4-7 N 64E 3 RAL Counter
0-3 RAL 5-7 O 1 K=1 RAL 4 65A 3 Level Reg. 1-3 1-3 P 1 K=0 RAH 0 65B 3 IR Bus 10-12 RAH 1-3 Q 1 K=1 RAH 0 65C 3 IR Bus 11-13 RAH 1-3 R 1 K=1 RAH 0 65D 4 Aux. Reg. 0-3 RAH 0-2 S 72A 8 ALU Register ALU Output Bus T 72B 8 RAM Output Bus ALU Output Bus T 77A 8 ALU Output Bus ALU A Input V 77B 8 M-Bus ALU A Input V 77C 8 RAM Output Bus ALU A Input W 78A 8 RAM Output Bus ALU B Input Z 78B 8 ALU B Bus ALU B Input Z 79A 8 Aux. Reg. ALU B Bus AA 79B 8 Mask Reg. ALU B Bus BB 79C 3
Priority Enc. ALU B Bus 0-2 CC 1 79D 4 IR Bus 3-6 ALU B Bus 4-7 DD 4 ALU Op K ALU B Bus 0-3 79E 4 IR Bus 3-6 ALU B Bus 0-3 DD 4 ALU OP K ALU B Bus 4-7 79F 3 IR Bus 5-7 ALU B Bus 5-7 EE 1 ALU B Bus 79G 8 IR Bus 8-15 ALU B Bus 0-7 FF 105A 8
M-Bus BOB Logic GG 105B 8 RAM Output Bus BOB Logic GG 106A 1 Stack Pointer Status Reg. 7 HH 3 Condition De- code 1,2,3 Status Reg. 0,1,2, 106B 4 ALU Out Bus 0-2, 7 Status Reg. 0-2 HH ______________________________________
The control subsystem D signals of the microcontroller will now be discussed in detail.
As shown in FIG. 5, the basic machine cycle of the microcontroller shown in FIG. 2 comprises eight time periods, T0-T7. All timing and control signals are referenced to one or more of these time periods. The signals depicted in the drawing are idealized waveforms. In practice, each signal has a finite rise and fall time which is not illustrated. For reference purposes, it can be assumed that each T period is 60 nanoseconds and hence one machine cycle is 480 nanoseconds. Signals T0-T7 are generated from an eight stage bit ring driven by a suitable variable frequency oscillator clock 130, shown in FIG. 2A, which is either associated with one of the external devices or synchronized by some suitable source.
In addition, a 3/4 clock 131 is also used for control of the RAM unit 50. The 3/4 clock has a 45 nanosecond pulse or 90 second period whose function will be explained in detail later in the specification. The clocks 130 and 131 are shown in FIG. 2A and the clock signals in FIG. 5.
Phase 1, 2 and 3 Timing Signals
Each of the phase 1, 2 and 3 timing signals shown in FIG. 5 is generated by one of the three phase latches which are arranged in a ring designated 89A in FIG. 2A. Each of these latches is supplied with the appropriate set and reset pulses developed from the 3/4 clock signal and the T0-T7 signals.
The phase 1 timing signal begins at the start of T7 and ends at the beginning of phase 2. The phase 2 timing signal begins during T2 when the 3/4 clock signal goes positive and ends at the beginning of phase 3. The phase 3 timing signal begins during T5 when the 3/4 clock goes positive and ends at the beginning of phase 1 or T7.
RAM Timing
The control signals for the RAM 38 involves the 3/4 clock, a read/write signal and the address signals. Since the RAM storage is either a source or destination of data, the read/write signal is the control line which determines its use and is supplied by control subsystem D. The RAM is addressed at T0 regardless of the instruction presently being executed except for the "Set Machine Level" instruction and one portion of the trap operation. The output data on a read cycle therefore appears on the RAM output data bus 63 and at the input to funnels 75B, 74C and 72B from the beginning of TO to the end of T5. On a write cycle, data appearing on the input bus 62 from T5 to the end of T7 is entered into the memory. The read/write control timing for the Set Machine Level instruction and the trap operation is different and will be discussed in detail later on in the specification when describing the operation of the SML instruction.
Port Control Signals
The first control signal for the input and output ports is the address signal generated by the port address decoder 26. "Address Signals 0-15" are generated by decoding bits 3-6 or 11-14 into one of 16 lines for any instruction which might involve an external funnel/register pair as a source or destination of data. A given address line forms one input control signal to the one funnel and one register as shown in FIG. 2E. A second control signal referred to as "select input or output port", corresponds to bit 7 or bit 15 of the appropriate instruction and is used to select either the addressed funnel or addressed register.
The third control signal applied to a funnel is the gate external funnel signal which places the data at the input to the funnel onto the micro data bus 15 at the correct time. This "Gate External Funnel" signal is shown in FIG. 4 and is active from the beginning of T0 to the end of T1.
The third control signal applied to the output port external register is also a timing signal which places the contents of the micro data bus into the selected register at the correct time. As shown in FIG. 4, this "Gate External Register" signal is active during T4.
Control subsystem D includes the logic for generating the gate signals for all the internal funnels shown in FIGS. 2A and 2B. The logic for each of these funnels will now be described in connection with FIGS. 6A to 6HH. These signals are not shown in FIG. 5 but are discussed in the description of each instruction later in the specification.
Funnel 54A
Funnel 54A connects the RAM data bus 63 ARH 50B. The control signal gate funnel 54A is generated as shown in FIG. 6A by ANDing together a "not trap" signal, a signal indicating that either an RAR or SIL instruction is being executed, and a signal indicating that it is either T0 or T1 time.
Funnel 54B
Funnel 54B connects bits 3-7 of the instruction data bus 58 to ARH 50A. The gate funnel 54B signal is generated as shown in FIG. 6B by ANDing together a "not trap" signal and a signal indicating that one of the following instructions are being executed: EXI, EID, BOR, BORI, BORL, BAL, or BR. ARH 50A stage 0 is not changed.
Funnel 54C
Funnel 54C connects the output of the program counter high 51B to ARL 50A. The gate funnel 54C is generated as shown in FIG. 6C by ANDing together a "not trap" signal with the signal indicating that any of the following instructions are being executed: EXI, EXID, BOR, BORI, BR, BAL, or BORL, and the branch on condition or bit is positive.
Funnel 55A
Funnel 55A connects the ALU out bus 73 to ARL 50A. The gate 55A signal is generated as shown in FIG. 6D by a "not trap" signal and by a decode of any of the following instructions: EXI, EID, BOR, BORI, BR, BAL, BORL, BOB=YES, or BOC=YES.
Funnel 55B
Funnel 55B connects RAM output bus 63 to ARL 50A. The gate funnel 55B signal is generated, as shown in FIG. 6E, by ANDing a "not trap" signal with a signal indicating that an RAR or SIL instruction is being executed.
Funnel 55C
Funnel 55C connects the ALU B bus bits 012 to ARL 50A. The gate signal for 55C is a "trap" signal generated, as shown in FIG. 6F, by the trap request latch.
Funnel 55D
Funnel 55D connects the output of the Program Counter Low 51A to ARL 50A. The gate signal funnel 55D is generated, as shown in FIG. 6G, by ANDing a "not trap" signal, the inverted gate funnel 55A signal and the inverted gate funnel 55B signal.
Funnel 56A
Funnel 56A connects the program counter low 51A to the ALU out bus 73. The gate funnel 56B signal is generated, as shown in FIG. 6H, by inverting the gate funnel 56B.
Funnel 56B
Funnel 56B connects the Program Counter High 51B to the ALU output bus 73. The gate funnel 56B signal is generated as shown in FIG. 6H, from the output of a latch which is set at T7 time or at T2 time and a 3/4 clock and reset at T1 or T4 or a decode of a BOB instruction.
Funnel 64A
Funnel 64A connecting lines 12-15 of the instruction data bus 58 to RAM address lines 4-7 is controlled by two gating signals, gate funnel 64A-1 and A-2. The gate funnel 64A-1 signal is generated, as shown in FIG. 6I, by either a gate low signal GI or the combination of the following signals: NOT GATE AUXILIARY TO RAM, NOT SIL DECODE, NOT GATE TRAP ADDRESS COUNTER TO RAM, NOT FIM OR SIM, NOT LRI, NOT GATE HIGH, NOT INHIBIT LINES 13-15.
The gate funnel 64A-2 signal is generated, as shown in FIG. 6J, by ANDing the following signals: GATE IR 13-15 TO ARL 5-7, NOT FIM AND NOT SIM, or a gate low signal.
The gate low signal is generated, as shown in FIG. 6I, from ORing two separate groups of signals. The first group of signals which are ANDed are R to R decode, a NOT IR3 decode, and a positive IR11 decode. The second group of signals which are ANDed are an R-R decode, a phase 1 timing signal, a positive decode of IR 4, 5, 6 and 7, a NOT IR 3 and a NOT IR11. This signal is used to control other funnels also.
Funnel 64B
Funnel 64B connecting lines 4-7 of the IR bus to lines 4-7 of the RAM address is controlled by a gate funnel 64B signal. This signal is generated, as shown in FIG. 6K, by one of four signals, an FIM decode and a phase 2 timing signal or an SIM decode and a not phase 2 timing signal or a gate high signal to be described, or an LRID decode.
Funnel 64C
Funnel 64C connecting lines 9, 13-15 of the IR bus to lines 4-7 of the RAM address is controlled by two gate signals, gate funnel 64C-1 and gate funnel 64C-2. Gate funnel 64C-1 is generated, as shown in FIG. 6L, by either an FIM decode and a phase 1 timing signal or an SIM decode and a phase 2 timing signal. Gate funnel 64C-2 is generated, as shown in FIG. 6M, by the gate high signal.
The gate high is also used in the control of subsequent funnels. The gate high signal is generated from one of three separate groups of signals which are ANDed together. The first group of signals is an R-R decode, an IR 3 and a NOT IR 11. The second group of signals is an R-R instruction, an IR 3, an IR 11 and a NOT IR 4, 5, 6 and 7 equal to NOT 0. The third group of signals which are ANDed together are an R-R decode, an IR 4, 5, 6 and 7, an IR 3 and an IR 11 and the NOT phase 1 signal.
Funnel 64D
Funnel 64D connecting the output lines 4-7 of the auxiliary register to RAM address lines 4-7 is controlled by a gate funnel 64D signal. The gate funnel 64D signal is generated, as shown in FIG. 6N, by a phase 1 timing signal ANDed with an FID decode or a phase 2 timing signal ANDed with an SID decode.
Funnel 64E
Funnel 64E connecting the RAL address counter lines 5-7 to the RAM address lines 4-7 is controlled by a gate funnel 64E signal. This signal is generated as shown in FIG. 60, by either a RAR decode, a BORL decode ANDed with a phase 2 timing signal and a NOT trap signal, or a BAL decode, a phase 2 timing signal and a NOT trap signal, or an SIL decode and a NOT phase 3 timing signal or by a positive trap signal. Line 4 of the RAM address lines is always forced to a 1 by a gate funnel 64E signal.
Funnel 65A
Funnel 65A connecting the level register to RAH is controlled by a gate funnel 65A signal. This signal is generated, as shown in FIG. 6P, by ANDing a NOT gate auxiliary to RAM with a NOT gate FIM or SIM to RAM and a NOT gate SIL to RAM signal.
Funnel 65B
Funnel 65B connecting IR bus line 10, 11, 12 to RAH is controlled by gate funnel 64B signal. This signal is generated, as shown in FIG. 6Q, from a gate FIM or SIM to RAM signal.
Funnel 65C
Funnel 65C connecting IR bus lines 11, 12, 13 to RAH is controlled by a gate funnel 65C signal. This signal is generated, as shown in FIG. 6R, by ANDing an SIL decode and a NOT phase 3 timing signal.
Funnel 65D
Funnel 65D connecting the auxiliary register bits 0-3 to RAH is controlled by gate funnel 65D signal which is the same as gate funnel 64D as shown in FIG. 6S.
The gate FIM or SIM signal to RAM, as shown in FIG. 6Q is generated by ANDing a phase 1 timing signal and an FIM decode or a phase 2 timing signal and a SIM decode. The gate SIL to RAM signal is generated by an SIL decode and a NOT phase 3
timing signal.
Funnel 72A
Funnel 72A connects the output of the ALU register to the ALU out bus 73. The control signal gate funnel 72A is generated, as shown in FIG. 6T, by inverting the gate funnel 72B signal.
Funnel 72B
Funnel 72B connects the RAM data bus 63 to the ALU out bus 73. The control signal gate funnel 72B is generated, as shown in FIG. 6T, by one of three signals which are OR'd together. These signals are a T7 timing pulse, a signal indicating that an RAR instruction is being executed or a signal indication that an SIL instruction is being executed.
Funnel 77A
Funnel 77A interconnects the ALU out bus 73 to the ALU A input 74. The control signal gate funnel 77A is developed, as shown in FIG. 6U, from the branch on bit op code 0010 shown in the table of FIG. 4, one line from decoder 53 signifying op code 0010 is connected to funnel 77A. This line is active for the period of T0-T6 when a branch on bit instruction is being executed.
Funnel 77B
Funnel 77B interconnects the bidirectional data bus 15 to the ALU A input 74. The control signal gate funnel 77B is generated, as shown in FIG. 6V, from a "Gate External Funnel" signal and a "NOT Branch on Bit" signal. The "Gate External Funnel" signal is generated from a timing signal, as shown in FIG. 5.
Funnel 77C
Funnel 77C interconnects the RAM output data bus 63 to the ALU A bus. The control signal gate funnel 77C is generated, as shown in FIG. 6W, by ORing together those outputs of decoder 53 corresponding to the respective op codes for the following instructions: Branch, Branch on Condition, Load Register Immediate, and Branch and Link, BOB with gate external funnel. The last input to the OR gate is a signal resulting from ANDing a T5 timing pulse with the decode for the store indirect or fetch indirect instructions. The output of the OR gate is inverted and used as the gate funnel 77C signal.
Funnel 78A
Funnel 78A connects the output data bus 63 from the RAM 38 to the ALU B input 75. The control signal gate funnel 78A is generated, as shown in FIG. 6Z, by any register to register instruction, op code 100 (except move bits 8-10 being equal to
110), where the auxiliary register is not used and "ANDing" this signal with a "not trap" signal. With reference to FIG. 4, if any of the following instructions, ANDR, ORR, XORR, ARC, or CR are being executed, the gate funnel 77 is generated provided a "trap" is not pending.
Funnel 78B
Funnel 78B connects the output of funnel 79 to the ALU B input 75. The control signal gate funnel 78B is, therefore, generated, as shown in FIG. 6Z, by inverting the control signal gate funnel 78A.
Funnel 79A
Funnel 79A connecting the Auxiliary Register 66 to the ALU B bus is controlled by a gate funnel 79A signal. This signal is generated, as shown in FIG. 6AA, by ANDing a "not trap" signal with any of the following instruction decodes: FID, SID, RR, BORI, or EXID.
Funnel 79B
Funnel 79B connecting the output of the mask register to the ALU B bus is controlled by gate funnel 79B signal. This signal is generated, as shown in FIG. 6BB, by ANDing a "trap" signal with a phase 1 timing signal.
Funnel 79C
Funnel 79C connecting three lines of the priority encoder 86 defining one of eight trap levels, to lines 0-3 of the ALU B bus is controlled by the gate funnel 79C signal. This signal is generated, as shown in FIG. 6CC, by ANDing a trap signal with a phase 2 timing signal.
Funnel 79D
Funnel 79D connects IR 3-6 to the ALU B bus. This signal gate funnel 79D is generated, as shown in FIG. 6DD, by ANDing a "not trap" signal with a RIM decode with bit 7 of the instruction equal to 0.
Funnel 79E
Funnel 79E is the inverted gate funnel 79D signal. Funnel 79E connects lines 3-6 of the IR bus to the ALU B bus.
Funnel 79F
79F connects lines 5-7 of the IR bus to lines 5-7 of the ALU B bus and is controlled by the signal gate funnel 79F. This signal is generated, as shown in FIG. 6EE, by ANDing a "not trap" signal with a BOB decode.
Funnel 79G
Funnel 79G connecting lines 8-15 of the IR bus to lines 0-7 of the ALU B bus is controlled by the gate funnel 79G signal. This signal is generated, as shown in FIG. 6FF, by ANDing a "not trap" signal with a decode of any of the following instructions: BOC, LRI, BR or BAL.
Funnel 105A
Funnel 105A connects the M Bus 15 to the BOB logic unit 104. The gate 105A signal is generated, as shown in FIG. 6GG, from a IR bit 11.
Funnel 105B
Funnel 105B connects the RAM output bus 63 to the BOB logic unit 104. The gate 105B signal is generated, as shown in FIG. 6GG, by inverting a gate 105A signal.
Funnel 106A
Funnel 106A connects one line from the Stack Pointer Logic 101 and three lines from the Condition Decoder 102 to the Status Register 100. The gate funnel 106A signal is a decode of an SIL instruction, as shown in FIG. 6HH.
Funnel 106B
Funnel 106B connecting lines 0-2 and 7 of the ALU bus to the Status Register 100 is controlled by gate funnel 106B signal which is the inverted gate funnel 106A signal, as shown in FIG. 6HH.
The logic for generating the gated driver control signals is also part of the control subsystem. FIGS. 7A through 7E illustrate the gated drivers for the ALU output bus 73 and bus 15 and the logic for generating the gate signals for drivers 110,
111, 112 and 114.
Gated Driver 110
The control signal for gated driver 110 which interconnects the ALU register 71 to the bus 15 as shown in FIG. 7B is generated by latch 110A. Latch 110A is set at the beginning of T0 and reset at the beginning of T2.
Gated Driver 111
The control signal for gated driver 111 which connects the output of the ALU register 71 to the ALU out bus 73 as shown in FIG. 7C is generated by latch 111A. Latch 111A is set by either a T4 timing signal and a trap signal or a T0 timing signal, a not trap signal and a not BOB instruction decode signal, or T2 and not link and not trap. Latch 111A is reset by T7 and not 3/4 clock, or T2 and link.
Gated Driver 112
The control signal for gated driver 112 connecting the program counter 51 to the ALU out bus 73 as shown in FIG. 7D is generated by latch 112A. Latch 112A is set by a T7 timing pulse, a trap signal and a not RAM clock signal or a T2 timing pulse, a link instruction decode and a RAM clock signal or a T0 timing pulse and a BOB decode. Latch 112A is reset by either a T2 timing signal, a not link instruction decode and a RAM clock, or a T5 timing pulse and a RAM clock signal.
Gated Driver 114
Gated driver 114 connecting the output of the status register 100 to the ALU out bus 73 as shown in FIG. 7E is controlled by a latch 114A. Set by RAM clock and T2 and trap reset by T4.
FIG. 5 illustrates the timing of these busses.
The logic for generating the various load register signals is also part of the control subsystem D.
Signal inputs to registers are gated into the register by specific load signals. The registers employ polarity hold latches which are set by the trailing edge of the load signal.
FIGS. 8A through 8K illustrate the logic for generating the specific load register signals. FIG. 5 shows the timing of these signals.
LIRD
The LIRD signal is supplied to the instruction register decoder 53 and is active for period T7. The LIRD signal is generated by ANDing a T7 signal from the bit ring counter with an appropriate control signal and functions to gate the contents of the instruction data bus into the instruction decoder 53 during T7 time. The logic is not shown in FIG. 8.
LARL
The Load Address Register Low Signal controls the loading of the ARL 50A from funnel 55. The LARL signal as shown in FIG. 8A is generated by either a T2 timing signal and a "not link" instruction decode or a T1 timing signal and a link decode signal and a not trap signal. LARL is therefore active at either T1 or T2 only as shown in FIG. 5.
LARH
The Load Address Register High signal controls the loading of ARH 50B from funnel 54. The LARH signal as shown in FIG. 8B is generated by either of two signals. The first is a T2 timing pulse and a decode from a not RAR or SIL instruction and not trap. The second is a T1 timing signal, a 3/4 clock signal and an RAR or SIL decode signal.
LPC
The Load Program Counter Signal loads the contents of the Address Register 50 into the Program Counter 51. The LPC signal as shown in FIG. 8C is generated from a T6 timing signal and a not EXI or EID decode.
LALUR
The Load ALU Register signal loads the output of the ALU 70 to the ALU Register 71. The LALUR signal as shown in FIG. 8D is generated by a T1 timing signal or a T5 timing signal and an SID or FID instruction decode.
LSR
The Load Status Register signal loads the output of funnel 106B from the ALU out bus 73, lines 0-2 and 7 into the four stages of the Status Register. The LSR control signal as shown in FIG. 8E is generated by T4 timing signal, a 3/4 clock signal, a not trap signal and an SIL decode. The four outputs of the funnel 106B are loaded in parallel into the Status Register 100 by LSR, whereas the four outputs of funnel 106A are each provided with their own load signal.
LCC1
Stage 0 of Status Register 100 is loaded with the value of line 0 from the Condition Decoder 102 representing condition code 1 CC1 (ALU bus=all zero) by the LCC1 signal. The load condition code 1 signal as shown in FIG. 8F is generated by a T2
timing pulse and a decode of any of the following instructions: SIM, FIM, BOB, SID, FID, RR or RIM and not trap. For RI instructions, CC1 is updated by the results of the half byte of the ALU bus being equal to 0 that is selected by bit 7 of the instruction.
LCC2
Stage one of the Status Register 100 is set when the value of line 1 from Condition Decoder 102 representing Condition Code 2 (ALU Bus.noteq.to all zeros) is positive by the LCC2 signal. The Load Condition Code 2 signal as shown in FIG. 8G is generated by a T2 timing signal and a decode of the following instructions: XORI, XORR CIM, or CR. Stage 1 is reset only by a BOC decode specifying a test for CC2, i.e., bit six of the instruction is on.
LCC3
Stage two of the Status Register 100 is loaded from funnel 106A by the LCC3 signal. Stage two represents the carry signal from ALU 70. The load condition code 3 signal as shown in FIG. 8H is generated by a T2 timing signal and a decode of any of the following instructions: AIC, ARC, AIM, AR, or T5 and a decode of the instructions FID or SID.
TSP
Stage four of the Status Register 100 functions as a trigger in response to a positive valued signal on the input to state four from funnel 106A. The Toggle Stack Pointer signal as shown in FIG. 8I is generated by a T5 timing signal and a BAL decode or a BORL decode, or an RAR decode when bits 14 and 15 of the RAR instruction are active and T5.
LMR
The Load Mask Register LMR signal loads the mask register 88 with the contents of the ALU out bus 73. The LMR signal as shown in FIG. 8J is generated by ANDing a T4 timing signal with an StM decode or a T5 timing signal with an SIL decode.
LAUR
The Load Auxiliary Register LAUR signal loads the auxiliary register 66 with the contents of the ALU out bus 73. The LAUR signal as shown in FIG. 8K is generated by a T5 timing pulse and an FID or SID decode; a T7 timing pulse, a 3/4 clock and a SIL; or a T4 timing pulse, a RAM address<0, a RAM write signal, and a not RID or SID signal.
LLR
The Load Level Register signal is generated by a T6 timing signal and an SML decode, and loads IRD 11-13 into the level register.
The Instruction Set
The function of each of the 30 separate instructions shown in FIG. 4 will now be described.
Individual Instructions
During an execution of an instruction, several different functions may occur. Each of these functions is generally common to a number of different instructions, so are described in detail at this point and merely referred to generally in the description of each instruction.
During the execution of certain instructions, it is necessary to set up address register high and address register low to fetch the next sequential instruction so that at T7 time of the current instruction cycle the output of ROS unit 52 can be loaded into the instruction register decoder 53. ARh and ARL are set up for the next instruction by transferring PCH and PCL to ARH and ARL through funnels 54C and 55D at T2 time. PCL is incremented by 1 at the beginning of T2. At T6 time, the program counter is updated by ARH and ARL so that at T2 time of the following instruction cycle ARH and ARL can again be updated from PCH and PCL plus 1, if the next sequential instruction is needed.
For certain instructions, for example the Execute Immediate and Execute Indirect instructions, the updating of the program counter at T6 is inhibited since the program counter reflects the address of the next instruction to be executed after the EXI or EID is executed.
Several instructions involve the addressing of an external funnel or an external register. This operation is the same for each of these instructions and was described in detail earlier. The operation, therefore, is referred to only generally in describing that portion of these instructions.
Several instructions involve the addressing of an internal register in RAM 38 through funnels 64 and 65 to either read data from the register or write data into the register. The read and write operations were discussed in detail in describing the overall operation of RAM 38, and hence, are not discussed in detail in each instruction.
Other operations which are common to two or more instructions, such as "link" will be described once in detail and then referred to generally in subsequent instructions.
______________________________________ 1. BRANCH (BR) A. INSTRUCTION FORMAT Bits 0-2 op code Bits 3-15 branch address ______________________________________
B. FUNCTIONAL DESCRIPTION
This instruction allows branching within 8K words of the control store. The branch address is represented by bits 3-15 of the BR instruction. The highest order bit located in stage O of ARH is not changed. Branching is, therefore, limited to the same 8K section of ROS where the branch instruction is stored.
Lines 3-7 from instruction decoder 53 are connected directly to funnel 54B which applies stages 1 through 5 of ARH with five of the six bits for ARH. The low order portion of the address is supplied from decoder 53 to ARL through funnel 79G,
78B, the ALU 70, ALU Reg. 71, funnel 72A, drive 111, ALU output bus 73 and funnel 55A.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 54B T7+ Connect IR 3-7 to ARH LARH T2 ARH loaded from funnel 54B Gate Funnel 79G T7+ Connect IR 8-15 to ALU B bus 82 Gate Funnel 78B T7+ Connect 82 to ALU B input LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T1-T7 Connect ALU Reg. to driver 111 Gate Driver 111 T0+ Connect funnel 72 to ALU out bus 73 Gate Funnel 55A T7+ Connect ALU out bus 73 to ARL LARL T2 ARL loaded from funnel 55 ______________________________________
D. NEXT ADDRESS
Unconditional branch type of instruction. The next address is generated by executing the instruction.
E. STATUS REGISTER CHANGE
No change.
2. BRANCH ON BIT (BOB)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bit 3 op code modifier Bit 4 0=Off, False; 1=On, True Bits 5-7 increment Bits 8-10 bit position to be checked Bits 11-15 register to be checked ______________________________________
B. FUNCTIONAL DESCRIPTION
The Branch on Bit instruction is a conditional branch instruction. Any bit of any internal or external register can be tested for an on (1) or off (0) condition. If the test is true, the branch is taken. If not true, the program counter is incremented by one and the next sequential instruction is taken. The branch address is the current program counter plus an increment of from 0-7 specified by bits 5-7 of the instruction.
Program counter high 51B is gated through funnel 54C and loaded into address register high 50B at T2 time.
The contents of the register specified by bits 11-15 are supplied to the Branch on Bit logic unit 104 along with bits 8-10 which specify the bit position to be checked. If bit 11 is a 0, an external funnel is indicated. This funnel is gated to the M bus and to the Branch On Bit Logic unit through funnel 105a. If bit 11 is a 1, an internal register is addressed and is gated through funnel 105B. If the value of the bit position defined by bits 8-10 matches the value of bit 4 of the instruction, the Branch On Bit logic unit indicates a BOB=YES signal. If the BOB logic is true, the address register low signal is loaded from the ALU register 71. If BOB logic is false, the address register low is loaded from program counter low through funnel 55D.
The branch address for ARL which comes from the ALU register 71 is generated by gating program counter low through funnel 56A and driver 112 onto the ALU out bus 73 through funnel 77A to the A input of the ALU. Bits 5-7 of the instruction register are gated through funnel 79F to ALU B bus 82 through funnel 78B to the B input of the ALU 70. The ALU is set to add the A and B inputs and the results are stored in the ALU register 71 at T1 time. An increment of 0 can be used as a one instruction wait loop.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 54C T7+ Connect PCH to ARH Load ARH T2 ARH loaded from funnel 54C If bit 11=1 Gate Funnel 64A T7+ Connect IR 12-15 to RAH Gate Funnel 65A T7+ Connect level Reg. to RAL Gate Funnel 105B T7+ Connect 63 to BOB logic 104 Read RAM T0 Read out addressed Reg. Set BOB Unit T0 Load Branch on Bit logic unit If bit 11=0 Gate External Funnel T0 Load M bus from funnel Gate Funnel 105A T7+ Connect M bus to BOB logic 104 Set BOB Unit T1 Load BOB unit Gate Funnel 56A T7+ Connect PCL to 112 Gate Driver 112 T7+ Connect funnel 56 to ALU out bus Gate Funnel 77A T7+ Connect 73 to ALU A Gate Funnel 79F T7+ Connect IR 5-7 to ALU B bus 82 Gate Funnel 78B T7+ Connect 82 to ALU B LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T7+ Connect funnel 72 to ALU out bus 73 If BOB=YES Gate Funnel 55A T2 Connect ALU out bus 73 to ARL If BOB=NO Gate Funnel 55D T2 Connect RAM out bus 63 to ARL LARL T2 ARL loaded from funnel 55 ______________________________________
D. NEXT ADDRESS
Conditional branch type of instruction. The next address is generated either by executing instruction or by transferring program counter to address register.
E. STATUS REGISTER CHANGE
No change.
3. BRANCH ON CONDITION (BOC)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bit 3 op code modifier Bit 4 0=Off, False; 1=On, True Bits 5-7 specified conditions Bits 8-15 branch address ______________________________________
B. FUNCTIONAL DESCRIPTION
The Branch on Condition instruction is a conditional branch instruction. Bits 5-7 of the instruction signify a reference to condition code CC1, CC2 or CC3. The condition code is matched against the condition code in status register 100. If bit
4 is a 1, then the selected condition codes will be tested for a 1. If any condition code is on, then Branch on Condition will equal YES and will be set to a true value. If bit 4 is a 0, then the specified conditions will be tested for a 0 and if any condition code is a 0, the Branch on Condition will be set to equal true. If the Branch on Condition is true, the branch address is generated and used for the next instruction. If false, the program counter is used for the next address.
The program counter high 51B is gated through funnel 54C and loaded into ARH 50B at T2 time. The branch address defined by bits 8-15 is transferred to the ALU register 71 through funnel 79G, ALU B bus 82, funnel 78B and ALU register 71. If the Branch on Condition is true, the output of the ALU register is transferred to ARL through gate 72A, driver 111, ALU output bus 73 and funnel 55A. If the Branch on Condition is false, program counter low is transferred to ARL through funnel 55D. If bit
6 of the instruction is on, then condition code 2 is reset at the end of the instruction.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 54C T7+ Connect PCH to ARH LARH T2 ARH loaded from funnel 54 Gate Funnel 79G T7+ Connect IR 8-15 to ALU B bus 82 Gate Funnel 78B T7+ Connect 82 yo ALU B LALUR T1 ALU Reg. loaded from ALU 70 If BOC=True Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T7+ Connect funnel 72 to ALU out bus 73 Gate Funnel
55A T7+ Connect ALU out bus 73 to ARL If BOC=False Gate Funnel 55D T7+ Connect PCL to ARL LARL T2 ARL loaded from funnel 55 ______________________________________
D. NEXT ADDRESS
Conditional branch type of instruction. The next address is generated either by executing instruction or by transferring program counter to address register.
E. STATUS REGISTER CHANGE
CC2 reset at T5.
4. FETCH IMMEDIATE (FIM)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bits 3-7 destination register Bit 8 op code modifier; 0=Fetch Bit 9 buffer or stack (0=buffer) Bits 10-15 address of the source register ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of this instruction is to transfer a byte of data from any position in the local store or program stack to any internal or external register.
The data path extends from RAM 38 through RAM output bus 63, funnel 77C to the ALU register 71. If the destination is an internal register, the path is from the ALU register 71 through funnel 72A, driver 111, ALU output bus 73 to the input of RAM 38. If the destination is an external register, the path extends from the ALU register 71 through driver 110, the M bus 15 to the selected external register.
The source register in RAM 38 is addressed through funnel 64C and 65B. Funnel 64C supplies IR bits 9, 13, 14 and 15 to RAH while funnel 65B supplies IR bits 10, 11 and 12 to RAL. If the destination register defined by IR 3-7 is external, i.e., bit 3 is equal to a 0, the external register is addressed as previously described by decoder 26.
If the destination register is an internal register, i.e., bit 3 is a 1, then funnel 64B supplies bits 4-7 to RAH while funnel 65A supplies the output of the level register to RAL.
C. CONTROL SIGNALS AND TIMING
______________________________________ Tim- Control Signals ing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 64C T7+ Connect IR 9, 13-15 to RAH Gate Funnel 65B T7+ Connect IR 10, 11, 12 to RAL Gate Funnel 77C T7+ Connect 63 to ALU A Read RAM T0 Read out addressed Reg. LALUR T1 ALU Reg. loaded from ALU 70 If bit 3=1 Gate Funnel 72A T1 Connect ALU Reg. to driver 111 Gate Driver 111 T1 Connect funnel 72 to ALU out bus 73 Gate Funnel 64B T1 Connect IR 4-7 to RAH Gate Funnel 65A T1 Connect level Reg. to RAL Write RAM T3 Write into addressed Reg. If bit 3=0 Gate Driver 110 T2 Connect ALUR 71 to M bus Load External Register T4 External register loaded from M bus ______________________________________
D. NEXT ADDRESS
Non-branch type of instruction. The next sequential address is generated by program counter and transferred to address register.
E. STATUS REGISTER CHANGE
CC1 changed at T2.
5. STORE IMMEDIATE (SIM)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bit 3 internal or external Bits 4-8 source register Bit 9 buffer or stack Bits 10-15 destination register ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of this instruction is to transfer the contents of a specified source register, either internal or external, to an internal buffer or stack register whose address is defined by bits 9-15. Bit 3 determines if the source register is either internal or external. The data path from an external register to RAM is through M bus 15, funnel 77B, ALU register 71, funnel 72A, driver 111 and ALU bus 73. The data path from an internal register back to RAM is RAM output bus 63, funnel 77C, ALU register 71, funnel 72A, driver 111 and ALU bus 73. An external register is addressed in a conventional manner. The internal register is addressed through funnel 64B and 65A. Funnel 64B supplies IR bits 4-7 to RAH while funnel 65A supplies the output of level register to RAL from the level register. The destination register in RAM 38 is addressed through funnel 64C and 65B. Funnel 64C supplies bits 9, 13, 14 and 15 to RAH while funnel 65B supplies bits 10, 11 and 12 to RAL.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 If bit 3= 0 Gate External Funnel T0-T1 Load M bus from funnel Gate Funnel 77B T0-T1 Connect M bus to ALU A LALUR T1 ALU Reg. loaded from ALU 70 If bit 3= 1 Gate Funnel 77C T0 Connect 63 to ALU A Gate Funnel 64B Phase 1 Connect IR 4-7 to RAH Gate Funnel 65A T0 Connect level Reg. to RAL Read RAM T0 Read out addressed Reg. LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T7+ Connect funnel 72 to ALU out bus 73 Gate Funnel 64C Phase 2 Connect IR 9, 13-15 to RAH Gate Funnel 65B Phase 2 Connect IR 10, 11, 12 to RAL Write RAM T3 Write into addressed Reg. ______________________________________
D. NEXT ADDRESS
Non-branch type of instruction. The next sequential address is generated by program counter and transferred to address register.
E. STATUS REGISTER CHANGE
CC1 changed at T2
6. REGISTER IMMEDIATE (RIM)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bits 3-6 constant Bit 7 H/L half byte Bits 8-10 ALU op code Bit 11 external or internal register Bits 12-15 register address ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of this instruction is to perform one of six different logical operations defined by bits 8-10 involving a 4 bit constant defined by bits 3-6 and the high or low half byte determined by bit 7 of an 8 bit byte stored in a register whose address is defined by bits 11-15. If bit 11 is a 0, the data path is from the external register to the ALU through M bus 15 and funnel 77B. If bit 11 is a 1, the data path from RAM extends from bus 63 through funnel 77C. The other input to the ALU is from funnel 79E if bit 7 is a 1, and from funnel 79D if bit 7 is a 0. Both of these funnels are supplied with the half byte of data defined by IR 3-6. Funnel 79D is supplied with the low half byte and funnel 79E with the upper half byte. The data from funnel 79E is supplied to ALU B bus 82 to funnel 78B and the ALU B input.
The ALU performs the defined logical function and the results are loaded into the ALU register 71. The ALU register is transferred to the source register through either 72A and driver 111, or through driver 110, M bus 15 to the external register. The external register is addressed in a conventional manner. The internal register is addressed through funnel 64A and 65A. Funnel 64A supplies IR 12-15 to RAH and funnel 65A supplies the output of the level register to RAL. Both external registers must have the same address if one is a source and the other a destination.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 If bit 7= 1 Gate Funnel 79E T7+ Connect IR 3-6 to ALU B bus 82 4-7 If bit 7= 0 Gate Funnel 79D T7+ Connect IR 3-6 to ALU B bus 82 0-3 Gate Funnel 78B T7+ Connect 82 to ALU B If bit 11= 0 Gate Funnel 77B T0-T1 Connect M bus to ALU A Gate External Funnel T0 Load M bus from funnel If bit 11= 1 Gate Funnel 77C T0 Connect 63 to ALU A Gate Funnel 65A T7+ Connect level Reg. to RAL Gate Funnel 64A T7+ Connect IR 12-15 to RAH Read RAM T0 Read out addressed Reg. LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T0+ Connect ALU Reg. to driver 111 Gate Driver 111 T0+ Connect funnel
72 to ALU out bus 73 Gate Funnel 65A T7+ Connect level Reg. to RAL Gate Funnel 64A T7+ Connect IR 12-15 to RAH Write RAM T4+ Write into addressed Reg. ______________________________________
D. NEXT ADDRESS
Non-branch type of instruction. The next sequential address is generated by program counter and transferred to address register.
E. STATUS REGISTER CHANGE
The condition codes 1-3 are set in accordance with the following table:
______________________________________ Register Immediate ALU S0- INST OP Cin M S3 CC1 CC2 CC3 ______________________________________ AND IMM AND 0 1 0111 Set OR IMM OR 0 1 1101 Set XOR IMM XOR 0 1 1001 Set Set ADD+ C IMM ADD CC3 0 1001 Set Set COMPARE IMM XOR 0 1 1001 Set Set ADD IMM ADD 0 0 1001 Set Set ______________________________________
7. REGISTER TO REGISTER (RR-MR)
A. INSTRUCTION FORMAT
______________________________________ Bit 0-2 op code Bit 3 internal/external Bits 4-7 destination register (operand A) Bits 8-10 op code modifier Bit 11 internal/external Bits 12-15 source register (operand B) ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of the Register to Register Move instruction is merely to move the contents of one register to another register. In a Register to Register Move operation, four different data paths are possible since the source register may be either internal or external and the destination register may be either internal or external.
If the source register defined by bits 11-15 is internal, data is placed on RAM output bus 63 and supplied to funnel 77C and loaded into the ALU register 71 at T1 time. If the source register is external, data from the selected funnel is placed on M bus 15 and gated through funnel 77B and loaded into the ALU register at T1 time. If the destination register is internal, the data is transferred from the ALU register 71 through funnel 72A, driver 111, ALU output bus 73 to the input of RAM 38. If the destination register is external, the data is transferred from the ALU register 71 through driver 110 to the M bus 15 to the selected register.
Addressing of the external funnel and/or register is conventional through decoder 26.
Addressing of an internal source register is through funnel 65A and funnel 64A. The funnel 65A supplies the level register to RAL, while funnel 64A supplies IR 12-15 to RAH. Addressing of an internal destination register is through funnel 64B which is supplied with IR 4-7 and sets RAH. Level register 87 is supplied to funnel 65A to set RAL.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Source is Internal Gate Funnel 77C T7+ Connect 63 to ALU A Gate Funnel 65A T7+ Connect level Reg. to RAL Gate Funnel 64A T7+ Connect IR 12-15 to RAH Read RAM T0 Read out addressed Reg. LALUR T1 ALU Reg. loaded from ALU 70 Source is External Gate Funnel 77B T7+ Connect M bus to ALU A Gate External Funnel T0-T1 Load M bus from funnel LALUR T1 ALU Reg. loaded from ALU 70 Destination is Internal Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T0 Connect funnel 72 to ALU out bus 73 Gate Funnel 65A T2+ Connect level Reg. to RAL Gate Funnel 64B T2+ Connect IR
4-7 to RAH Write RAM T4+ Write into addressed Reg. Destination is External Gate Driver 110 T7+ Connect ALU Reg. to M bus Load External Register T4 Register loaded from M Bus ______________________________________
REGISTER TO REGISTER INSTRUCTION OTHER THAN MOVE (RR)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bit 3 internal/external Bits 4-7 destination register Bits 8-10 op code modifier Bit 11 internal/external Bits 12-15 source register ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of the Register to Register Instruction Other Than Move is to perform a specified ALU operation on the data in the two registers whose addresses are defined by bits 3-7 and 10-15 of the instruction. The result of the ALU operation (except for COMPARE) is stored in the register defined by bits 3-7. This register is defined as the destination register. Bits 10-15 define the source register RS. One register must be an internal register and the other an external register, or both registers can be the same. The auxiliary register can be either an internal or external register for the instruction so that an external register and the auxiliary register can be involved, or an internal register and the auxiliary register can be involved in the operation. The following is a chart of the six possible destination and source register combinations:
______________________________________ Destination Register Source Register ______________________________________ External Internal Internal External External Auxiliary Auxiliary External Internal Auxiliary Auxiliary Internal Internal Internal (same address) ______________________________________
The contents of both registers are supplied to the ALU, operated on, and stored in the ALU register 71. The ALU register is then transferred to the destination register. The data path from the external register to the ALU is the same regardless of whether it is a source or destination. This path extends from the external funnel specified by the address to the M bus 15 through funnel 77B to the A input of the ALU 70.
The data path from the internal register to the ALU is the same regardless of whether it is a source or destination. This path extends from RAM output bus 63 through funnel 78A to the B input of ALU 70. This path is used when the other register is an external register. When the other register is the auxiliary register, the data path is from RAM output bus 63 through funnel 77C to the A input of the ALU 70. The data path from the auxiliary register to the ALU is through funnel 79A, ALU bus 82, funnel 78B to the B input of the ALU. The data path from the ALU register 71 to the destination register is as follows: if the destination register is an external register, the path is through driver 110, the M bus, to the selected external register. If the destination register is an internal register, the path is through funnel 72A, driver 111, ALU output bus 73 to the write input of RAM 38. If the destination register is the auxiliary register, then the auxiliary register 66 and RAM 38 location 00
are supplied from the ALU output bus 73.
Addressing of the external register and funnel is through decoder 26. Addressing of the RAM is through funnels 65A and 64A where the auxiliary register is the source register, and through funnel 65A and 64B where an internal register is the destination register. The ALU register 71 is loaded at T1 time with the results of the ALU operation. The external register is loaded at T4 time.
D. NEXT ADDRESS
Non-branch type of instruction. The next sequential address is generated by program counter and transferred to address register.
E. STATUS REGISTER CHANGE
The following chart indicates what occurs with the condition codes CC1 through CC3 for the various ALU ops for an R to R instruction which is not a move:
______________________________________ Register to Register ALU S0- INST OP C-IN M S3 CC1 CC2 CC3 ______________________________________ AND REG AND 0 1 0111 Set OR REG OR 0 1 1101 Set XOR REG XOR 0 1 1001 Set Set ADD+ C REG ADD CC3 0 1001
Set Set COMPARE REG ADD 0 1 1001 Set Set ADD REG ADD 0 0 1001 Set Set MOVE PASS 0 1 1111 Set A ______________________________________
8. LOAD REGISTER IMMEDIATE (LRI)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bit 3 internal or external register Bits 4-7 register address Bits 8-15 data constant ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of this instruction is to load an 8 bit constant specified by bits 8-15 to either an internal register or an external register whose address is specified by bits 3-7.
Since there is one data source and two potential destinations, two potential data paths and two potential addresses are involved. Bit 3 of the instruction determines which data path is selected and which address is involved. If bit 3 is equal to a 0 indicating an external register, the data path extends from the instruction decoder 53, lines 8-15 through funnel 79G ALU Bus 82, funnel 78B to ALU Reg 71. The ALU Reg is loaded at T1 time. From ALU Reg 71 the path extends through drivers 110 to Bus 15 to the selected external register. The external register is loaded at T4 time.
The address of the external register is supplied from instruction decoder 53 to external register address decoder 26 which selects the appropriate register.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 79G T7+ Connect IR 8-15 to ALU B bus 82 Gate Funnel 78B T7+ Connect 82 to ALU B LALUR T1 ALU Reg. loaded from ALU 70 Gate Driver 110 T7+ Connect ALU Reg. to M bus Gate External Register T4 Register loaded from M bus ______________________________________
If bit 3 is equal to a 1, the data path is the same to the ALU register. However, from the ALU register 71, the data path to the internal register is through funnel 72A Drivers 111, ALU output Bus 73 to the input of RAM 38. The RAM address specified by bits 4-7 is supplied from IR decoder 53, lines 4-7 to funnel 64B for RAM address high. The four low order address bits for RAL are supplied from level register 87 through funnel 65A.
The following control signals occur at the times indicated to cause the appropriate action. The sequence is the same to the point that the ALU register 71 is loaded. From then on the sequence differs as follows:
______________________________________ Control Signals Timing Function ______________________________________ LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T1 Connect ALU Reg. to driver 111 Gate Driver 111 T1 Connect funnel 72 to ALU out bus 73 Gate Funnel 64B T7+ Connect IR 4-7 to RAH Gate Funnel 65A T7+ Connect level Reg. to RAL Write RAM T4 Write into addressed Reg. ______________________________________
D. NEXT ADDRESS
Non-branch type of instruction. The next sequential address is generated by program counter and transferred to address register.
E. STATUS REGISTER CHANGE
No change.
9. EXECUTE IMMEDIATE (EXI)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bits 3-7 page address Bits 8-10 op code modifier Bits 11-15 register address ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of this instruction is to branch unconditionally to an instruction stored in an address determined by the page address bits 3-7 and the contents of the register whose address is specified by bits 11-15. It will execute the instruction at this address and will then return to the next sequential instruction. Bits 3-7 determine four of the five address register high bits while the eight address register low bits are determined by the contents of the addressed register, the high order bit 0 of the address register high is not changed.
The first data path extends from IR decoder 53, lines 3-7 to address register high, lines 1-5. This path involves only funnel 54B.
The second path which is established to ARL 50A originates at either an external funnel or an internal register. If bit 11 is a 1, the register is internal. If bit 11 is 0, the source is an external funnel. The path from an external funnel to ARL 50A is through the M Bus 15, GATE 77B, ALU REG 71, funnel 72A, driver 111, ALU out Bus 73 and funnel 55A. The path from an internal register to ARL 50A is from the RAM output data Bus 63, funnel 77C, to ALU REG 71. From ALU REG 71 to ARL 50A the path is the same as for the external register.
If bit 11 is a 0, the external register address is supplied from the external register address decoder 26 which is connected to IRD 53 which then selects the correct external register. If bit 11 is a 1, the internal register address is generated through funnel 64A from level register 86 to RAL 60A.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 54B T7+ Connect IR 3-7 to ARH LARH T2 ARH loaded from funnel 54 If bit 11= 0 Gate External Funnel T0 Load Reg. from M bus Gate Funnel 77B T7+ Connect M bus to ALU A LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T7+ Connect funnel 72 to ALU out bus 73 Gate Funnel 55A T7+ Connect ALU out bus 73 to ARL LARL T2 ARL loaded from funnel 55 If bit 11= 1 Gate Funnel 64A T7+ Connect IR 12-15 to RAH Gate Funnel 65A T7+ Connect level Reg. to RAL Read RAM T0 Read out addressed Reg. Gate Funnel 77C T7+ Connect 63 to ALU A LALUR T1 ALU Reg. loaded from ALU 70 Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T7+ Connect funnel 72 to ALU out bus 73 Gate Funnel 55A T1 Connect ALU out bus 73 to ARL LARL T2 ARL loaded from funnel 55 ______________________________________
D. NEXT ADDRESS
The address register-program counter interaction is inhibited during this instruction so that the program counter can hold the address of the next instruction to be executed after the execute cycle is finished. This provides an automatic link back to the instruction following the original Execute instruction. Consecutive Execute instructions are legal and will operate. However, a conditional Branch instruction which is successful, or any successful branch, will destroy the function of the auto link operation.
E. STATUS REGISTER CHANGE
No change.
10. EXECUTE INDIRECT (EID)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bits 3-7 page address Bits 8-10 op code modifier Bits 11-15 register address ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of the EID instruction is the same as the Execute Immediate instruction. The difference is that the low order address of 8 bits is obtained by adding the value in the register specified by bits 11-15 to the contents of the auxiliary register. This permits generating a variable displacement number.
The data path and the controls for loading ARH are the same as described in connection with the EXI instruction.
The data path and controls for generating the ARL input are different up to the point that the ALU register 71 is loaded. From that point on, they are identical to the EXI instruction. Initially, the instruction sets the ALU to an ADD function mode. The data path from the auxiliary register to the input 75 of the ALU involves Gates 79A and 78B. The data paths to the ALU input 74 depends on whether bit 11 is a 1 or 0. If bit 11 is a 1, the data source is an internal register and the path involves the RAM output Bus 63 and funnel 77C to the ALU register input 71. If bit 11 is a 0, the data source is an external register and the path includes the M Bus 15 and funnel 77B.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Auxiliary Reg. T0 Connect aux. reg. to funnel 79A Gate Funnel 79A T7+ Connect AUX Reg. to ALU B bus 82 Gate Funnel 78B T7+ Connect 82 to ALU B LALUR T1 ALU Reg. loaded from ALU 70 If bit 11=1 Gate Funnel 64A T7+ Connect IR 12-15 to RAH Gate Funnel 65A T7+ Connect Level Reg. to RAL Read RAM T0 Read out addressed Reg. Gate Funnel 77C T7+ Connect 63 to ALU A If bit 11=0 Gate External Funnel T0 Connect funnel to M bus Gate Funnel 77B T7+ Connect M bus to ALU A LALUR T1 ALU Reg. loaded from ALU 70 ______________________________________
The internal page address and external register address are generated as described for the EXI instruction.
D. NEXT ADDRESS
Non-branch type of instruction. The next sequential address is generated by program counter and transferred to address register.
E. STATUS REGISTER CHANGE
No change.
11. FETCH INDIRECT AND INCREMENT (FID)
A. INSTRUCTION FORMAT
______________________________________ Bits 0-2 op code Bit 3, 5-10 fetch op code modifier Bit 4 increment control Bits 11-15 register address destination ______________________________________
B. FUNCTIONAL DESCRIPTION
The function of the Fetch Indirect and Increment instruction is to transfer a byte of data from a RAM storage location defined by the contents of the auxiliary register to either an internal or external register whose address is defined by IR bits 11-15 and then selectively increment the value of the auxiliary register by 1. The increment can be inhibited by making bit 4 a 1.
The data path from the internal register defined by the auxiliary register is from the RAM output bus 63, funnel 77C to the ALU register 71. If bit 11 is a 1, the destination register is internal so that the data path continues from ALU register
71 through funnel 72A, driver 111, and ALU output bus 73 to the input of RAM 38. If the destination has been specified as internal register 0, the auxiliary register is not updated with the contents of the ALU register 71. If bit 11 is a 0, the destination register is external and the data path extends from the ALU register 71 through driver 110, M bus 15 to the selected external register. The above operation is completed at T4 time. The value of the auxiliary register 66 is supplied to ALU
70 through funnel 79A, ALU B bus 82 and funnel 78B. If bit 4 is a 0, the ALU adds 1 to this value and stores the result in ALU register 71 at T5 time. The updated value is then transferred to register 00 of the RAM at the correct level and to the auxiliary register 66 at T6 time. The path from the ALU register 71 extends through funnel 72A, driver 111 and the ALU out bus 73.
The initial RAM address defined by the contents of the auxiliary register 66 is established through funnels 64D and 65D which are connected to the output of the auxiliary register 66. The address of the external destination register is established by decoder 26 and is conventional, as previously described. The address of the internal destination register is generated through funnels 64A and 65A. Funnel 64A is supplied with IR bits 12-15 while funnel 65A is supplied with the current level from level register 87.
The auxiliary register address 00 is generated for RAL by not selecting any of the funnels 64, while the current level is gated through funnel 65A from the level register 87.
C. CONTROL SIGNALS AND TIMING
______________________________________ Control Signals Timing Function ______________________________________ LIRD T7 IR bus loaded into IRD 53 Gate Funnel 77C T7+ Connect 63 to ALU A Gate Funnel 64D T7+ Connect AUX Reg. 4-7 to RAH Gate Funnel 65D T7+ Connect AUX Reg. 0-4 to RAL Read RAM T0 Read out addressd Reg. LALUR T1 ALU Reg. loaded from ALU 70 If bit 11=1 Gate Funnel 72A T7+ Connect ALU Reg. to driver 111 Gate Driver 111 T7+ Connect funnel 72 to ALU out bus 73 Gate Funnel 64A T7+ Connect IR 12-15 to RAH Gate Funnel 65A T1 Connect level Reg. to RAL Write RAM T4 Write into addressed Reg. If bit 11=0 Gate Driver 110 T7+ Connect ALU Reg. to M bus Load External T4 Register lo