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United States Patent4276594
MorleyJune 30, 1981
Title
Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same
Abstract
A digital computer with the capability of incorporating multiple central processing units (CPU's), utilizes an address and data bus between each central processing unit and from one to fifteen intelligent composite memory and input/output modules (MIO). Data is transferred to and from each MIO and the CPU synchronously by a bus during one phase of a three phase clocking cycle. During a second phase of the clocking cycle data on one or more low speed serial data channels within each MIO is transferred to and from the MIO and external devices. During the third phase of the clocking cycle data on a high speed direct memory access channel (DMA) is transferred to and from the MIO and one or more external devices. Additional CPU's can be interconnected with the first CPU by means of an inter-processor buffer module (IPB) which interconnects to the bus at one end and the additional CPU, by means of a bus, at its other end. The IPB may be a software modifiable MIO and can store data addressable by the two interconnected CPU's. In turn, the additional CPU and its associated bus interconnects by the second bus with from one to fifteen additional MIO's or IPB's, allowing cascading of CPU's and associated MIO's and IPB's. Since all data transfers to and from the MIO's and external devices occur at time phases separate from the first time phase in which the CPU communicates with the MIO's and IPB's, the computational speed of any CPU is independent of the quantity of data transferred between the MIO's and IPB's and associated external devices or additional CPU's.
Inventors:Morley; Richard E. (Greenville, NH)
Assignee:Gould Inc. Modicon Division (Rolling Meadows, IL)
Appl. No.:916274
Filed:June 16, 1978
Current U.S. Class:713/600 
Field of Search:364/2MSFile,9MSFile
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Other References
H Loren, "Parallelism in Hardware and Software: Real and Apparent Concurrency", Chaps. 11,12,18,19; Prentice-Hall Pub. Co., 1972. .
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1084 Model Programmable Controller, Modicon Corp. Brochure..~
Primary Examiner: Chapnick; Melvin B.
Attorney, Agent or Firm:Mattern, Ware, Davis & Stoltz
Parent Case Text


cl CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part application of U.S. patent application bearing Ser. No. 873,018, filed Jan. 27, 1978, now abandoned.
Claims

Having described the invention what is claimed is:
1. A computer comprising:
(A) a central processing unit (CPU) for the processing of data, the CPU having a processor;
(B) means, connected to the CPU for providing a communication path to and from the CPU;
(C) a clock, connected to the communication path means, for generating a repetitive multi-phase clock cycle; and
(D) a composite, intelligent memory and input/output module (MIO), connected to the communication path means, so as to store and transfer data to and from the CPU and to and from external devices, the data including all application code for execution by the CPU as well as all data used in the execution of the application code, the MIO comprising:
(1) a public memory for the storage of data accessible to both the CPU and the external devices during different phases of the multiphase clock cycle,
(2) a microprocessor responsive to the phases of the multi-phase clock cycle so as to control public memory access by the CPU and the external devices,
(3) a microprocessor bus connecting the public memory to the microprocessor,
(4) means, responsive to the microprocessor and connected to the microprocessor bus, for interfacing data to and from the external devices with the public memory, and
(5) means, responsive to the microprocessor and connected between the public memory and the communication path means, for interfacing data to and from the public memory and the CPU;
whereby data transfer to and from the public memory of the MIO to the communication path means occurs during a distinct phase of the clock cycle and the transfer of data to and from the public memory of the MIO with the external devices occurs during another distinct phase of the clock cycle.

2. The computer defined in claim 1, wherein the processor of the central processing unit (CPU) comprises:
(1) an arithmetic logic unit for performing computations,
(2) a second microprocessor for performing diagnostics, power up and control of the CPU, and
(3) a user programmable, writable control store, interconnected with the arithmetic logic unit and second microprocessor for storing the microcode necessary to translate user instructions into instructions readable and executable by the arithmetic logic unit under the control of the second microprocessor.

3. A computer defined in claim 1, wherein the multi-phase clock cycle has three distinct phases and wherein the MIO microprocessor is responsive to these three phases for control of public memory access by the CPU and parallel I/O devices and serial I/O devices, and wherein the means for interfacing data to and from the external devices with the public memory has separate connections to the parallel I/O devices and the serial I/O devices.

4. The computer defined in claim 1, wherein each phase of the multi-phase clock cycle has a duration of 500 nanoseconds.

5. The computer defined in claim 1, wherein the MIO is communicable between the first named CPU and a second CPU as an interprocessor buffer, thereby allowing hierarchical control of one CPU by another CPU.

6. The computer as defined in claim 1, wherein the communication path means comprises a bus.

7. A digital computer comprising:
(A) a first central processing unit (CPU);
(B) a bus interconnected to the central processing unit;
(C) a clock, interconnected to the bus, for repetitively generating at least two distinct clock phases per generation of a clock cycle; and
(D) up to N composite, intelligent memory, and input/output modules (MIO's), each interconnected to the bus, N being a positive integer greater than one, and each MIO having,
(1) a public memory for the storage of data including application code for execution by the CPU and data used in the execution of the application code accessible to both the CPU and external devices during different phases of the cycle,
(2) a first buffer for data transferral from the public memory to the bus,
(3) a second buffer for data transferral from the public memory to interconnected external devices, and
(4) means, responsive to the clock phases and communicating with the first and second buffers, for controlling the access to and from the public memory by the CPU during one clock cycle phase and for providing access to and from the public memory by external devices during at least one other clock cycle phase;
whereby data transfer to and from the public memory of each MIO to the bus occurs during a distinct phase of the clock cycle and the transfer of data to and from the public memory of each MIO with external devices occurs during another distinct phase of the clock cycle.

8. A digital computer as defined in claim 7 wherein the means for controlling access between each public memory and each first and second buffers for each MIO is a microprocessor.

9. A digital computer as defined in claim 8, wherein each MIO further comprises a third buffer for data transferral from the public memory to serial input/output devices and wherein the second buffer is connected to parallel data transfer external devices, wherein the clock generates a three-phase clock cycle and wherein the MIO public memory is accessible to the bus during a first phase of the clock cycle, is communicable with a serial input/output device during a second phase of the clock cycle and is communicable with a parallel input/output device during the third phase of the clock cycle.

10. A digital computer as defined in claim 9, wherein each phase of the three-phase clock cycle has a duration of 500 nanoseconds.

11. A digital computer as defined in claims 7, 8, or 9 wherein the central processing unit further comprises a microprocessor for performing diagnostics with respect to the central processing unit.

12. A digital computer as defined in claim 11, wherein the central processing unit includes a writable control store interconnected with the CPU microprocessor and wherein a series bit slice processor interconnects with the writable control store for execution of user instructions via a microcode stored in the writable control store.

13. A digital computer as defined in claim 7, further comprising:
(E) up to P interprocessor buffers (IPB's) connected to the bus, P being a positive integer;
(F) up to P additional buses, each additional bus connected to only one of the interprocessor buffers; and
(G) up to P additional CPU's, each connected to only one of the additional buses, and each communicable with the first CPU via the corresponding interprocessor buffer.

14. A digital computer as defined in claim 13, wherein each interprocessor buffer comprises a public memory and means for operating during the clock phases of the clock cycle so as to give access of the corresponding interprocessor buffer public memory to the first central processing unit during one clock phase and to the interconnected additional central processing unit during another clock phase.

15. A digital computer as defined in claim 14, wherein the accessibility of the public memory in each interprocessor buffer to the first central processing unit occurs during the same time that the first central processing unit has access to the public memories of other interconnected MIO's and IPB's.

16. A digital computer as defined in claim 15, wherein the total number of MIO's and IPB's that can be connected to one bus is fifteen.

17. A digital computer comprising:
(A) at least first and second central processing units (CPU's),
(B) a first bus connected to the first central processing unit,
(C) a second bus connected to the second central processing unit,
(D) a clock for generating a repetitive clock cycle having at least first and second distinct clock phases per clock cycle; and
(E) an interprocessor buffer (IPB) having
(1) a first public memory for the storage of data, the data including the application code for execution by the first CPU as well as the data used in the execution of this application code accessible to both the first and second CPU's during different phases of the clock cycle,
(2) means, connected to the first bus and to the first public memory, for providing data transfer to and from the first bus and the first public memory,
(3) means, connected to the second bus and to the first public memory, for providing data transfer to and from the second bus and the first public memory, and
(4) a first microprocessor responsive to the phases of the clock cycle for at least control of first public memory access by the first CPU via the first bus and first bus transfer means during the first clock phase and public memory access to the first public memory by the second CPU via the second bus and second bus transfer means during the second clock phase; and
(F) at least one composite intelligent memory and input/output module (MIO), connected to the second bus so as to store and transfer data to and from the second CPU and to and from external devices, the data, in combination with the data in the first public memory, including all application code for execution by the second CPU as well as all data used in the execution of the application code, the MIO comprising:
(1) a second public memory for the storage of data accessible to both the second CPU and the external devices during different phases of the repetitive clock cycle,
(2) a second microprocessor responsive to the phases of the repetitive clock cycle so as to control memory access to the second public memory by the second CPU and the external devices,
(3) a microprocessor bus connecting the second public memory to the microprocessor,
(4) means, responsive to the microprocessor and connected to the microprocessor bus, for interfacing data to and from the external devices with the second public memory, and
(5) means, responsive to the microprocessor and connected between the second public memory and the second bus, for interfacing data to and from the second public memory and second bus;
whereby data transfer to and from the first public memory with the first and second buses occurs during distinct phases of the clock cycle and the transfer to and from the second public memory with external devices and the second bus occurs also during distinct phases of the clock cycle.

18. A method of processing and transferring data between a first location and a second location interconnected thereto by a bus and between the second location and communicating external devices, comprising the steps of:
(1) processing data, including specifying and executing application code at the first location;
(2) generating repetitive clock cycles, each clock cycle having at least first, second, and third distinct clock phases;
(3) reading all data necessary for specifying and executing application code from any of up to N second locations at the first location, where N is a positive integer, by performing the following substeps:
(a) during the third phase of the clock cycles informing any second location of an address within that particular second location where data is to be read by the first location,
(b) during the first phase of the clock cycles transferring data from the selected address location of the second location defined in Step 3a to the bus interconnecting the first location with each second location, and
(c) during the second phase of the clock cycles reading at the first location the data placed on the bus by the selected second location defined in Step 3a during the first phase of the clock cycle,
(4) writing data from the first location with any of up to the N second locations by performing the following substeps:
(a) during the first phase of the clock cycles putting an address on the bus by the first location, the address representing a memory location in one of the second locations where data is to be transferred from the first location,
(b) during the second phase of the clock cycles putting data to be transferred to the selected address location of the second location defined in step 4a on the bus, and
(c) during the third phase of the clock cycles transferring data placed on the bus during the second clock phase into the selected address location of the second location defined in step 4a; and
(5) transferring data to and from the second locations and communicating external devices during at least some of the second clock phases;
whereby the transfer of data to and from the first and second locations is independent of the transfer of data to and from the second locations and external devices.

19. A method of processing and transferring data between a first location and a second location interconnected thereto by a bus and between the second location and communicating external devices as defined in claim 18, further comprising the steps of:
(6) at some of the second locations transferring data to and from communicating external devices via a direct memory access port during at least some of the third phases of the clock cycles.

20. A method of processing and transferring data between a first location and a second location interconnected thereto by a bus and between the second location and communicating external devices as defined in claim 18 or 19, further comprising the steps of:
(7) transferring data to and from the first location and a third location during at least some of the first phases of the clock cycles;
(8) transferring data to and from the third location and a fourth location during at least some of the second phases of the clock cycles; and
(9) processing data at the fourth location;
whereby the transfer of data to and from the first location and the second and fourth locations is independent of the transfer of data to and from the second location and external devices and independent of the processing of data by the fourth location.

21. A method of processing and transferring data between a first location and a second location interconnected thereto by a bus and between the second location and communicating external devices as defined in claim 20 further comprising the steps of:
(10) generating a second repetitive clock cycles synchronized with generation of repetitive clock cycles in step 2;
(11) reading data at the fourth location from any of up to P fifth locations, interconnected to the fourth location by a second bus, where P is a positive integer, by performing the following substeps:
(a) during the third phase of the second clock cycles informing any fifth location of an address within that particular fifth location where data is to be read by the fourth location,
(b) during the first phase of the second clock cycles transferring data from the selected address location of the fifth location defined in step 11a to the second bus interconnecting the fourth location with the fifth location, and
(c) during the second phase of the second clock cycles reading at the fourth location the data placed on the bus by the selected fifth location defined in step 11a during the first phase of these clock cycles;
(12) writing data from the fourth location with any of up to P fifth locations by performing the following substeps:
(a) during the first phase of the second clock cycles putting an address on the second bus from the fourth location, the address representing a memory location in one of the fifth locations where data is to be transferred from the fourth location,
(b) during the second phase of the second clock cycles putting data to be transferred to the selected address location of the fifth location defined in step 11a on the second bus from the fourth location, and
(c) during the third phase of the second clock cycles transferring data placed on the bus during the second clock phase into the selected address location of the fifth location defined in step 12a; and
(13) transferring data to and from the fifth locations and communicating external devices during at least some of the second phases of the second clock cycles;
whereby the transfer of data to and from the fourth and fifth locations is independent of the transfer of data to and from the fifth locations and external devices.

22. A computer as defined in claim 5, wherein the second CPU operates on a repetitive multi-phase clock cycle generated by the clock as transferred to the second CPU by the interprocessor buffer, thereby making the second CPU operating on a slave basis with respect to the multi-phase clock cycle of the first CPU.

23. A computer as defined in claims 2, 5 or 22, wherein each MIO has means for data transferral from the public memory to serial input/output devices.

24. A computer as defined in claims 1 or 2 further comprising up to N additional intelligent memory and input/output modules (MIO's) of the same configuration as the first named intelligent MIO, each additional MIO operating in synchronism to the phases of the multi-phase clock cycle so as to enable the central processing unit to access any public memory of any MIO during one of the phases of the multi-phase clock cycle and thereby to allow the application code for execution by the CPU to be resident within any of the MIO public memories with the microprocessor of each MIO responsible for access control of its respective public memory by the CPU and interconnected external devices.

25. A computer as defined in claims 1 or 2 further comprising up to N additional intelligent memory and input/output modules (MIO's) of the same configuration as the first named intelligent memory and input/output module, each MIO operating in synchronism to the phases of the multi-phase clock cycle so as to enable the central processing unit to access any public memory of any MIO during one of the phases of the multi-phase clock cycle and thereby to allow the application code for execution by the CPU to be resident within any of the MIO public memories with the microprocessor of each MIO responsible for access control of its respective public memory by the CPU and the interconnected external devices, and wherein up to P of the MIO's are communicable between the first named CPU and one of P additional CPU's, the P MIO's acting as interprocessor buffers, wherein for each interprocessor buffer the public memory is accessible by the first and corresponding P additional CPU's during different phases of the multi-phase clock cycle, thereby allowing hierarchical control of one or more CPU's by another CPU, wherein P is a positive integer equal to or less than N+1.

26. A computer as defined in claims 1 or 2, wherein the MIO microprocessor further has means for performing initialization during power-up and processes all interrupt handling of the CPU.

27. A computer comprising:
(A) a central processing unit (CPU) for the processing of data, the CPU having a processor;
(B) means, connected to the CPU for providing a communication path to and from the CPU;
(C) a composite, intelligent memory and input/output module (MIO) connected to the communication path means, so as to store and transfer data to and from the CPU and to and from external devices, the data including all application code for execution by the CPU as well as all data used in the execution of the application code, the MIO comprising:
(1) a public memory for the storage of data accessible to both the CPU and the external devices during different periods of time,
(2) a microprocessor to control public memory access by the CPU and the external devices during the different periods of time,
(3) a microprocessor bus connecting the public memory to the microprocessor,
(4) means, responsive to the microprocessor and connected to the microprocessor bus, for interfacing data to and from the external devices with the public memory, and
(2) means, responsive to the microprocessor and connected between the public memory and communication path means, for interfacing data to and from the public memory and the CPU;
whereby data transfer to and from the public memory of the MIO to the communication path means occurs during different periods of time than the transfer of data to and from the public memory of the MIO with the external devices.

28. The computer defined in claim 27, wherein the processor of the central processing unit (CPU) comprises:
(1) an arithmetic logic unit for performing computations,
(2) a second microprocessor for performing diagnostics, power up and control of the CPU, and
(3) a writable control store, interconnected with the arithmetic logic unit and second microprocessor for storing the microcode necessary to translate user instructions into instructions readable and executable by the arithmetic logic unit under the control of the second microprocessor.

29. A computer as defined in claim 28 further comprising a clock for generating a repetitive multi-phase clock cycle, each phase representing one of the different periods of time that the MIO public memory is accessible to the CPU and external devices, wherein the computer further comprises up to N additional intelligent memory and input/output modules (MIO's) of the same configuration as the first named MIO, each additional MIO operating in synchronism to the phases of the multi-phase clock cycle so as to enable the central processing unit to access any public memory of any MIO during one of the phases of the multi-phase clock cycle and thereby to allow the application code for execution by the CPU to be resident within any of the MIO public memories with the microprocessor of each MIO responsible for access control of its respective public memory by the CPU and interconnected external devices, where N is a positive integer.

30. A computer as defined in claim 29 wherein the second microprocessor of the CPU performs an initialization function including assigning each MIO a unique block number and to uniquely and contiguously define the address space of all the MIO public memories.

31. A computer as defined in claim 29 wherein the communications path means is a bus, and wherein the computer further comprises:
(D) up to P interprocessor buffers (IPB's) connected to the bus, P being a positive integer;
(E) up to P additional buses, each additional bus connected to only one of the IPB's; and
(F) up to P additional CPU's, each connected to only one of the additional buses, and each communicable with the first CPU via the corresponding IPB.

32. A digital computer as defined in claim 31, wherein each interprocessor buffer comprises a public memory and means for operating during the clock phases of the clock cycle so as to give access of the corresponding interprocessor buffer public memory to the first central processing unit during one clock phase and to the interconnected additional central processing unit during another clock phase.

33. A digital computer as defined in claim 32, wherein the accessibility of the public memory in each interprocessor buffer to the first central processing unit occurs during the same time that the first central processing unit has access to the public memories of other interconnected MIO's and IPB's.

34. A computer as defined in claim 33, wherein each of the P additional CPU's through the respective P additional bus has associated with it one or more MIO's or IPB's for the respective transfer of data from the additional CPU to external devices and to further additional CPU's, and wherein the interconnecting IPB's have means for generating a slave clock cycle in response to the first clock cycle so that the multi-phase clock cycle associated with the first named CPU controls the clock cycle of each P additional CPU and the further additional CPU's.

35. A computer as defined in claim 1, wherein the MIO has means for data transferral from the public memory to serial input/output devices.

36. A computer as defined in claims 5 or 22, wherein each microprocessor further has means for performing initialization during power-up.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital computers and specifically to the architecture and methodology used in fabricating digital computers.

2. Description of the Prior Art

Computer architecture since the inception of the digital computer has undergone relatively few basic changes. Most computers comprise a large memory, an arithmetic logic unit (ALU) and an input/output (I/O) section. The computer functions by considering the memory as a single unit. The memory can be any size within the addressing capabilities of the ALU, but it is a single unit in a block diagram point of view. When an external event occurs the input/output module "interrupts" the ALU and forces the ALU to store its state at the time of the interrupt and to subsequently service that interrupt. After ascertaining the "where" and "what" of the interrupt, appropriate sub-routines are called from memory to service the interrupt. The decision must be made and the appropriate memory fetches must be executed. At the conclusion of the interrupt the ALU returns to its previous state and continues on with its internal computation.

A more advanced computer architecture utilizes the same three modules with the I/O still interrupting the memory. Here the ALU further has enhanced capability by means of "stunt boxes" and an onboard cache memory. This onboard cache memory allows the execution of small sub-routines directly on the ALU without having to use the slower bus structure connecting the three basic modules.

The memory in such an advanced computer has several ports, only one of which may be used at a single time. In order for the I/O to communicate with the memory it is necessary that the same bus be utilized that interconnects the memory with the ALU. However, for getting high speed data into memory a direct memory access (DMA) is used. This DMA is executed by interrupting the ALU and subsequently shutting down the basic bus which interconnects the ALU with the memory and the I/O and transferring bus control to the DMA channel and executing the data transfer from a disk or other associated external device. Thus, in this type of prior art advanced computer architecture the DMA I/O ports access the memory using the bus interconnecting the memory with the CPU. The DMA however is able to communicate with the memory without using the CPU. This generally brings about the common misconception that I/O and the CPU run independendly of each other. This however is not the case, for in a conventional DMA scheme transfers to and from memory occur during the execute cycle of the CPU. This works well as long as the total time required by the DMA's I/O is less than the execute time available. When this rate is exceeded either the CPU performance degrades rapidly or the DMA cannot take the I/O. Either occurrence usually has disastrous results.

Furthermore, prior art computer architecture when handling serial I/O devices such as terminals usually requires the interpretation of each character as received and often a response character. In a conventional architecture this is done by interrupting the CPU after each character. The CPU requires many CPU cycles to store away its current state, interpret the character and then to restore its previous state. This limits the number of simultaneous serial I/O channels that can be handled by the CPU. For example, if it takes a CPU one hundred microseconds to handle a character, this limits the system to ten 9,600 baud ports. To handle more ports it is necessary to add external processors to handle the handshaking. This makes the system more complex and expensive.

Thus the basic computer architecture bus is limited and single minded. It can only do one thing at a time and must do it over the memory port bus. In order to make the computer run faster, it is necessary to make the speed of execution of a single instruction faster. The classical architecture is thus analogous to a supersonic jet making more and more trips across the Atlantic as opposed to the "air bus" which is the analogous equivalent to the present invention as disclosed herein.

It has also been found difficult for prior art computer architectures to function as multi-processors. Multiprocessors by virture of the inherent architecture used to data cannot significantly enhance computer capability since, in effect, transfer between shared memories means that one CPU is shut down while the other does a memory access transfer. Common data base is of course important, but the rate of execution of a program is not substantially enhanced using such a multi-processor approach.

In the present invention the solution to the problem of greater computational speed by a digital computer is accomplished by a totally new approach by utilizing a basic change in digital computer architecture. The present invention is a digital computer that uses partitioned memory, which is always available to external events, independent of internal arithmetic logic unit requirements. The central processor or arithmetic logic unit continues to run at a given rate, yet, for most computational requirements is never stopped with respect to external events. To achieve this result the memory and the I/O are combined into a single intelligent module with the memory structure utilizing multi-synchronous ports. The central processing unit (CPU) thus communicates with the composite intelligent memory and input/output module (MIO) during one phase of a three phase clock cycle, while the other two phases of the clock cycle enable the MIO to communicate with external devices. Thus, unlike the prior art computer architecture, the amount of data transferred between the memory and the external devices can never adversely affect the computational abilities of the CPU since access to the memory by the CPU can never be impeded by data transfer to and from external devices.

Furthermore, the present invention, by use of interprocessor modules (IPB), which may be software modified MIO's, allows the addition of any number of additional CPU's with their own associated MIO's and IPB's. The IPB with its associated memory allows two interconnected CPU's to communicate with each other through the use of shared memory. However, since the IPB, like the MIO, utilizes the same three phase timing cycles, interference between communicating CPU's is prevented. A cascade arrangement of CPU's with associated MIO's is achievable by the present invention. Thus a multi-processor digital computer is realizable in a simple and straightforward way.

SUMMARY OF THE INVENTION

A digital computer according to the present invention comprises one or more central processing units (CPU's) communicating by a bus with one to fifteen composite intelligent memory and input/output modules (MIO's) or with from one to fifteen interprocessor modules (IPB's) or a combination of MIO's and IPB's totaling from one to fifteen modules. Each MIO is a combination of memory and I/O channels which provides for high speed input/output to and from memory and external devices without requiring the use of the bus interconnecting the MIO with the CPU. Each CPU, MIO, and IPB is packaged in a separate physical block which is connected to the bus. Up to sixteen blocks can be connected to a single bus, only one of which may be a CPU. Since, as explained below, data is transferable from a public memory portion of each MIO with external devices and the CPU during separate phases of a three phase clock cycle, the CPU can operate in parallel with each of the I/O channels of each MIO connected to the bus without interference with the I/O channels, and vice versa.

Each MIO, according to the preferred embodiment of the present invention, can transfer in or out up to 2.66 megabytes, each byte having eight bits, or 666,000, thirty-two bit words per second. With fifteen MIO's servicing one CPU, the CPU can handle a simultaneous input/output rate of 40 megabytes, a rate comparable with the largest of mainframe computers in existence at the time of this writing. At the same time, the CPU can be performing computations at 100% efficiency.

Each MIO unit has a public memory, an input/output control section, and an onboard microprocessor. The public memory of each MIO range in size from 64K bytes to 256K bytes. The CPU assigns unique address space for each byte in each public memory of each MIO. When fifteen MIO's are interconnected to the bus, a maximum addressable memory of 3.75 megabytes is obtained.

A three phase public memory is used in each MIO. Each memory phase has a duration of 0.5 microseconds and dedicates the public memory of the MIO in turn to the CPU, serial input/output, and direct memory access (DMA) input/output. The CPU accesses the public memory using the bus which has a thirty-two bit wide data path. High speed parallel input/output is performed using known DMA techniques. Low speed serial input/output is performed using the microprocessor in the MIO to transfer the data to and from the public memory and the associated external device or devices.

The microprocessor controls the handshaking between the MIO and its peripheral device or devices, including generating interrupts to the CPU so as to indicate the completion of a desired input/output command. The microprocessor also performs a diagnostic check of the public memory on power initiation (power up) and when instructed to do so by the CPU. It also has a 300 baud diagnostic port which has facilities for de-bugging microprocessor input/output programs resident in private memories within the MIO.

The CPU is built around a series bit slice logic processor. In the present invention, a 64-bit wide processor that is microprogrammable is utilized. Instructions to the CPU cause micro-instructions to be executed from a 4K.times.128-bit writable control store. These micro-instructions are user programmable. The CPU has 16,32-bit general purpose registers and incorporates a microprocessor for hardware diagnostic checking and for loading the microcode into the writable control store. The standard microcode instruction set supports a wide range of logical, fixed and floating point operations.

The bus interconnecting the CPU with the MIO's and IPB's is a three phase clock cycled bus, each clock phase corresponding to one of the MIO public memory access phases. The bus has 32 data/address lines which are used as address lines during one clock phase and as data lines in another clock phase. In addition, there are eight unary select CPU interrupt level lines controlled by the microprocessors in the MIO's. There are also control lines by which the CPU's can interrupt each of the MIO microprocessors. Each phase of the three phase clock cycle utilized by the bus is 0.5 microseconds in duration and is thus synchronized with the three memory phases of the MIO's.

Each interprocessor buffer (IPB) communicates by the bus with the first CPU and by a slave bus with an additional CPU with associated additional MIO's and/or IPB's. The IPB also operates on a three phase clock cycle; the clock cycle communicating with the CPU operating synchronously with other IPB's and MIO's interconnected to the same bus associated with that particular CPU. The IPB also contains pubic memory which may be accessed by either of the interconnected CPU's.

The slave bus interconnects and communicates data from the IPB to the second CPU during one of the other two clock cycles of the three phase clock cycle. In this manner, CPU's with associated MIO's and additional IPB's can be cascaded to the first CPU. A network of resultant CPU's, MIO's and IPB's is thus obtained with all data communication between external devices and this resultant computer taking place through the MIO's so as not to affect the computational speed of the CPU's. The result is addition of memory to one or more central processing units in a manner that does not degrade execution time of the CPU's but which provides for high speed data communication between the computer and external devices by use of the MIO. Multiprocessor capability is synergistically realized by incorporation of interprocessor buffers which provide for communications to and from central processing units as well as MIO's while again not degrading the execution time of each CPU.

A guiding principle of hardware design which is also a global system concept may be expressed in terms of ease of use and reliability, however, these principles can be summarized as no nonsense and the belief that it is possible to deliver solutions to complex problems without making them more complex or creating new problems. It means control of design and manufacturing processes at each level and attention to detail at each level. Another way of stating the philosophical requirements is that to strive for benchmark performance in hardware as many manufacturers do is self defeating because the true power of the computer system is in its architecture, its availability, its parallel I/O, and its software concepts. To push for higher performance or the use of exotic technology in hardware would merely reduce the amount of memory which could be placed on line, make reliable components more difficult to obtain, and make the equipment more difficult to repair. For this reason design is aimed at the very center of current silicon technology rather than at its fringes. Well known techniques of improving maintainability and reliability will, of course, be used, but they will be pursued with exceptional vigor and innovation in this area will be stressed.

At the risk of redundancy, some practical aspects of the hardware philosophy can be stated. First, diversions into conventional thinking are to be avoided in order to take full advantage of our clean slate and architectural power. For example, automatic system start-up, avoidance of "swapping," absolute system partitioning, non-removable disk, editing and prompting by means of color, just to mention a few. Second, the "slower is faster" idea means extremely solid, uncritical timing margins, low component stress, and adherence to established yet modern technologies. Third, on-line performance tests to insure valid operation at the module level are to be incorporated, insuring that each electronic assembly functions properly and correctly regardless of its system environment. The same principles are extended to firmware and system software design as to protection of circuitry from power line transients by means of several levels of isolation. This is merely one aspect of a commitment to build "crash proof" equipment. Such commitment also extends to memory addressing hardware within the CPU. Fourth, is the designing in of adequate "hooks" for manufacturing test and advance planning for manufacturing process control including component and module preconditioning, inspection, traceability, etc.

OBJECTS OF THE INVENTION

It is therefore a principal object of the present invention to provide a digital computer which incorporates at least one central processing unit with one or more composite memory and input/output modules (MIO's) which provide for memory access between the CPU and the MIO during one phase of at least a two phase clock cycle, with the other phase or phases of the clock cycle providing memory access between the MIO and one or more external devices.

An additional object of the present invention is to provide a digital computer of the above description in which a three phase cycle is incorporated in each MIO for memory access from the public memory of the MIO with the CPU during one phase of the three phase clock cycle, with one or more serial input/output channels to external devices during a second phase of the clock cycle, and with a direct memory access parallel channel for high speed data transferral during a third phase of the clock cycle.

Another object of the present invention is to provide a digital computer of the above character in which each MIO further incorporates a microprocessor for controlling the handshaking between the public memory and external devices interconnected to either the serial input/output channels or the data memory access channel as well as to and from the CPU.

A further object of the present invention is to provide a digital computer of the above character in which the microprocessor within the MIO further performs a diagnostic check of the public memory within the MIO during power initiation and also when instructed to do so by the central processing unit.

A still further object of the present invention is to provide a digital computer of the above character further incorporating one or more interprocessor buffers (IPB's) connected to the bus so as to allow communication from the central processing unit to a second bus associated with a second central processing unit, which by the second bus can communicate with one or more MIO's and/or additional IPB's for communication with still further central processing units.

Another object of the present invention is to provide a digital computer of the above description wherein the interprocessor buffer communicates with the first CPU during the same phase of the clock cycle in which the other MIO's or interprocessor buffers connected to the bus communicate with the same CPU and where the interprocessor buffer communicates with the slave bus associated with the second CPU during one of the other phases of the clock cycle in a manner analogous to the operation of the MIO's with interconnected external devices.

A still further object of the present invention is to provide a digital computer of the above character in which the bus interconnected between the CPU and the MIO's or IPB's utilizes a three phase clocked operation for communicating with the MIO's in which two of the phases concern the placing of the address and the desired data on the bus and the third phase concerns the actual reading or writing of the data from or to the public memory of the associated MIO.

A still further object of the present invention is to provide a digital computer of the above description in which the address space for the public memories in each MIO associated with the bus connected to one CPU is uniquely identifiable by the CPU.

Another object of the present invention is to provide a digital computer of the above description in which each MIO, IPB, or CPU is housed in a separate block.

Another object of the present invention is to provide a digital computer of the above description in which two blocks form a portion of a functional support unit which further houses a power supply for driving the electronic circuitry within the two blocks, the functional support unit further housing a portion of the bus which is in turn connected to other functional support units placed below or above itself, thus providing for reliable and easy field installation of the resultant digital computer.

A still further object of the present invention is to provide a digital computer of the above description which can be configured in a multi-CPU arrangement without degrading the computational speed of the individual CPU's forming the multiprocessor system.

A further object of the present invention is to provide a digital computer of the above description in which each CPU, MIO, IPB and power supply associated therewith has a resident microprocessor for, among other things, diagnostics and initiation upon start up.

Another object of the present invention is to provide a digital computer of the above description being relatively inexpensive to manufacture yet having a high reliability.

Other objects of the present invention will in part be obvious and will in part appear hereinafter.

THE DRAWINGS

For a fuller understanding of the nature and objects of the invention, please refer to the following detailed description which makes reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a typical configuration of the digital computer according to the present invention illustrating the use of multiple central processing units, each central processing unit communicating with one or more composite memory, input/output modules (MIO's) and with one or more interprocessor buffers (IPB's) by means of an interconnected bus, also illustrating the power supply modules and interconnection of the MIO's with external devices;

FIG. 2A is a block diagram of the digital computer illustrating the use of one CPU as the hub CPU and four additional CPU's as satellite CPU's;

FIG. 2B is a block diagram of the digital computer according to the present invention illustrating the use of one central processing unit with the maximum number of interconnected MIO's; and further illustrating the communication of the MIO with the external world at a rate of the maximum 2.66 megabytes per second per MIO;

FIG. 3 is a diagrammatic representation of the interconnection of the memory portion of the MIO with either the interconnected CPU via the bus or with a high speed direct memory access input/output channel or with the low speed serial or parallel input/output channels;

FIG. 4 is a block diagram illustrating the interconnection of the MIO with the bus connected to the CPU and additional MIO's and/or IPB's and with both the serial input/output channels and the direct memory access input/output channel;

FIG. 5 is a more detailed block diagram of the MIO illustrating the onboard microprocessor with its associated read-only memory (ROM) and random access memory (RAM) as well as the microprocessor bus and the asynchronous communication interface adapters for communication with serial input/output devices and a parallel interface adapter communicating with a direct memory access control logic module for transferring data to and from parallel input/output devices such as disks;

FIG. 6A illustrates the interconnection of a central processing unit with multiple MIO's illustrating the interconnection of the bus with the public memory during the first phase of a three phase timing cycle;

FIG. 6B is similar to FIG. 6A showing the interconnection of the public memory with the serial input/output channels during the second phase of the three phase clock cycle;

FIG. 6C is similar to FIGS. 6A and 6B illustrating the interconnection of the public memory with the parallel input/output channel during the third phase of the three phase clock cycle;

FIG. 7 is a block diagram illustration of prior art computer architecture showing communication of the direct memory access to and from the memory and input/output utilizing the same data bus interconnecting the CPU with the memory;

FIG. 8 is another block diagram illustrating prior art computer architecture illustrating the operation of such architecture for serial input/output;

FIG. 9 is a diagrammatic representation of a read cycle as performed by the bus interconnecting the CPU with the MIO's and IPB's;

FIG. 10 is a diagrammatic representation of the write cycle for the bus similar to the read cycle shown in FIG. 9;

FIG. 11 is a block diagram of the MIO when operating as both a parallel input/output and as a serial input/output;

FIG. 12 is a block diagram similar to FIG. 11 illustrating the use of the MIO for only serial input/output purposes;

FIG. 13 is a block diagram of the MIO similar to FIGS. 11 and 12 illustrating its use for communicating with two disks;

FIG. 13A is a detailed block diagram of the central processing unit of the present invention;

FIG. 14 is a perspective view of a functional support unit of the present invention housing two blocks, each block housing either a CPU, MIO or IPB and the associated power supply and bus forming the rest of the functional unit, as well as the pedestal upon which the functional support unit rests which in turn houses the constant voltage transformers and rectifiers for producing raw DC voltage;

FIG. 15 is a perspective view of the digital computer similar to that shown in FIG. 14, also illustrating a disk module placed atop the pedestal for communication with the blocks of the functional support unit;

FIG. 16 is an exploded perspective view of the functional support unit shown in FIGS. 14 and 15;

FIG. 17 is a perspective view of a color cathode ray tube (CRT) terminal for user interaction with the computer according to the present invention;

FIG. 18 is a perspective view of a line printer that may be used as an external device with the computer of the present invention;

FIG. 19 is a flow block diagram illustrating the execution of instructions within the computer of the present invention;

FIG. 20 is a diagrammatic block diagram showing the input/output programming utilized by the computer of the present invention;

FIG. 21 is a diagrammatic block diagram illustrating the input/output command blocks used with the retrieval and transferral of data to and from external devices;

FIG. 22 is a block diagram of the types of interrupts associated with the computer of the present invention;

FIG. 23 is a schematic diagram of a terminating network for the bus used to interconnect the CPU with the MIO's and IPB's;

FIGS. 24A and 24B illustrate a comparison of thresholds and show typical cable waveforms of the bus used to interconnect the CPU with the MIO's and IPB's;

FIG. 25 is a set of waveforms illustrating the clock pulse sent and received by the computer;

FIG. 26 is a group of waveforms illustrating the clock and skew characteristics of the computer;

FIG. 27 is a hardware block diagram of a multiprocessor configuration of a digital computer according to the present invention illustrating the use of multiple CPU's, MIO's and a single IPB, and is similar in format to FIG. 1;

FIG. 28 illustrates the bus-memory access function's timing diagram during each phase of the three phase clock cycle;

FIG. 29 is a block diagram of the bus interrupt poll mechanism;

FIG. 30 is a series of waveforms illustrating the basic cycle timing of a computer according to the present invention;

FIG. 31 is a series of waveforms illustrating the read cycle timing for block data to the CPU;

FIG. 32 is a series of waveforms illustrating the write cycle timing from the central processing unit to the MIO;

FIG. 33 is a series of waveforms illustrating the transfer cycle timing from one block to another block;

FIG. 34 is a series of waveforms illustrating the interrupt request, interrupt poll and interrupt acknowledge timing relationships;

FIG. 35 is a simplified block diagram of the central processing unit;

FIG. 36 is a block diagram illustrating the partitioning and diagnostic aspects of the central processing unit;

FIG. 37 is a block diagram illustrating additional details of the partitioning and diagnostics aspects of the central processing unit;

FIG. 38 illustrates a more detailed block diagram of the central processing unit;

FIG. 39 is a series of waveforms illustrating the timing relationship of the central processing unit with the bus and SYNC pulse;

FIG. 40 is a diagrammatic representation of the microcode word;

FIG. 41 illustrates the logic used to count, control and perform fast microcode loops;

FIG. 42 is a schematic block diagram illustrating how the 8-bit IR bus is driven from the IR register, the decode register, the pointer register, or directly from the right-most byte of the DBUS;

FIG. 43 illustrates the virtual address and map formats used in the digital computer;

FIG. 44 is a block diagram of the memory mapping hardware;

FIG. 45 is a block diagram illustrating the 64 bit authorization vector specifying whether a fault should occur for each type of cycle requested as a function of the block domain and its data type;

FIG. 46 is a block diagram of the MIO board;

FIG. 47 is a more detailed block diagram of the MIO board;

FIG. 48 is a block diagram of the memory board;

FIG. 49 illustrates general timing diagrams for the MIO microcomputer board;

FIG. 50 illustrates timing diagrams of a 256 kilobyte memory board;

FIG. 51 is a block diagram illustrating a large multiprocessor configuration computer according to the present invention and is similar in format to FIGS. 1 and 27;

FIG. 52 is a diagrammatic representation of the display format for a total access port;

FIG. 53 is a diagrammatic representation of the keyboard used in the total access port;

FIG. 54 is a diagrammatic representation of a preferred 9600 baud MIO channel driving a color CRT for the total access port;

FIG. 55 is a simplified block diagram of an overview of the power supply system to power the computer;

FIG. 56 is a block diagram of the power supply system;

FIG. 57 is a schematic diagram of a portion of the power supply system illustrating the provision for controlling system ground loops;

FIG. 58 is a diagrammatic representation of the major states of the functional support unit;

FIG. 59 is a schematic diagram illustrating system power control of the slave buses;

FIG. 60 shows a series of waveforms illustrating the behavior of the system on power-up, during a power dip, and on an unpowered shutdown;

FIG. 61 is a diagrammatic representation showing the typical screen format on the CRT;

FIG. 62 is a block diagram illustrating the power budget for a minimally configured digital computer according to the present invention;

FIG. 63 is a diagrammatic representation of the modular packaging philosophy for the digital computer according to the present invention; and

FIGS. 64A-64C are perspective views of different size configurations of the computer according to the present invention, FIG. 64A showing a large system comprising three lower pedestal portions, four disk drive modules, and nine functional support units, FIG. 64B showing a smaller system comprising a lower pedestal portion, two disk drive modules and two functional support units, and FIG. 64C showing a small system comprising a lower pedestal portion, a single disk drive module and three functional support units.

DETAILED DESCRIPTION

General Characteristics

As best seen in FIG. 1, a digital computer 20 according to the present invention comprises one or more central processing units 22 (CPU's), one or more composite memory and input/output modules (MIO's) 24, one or more interprocessor buffers (IPB's) 32, a bus 26 for interconnecting the MIO's and IPB's to the CPU, and one or more power supply modules 59 for providing the necessary DC power to drive each CPU, MIO, or IPB. Each MIO communicates with one or more external devices 31 by either a parallel direct memory access (DMA) port 28, or one or more serial input/output channels 30. As indicated by the phantom extension of bus 26, a total of fifteen MIO's or IPB's (or combination thereof) can interconnect with bus 26 along with CPU 22. Thus sixteen modules (CPU, MIO or IPB) can be connected to the bus at any one time. Although it would be possible to have the bus interconnect with more modules, the preferred embodiment of the present invention has kept the bus length to no more than ten to twenty feet due to the propagation delays of signal travel as dictated by the speed of light.

As shown in FIG. 1 a multiprocessor, that is a multi-CPU configuration, can be obtained by use of one or more interprocessor modules 32 (IPB's) which communicates with bus 26 associated with the first CPU at one end and with a slave bus 26', otherwise identical to bus 26, at its other end. The slave bus is interconnected with a second CPU 22'. The slave bus 26' may also have from one to fifteen MIO's or IPB's interconnected to it. For example, as shown in FIG. 1, slave bus 26' has one MIO
24' and one IPB 32' associated with it. In turn IPB 32' connects to a second slave bus 26" interconnected with a third CPU 22" and one or more MIO's or IPB's. Such a cascading of CPU's can continue indefinitely in the digital computer of the present invention.

As also shown in FIG. 1 bus 26 can interconnect with a second IPB 32" which in turn connects to a fourth CPU 22'" and one or more MIO's and IPB's. This arrangement of additional CPU's is thus configured in a "string" or "star" configuration with the first CPU 22 acting as the hub and the additional CPU's (such as CPU 22'") acting as satellites. FIG. 2A illustrates one CPU 22 associated with four satellite CPU's 22', 22", 22''', 22'''' by means of four IPB's, 32, 32', 32", 32'''. One or more MIO's or IPB's in turn interconnect with the satellite CPU's. As shown in FIG. 2B a configuration of one CPU 22 communicating with fifteen MIO's is possible in the preferred embodiment of the present invention. As also shown in FIG. 2B each high speed parallel DMA channel can transfer data into and out of the public memory within the MIO at a rate of 2.66 megabytes per second. In addition the public memory associated with each MIO has a unique and continuous address with respect to the CPU in order to make the data within each MIO uniquely available to the CPU. Besides the high speed DMA channel shown in FIG. 2B for each MIO, one or more serial input/output channels 30 are also associated with the MIO for interconnection with external devices. With the parallel high speed DMA channels of each MIO associated with the CPU on the bus, extremely high speed input/output to and from memory can take place without requiring the use of bus 26. This is one of the powerful features of the present invention's architecture since it enables the resultant computer to have high data rate communication with the external world without degrading the execution time of the central processing unit. As a result, maximum throughput is obtained.

Digital computer 20 is able to obtain this result by utilization of a three phase cycle for each MIO and IPB. Each memory phase has a duration of 0.5 microseconds and is dedicated in turn to the central processing unit 22 interconnected on bus
26, the serial input/output channels 30, and the direct memory access (DMA) input/output channel 28. FIG. 3 shows in diagrammatic form the transferral of information to and from public memory 33 associated with the MIO to the CPU, serial input/output, and a DMA input/output during the three phase clock cycle associated with the MIO. Thus, for one complete clock cycle, that is every 1.5 microseconds, the MIO makes its public memory available for reading and writing to the CPU, the serial input/output, and the DMA input/output.

As shown in FIGS. 4 and 5, the MIO incorporates a public memory 33, a bus interface 34 connected to bus 26, a microprocessor 36 associated with the low speed serial channel interface 35 connected to serial input/output channels 30, as well as connected to a diagnostic channel 37, and a direct memory access (DMA) interface 38 interconnected to the direct memory access channel 28.

The low speed serial input/output is performed using microprocessor 36 in the MIO. In the preferred embodiment of the present invention this microprocessor is a type 6800 Motorola microprocessor with associated integrated circuit chips.

As shown in FIG. 5, the microprocessor 36 has a bus 43 and an associated private memory 39 comprising read only memory 40 (ROM) and random access memory 41 (RAM). The ROM contains the programs that control the microprocessor in performing memory diagnostics and refresh as well as input/output control. The microprocessor 36 thus controls the handshaking between the MIO and its peripheral devices, including generating interrupts to the central processing unit 22. The microprocessor in addition performs a diagnostic check of the memory during power up and when instructed to do so by the CPU. It also has a three hundred baud diagnostic port 37 associated with a peripheral chip 51. This port has facilities for debugging microprocessor input/output programs.

As shown in FIG. 5 asynchronous communication interface adapters (ACIA's) 42 are used for the serial I/O channels 30 through communication with microprocessor bus 43. This utilizes standard state of the art techniques. Characters coming in on a serial I/O port 30 are processed by the microprocessor before being placed in main public memory 33. The asynchronous communication interface adapters permit asynchronous ASCII transmission at up to 9600 baud. Hence a character at a time, blocked record at a time, and records terminated with a carriage return signal or other delimiter can be handled without CPU intervention.

Parallel input/output is entered directly into memory using direct memory access control logic techniques. Setting up transfer counts and addresses and performing handshaking is controlled by the microprocessor through a parallel interface adapter 44 in conjunction with a direct memory access control logic module 45. A direct memory access bus 46 having a 32-bit width interconnects the DMA control logic module 45 with public memory 33 for rapid data transfer. The direct memory access parallel input/output channel 28 is thus a 32-bit wide channel and has an input/output rate of 2.66 megabytes per second, each byte representing eight bits of data. Microprocessor 36 in the MIO block illustrates the use of state of the art microprocessors to interface a large data based machine by means of available semiconductor integrated circuit chips. Such microprocessors are similarly used in each CPU, IPB and power supply module to achieve this end result.

FIGS. 6A, 6B, and 6C illustrate in diagrammatic form the three phase operation of the MIO. Thus during phase one the CPU 22 has access by bus 26 with the public memory in each interconnected MIO 24. During phase two of the clock cycle the low speed serial input/output channel 30 has access to the public memory within each MIO, while in the third phase of the clock cycle the parallel input/output channel 28 has access to and from the public memory within the MIO. Thus it is readily apparent that the amount of utilization of either the serial input/output 30 or the parallel input/output 28 will not degrade the CPU's utilization of the public memory in each of the associated MIO's. This is a marked departure from the conventional architecture as shown in FIG. 7 where the DMA input/output ports access memory using the bus which interconnects the memory with the CPU. In some of the more advanced architectures or digital computers the input/output access to the memory can be done directly without using the CPU. However, this does not mean that the input/output and the CPU run independent of each other. Thus, in a conventional DMA scheme transfers to and from the memory occur during the execute cycle of the CPU. This works well as long as the total time required by the DMA input/outputs is less than the execute time available. When the input/output rate is exceeded, either the CPU performance degrades rapidly or the DMA input/output cannot take the input/output data, which usually has disastrous results.

In the present invention each MIO can support a 2.66 megabyte transfer rate into the public memory of the MIO, independent of bus 26 and CPU 22. As memory accesses by the CPU are phased with the input/output into one MIO clock cycle, the CPU can be doing computations out of the same memory into which are running a 2.66 megabyte direct memory access transfer without any CPU slowdown.

Likewise, when handling serial input/output devices such as interactive terminals, they usually require the interpretation of each character as received and often a response character. As shown in FIG. 8, in a conventional architecture, this is done by interrupting the central processing unit after each character. This CPU requires many CPU cycles to store away its current state, interpret the characters and then restore it to its previous state. This limits the number of simultaneous serial input/output channels that can be handled by the central processing unit. For example, if it takes the central processing unit 100 microseconds to handle a character, this limits the system to ten 9,600 baud ports. To handle more ports, it is necessary to add external processors to handle the handshaking. This makes the system more complex and obviously more expensive.

In the present invention, these "external" processors are built into the MIO, and these function within the operating system's software associated with the computer 20. As a result, the computer 20 can handle up to 60 ports, each running at up to 9,600 baud, on a single central processing unit simultaneously with full CPU computations. In this configuration, there would be 15 MIO's as shown in FIG. 2B, each MIO with four serial input/output channels. This configuration is discussed more fully later in this description.

Just as each MIO utilizes a three-phase clocking system for utilization of its public memory with the associated CPU, its serial input/output, and its parallel input/output, so the bus 26 is also a three-phase bus. Each phase of the three-phase clock cycle has a 0.5 microsecond duration synchronized with the phases of the MIO. This 500 nanosecond time slot is sufficient for the bus to communicate over its entire length between any of the modules communicating thereon. In the present computer the bus has 32 data/address lines, these lines being used as address lines in one phase of the three-phase clock cycle and as data lines in another phase of the clock cycle. There are also 8 unary select CPU interrupt level lines controlled by the microprocessors within the associated MIO's. There are also control lines by which the central processing unit can interrupt each of the MIO microprocessors.

As shown in FIG. 9, the bus reads information from an MIO by the central processor, during phase 1, putting the address on the bus associated with the data that it desires to read. This data as well as all other data communicated on bus 26 is stored in buffers within each MIO bus interface 34. However, since the address space for the data in all the MIO's has a unique addressable location, the fact that MIO's other than the one with the desired address read the desired address as placed on the bus by the CPU is immaterial to the proper operation of the system.

In phase 2 the MIO with the appropriate address transfers data from the public memory to the bus interface, making the data available to the bus. This phase 2 read cycle thus corresponds to the phase 1 cycle for the MIO in which the public memory of the MIO is communicable to the data bus. During phase 3 of the bus cycle, the CPU actually reads the data placed on the bus by the MIO. Alternatively the CPU can, by entering into a write cycle, cause the data placed on the bus during phase 2
to be stored in a desired public memory location of another MIO. This provides for rapid data transfer between MIO's. This result is accomplished since all the MIO's "listen" when the CPU or other MIO puts data on the bus. This listening does not adversely affect their own three phase data clocking cycle.

A pictorial representation of a write cycle is shown in FIG. 10. In this case phase 1 of the bus has the central processing unit putting the address on the bus for the location in a particular MIO where data is to be deposited. During phase 2
of the bus cycle, the central processing unit puts the data on the bus for storage in the interfaces of the MIO's while during phase 3 the MIO with the correct address space transfers this data from its bus interface to its public memory 33. Thus, the third phase of the write cycle corresponds with the first phase of the MIO cycle in which the MIO allows access to and from the public memory with the bus.

As explained earlier, the MIO can transfer one 32 bit word into or out of the public memory along its DMA input/output channel once every 1.5 microseconds. This is equivalent to a transfer rate of 2.66 megabytes per second per MIO. The pictorial representation of such a parallel operation of the MIO is shown in FIG. 11. The parallel transfer of data once initiated is directed into public memory 33 from the parallel channel 28 without requiring the use of the microprocessor 36
associated with the MIO module 24. It also is independent of bus 26 or the CPU. However, initial set up of the data transfer is under the control of microprocessor 36 through the PIA (see FIG. 5).

Transfer is initiated by means of the microprocessor 36 which is given the memory address and data count for the transfer. At the completion of the transfer, the microprocessor interrupts the central processing unit or continues with additional data transfers until commanded to interrupt the central processing unit. This interrupting of the central processing units is performed on one of the eight interrupt lines associated with bus 26.

Hardware handshaking is accomplished by means of a ready/done control line 47 on both input and output. The parallel MIO is also equipped with two serial ASCII channels 30 to allow terminals to be connected to the MIO when operating in this configuration. It should be noted that the architecture employed for the MIO does not limit the phase 2 cycle of the memory to two serial input/output channels but indeed is unlimited in its architectural sense. It is just the size of the printed circuit board upon which the MIO is fabricated which limits the serial channel to two channels when utilizing the direct memory access parallel channel.

FIG. 12 illustrates the use of an MIO for only serial input/output. In this configuration up to four serial ASCII channels can have access simultaneously with the public memory 33. Each serial ASCII channel has selectable speeds up to 9,600
baud. Serial channel interfacing is by means of four wires and obeys full duplex RS 232 protocol, this protocol being known in the art. Transfers can be by a character at a time, fixed length records at a time, or variable length records with terminator characters. All characters are under control of the microprocessor 36 associated with the MIO.

FIG. 13 illustrates the use of an MIO to control up to two disks 48 and 49 on separate parallel channels associated with direct memory access interface 38. These disks can be considered external devices 31 as shown in FIG. 1. The disks typically have a simultaneous transfer rate of 1.2 megabytes per second on each channel 28. The channels are totally independent enabling reads and writes to take place simultaneously on both disks. The microprocessor 36 in conjunction with the hardware controller of the direct memory access interface handles all of the handshaking with the disks, including error detection and correction.

Neither the central processing unit nor the bus 26 is used in the data transfer, thus completely eliminating one of the major causes of system slowdowns in classical computer architectures. Multiple disk MIO's can be connected to a single bus, each of which runs independently of the other MIO's in the interconnected CPU area.

FIG. 13A is a more detailed block diagram of a central processing unit 22. The central processing unit is built around series bit slice logic and in the preferred embodiment of the present invention uses the 2901 bit slice logic series of components built by both Motorola and Advanced Micro Devices of 901 Thompson Place, Sunnyvale, Calif. 94086. This series of devices is a variable width processor which is controlled by a writable control store 52. In essence the bit slice processor is a series of four-bit chips that are put side by side to make up a 64-bit word which is utilized in the central processing unit 22. For arithmetic operations there are also carry forward and borrow bits that can shuffle to the right or the left of this
64-bit word.

Instructions to the central processing unit cause micro-instructions to be executed from the writable control store. In the preferred embodiment of the present invention this writable control store has a 4,000.times.128 bit memory. The micro-instructions are user programmable in order to allow flexibility to the user. The central processing unit has sixteen 32-bit general purpose registers 52.

As was noted earlier, the memory associated with each MIO 24 is 32 bits wide. That means that 32 bits of information can be moved into or out of the memory every 500 nanoseconds. However, as explained earlier, the public memory of the MIO is only associated with the CPU during one of three phases of the 1.5 microsecond clock cycle. Therefore, the central processing unit only sees one-third of that nanosecond rate which corresponds to 32 bits every 1.5 microseconds. In this way, the computer takes advantage of the memory at the highest rate that it can function without degrading its performance but also provides for relatively reliable bus operation by not requiring the bus 26 to operate with full data transfers every 500
nanoseconds. The 2900 series bit slice logic used in the central processing unit 22 operates in the 50 to 125 nanosecond time frame as can the writable control store. By means of this architecture, all of the selected components can be used to their fullest advantage. That is, current state of the art memory access times have a high reliability in the 500 nanosecond range as used in the public memory and writable control store, while the bus 26 when used to service up to 15 MIO's and an associated CPU, by having a length of approximately 10 feet, has a reliable speed in the 1.5 microsecond range. Thus, the bus runs at a speed that is convenient to it while the memory at the MIO runs in a speed that is convenient to it while the bit slice chips in the CPU operate at a speed that is compatible with the other circuit components. Thus, there are no artificial bottlenecks within the computer architecture of the present invention. That is, the present invention is a computer architecture which utilizes the maximum number of process bits through a given configuration.

Referring again to FIG. 13A, the central processing unit further incorporates a microprocessor 54 whose function is for hardware diagnostics and for loading the microcode into the writable control store when specified by the user and during power start up. Thus, the microprocessor 54 is not involved with the actual computation performed by the central processing unit. A standard microcode set can be utilized within the writable control store to support a wide range of logical fixed and floating point operations. The writable control store 52 is used to generate instructions in a virtual manner to operate with software that is used in conventional machines. Thus the 64-bit wide bit slice processor 50 is really limited in doing three things--moving bit to the left and right, adding in a binary fashion, or selecting registers. An instruction such as "multiply" is thus out of the scope of direct performance by the bit slice processor. But a multiply is really a sequence of add and shifts, and thus a subroutine that selects the appropriate register "adds" and "shifts" is located in the writable control store. When regular software specifies a "multiply" instruction, a pointer goes to the appropriate subroutine in the writable control store which then instructs the bit slice processor how to perform the requested instruction. It is thus the writable control store that stores the microcode for performing the user designated instructions.

The use of a 64-bit wide word in the central processing unit allows the computer to do high precision arithmetic with double word accuracy. Thus two consecutive 32-bit words are put side by side within the accumulator of the bit slice processor when an arithmetic operation is to be performed from such data. For instance, if a multiplication of two 32-bit words is performed, the result ends up as a 64-bit word and it is thus much easier to use a 64-bit accumulator than a 32-bit accumulator.

A basic set of microcodes stored in the writable control store can represent the assembler level language which the user normally uses to write his application programs. However, the capability does exist for the user to write his own microcode for specialized applications.

Sixteen 32-bit registers 89 for general use are also with CPU 22. Finally, a clock 56 which communiates with bus 26 generates the three-phase clock cycle, each phase having a 0.5 microsecond duration. Referring to FIG. 1, it should be noted that the first central processing unit 22 is solely utilized for the clock function. When other central processing units are coupled to the first central processing unit by an interprocessor buffer (IPB), the third clock phase of the first central processing unit is used for communication between the IPB and the second central processing unit, such as CPU 22'. Thus the third phase clock cycle of the first central processing unit is interpreted as the first clock cycle of the additional central processing unit. Thus, the slave bus 26' is truly a slave and is not activated by clock cycles from the second CPU but only from clock cycles of the first CPU. The circuitry resident within the additional central processing unit synchronizes its clock and allows tolerance for deskewing.

FIGS. 14, 15 and 16 illustrate the packaging of computer 20. The lower pedestal portion 58 houses constant voltage transformers and rectifiers necessary for generating the raw DC power for energizing the power supplies modules 59 which are used in turn to power the central processing units 22, MIO's 24 and IPB's 32. (See FIG. 1) The MIO's, IPB's, CPU's are individually housed in blocks 60 which combine with the power supply 59 and bus module 61 to form what is called a functional support unit
62. The functional support unit is thus a housing and power supply for two blocks, each block being either a CPU, MIO, or IPB. These blocks are field installable modules. The power supply 59 provides the smoothed DC power to drive each block 60. The power supply 59 includes a CRT 64 and four control switches 65, which are under the control of a microprocessor resident within the power supply. The CRT is used to display in plain English the hardware status of the blocks 60 as well as the power supply 59. The switches are used for hardware control of the blocks 60. As is evident in FIG. 15 the functional support units can be stacked on top of each other. In addition, since the MIO'DMA input/output can be associated with a disk, a disk drive module 66 can be placed atop pedestal 58, in essence taking the place of one of the functional support units.

FIG. 16 illustrates in more detail the functional support unit internal configuration. As seen therein, the input/output channels from the blocks 60 emanate from the rear portion of the blocks 60. These blocks have an approximate relay rack width and the two may slide in and out of the functional support unit 62.

The disks within the disk drive module 66 are of the Winchester-type and have moving heads. For high reliability these disk drives have a non-removable field storage medium. Since the heads are integral with the sealed storage medium, no head alignment is required as in other types of disk drive modules. The data transfer rate is 1.2 megabytes per second, thereby allowing each MIO to potentially service two disk drive modules. The spindle speed of these modules is 3,600 revolutions per minute, while the access time is 10 milliseconds to 60 milliseconds with a latency of 8.3 milliseconds average.

As best seen in FIG. 17 a CRT terminal 68 is the basic unit by which the user communicates with the computer. This terminal is thus another one of the external devices 31, shown in FIG. 1, that can be interconnected with one of the MIO input/output channels. The terminal incorporates a color CRT screen 69 which makes possible a more sophisticated user interface to the computer system. It also has a full upper and lower ASCII keyboard 70, as well as a 3M cartridge tape receptacle 71
for use in program loading and storage. The terminal can be connected to any of the serial ASCII ports 30 associated with the MIO's and communicates with the MIO's at 9,600 baud. Alternatively, the terminal could operate from one of the DMA input/output ports 28 for providing full page real time display of data within a particular MIO. In this configuration the user, with appropriate controls, can actually "flip" through "pages" of data stored in the MIO's in a manner analogous to flipping through the pages of a book. This function, which is user controllable from the CRT terminal 68, can provide a means to easily access information within storage where a particular address is unknown to the user.

FIG. 18 illustrates a line printer 72 that can be interconnected as an external device 31 to one of the serial input/output ports 30 associated with an MIO 24. The line printer in the preferred embodiment of the present invention is manufactured by Printronix of 17421 Derian Ave., Irvine, Calif. 92714. It has a print capability of up to three hundred lines per minute. It is a matrix printer and can print a full upper and lower case ASCII set.

Printing can be up to one hundred and thirty-two columns wide on up to six part paper. This printer also has full graphic capability, enabling it to plot graphs and drawings with up to one thousand points per line.

FIG. 19 illustrates the types of instructions that are utilized by the computer 20. The central processing unit 22 executes thirty-two bit macro instructions 73 that it receives from one of the public memories 33 associated with any MIO 24. These macro instructions are of the familiar operation code, source, destination and modifier format. The central processing unit executes an instruction by a series of micro instructions 74 which control the 2900 series bit slice processor 50
associated with the CPU. The macro instruction addressing modes include immediate, register, direct, indirect, indexed, and stack. The data modes include bit, byte, halfword, word, doubleword, floating point, double precision floating point, decimal, and packing decimal. The instructions of course can vary for the particular application to which the computer is assigned. The instructions shown in FIG. 19 are specific to an application utilizing the 2900 series bit slice processor and specifically with a language associated and particularly formated for the disclosed computer, having a pseudonym "FASL". As shown in FIG. 19 the execution of the instruction first requires a fetch from the public memory 33 for the macro instruction, the macro instruction pointing to a particular micro instruction nest of code which configures the 2900 series processor into a special configuration, by means of the writable control store 52. The result may be stored in temporary thirty-two bit registers 89 for later use. This procedure in instruction fetching and solving is well described in 2900 series bit slice processor literature.

SUBSECTION DETAILS

BUS DESCRIPTION

One important characteristic of the bus is that it is synchronous as are all system activities, using the bus as a sync reference. Although this does not make for maximum burst transfer rate, it insures predictability and total transparency of DMA and microprocessor activity. This is much more important in terms of overall philosophy. Moreover, the 1.5 microsecond bus transition time permits multiplexing of address and data on the bus signal lines making possible interconnection of blocks in a clean and straightforward manner. Within the CPU, microcode cycles are also synchronized to the 500 nanosecond clock so that resychronization overhead is not required and all system activities proceed without random phase relationships.

BUS--INTRODUCTION

This specification defines the main bus of the digital computer 20. The bus is a moderate-speed, parallel interface between blocks 60 which provides for bidirectional data transfer, initialization, system configuration, and all communication between blocks.

The bus connection is made with 3M-style flat cables and connectors. All signals are in parallel to all blocks and all slots on the bus are identical.

Timing on the bus occurs in three-phase cycles, referenced to a master clock. Each cycle permits a memory access by the bus. One phase is dedicated to local microprocessor access and refresh of the large RAM 41 in each block. The second phase is used for bus access to the RAM, and the third phase is used for DMA data transfer in those blocks that require high-speed transfer.

All bus operations are on full 32-bit words. The CPU 22 may modify a byte if it rewrites the other three bytes at the same time.

BUS--MECHANICAL (see FIG. 1, bus 26)

The bus is carried on three 50-conductor 3M-style flat cables, each cable provides 22 signal wires, 4 +5 v wires, and 24 grounds.

A cable assembly consists solely of cable and female connectors. Assuming each block has bus connectors only on its lower board, two more connectors are needed than blocks in the system. A terminator plugs into the remaining connector at each end.

All terminators are identical. Each contains 44 resistors, 3 capacitors, and a 3M male connector. This should nestle in an appropriate slot in the side of the top and bottom blocks on the bus.

It is expected that cable length will not exceed 20 ft. in this system, more likely 10 ft. for a single cabinet system. The three bus connectors occupy the frontmost three positions of the six available at the edge of the lower board in each block. IPB blocks use the rear three positions.

All connectors have similar pin assignments so that identical terminators can be used. Furthermore, any cable or terminator can be plugged in upside down and will still work properly.

Every signal is shielded between two grounds. The CPU board supplies +5 v on pins 24 thru 27 for the terminators (max. 1.32 amp per cable.)

BUS--ELECTRICAL

Bus logic levels are open collector "party line" TTL. Receivers with hysteresis or high threshold are used to provide noise immunity. With the exception of special power sequencing control lines, all signals are active-low, open collector.

Each bus line is terminated at both ends with a 120 equivalent resistor divider which establishes a +3 v minimum high level when the line is open. Drivers must be able to sink minimum 60 mA at maximum 0.8 V. Receiver thresholds, must guarantee 1
volt minimum noise immunity at high and low levels.

A recommended terminating network is shown in FIG. 23.

Recommended alternate transceivers are AM26S10, AM26S11 (second sourced by TI) and AM2905-7 (second sourced by Motorola). These devices all are capable of sinking 100 ma @ 0.8 V and thus are acceptable drivers for any line. All are quads.

In the present design, the AM26S10 transceiver is used throughout.

FIGS. 24A and 24B give a comparison of thresholds and show typical cable waveforms.

CLOCK

The clock 56 is well isolated from other bus and system signals to minimize noise and distortion of rising and falling edges since either edge may be used by a block for timing. The falling edge is the primary timing event. Pulse-to-pulse jitter observed at the receiver output within a block should not exceed .+-.10 ns with respect to this edge of .+-.20 ns at the rising edge. Asymmetry of the clock waveform as observed at the receiver output within a block should not exceed .+-.10 nsec from the nominal midpoint of each clock interval. FIG. 25 illustrates this clock waveform.

SYSTEM TIMING

CLOCK AND SKEW (See FIGS. 13A and 26)

All system timing is derived from a single phase clock 56 at 4.00 MHz, 50% duty cycle. This is generated with an 8.00 MHz crystal oscillator and a flipflop on the CPU board, and is driven on the bus 26 with a standard open-collector driver.

The clock is received with standard receivers having hysteresis. This, plus the delay along the length of the bus, implies that a block's conception of where the clock edge occurs may differ up to .+-.50 ns from the CPU's conception of the same clock edge. Since only one receiver per block may actually be on the bus, the block must use the output of this receiver as its reference.

Worst-case occurs with CPU and addressed block at opposite ends of the cable. Both CPU and block use the same receiver type from different manufacturers, which may have widely differing propagation delays, but this is the closest that the two clocks can come to simultaneity in practice. Using the signal that drives the clock in the CPU is unsuitable, because in multiprocessor configurations, the IPB pulls down a bus line called SLAVE, which disables the clock and sync drivers in the CPU. On the slave bus (e.g., 26' in FIG. 1), the clock and sync are driven by the IPB. Besides, the extra skew introduced by the driver chip would be unwelcome.

Expecting a propagation delay of 2 ns/ft. max., a 10 ft. bus would cause 20 ns difference between the same reference falling edge at opposite ends of the bus; a 25 ft. bus would cause 50 ns difference.

Using 26S10, max. propagation delay is 30 ns; typical is 18-20 ns; minimum unspecified, conservative estimate 5 ns, allowing a total of 25 ns skew due to differences between chips. The total skew if the CPU has a fast receiver and the block has a slow one, is +75 ns later than the CPU sees the clock edge. Any further buffering of the clock on either board adds to the problem.

Allowing the data to remain for one more edge (either polarity) allows a minimum 100 ns of deskewing, which should handle worst case for both edges. The worst case negative skew would be a fast receiver IPB driving a slow receiver CPU at the opposite end of the bus. The CPU would lag 75 ns, so 25 ns deskewing is assured when opposite clock edges are used.

To insure consistency of bus timing, all units drive the bus clock on the falling edge (as observed on the bus itself). All units receiving signals from the bus clock on the previous rising edge. The signal called SYNC is a special case. This signal changes at the rising edge of clock.

SYSTEM OVERVIEW

FIGS. 1 and 27 present an overview of the digital computer 20. A basic system consists of a bus, a CPU, and one of more MIO units. A maximum of sixteen blocks (comprising MIO's, IPB's or disks) may be attached to a bus. Multiprocessor configurations are achieved by use of the IPB.

As seen in FIG. 16, blocks 60 are mounted in functional support units 62 (FSU). An FSU contains a maximum of two blocks and its own power supply. FSU's stack together on a pedestal. Blocks are connected via the bus. Certain bus signals are also available to the FSU.

A unique feature of the digital computer is that each block in the system, including the power supply, is microprocessor controlled. A Motorola 6800 provides several functions on each block including: Module initialization, diagnostic capability, I/O handling, and DMA control. The exact functions of each 6800 on each module will be discussed with the module.

HARDWARE SELECTION

An important feature of the digital computer system is its extensive use of dynamic NMOS RAMS. These are, at present, the highest density form of this well established memory technology. The CPU uses 4K rams as its microcode store and MIO's use the 16K ram as the primary "core" of the system. These devices were chosen because there is a great deal of activity in the semiconductor industry in this area of development, with 64K chips now appearing on the horizon and 16K RAMS well established. Motorola was selected as a prime source for this chip due to their conservatism and volume production capabilities. These devices are, in addition, available from several other vendors and, as stated earlier, conservative timing allows the use of the highest yield parts. Since Dynamic NMOS memory have highly capacitive inputs and since they generate large current spikes when operating, careful attention has been paid to address drivers and memory power distribution. As stated earlier, local regulating and interlock circuitry serves to protect chips against many contingencies including in process mishandling. In addition, this technique tends to isolate current switching spikes from other power supply busses.

The CPU arithmetic unit uses the AMD2901 bipolar 4 bit slice microprocessor chip. This chip is now commonly used in the industry and is available from several vendors. The new 2903 chip contains several enhancements including improved multiply and divide logic plus register file expansion hooks.

The 6800 Motorola microprocessor is used extensively throughout the system. This approach has been taken so that firmware development facilities and techniques can be standardized. Standard ROMs, RAMs, and peripherals are used with this microprocessor in such a way that every module has a standardized memory map and an onboard debugger port. It is believed that this is a significant step towards manufacturability and maintainability.

Mass memory is of two types, Winchester Disk and 3M Data Cartridge cassette. Winchester Disk technology uses a radial arm positioned moving head assembly within a sealed cartridge. The head positioner uses a prerecorded servo track on one of the disk surfaces as a feedback mechanism for seeks. The Control Data Corporation 24 and 80 megabyte (unformatted) can be used. The disk will be used primarily for mass memory, not for swapping. When used, large (4K byte records) will be transferred via a DMA channel to the MIO transparent to the system bus. The 6800 located on the disk controller MIO will translate the record number requested by the system to a physical disk address and will perform the required operations to transfer the data to memory. File management will be kept very simple, with track replacement and protection handled entirely by tables stored locally by the 6800. The reduced average number of seeks performed by the disk should increase its overall MTBF.

In a similar fashion, the 3M tape cassettes which are located at the user's terminals (TAP) and are used primarily for loading and backing up of files, will not be used as an active storage device, thus keeping the number of passes across the tape head to a minimum and promoting longer life. In addition, the tape will initially be operated at the ANSI standard 1600 BPI format until such time as 6400 BPI technology is firmly established.

Units will contain various built-in test features permitting exercise of module functionality to the interface level. Loopback tests on communication channels and on the bus will be accomplished under control of local 6800 processors. Verification of connector integrity and power supply voltage application by the FSU microprocessor will be performed, as mentioned earlier. Performance testing firmware will be built into the operational program for each MIO using the hardware facilities described in addition to normal operational paths.

As mentioned earlier, the address map of each 6800 has been standardized as shown in FIG. 27. An on-board debugger is always resident in the system. This is used both for firmware development and can be used for field service debug. It is a port allowing access into any unit to permit inspection of I/O points, running of diagnostics, testing of memories, or dumping of contents.

Each 6800 system also contains a "dead man" interlock device which forcibly resets the microprocessor if it fails to honor interrupt for an excessive period of time. This may be considered a performance monitor. A block output signal related to this timer is monitored by the FSU microprocessor as a status indication of the "run" condition of each block. In addition, the "dead man" timer reset feature insures that a diagnostic command can have unconditional access to the 6800 in a situation where the firmware/hardware is causing "pathologic" behavior.

Each block attaches to the bus which provides data, control, and timing signals synchronously to all modules. Each bus has one and only one CPU module. The master CPU generates timing pulses which are passed to slave CPU's via the IPB. A bus may have a maximum of fifteen IPB modules. They each must interface to a different bus to allow for proper timing chains.

System I/O is handled via the MIO blocks. Each MIO module provides four serial I/O channels and may provide one or more 32 bit DMA channels. Maximum I/O throughput is specified at 2.67 megabytes per second. The DMA channel allows one 32-bit transfer in either direction per bus cycle (1.5 microsecs). Interprocessor communications appear as a DMA operation through an IPB.

The computer supports eight levels of interrupt from each block. Each block may request interrupts on several levels simultaneously. The CPU uses a polling mechanism to determine which block generated the interrupt request at each level. The interrupt request at each level is the `OR` of the requests from each block at that level. Thus multiple blocks may interrupt at the same level. The CPU may generate an outerrupt to any block on the bus. An outerrupt indicates to the addressed microprocessor that an extraordinary event has occurred. Data is stored in a predefined location in the RAM area.

BUS (See FIGS. 1 and 27)

The bus is the interface between blocks in the computer. It is a parallel, synchronous data and control bus. Data transfers are bidirectional and 32-bits wide. Control signals include command, initialization, timing, and status information.

BUS TIMING

The bus is a synchronous device and provides the master system timing pulses to all blocks. Each bus cycle is 1.5 microsecs long and is initiated by the SYNC pulse. Each cycle consists of three phases: PH.phi., PH1, and PH2. Each block also runs on the same cycle and the phases define both local and global activities.

The cycle phase determines the interpretation of the data lines on the bus as shown in Table 1:

TABLE 1 ______________________________________ Phase Data Lines ______________________________________ PH.phi. Memory Address PH1 Memory Address PH2 Data ______________________________________

The use of these timing phases with respect to memory access will be discussed later.

In a multiprocessor configuration, the SYNC signal is propagated through the IPB from the master CPU. On a slave bus, the normal timing is disabled by the SLAVE signal. This allows the IPB to assert the timing signal from the master bus to the slave bus. The IPB delays the SYNC pulse for one phase to the slave bus. This phase delay synchronizes accesses to the memory in the IPB by the master and slave buses as shown in Table 2:

TABLE 2 ______________________________________ Master Slave Master Slave Phase Phase Activity Activity ______________________________________ PH.phi. PH2 Memory Data Address PH1 PH.phi. Memory Memory Address Address PH2 PH1 Data Memory Address PH.phi. PH2 Memory Data Address PH1 PH.phi. Memory Memory Address Address ______________________________________

The phase delay allows for proper access of the IPB memory which is used for data transfers between processors.

There are three types of bus activities: memory access, interrupt, and initialization.

Memory Access Cycles

Memory access cycles permit five types of operations to be performed: read, write, transfer, outerrupt, broadcast. FIGS. 28 and 30-33 show the activity during each phase for these operations.

Read Cycle

The read cycle allows the CPU to read 32-bits of data from either an MIO or an IPB. The read starts at the beginning of PH.phi. when the CPU places the address on the data lines and makes the READ signal true. These are held until the end of PH1 while the data is being fetched. During PH2, the data is placed on the bus and READ is made false.

Broadcast

The broadcast feature allows access to more than one MIO/IPB for a read/write operation. All blocks which are enabled to receive broadcast messages respond. High-order address bits are ignored. On a read operation, the data on the bus is the `OR` of the read data from each block. A write operation places the same data in each block.

Interrupt Cycles

A block requests an interrupt in the CPU by asserting the interrupt line corresponding to the level at which the block wishes the interrupt to be handled. A block may request an interrupt on up to eight levels simultaneously. A block continues to assert the requests until the CPU acknowledges the request. CPU handling of an interrupt request is via a poll and acknowledge sequence.

Interrupt Poll Cycle

The CPU executes a poll cycle when it wishes to determine the source of an interrupt request. INT POLL is made true and bits 24-26 of the data bus are loaded with the interrupt request level during PH.phi. and PH1.

Write Cycle

The write cycle allows the CPU to write data to memory in either an MIO or an IPB. Write requires three phases but the phases overlap bus cycles. The data is placed on the bus during pH2 and the address is loaded during PH.phi.. The actual memory write occurs during PH1. Because the data is latched, writes may take place on consecutive cycles at different memory locations with the same data.

Transfer Cycle

The transfer cycle is a combined read and write cycle. The data from the read is latched during PH2 of the cycle and used as write data during the next cycle. A memory-to-memory transfer can be made external to the CPU using just the characteristics of the bus.

Outerrupt

The outerrupt is a write cycle which causes a flag to be set in the MIO/IPB microprocessor. The flag indicates a high priority activity has been loaded into the RAM for the microprocessor's attention.

During PH2 of the cycle, all blocks having a request at that level set the appropriate bit in bits .phi.-15 of the data bus to identify themselves. The CPU then has a list of all blocks requesting an interrupt at a given level.

FIGS. 29 and 34 illustrate the interrupt poll logic.

Interrupt Acknowledge Cycle

The CPU executes an interrupt acknowledge cycle. The interrupt acknowledge cycle involves a read with the INT ACK line true. The address on the data bus is used to specify a block in the requesting device and an address within that block that contains data for that interrupt request. The INT ACK signal also causes the block to clear its request at that level.

Initialization

Each block has its own initialization sequence which is controlled by the resident microprocessor. With respect to the remainder of the system, the ANONYMOUS signal is set true, address registers cleared, and block number is reset. This initialization is always performed on power-up and may be performed on request from the CPU.

Initialization Cycle

The initialization cycle is activated when the CPU asserts INIT as true during PH.phi. and PH1 of a cycle. This is the same as a power-up sequence and results in all memory and block assignments being reset.

Block Number Assignment

Memory and block number assignment is accomplished under command from the CPU. Block numbers are assigned to blocks in memory size order. The largest blocks have the lowest numbers. A series of interactions via the bus enables each block to determine its unique position on the bus and to set its address limit registers.

The sequence is started when the CPU asserts STEP during PH.phi. and PH1. Each block immediately sets its BUSY line, does initialization, clearing BUSY when complete. At this time, the block puts its high-order memory bit on the SERIAL DATA line. A sequence of functions is performed which allows the MIO/IPB module to dynamically assign their memory space and block number. Blocks are numbered with the largest module having the lowest number and base address registers. The smallest module will have the highest block number and highest memory space. Blocks with the same memory size are ordered by serial number. An o