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United States Patent4170791
Daughton , ; et al.October 9, 1979
Title
Serial data communication system for a reproduction machine
Abstract
A data communication system for an electrophotographic type reproduction machine or copier having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data buses. The interface is connected to the master unit via the address and data buses, and includes a memory connected to the data bus for temporarily storing command and output data bytes from the master unit pending transmittal thereof to the remote units and for storing input data bytes from the remote units pending transfer thereof to the master unit. A first communication path, along which command and data bytes from the interface memory are transmitted to the remote units, couples the interface with the remote units. A second communication path, along which input data bytes from the remote units to the interface memory are transmitted, couples the remote units with the interface.
Inventors:Daughton; John W. (Fairport, NY), Gillett; Kenneth  (Redondo Beach, CA), Nelson; Frank  (Sherman Oaks, CA), Wilczek; Stephen P.  (Rochester, NY)
Assignee:Xerox Corporation (Stamford, CT)
Appl. No.:829012
Filed:August 30, 1977
Current U.S. Class:710/305 700/3 
Field of Search:364/9MSFile,2MSFile,104,107 355/14
U.S. Patent Documents
4016549April 1977Hutner
4035072July 1977Deetz et al.
4054380October 1977Donohue et al.
4058850November 1977Sheikh
4062061December 1977Batchelor et al.
Primary Examiner: Chapnick; Melvin B.
Claims

We Claim:
1. In a reproduction machine having a plurality of devices for controlling operation of said machine, a data communication system comprising:
a. a master unit including a programmable controller for controlling at least some of said devices, memory storage means for storing programs and command and data bytes, and an address and data bus,
b. interface means connected to said address and data bus of said master unit and including:
1. means connected to said data bus for storing a command byte,
2. means connected to said data bus for storing an output data byte,
3. means for transmitting said command and output data bytes along a first communication path, and
4. means for storing an input data byte, said input data byte storing means connected to receive data along a second communication path, and connected for providing said received data to said data bus of said master unit, and
c. a remote unit connected to receive said command and output data bytes from said first communication path and for transmitting input data bytes to said input data byte storing means of said interface means along said second communication path, said remote unit connected for sensing operation of at least some of said devices and for operating said devices,
said interface means including means for generating a simplex/duplex bit in said command byte for initiating a simplex mode of operation in said remote unit wherein data is read by said master unit from said remote unit and for initiating a duplex mode of operation in said remote unit wherein data is read by said master unit from said remote unit and data is written into said remote unit by said master unit,
said remote unit further including circuit means responsive to said simplex/duplex bit for operating said remote unit in either of said simplex and duplex modes.

2. A data communication system as recited in claim 1 wherein at least one data read and data write command of said master unit utilizes said data bus and a common dedicated address for both said read and said write commands, said interface means further including means for decoding said address to provide a first function associated with said read command and a second, different function, associated with said write command.

3. A data communication system as recited in claim 2 wherein said first function includes reading from said input byte storing means and said second function includes writing into said output byte storing means.

4. A data communication system as recited in claim 3 wherein said dedicated address is decoded in said interface means for starting transmission of said command byte in said command byte storing means.

5. A data communication system as recited in claim 1 wherein said memory storage means includes a dedicated address for both reading and writing said command byte from and to said command byte storing means.

6. A data communication system as recited in claim 1 wherein said system further comprises means for receiving an interrupt for said master unit.

7. A data communication system as recited in claim 6 wherein said master unit reads said command byte from said command byte storing means and stores said command byte in said memory storage means upon receipt of an interrupt, said master unit writing said stored command byte from said memory storage means into said command byte storing means after servicing said interrupt.

8. A data communication system as recited in claim 7 wherein data from said command byte storing means and said output data byte storing means is serially shifted to a remote unit.

9. A data communication system as recited in claim 8 wherein said output data byte in said output data byte storing means is serially shifted through said command byte storing means.

10. A data communication system as recited in claim 9 wherein said output data byte storing means includes a shift register, said interface means including means for serially loading zero bits into said shift register simultaneously with serially shifting said output data byte through said command byte storing means.

11. A data communication system as recited in claim 1 wherein said system further comprises a plurality of remote units each connected to said interface means by first and second communication paths.

12. A data communication system as recited in claim 11 wherein said command byte has bits thereof defining one of said plurality of remote units and said system further comprises means for decoding said defining bits to select one of said remote units.

13. A data communication system as recited in claim 12 wherein said decoding means is positioned in each of said remote units.

14. A data communication system as recited in claim 11 wherein a separate clock synchronizing communication path is interconnected between said master unit and each of said plurality of remote units.

15. In a reproduction machine having a plurality of devices for controlling operation of said machine, a data communication system comprising:
a. a master unit including a programmable controller for controlling at least some of said devices, memory storage means for storing programs and command and data bytes, and an address and data bus,
b. interface means connected to said address and data bus of said master unit and including:
1. means connected to said data bus for storing a command byte,
2. means connected to said data bus for storing an output data byte,
3. means for transmitting said command and output data bytes along a first communication path, and
4. means for storing an input data byte, said input data byte storing means connected to receive data along a second communication path, and connected for providing said received data to said data bus of said master unit, and
c. a plurality of remote units connected to receive said command and output data bytes from said first communication path and for transmitting input data bytes to said input data byte storing means of said interface means along said second communication path, said remote units connected for sensing operation of said devices and for operating said devices, said interface means further including:
a. means for generating a simplex/duplex bit in said command byte for initiating a simplex mode of operation in said remote units wherein data is read by said master unit from said remote units and for initiating a duplex mode of operation in said remote units wherein data is read by said master unit from said remote units and data is written into said remote units by said master unit,
b. a remote command byte register connected to said command byte storing means for receiving said command byte including said simplex/duplex bit, and
c. means for transmitting the command byte in said remote command byte register and the output data byte in said output data byte storing means in bit serial form along said first communication path,
each of said remote units further including circuit means responsive to said simplex/duplex bit for initiating either said simplex or duplex mode of operation.

16. A data communication system as recited in claim 15 wherein said interface means further comprises:
parity generating means connected to said command byte storing means for generating a parity bit,
said remote command byte register storing said parity bit, said transmitting means transmitting said parity bit as part of said command byte along said first communication path,
each of said remote units further including means for generating a parity-remote bit and means for comparing said received parity bit with said parity-remote bit.

17. A data communication system as recited in claim 16 wherein each of said remote units further include means for preventing the utilization of output data bytes received from said master unit if said received parity bit and said parity-remote bit do not compare.
Description
RELATED APPLICATIONS

Ser. No. 829,011 filed Aug. 30, 1977

Ser. No. 829,013 filed Aug. 30, 1977

Ser. No. 829,014 filed Aug. 30, 1977

Ser. No. 829,015 filed Aug. 30, 1977

TABLE OF CONTENTS

Subject

Background of the invention

Field of the Invention

Description of the Prior Art

Summary of the invention

Brief description of the drawings

Detailed description of the preferred embodiment

System Overview

Machine Description

Master/Area Communication System

Macs optical Link

Macs i/o instructions and Operational Overview

Table 1

Simultaneous Area Operation

Status Read and Write Commands

Table 2

Table 3

Table 4

Master Controller

Master I/O Interface

Parity Generator

Clock Generator

Shift Controls

Address Decoder

Status Input and Output Control

Interrupt Flip-Flop

Area I/O Interface

Area Controller Operation

Port Structure

Area Microprocessor and Interface

Pseudo-Interrupt Operation

Table 5

Table 5a

Machine Clock Interrupt

Real Time Interrupt

Software Description and Organization

State Checker

Table 6

Interrupt Handler

Paper Path Area Controller

Table 7

Rdh/adf control Console--Controller 8

Table 8

Rdh/platen Servos--Controller 10

Table 9

Master/Servo Software Communications

Table 10

Phase Lock Loop Control

Servo Controller Software

Process Controller 12

Master/PCR Software Communication

Table 11

Table 12

Pcr software

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is in the field of electrophotographic reproduction machines, and particularly those machines controlled by digital computers.

2. Description of the Prior Art

Electrophotographic copying machines are well known within the prior art and typically employ mechanical or combinations of mechanical and electrical control logic for system control. Such control means is responsible for maintaining synchronism between the various operational stations of the reproduction machine and to ensure proper operation of the machine during the various operating modes. These control devices have become increasingly complex as the level of sophistication has increased within the reproduction machine itself. With the advent of variable magnification machines and color copiers the logical control means necessary to achieve proper synchronization and operation has become increasingly complex and expensive. Consequently, attempts to obtain efficient operation of these machines has developed utilizing digital computing device controllers which are programmed to carry out a sequence of operational tasks. Some of these digital device controls are quite specialized and govern only particular localized tasks or operations of the machine such as disclosed in U.S. Pat. No. 3,876,106. System operation as a whole has also been achieved in the prior art utilizing computers with relatively large CPU and memory storage units. Examples of these prior art devices are disclosed in U.S. Pat. Nos. 3,936,182, 3,914,047 and 3,940,210.

With the advent of larger and more complex photo-reproduction machines the various tasks needed to be performed by the machine have become increasingly large. Particularly, an operator may select from a variety of modes of operation, each one designating a particular sequence of operations which must be stored in the computer control means. In some cases the advantages of speed and efficiency of the computer control system has been outweighed by its prohibited cost and large physical dimensions required to store and execute programs defining the desired number and permutations of operational tasks. Still further cost and size restraints come into play when system flexibility is desired by way of expanding the computer control to various other controlled devices or operating stations as would be typical in the offering of a single model copier with various optional attachments. Thus, special purpose hardware may typically be employed as an alternative or addition to the utilization of the central digital computing controller.

Yet another disadvantage of the prior art in computer control devices lies in malfunctioning of the computers due to noise and radio frequency interference resulting primarily from the computer being exposed to the various electrical transients produced by operation of solenoids, motors, relays and the like. Consequently, there exists a need for an ever expanding digital computer capability and at the same time a need to isolate and remove the central controller from the environment of the reproduction machine to achieve error free operation.

SUMMARY OF THE INVENTION

Consequently, it is an object of the invention to eliminate the disadvantages of the prior art by providing an electrophotographic reproduction machine utilizing a distributed microprocessor controller.

Another object of the invention is to provide a reproduction machine having a central or master micro-controlled processor operable in conjunction with an area micro-controlled processor wherein certain system tasks are allocated to the master microprocessor and certain other particular device oriented tasks are allocated to the area microprocessor.

Yet another object of the invention is to provide a micro-controlled photographic reproduction machine utilizing an optical communication link between a central master controller and the various controlled devices so as to achieve an effective error free operation of the master microprogram controller from radio frequency interference generated within the reproduction machine.

Yet another object of the invention is to provide a computer controlled electrophotographic reproduction machine utilizing a single interrupt scheme for enabling simultaneous monitoring of a plurality of control devices in a bit serial communication fashion.

Yet a further object of the invention is to provide a computer controlled photographic reproduction machine wherein a central master controller is interconnected via optical links to at least one passive area controller and at least one active area controller wherein each active controller incorporates a separate microprocessor for controlling specific device tasks, and the passive and active controllers operate together in operative relationship with the master controller to maintain a synchronous control of the entire machine.

The foregoing and other objects of the present invention are attained utilizing a master microprogram controller which is operatively connected to various devices within the operating stations of the photographic reproduction machine and an active microprogrammed controller for controlling a particular device or devices (or portions thereof) such as those devices associated with a particular operating station. The master and active controller are interconnected via an optical link which serves to isolate the master controller from the direct I/O environment. Additional optical links may be provided to interface the master controller with a plurality of passive controllers which serve to latch the output of the master controller to the various controlled devices and serve to forward sensed output data from the operating station to the master controller for processing. The master, passive, and active controllers are all operably connected to one another to control the various devices of the machine.

More generally, the invention provides a reproduction machine having a plurality of operating stations and a plurality of devices for controlling operational tasks within the operating stations. The machine comprises a master programmable controller for controlling some of the devices and an area programmable controller for controlling other of the devices. The master and area controllers are cooperatively operative to control the operating task of the operating stations.

A further object of the invention is to provide a data communications system comprising a programmable master controller having memory storage means and command byte generating means and a plurality of area controllers each having means for receiving command bytes from the master controller and means for providing input data bytes to the master controller. The additional controllers are interconnected to the master controller and have corresponding input data bits of their input data bytes ORed together. The additional controllers simultaneously transmit bytes in response to a pre-determined command byte from the master controller and corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein. The communications system may be utilized in a reproduction machine or more generally for data communications or for control of other types of machines. The simultaneous transmission technique may be utilized to quickly poll a plurality of additional controllers, and the programmable controller may be configured such that the simultaneously received bytes serve to interrupt the master programmable controller in response to the bits received to cause program interrupt jumps to sub-routines servicing the additional controllers.

The invention is additionally directed to a reproduction machine having a plurality of operating stations and a plurality of devices for controlling operational tasks of the operating stations wherein are provided means for sensing various operational parameters associated with said devices, a master controller having an arithmetic and logic control means for controlling the devices in accordance with the sensed operational parameters and a stored operation program and interface means connected in a communication path between the master controller and the devices, the interface means comprising a fiber-optic communication path which isolates the master controller from electrical noise and transients associated with said devices.

The invention is also directed to a copier/duplicator machine having a plurality of devices for controlling different operations within the machine and comprising a programmable controller including program memory storage means, addressing means, arithmetic and logic means, and means for generating data words for controlling some of the machine devices. The machine utilizes a first document exposure station, means for imaging the document along a first optical path, a second document exposure station which is distinct from the first exposure station, means for imaging the document at the second exposure station along a second optical path, and means for imaging the document along both the first and second optical paths onto a receiving means. The first and second optical paths have at least some portions thereof distinct from one another and the optical imaging means is controlled by the programmable controller.

Yet another feature of the invention is directed to a control system for a reproduction machine which comprises a programmable controller having program storage means for storing an operational program controlling at least some portion of the machine, means for sensing analog data from the machine, analog-to-digital conversion means for generating digital data for processing in said controller in accordance with said operational program, digital-to-analog conversion means for converting the process data into analog signals, and means for controlling at least some portion of said machine in response to the analog signals.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the instant invention will become clear in reference to the foregoing specification taken in conjunction with the drawings wherein:

FIG. 1 is a block diagram of the overall master/area communication system;

FIG. 2 is a schematic illustration of various mechanical components of the copier/duplicator;

FIG. 3 is a block diagram showing the major components of the master unit and an active and passive area controller;

FIGS. 4A and 4B illustrate the master I/O interface and its input and output lines for interconnection to an area controller;

FIG. 4C shows a fiber optic interconnection link utilized for the communication channels;

FIGS. 5 and 6 illustrate the transmission format for data communicated between the master and area controllers;

FIGS. 7A and 7B illustrate the interconnection of various data and address lines from the master tri-state bus to the master I/O interface;

FIG. 8 shows a schematic drawing of key registers utilized in the master I/O interface for transmitting a command and data word;

FIGS. 9A and 9B are schematic drawings illustrating the key input registers in the master I/O interface;

FIG. 10 is a schematic drawing of the parity generator circuit utilized in the master I/O interface;

FIG. 11 shows the clock generating circuit utilized in the master I/O interface;

FIG. 12 shows the logic and timing control circuitry utilized in shifting input data into the master I/O interface;

FIG. 13 shows a timing chart illustrating the overall timing sequence for transmitting and receiving data between the master and area controllers;

FIGS. 14A and 14B are schematic diagrams of further timing and control circuits utilized in the master I/O interface;

FIGS. 15 and 16 show decode logic for the master I/O interface;

FIG. 17 is a schematic diagram of the status write register utilized in the master I/O interface;

FIGS. 18A and 18B are schematic diagrams of the status read register utilized in the master I/O interface;

FIG. 19 is a schematic diagram of the interrupt flip-flop;

FIGS. 20A-20C show schematic diagrams of the key input and output registers and control logic for the area controllers;

FIG. 21 shows the clock generating circuitry utilized in the area controllers;

FIG. 22 is a timing diagram showing the timing sequence of data within the area controller;

FIGS. 23A and 23B show input and output port connections between the host machine and the area controller;

FIG. 24 shows a block diagram of the area microprocessor and its interface circuitry within the area controller;

FIG. 25A is a block diagram showing details of the area microprocessor external memory;

FIG. 25B is a block diagram showing details of the I/O buffers and selection circuit for the area microprocessor;

FIG. 25C is a block diagram showing details of the area microprocessor interrupt and clock detection circuits;

FIG. 26 illustrates details of the area microprocessor interface circuitry for the area controller;

FIG. 27 is a block diagram illustrating input and output port connections for a psuedo interrupt operation;

FIG. 28 is a block diagram showing the different computer states in accordance with the present invention;

FIG. 29 is a flow chart illustrating the overall structure of a machine state;

FIG. 30 is a flow chart of the state checker module for controlling changes of state within the machine;

FIG. 31 is a block flow diagram indicating construction of the Q TABLE utilized to control events in the machine;

FIGS. 32A and 32B are partial flow charts showing the interrupt handler module;

FIG. 33 is a block schematic diagram showing the major portions of the paper path controller utilized in accordance with the invention;

FIG. 34 is a schematic illustration of the major mechanical and electrical sensors and actuators utilized in the paper path area controller;

FIG. 35 is a block diagram showing the major components of the RDH/ADF control console controller;

FIG. 36 is a schematic drawing illustrating the major mechanical and electrical sensors and actuators utilized in the RDH/ADF control console controller as well as the servo controller;

FIG. 37 illustrates a block diagram of the servo controller showing the key components thereof;

FIG. 38 is a schematic drawing of the key platen scanning components;

FIG. 39 is a block diagram showing the port structure utilized for the master-servo controller communication path;

FIG. 40 is a flow chart showing the major steps utilized for the communication routine between the master and area servo controller;

FIGS. 41-43 show logic circuitry utilized in the phase lock loop control of the servo controller;

FIG. 44 illustrates an overall flow chart of the operation of the servo controller software;

FIG. 45 is a flow chart showing the executive routine utilized in the servo area controller;

FIG. 46 is a flow chart showing the phase lock state utilized in the servo area controller;

FIG. 47 is a flow chart showing the various scroll states applicable in the servo area controller;

FIGS. 48-54 show various state flow charts for controlling the platen scanning lamp and carriage applicable in the servo area controller;

FIG. 55 is a block diagram showing the input and output port connections utilized in the process area controller;

FIG. 56 is a flow chart showing the overall sequence governing the communications between the process controller and the master unit;

FIG. 57 illustrates the different filtering techniques utilized in performing the analog-to-digital readings utilizing the process controller; and

FIGS. 58 and 59 are flow charts showing the key operational steps utilized in operating the process controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

System Overview

FIG. 1 is a block diagram of the overall Master/Area Communication System (MACS) utilized in controlling the copier/duplicator in accordance with the instant invention. MACS comprises a master unit 1 including a master controller 2 in combination with a master I/O interface 4. The master controller 2 contains a microprocessor and memory units which govern the various tasks and operational procedures utilized in operating the copier/duplicator. The master I/O interface 4 is responsible for interconnecting the various address and data bytes from the master controller 2 to a plurality of area controllers 6, 8, 10, 12 and 14 which are responsible for specific tasks in the operation of the copier/duplicator. Each area controller 6, 8, 10, 12, 14 is dedicated to performing a group of functions which are physically and/or logically related. The area controllers take on two general forms, an active controller which has its own processor control capabilities and a passive controller which has no processing capabilities per se and is simply utilized to latch outputs from the master controller and feed inputs thereto on the command of the master controller. FIG. 1 illustrates five area controllers but it is within the scope of the invention to utilize any number of area controllers consistent with the address capabilities of the master controller. Illustrated in FIG. 1 are three passive area controllers, namely, the paper path controller 6, RDH/ADF control console controller 8 and finishing station controller 14. Two active controllers are illustrated, namely, the RDH/platen servo controller 10 and processor controller 12. The master controller 2 is responsible for the majority of system control processing tasks whereas the area controllers are responsible for the machine control functions. Input and output data are transmitted between the master controller 2 and the area controllers 6, 8, 10, 12, 14 in a serial communications path via Master/Area Communication Channels 16 which may take the form of a plurality of fiber optic connections. The utilization of fiber optics interconnection for the MACS transmission channels greatly reduces control susceptibility to electromagnetic interference generated in the machine. Typically, it is desirable to physically position the area controllers in close proximity to the particular device or devices controlled thereby.

Machine Description

For a general understanding of an electrophotographic printing machine in which the features of the present invention may be incorporated, reference is had to FIG. 2 which depicts schematically the various components thereof. Although the control logic employed in the electrophotographic printing machine of FIG. 2 is particularly well adapted for use therein, it should become evident from the following discussion that it is equally well suited for use in a wide variety of printing machines and is not necessarily limited in its application to the particular embodiment shown herein.

Inasmuch as the practice of electrophotographic printing is well known in the art, the various processing stations for producing a copy of an original document are herein represented schematically. Each processing station will be briefly discussed hereinafter.

As in all electrophotographic systems of the type illustrated, a drum 110 having a photoconductive surface 112 entrained about and secured to the exterior circumferential surface of a conductive substrate is rotated, in the direction of arrow
114, through the various processing stations. One type of suitable photoconductive material is a selenium alloy such as described in U.S. Pat. No. 2,970,906 issued to Bixby in 1961. Preferably, the conductive substrate is aluminum.

Initially drum 110 rotates a portion of photoconductive surface 112 through charging station A. Charging station A employs a corona generating device, indicated generally by the reference numeral 116, to sensitize a portion of photoconductive surface 112. Corona generating device 116 is positioned closely adjacent to photoconductive surface 112. When energized, corona generating device 116 charges the portion of photoconductive surface 112 therebeneath to a relatively high substantially uniform potential. A suitable corona generating device may be of the type described in co-pending application Ser. No. 748,805 filed in Dec. 8, 1976, now U.S. Pat. No. 4,086,650, issued Apr. 25, 1978, the relevant portions thereof being hereby incorporated into the present application. As described therein, the corona generating device includes a corona discharge electrode having a conductive shield located adjacent thereto. The electrode is coated with a relatively thick dielectric material so as to substantially prevent the flow of conductive current therethrough. Photoconductive surface 112 is charged by means of a displacement current or capacitive coupling through the dielectric material. The flow of the charge to photoconductive surface 112 is regulated by means of a D.C. bias applied to the shield.

Thereafter, drum 110 rotates the charged portion of photoconductive surface 112 to exposure station B. Exposure station B is arranged to produce a light image of an original document or series of documents being reproduced. In the electrophotographic printing machine depicted in FIG. 2, exposure station B operates in one of two modes. In one mode, a plurality of original documents are recirculated in an automatic document handling system (ADH) so that sets of collated copies may be formed by the printing machine. In the other mode of operation, a single original document is placed on the platen and reproduced by the printing machine. If the platen scan optics are used, mirrors 118 and 120 are moved into the operative position depicted in FIG. 2. An original document is placed face down upon a transparent platen 122, such as a glass plate or the like. Lamp 124 illuminates the original document disposed on platen 122. Lamp 124 moves across the original document disposed on platen 122 to illuminate incremental portions thereof. The light rays transmitted from the original document are reflected by full rate mirror 126 to half rate mirror 128. Half rate mmirror 128 reflects the light rays through lens 130 onto mirrors 118
and 120. These mirrors reflect the light image of the original document onto the charged portion of photoconductive surface 112. Drum 110 rotates in synchronism with the movement of the platen scanning optics. Thus, the charged portion of photoconductive surface 112 is irradiated to record an electrostatic latent image thereon corresponding to the information areas of the original document disposed to the informational areas of the original document disposed on platen 122.

In the automatic document handling system for making pre-collated copy sets, the repeated collated imaging of a set of original documents is obtained by placing and retaining the original documents on an elongated windable document holding web
132. This web is wound between two spaced web scrolls positioned and wound so as to obtain the document between the turns of the web scrolls. The web is repeatedly wound and unwound from one scroll to the other scroll (recirculated) to repeatedly expose individual documents thereon in an exposed portion of the web extending between the scrolls. The documents are optically exposed on the web between scrolls for copying. The details of the automatic document handling system are more fully disclosed in U.S. Pat. No. 4,008,956 issued to Stemmle et al in 1977, the relevant portions thereof being hereby incorporated into the present application. During the forward movement of web 132, a lamp (not shown) illuminates the original documents disposed thereon. Mirror 134 reflects the light rays toward stationary mirror 136 which, in turn, reflects the light rays toward rotatable mirror 138. Rotatable mirror 138 transmits the light rays through lens 140. The light image transmitted through lens 140 is reflected by mirror 142 onto the charged portion of photoconductive surface 112. In the ADH mode of operation, mirrors 118 and 120 are positioned remotely from the optical light path.

In the reverse scan mode, i.e. web 132 advances in the opposite direction to the forward movement, mirror 134 rotates 90.degree. about its axis and reflects the light rays transmitted from the original document onto mirror 144. Mirror 138 also rotates 90.degree. about its axis to receive the light rays transmitted from light rays 144. Thus, mirror 138 directs the light rays received from mirror 144 through lens 140. Once again, the light image transmitted through lens 140 is reflected by mirror 142 onto the charged portion of photoconductive surface 112. At this time, mirrors 118 and 120 are positioned remotely from the optical light. The foregoing optical system for the ADH system is disclosed in U.S. Pat. No. 4,008,958 issued to Kingsland in 1977, the relevant portions thereof incorporated hereby into the present application. Thus, in either mode or operation, an electrostatic latent image is recorded on photoconductive surface 112.

As drum 110 continues to rotate in the direction of arrow 114, the electrostatic latent image recorded thereon is advanced to development station C. Development station C includes a developer unit 146 having a housing 148 with a supply of developer mix contained therein. The developer mix comprises carrier granules having toner particles adhering triboelectrically thereto. Preferably, the carrier granules are formed from a magnetic material with the toner particles being made from a heat settable plastic. Developer unit 146 preferably is a magnetic brush development system. In a system of this type, the developer mix is brought through a directional flux field to form a brush thereof. As depicted in FIG. 2, developer unit 146
includes a pair of developer rollers 150 and 152. Each developer roller includes a stationary magnetic member having a non-magnetic, rotatable tubular member interfit telescopically thereover. The tubular member is rotated to advance the developer material into contact with the electrostatic latent image recorded on photoconductive surface 112. The developer material is advanced to developer roller 150 and 152 by paddle wheel 154 disposed in the sump of housing 148. Developer rollers 150 and 152
advance the developer mix into contact with the electrostatic latent image and the toner particles are attracted electrostatically thereto forming a toner powder image on photoconductive surface 112. As successive electrostatic latent images are developed, the toner particles within the developer mix are depleted. Additional toner particles are stored in toner cartridge 156. A sample electrostatic latent image is recorded on photoconductive surface 112 and developed. The density of the toner particles adhering thereto is detected via an ADC sensor 157 (not shown) and compared to a reference density. The error signal developed thereby controls the dispensing of toner particles from cartridge 156. In this manner, the concentration of toner particles within the developer mix is maintained substantially constant. Developer rollers 150 and 152 are electrically biased to a suitable voltage. This voltage is adjustable and depends upon the original document as well as the duration of time that the printing machine is activated. After the toner powder image has been developed on photoconductive surface 112, corona generating device 158 applies a charge thereto so as to pre-condition toner powder image for transfer. Preferably, corona generating device 158 is also of the type described in copending patent application Ser. No. 748,805 filed in 1976, the relevant portions thereof being hereby incorporated into the present application.

Ideally, carrier granules remain in housing 148 of developer unit 146. However, inasmuch as the sealing arrangement is imperfect, carrier granules may adhere to photoconductive surface 112 of drum 110. A scavenging roller 160 is provided for removing these carrier granules. Scavenging roller 160 comprises a magnetic member and a rotatable, non-magnetic tubular member interfit telescopically thereover. The tubular member rotates relative to the magnetic member. In this manner, the magnetic carrier granules are attracted from photoconductive surface 112, while the toner powder images remain undisturbed thereon.

With continued reference to FIG. 2, a sheet of support material is advanced by sheet feeding apparatus 162 or 164 from either tray 166 or tray 168. Conveyer system 170 advances the sheet of support material to transfer station D. Rollers 172
speed up or slow down the advancing sheet of support material so as to ensure that it moves into contact with drum 110 in a timed sequence so that the toner powder image developed thereon contacts the advancing sheet of support material at transfer station D.

Transfer station D includes a corona generating device 174 which charges the backside of the sheet of support material to a level sufficient to attract the toner powder image from photoconductive surface 112. Preferably, corona generating device
174 is also of a type described in copending U.S. patent application Ser. No. 748,805 filed in 1976, the relevant portions thereof being hereby incorporated into the present application.

After transfer of the toner powder image to the sheet of support material, a vacuum stripping system 176 separates the sheet from photoconductive surface 112 and advances it to fusing station E. If vacuum stripper 176 fails to separate the sheet from photoconductive surface 112, a redundant mechanical finger, i.e. stripper finger 198 activated by solenoid 199 (not shown), is provided to ensure separation of the sheet therefrom.

Fusing station E includes a fuser assembly, indicated generally by the reference numeral 178. Fuser assembly 178 fuses the transferred toner powder image to the sheet of support material. A suitable fuser comprises a heated fuser roll 180 and a resilient backup roll 182 in contact therewith. In this manner, the sheet of support material advances between fuser roller 180 and backup roller 182 with the toner powder image contacting fuser roller 180. Preferably, fusing assembly 178 is of a type described in U.S. Pat. No. 3,912,901 issued to Strella et al in 1975.

After the toner powder image is permanently affixed to the sheet of support material at fusing station E, a series of rollers advance the copy sheet either to finishing station F or to duplex tray 183. When duplex copies are being reproduced, the sheet of support material with the toner powder image permanently affixed on one side thereof is advanced to duplex tray 183. In the ADH mode of operation, a plurality of sheets are stored in duplex tray 183 having the corresponding toner powder images permanently affixed to one surface thereof. After web 132 with the original documents thereon has advanced through one pass, the odd numbered sheets are copied. During the next forward scan, the even numbered sheets are copied and the information contained therein placed on the reverse side of the copy sheet. This sequence may be reversed. Tray 183 is arranged to hold a plurality of sets of copies therein. Each sheet of support material having the toner powder image permanently affixed to one surface thereof is advanced from tray 183 by sheet feeding apparatus 184 onto duplex conveyer 185. Duplex conveyer 185 advances the copy sheet to conveyer system 170 where the sheet once again is advanced to transfer station D so as to receive the toner powder image corresponding to the second side thereof. Once again, the reverse side of the copy sheet passes through transfer station D and fusing station E. However, at this time the copy sheet is advanced to finishing station F. This duplexing arrangement is described more fully in copending application Ser. No. 767,012 filed Feb. 9, 1977, the relevant portions thereof being hereby incorporated into the present application.

After the toner powder image has been permanently fused to the copy sheet, either the duplex or simplex copy sheets are advanced by a series of rollers 186 to finishing conveyers 188. Finishing conveyors 188 advance the copy sheets to trays 190
or 192. The sheets are stacked in one tray, e.g. tray 190 with the odd sides up and the even sides face down, while in the other tray, e.g. tray 192 with the even sides up and the odd sides down. This orientation is required because of the forward and reverse movements of web 132. After the requisite number of copies have been stacked in the appropriate tray, i.e. sufficient copies to define a collated set thereof, staplers 194 and/or 196 are actuated to permanently secure the sheets to one another. In this manner, sets of collated copies are stored in trays 190 and 192 with each set having the copies thereof stapled to one another.

Invariably, after the sheet of support material is separated from photoconductive surface 112, some residual toner particles remain adhering thereto. These residual toner particles are removed from photoconductive surface 112 at cleaning station G.

Initially, discharge lamp 204 floods photoconductive surface 112 to assist in the dissipation of any electrostatic charge remaining thereon prior to the cleaning thereof. Residual toner particles are then brought under the influence of a corona generating device 200 adapted to neutralize the remaining electrostatic charge on photoconductive surface 112 and that of the residual toner particles. Preferably, corona generating device 200 is of a type described in copending U.S. application Ser. No. 748,805 filed in 1976, the relevant portions thereof being hereby incorporated into the present application. The neutralized toner particles are cleaned from photoconductive surface 112 by a rotatably mounted fibrous brush 202 in contact therewith. In addition, subsequent to cleaning, a discharge lamp 206 illuminates photoconductive surface 112 to dissipate any residual electrostatic charge remaining thereon prior to the charging thereof for the next successive imaging cycle.

It is believed that the foregoing description is sufficient for purposes of the present application to illustrate the general operation of an electrophotographic printing machine. Referring now to the specific subject matter of the present invention, FIGS. 3 through 27 describe the control system for the electrophotographic printing machine of FIG. 2 in greater detail.

Master/Area Communication System

FIG. 3 illustrates a more detailed block diagram of the master controller and the active and passive area controllers of FIG. 1. For simplicity of illustration only one passive area controller such as the paper path controller 6 and a single active controller such as the process control controller 12 is illustrated. The master controller 2 comprises a central processing unit and system controller identified as a master microprocessor 300. A number of existing microprocessor systems may be utilized to practice the present invention and the detailed description herein utilizes the INTEL 8080A-2 CPU and INTEL 8238 System Controller. The master microprocessor 300 is shown connected to memory units utilized to store program memory and for temporary storage of various control and sense parameters. The memory units comprise a read only memory (ROM) 302, a random access memory (RAM) 304 and a non-volatile memory (NVM) 306. The ROM memory may be for example a 48KB (bytes) mask programmable ROM, while the RAM may comprise a 2KB (byte) static MOS scratch pad memory and a 1 KB (bit) flag storage MOS RAM (bit D7 of RAM). The ROM may be fabricated, for example, using 2 K.times. 8 ROM chips model No. 8316A, and the RAM memory may be implemented using 1K.times. 1 chips, model No. 2102. The NVM may be fabricated using 512.times. 1 RAM chips model No. 52222 (American Microsystems Inc.). Equivalent chips may of course be utilized as for example the NVM may be fabricated from
256.times. 4 chips (model No. 5101L) if desired. The memory units are interconnected to the master microprocessor 300 by means of a tri-state master system bus 308 which is also interconnected to the master I/O interface 4. The tri-state master system bus comprises eight data lines DO-TS through D7-TS, sixteen address lines AO-TS through A15-TS and a number of control and clock lines. The master microprocessor 300 is supplied with clock signals from the clock source 310 (INTEL clock generator 8224
for example) and is powered by an external power supply 312. Power for the various circuits in the master controller 2 as well as the master I/O interface 4 is first filtered by means of a filter circuit 314. A power normal signal is also fed to the master controller along line 316 from the power supply to indicate that power is up to normal operating levels. A reset signal from reset circuitry 318 is utilized to reset the various registers throughout the master controller and master I/O interface during a power up or initialization sequence. The power supply 312 also supplies power to the various remote controllers by means of lines 320.

A more detailed description of the master controller 2 may be found in copending application Ser. No. 758,117, filed Jan. 10, 1977, entitled Direct Memory Access for Refresh of a Programmably Controlled Machine, assigned to Xerox Corporation.

The passive area controller exemplified by the paper path controller 6 comprises an area I/O interface circuit 340, latches 342 and drivers 344 which provide outputs to one or a plurality of machine controlled devices. Sense data is supplied from various sensing means to represent the current device operational state whose function is governed by the particular passive controller of interest. The sensed data is fed to buffers 346 and subsequently to the area I/O interface 340 for transmission along the master area communication channel 16 to the master unit 2. The active area controllers are similar in function to the passive area controllers and likewise contain an area I/O interface 340, latches 342 and drivers 344. Sensed data may be provided to the master unit 2 through buffers 346, the I/O interface 340 and the communication channel 16. Additionally, however, the active area controller contains an area microprocessor/interface 348 which is separate and distinct from the master microprocessor 300. Shown in FIG. 3 the area microprocessor/interface 348 is connected by means of an area system bus 350 to a plurality of latches 354 which feed drivers 344 to control various machine parameters. The area microprocessor/interface 348 may additionally provide input information to latches 352 for subsequent feeding to the master unit 2 via the area I/O interface 340. The area microprocessor/interface 348 may also be utilized to control analog data to various machine devices and to sense analog data from various machine sensing means utilizing D/A converters 364 and A/D converter 366 respectively. Data which is not controlled by the area microprocessor/interface 348 may be fed to and from the master unit 2 by means of the direct paths 360 and 362 as illustrated in FIG. 3.

The servo controller 10 is similar to the process controller 12 and supplies a machine clock signal to the master unit 2 along channel 370 (see dotted line in FIG. 3). This signal is derived from the photoreceptor drum of the copier/duplicator and is passed along a fiber optic link of channel 370 to provide an interrupt signal to the master microprocessor 300. The machine clock signal thus enables a snychronization of the master microprocessor 300 to the actual copier/duplicator machines operation.

The Master Area Communication System utilizes a set of bi-directional communication channels 16 which independently couple each area controller 6, 8, 10, 12, 14 to the master unit 1. Each channel 16 comprises three groups of signal lines, namely, data-in, data-out and clock. The data-in and data-out lines are defined relative to the master controller and in the description set forth herein this terminology has been maintained throughout even in relation to data in area controllers 6, 8,
10, 12, 14. Data transfers between the master and area controllers is in bit serial form in eight bit increments (bytes). An I/O transaction may be an input only transaction or a combined input/output transaction as specified by an initiating command byte from the master unit 1. All transmissions are in synchronism with and at the same rate as the 1.25 MHz clock signal from the master unit 1. All MACS communication is initiated by and under control of the master unit 2. Communication is always between the master unit 1 and the area controllers and communication never takes place directly between the area controllers.

FIG. 4 is an expanded block diagram of the master I/O interface 4, the communication channels 16 and their interconnection with the various area I/O interfaces 340. The data bus 414 forms part of the master system bus 308. For ease of illustration, only one such area I/O interface 340 is drawn although similar components are utilized for all area controllers.

FIG. 4 illustrates input data lines and output data lines for as many as six different area controllers. One fiber optic interconnecting link 398 is provided for input data between each of the area controllers and the master I/O interface 4. Data from the area controllers (input data) is fed to receiver amplifiers 400 interconnected to each of the fiber optic links 398. The received data is "ORed" by means of OR gate 404 and fed as an input to multiplexer 406. In normal operation the data is only received from a particular area controller in response to a command from the master unit and consequently only one area controller will be active in transmitting data at any one time. (An exception to this rule exists in the simultaneous transmit and receive mode which will be explained more fully below). Individual data lines 408 from each of the data-in lines of the area controllers are also fed to multiplexer 406 where they may be selected for particular test modes to isolate faults in a particular area controller. Data received from the OR gate 404 is passed through the receiving mux 406 and fed to a Serial Data Input (SDI) register 410 which in turn feeds the data to a Command Check Byte (CCB) register 412. The SDI and CCB registers provide the input data in parallel form to a master data bus 414 which forms the eight data lines D0-TS through D7-TS of the master system bus 308.

Output address words from the master controller 2 are provided along the master data bus 414 to a Master Command Byte (MCB) register 416. Output data is provided from the data bus 414 directly to a Serial Data Out (SDO) register 418. The MCB register 416 is utilized together with a parity generator 420 to load an Area Command Byte (ACB) register 422. ACB register 422 is ten (10) bits long and holds an area command address word whereas the SDO register 418 is an eight (8) bit register storing the Data Out Byte. Together, these registers provide a serial output data stream of eighteen (18) bits to each of the area controllers via the fiber optic interconnecting links 16. The ACB register 422 effectively provides an addressing means to select a particular area controller and to select a particular group of input or output data lines within the selected area controller. The SDO register 418 provides the actual data to be transmitted to the designated area and output lines (ports). The gating of the various input registers (SDI register 410, and CCB register 412) and output registers (ACB register 422 and SDO register 418) as well as the MCB register 416 are controlled by a control logic circuit 424. The control logic circuit 424
receives address lines A0-TS through A18-TS as well as a plurality of control lines from the master system bus 308 to effectively decode and control the data on the master data bus 414. Shifting of the registers is synchronized with a 1.25 MHz clock signal from clock generator 426 which provides a 1.25 MHz clock signal to each of the area controllers. These clock signals are fed along line 428 to drivers 402 for transmission via fiber optic links 398 to the area controllers.

Output data from ACB register 422 and SDO register 418 is likewise shifted at the 1.25 MHz rate to a master data out line 425 and subsequently to drivers 402 and fiber optic links 398. Output data is also fed via a turnaround test line 430 to multiplexer 406 to optionally provide input data to the CCB register 412 and SDI register 410 in a master test mode of operation.

The control logic 424 decodes the address bits on the master system bus 308 address lines to determine if the address decode corresponds to the master I/O interface 4 so that the input and output registers may be appropriately gated.

The area I/O interface 340 comprises area input register 450, area output register 452 and control logic 454. The control logic 454 decodes the address received from the ACB register 422 of the master I/O interface 4 and selects particular groups of the input and output lines for providing or receiving data respectively. Each area controller is provided with a plurality of output ports 456 and input ports 458. In the preferred embodiment there are eight input ports and eight output ports wherein each port may contain as many as eight separate lines. Consequently, there may be sixty-four separate input signals and sixty-four separate output signals to and from any given area controller. More specifically in terms of the detailed implementation of the control logic, input and output ports may be defined in terms of buffers and latches. Output data bytes are stored in output ports or latches either for direct use by the machine or for use by other circuits in the area controller such as the area microprocessor/interface 348 (FIG. 3). Input data bytes selected for transmittal to the master unit 2 are routed through buffers or input ports. Data is fed to the input ports directly from the host machine. In the case of data from the area microprocessor sent to the master unit 1, the data is fed to latches which are used as input ports.

The particular I/O interface 340 shown in FIG. 3 is common to both active and passive area controllers. The additional circuitry utilized in the active controllers is described in detail in relation to the more detailed implementation set forth hereafter.

MACS Optical Link

The master/area communication channel 16 may comprise data channels implemented by simple wire conductors or, alternately, by fiber optic links as illustrated in FIG. 4C. The fiber optic apparatus shown in FIG. 4C is common to both the clock and data lines, and a separate driver and receiver circuit are utilized for each channel 16. The light source is typically an LED and the received data from amplifier 400 is passed through a discriminator to produce two level logic signals.

MACS I/O Instructions and Operational Overview

Preparatory to all serial communications over MACS, the master microprocessor 300 first generates a Master Command Byte into the MCB register 416 via the master system bus 308 and particularly the master data bus 414 forming part thereof. The Master Command Byte is effectively a ten (10) bit area command address word which specifies which of the six possible area controllers is to participate in the MACS communication. Actual data transfer of the data in the SDO register 418 follows immediately the transfer of the Master Command Byte. The command information specifies both the type of transfer, such as input (read) or input/output (duplex transmission) as well as the specific group of eight bits to be sensed (input operation) or to be sensed and set (duplex operation). The contents of the MCB register 416 are uneffected by the transmission of the Area Command Byte inasmuch as the contents of the MCB register 416 are shifted into the ACB register 422 and then serially shifted from the ACB register 422 to all of the area controllers. The MCB register 416 can only be altered by a subsequent MCB write operation directed by the master microprocessor 300.

In relation to FIGS. 3 and 4, the master microprocessor 300 initiates and controls communication over MACS through the master I/O interface 4 via the master system bus 308. Both control and data transfers are performed through execution by the master microprocessor 300 of a sequence of memory reference instructions to specific, dedicated addresses. These addresses are decoded directly off of the master system bus 308 and interpreted by the master I/O interface 4 to cause a desired I/O operation to occur.

Two memory addresses are dedicated for writing into the MCB register 416 by the master microprocessor 300. The "LOAD MCB" instruction is utilized to load the MCB register with a Master Command Byte in preparation for an I/O transmission. This instruction is utilized together with a subsequent write operation namely, the "LOAD SDO AND START TRANSMISSION" instruction which loads the output data byte from memory (via the master data bus 414) into the SDO register 418. Additionally, the "LOAD SDO AND START TRANSMISSION" instruction constructs and loads the Area Command Byte into the ACB register 422 from the MCB register 416. One bit of the ACB register is set by the parity generator 420 and a second bit of the ACB register is set by a command signal indicating a duplex or read only transmission, the R/D bit. Finally, the "LOAD SDO AND START TRANSMISSION" instruction is effective to start the actual MACS transmission. The Area Command Byte residing in the ACB register 422 is transmitted first followed by the Data Out Byte residing in the SDO register 418.

A second dedicated memory address is utilized for writing into the MCB register. This alternate address is utilized in executing the "LOAD MCB AND START TRANSMISSION" and is effective to load a Master Command Byte from memory (master data bus
414) into the MCB register 416. Additionally, this instruction constructs and loads the Area Command Byte into the ACB register 422 appropriately setting the read/duplex bit and the parity bit. Finally, the instruction is utilized to start the actual MACS transmission. "LOAD MCB AND START TRANSMISSION" consequently eliminates time delays associated with loading the SDO register 418 when initiating input only MACS transmissions (R/D bit equals zero).

The start of a MACS transmission for both the input only or combined input/output (duplex) operation causes the broadcast of the serial bit stream from the least significant bit position of the ACB register 422 simultaneously to all area controllers. Each area output register 452 of the area controllers simultaneously receives the transmitted Area Command Byte from the ACB register 422 followed by the Data Out Byte transferred from the SDO register 418. The Data Out Byte is serially shifted through the ACB register 422.

The transmission format for data in the various registers is illustrated in FIGS. 5 and 6. With reference to FIG. 5, the data bits D0-D7 from the master data bus 414 are parallel loaded into the master command bit register 416 during a "LOAD MCB" instruction for example. Bits DO-D2 are termed the Byte Address bits C1-C3 and are utilized to select a group of eight input (sensed) lines as well as a group of eight output signals from a designated input and output port of a designated area controller. The designation of the area controller is made by means of Channel Select bits, CS1-CS3 which correspond to bits D4-D6 respectively from the data bus. Data bits D3 and D7 are not utilized in the MCB register 416 although bit D7 is available as a reserve command bit for special use if desired.

In a typical transmission operation the contents of the MCB register 416 are parallel loaded into the ACB register 422 (with the exception of bit D3). As shown in FIG. 5, Byte Address bits C1-C3 are loaded into bits 1-3 of the ACB register 422, and the Channel Select bits CS1-CS3 are loaded into bits 4-6 of the ACB register 422. The 0th bit of the ACB register 422 is loaded with a "one" bit to indicate a Start of Transmission (ST). Bit 7 of the ACB register 422 is loaded by the parity generator 420 to provide either an even or odd parity over the preceding ACB bits 0-6. Bit 8 of the ACB register 422 is loaded from the reserve command bit D7 of the MCB register 416 whereas bit 9 of the ACB register is loaded with a "R/D" bit indicative of a read only (R) operation or a duplex (D) input/output operation as dictated by the type of instruction being executed by the master microprocessor 300. Consequently, the ACB register 422 contains the necessary byte and channel selection bits supplied by the MCB register and the Area Command Byte is transmitted prior to the actual Data Out Byte from the SDO register 418.

The terminology "Area Command Byte" is utilized to refer to all of the bits in the ACB register 422 even though the register is ten bits long. Typically, however, a byte is eight bits long and in particular, the Data Out Byte is composed of the eight bits L1-L8 stored in the SDO register 418 as shown in FIG. 6. FIG. 6 illustrates the transmission format of data being sent to and from the master unit as would apply, for example, in a typical duplex operation. The Area Command Byte always precedes the Data Out Byte sent from the master I/O interface 4. Upon receipt of the ST bit, each area controller examines the Byte Address C1-C2 for potential selection of a group of eight input lines and eight output lines (the input and output ports). Next, each area controller samples the Channel Select bits CS1-CS3 and compares their value with a three-bit identification value (hard-wired) unique to each area controller. The single area whose unique identification value matches the received channel select value determined by the Channel Select bits CS1-CS3 will remain active and proceed to interpret the data transfer command as an input only or duplex operation and to act upon the Data Out Byte as required. All other areas cease to participate further in the MACS transmission. The active area controller selected transfers the value of the selected group of eight input bits (designated by the Byte Address) to its area input register 450 (see FIG. 4) and shifts this data, as a Data In Byte back to the master unit 1 in a time sequence as illustrated in FIG. 6. As seen therein, the first bit of the Data In Byte is transmitted after the parity bit from the master controller is received in the area controller. The last Data In bit is transmitted while the fifth bit is being received from the Data Out Byte. Consequently, the duplex operation involves the simultaneous transmission and reception of data by the master I/O interface 4. The selected area not only transmits the Data In Byte but also selects the designated group of eight output lines specified by the Data Out Byte received from the master I/O interface 4. Area timing is such that, for duplex operation, the Data In Byte is shifted back to the master unit 1
overlapped in time with the Data Out Byte. An entire duplex transfer requires eighteen shift clocks to be completed as illustrated in FIG. 6.

After the Input Data Byte has been loaded into the SDI register 410 (FIG. 4) the master controller 2 may read the input data by executing a "READ SDI" instruction or alternately "READ SDI AND START TRANSMISSION" instruction. The "READ SDI" instruction completes the I/O operation and transfers the data from the SDI register 410 to the master controller 2 via the master data bus 414. The master I/O interface 4 then waits for the next I/O command. The "READ SDI AND START TRANSMISSION" instruction automatically reinitiates data transfer utilizing the previously established Master Command Byte which remains stored in the MCB register 416. Now, however, the input only mode is selected, e.g. bit R/D of the ACB register is set to "0". In the input only mode, the SDO register 418 contains all zero's inasmuch as it is serially loaded with zero's during a data transfer. The utilization of the "READ SDI AND START TRANSMISSION" instruction is advantageous for rapid multiple readings of input data as required for effective digital filtering of inputs. Typically, for example, software filtering utilizing this rapid multiple reading technique requires three consistent consecutive input data bytes. If three such consistent consecutive bytes are received, the data is taken to be free from error.

The master I/O interface 4 also provides facilities for reading the CCB register 412 and MCB register 416 for interrupt processing and diagnostic purposes.

Table 1 listed below shows the specific addresses utilized by the master microprocessor 300 of the master controller 2 for control and data transfers.

TABLE I ______________________________________ ADDRESS (HEX) READ FUNCTION WRITE FUNCTION ______________________________________ EDFC READ MCB LOAD MCB EDFB READ SDI & LOAD SDO & START I/O START I/O EDFA READ SDI LOAD MCB & START I/O EDF9 READ STATUS WRITE STATUS EFF8 READ CCB NO OP ______________________________________

Simultaneous Area Operation

In addition to communication between the master unit 1 and the specific area controllers 6-14, the master unit 1 may communicate with all of the area controllers simultaneously. To achieve simultaneous communication, the Channel Select bits are set to address 7 (CS3, CS2, CS1=111) in the Master Command Byte. Each area controller recognizes channel 7 as a simultaneous mode transmission and consequently a common data byte may be simultaneously transmitted to each area controller. A common Output Data Byte is thus fed to the same output port in all area controllers as specified by the Byte Address bits C1-C3 (C1-C3=111 is used in practice). Additionally, this procedure allows the master unit 1 to read inputs for more than one area controller with a single I/O transaction. Inasmuch as the input lines are "ORed" together into a single serial input register, namely, the SDI register 410, mutually exclusive bit positions are assigned within the common Input Data Byte to the area controller during the simultaneous mode transmission. All bit positions within the common Input Data Byte not specifically assigned to an area controller are strapped to a value of "0" to avoid interference at the master unit 1. The simultaneous area operation may be utilized, for example, to effect a pseudo-interrupt procedure which is effectively a polling of various input data lines to the master unit 1 from each (or any desired number) of the area controllers. The master microprocessor 300 has a single interrupt line which is actuated by the machine clock signal along channel 370 (FIG. 3). This interrupt however, initiates a polling of the area controllers under a simultaneous addressing mode (address 7) to sample selected lines of the area controllers as a pseudo-interrupt byte. As a result, a single interrupt line of the master microprocessor 300 may be expanded into a plurality of pseudo-interrupt inputs from the area controllers.

Status Read and Write Commands

In addition to the memory read and write commands listed in Table I, the master microprocessor 300 may execute status read and write instructions (also listed in Table I) to sense and control certain discrete master controller functions. The master microprocessor 300 operating under program control consequently may execute read and write memory reference instructions to address X'EDF9'. Data bytes transferred across the master data bus 414 during status read and write operations are called Master Status Read Bytes and Master Status Write Bytes respectively. The function of each bit in the Status Bytes is set forth in Tables 2, 3 and 4 below.

TABLE 2 __________________________________________________________________________ Master Status Read Byte MASTER DATA BUS BIT POSITION BIT NAME FUNCTIONAL DESCRIPTION OF BIT __________________________________________________________________________ 7 CLKFT Clock Fault; when set indicates that no shift clock is being transmitted to the areas. If this FLAG is set, the software will inspect bit 6 to determine the polarity of the clock. 6 ASHFTCLK Area Shift Clock State; direct indication of the state of the CLOCK output to the area con- trollers. 5 -- 4 -- 3 -- Not defined 2 -- 1 -- 0 HOLD Transmission incomplete. Equals "1" only when transmission is in progress. __________________________________________________________________________

TABLE 3 __________________________________________________________________________ Master Status Write Byte MASTER DATA BUS BIT POSITION BIT NAME FUNCTIONAL DESCRIPTION BIT __________________________________________________________________________ 7 CLKEN When set to "0", disables the clock to all area controllers. (Forces clock low). When set to a "1", enables the clock to each area controller. 6 -- Not defined. 5
RC3 Receiver Control Bit 3 4 RC2 Receiver Control Bit 2 3 RC1 Receiver Control Bit 1 RC3, RC2, RC1 are defined in Table 4. 2 CFTOK Area C/F Test OK Flag. When set to a "1", causes the Area C/F test passed light (LED) to be on, when set to a "0", extinguishes the light. 1 MTOK Master Test OK Flag. When set to a "1", causes the "Master test pass" light (LED) to be On, when set to a 0, extin- guishes light. 0 PARTIY When set to a "1", creates parity error in the parity bit transmission, by complementing correct parity. When set to a "0", correct parity is generated. __________________________________________________________________________

TABLE 4 ______________________________________ Master Status Write Byte- Receiver Control Bits RC3 RC2 RC1 Input Selected ______________________________________ 0 0 0 The `ORed` serial data input lines from all areas is selected. This setting is for normal MACS operations. 0 0 1 The serial data input line from the single . . . Area specified by the RC bits (Area 1, . . . 2 . . . 6) is selected. These RC settings . . . are test modes to isolate a failing Area Controller. 1 1 1
The serial data output line from the Master SDO/ACB registers is selected. This is a master turnaround test mode to isolate Master failures. At the com- pletion of a serial transmission in this mode, the SDI/CCB registers will contain the contents of the SDO/ACB registers. ______________________________________

Master Controller

A more detailed description of the master I/O interface 4 and the various area controllers and their interconnection in the Master/Area Communication System is set forth in FIGS. 7-27. The master I/O interface 4 is connected to the master controller 2 by means of the tri-state master system bus 308 which comprises sixteen address lines (A00-TS through A15-TS), eight data lines D0-TS through D7-TS) and a plurality of control or status lines to be set forth hereinbelow. As indicated in FIG. 7, the address and data lines coming from the tristate master system bus 308 are passed through buffers 800 to provide two-level logic signals for the master I/O interface 4. Various of the signals are inverted as for example the not interrupt acknowledge signal (NINTAIO-TS) which becomes the interrupt acknowledge I/O signal (INTAIO) for use in the master I/O interface 4 logic circuitry. The various control signals are derived from the master controller 2 as explained in detail in the aforementioned copending application entitled "Direct Memory Access for Refresh of a Programmable Control Machine". Most of these signals are derived from the Intel 8080A-2 microprocessor and reference is made to the Intel Users Manual dated September
1975 for detailed description thereof.

A brief description of the various control signals from the master controller 2 is set forth herein. In the following description the letter N preceeding a signal neumonic is indicative of the logical inverse signal or the "bar" signal. Thus, the NDBIN signal is low, and the DBIN signal is high when data is loaded into the data lines D0-D7 of the microprocessor 300.

NRESET-TS is a logical 0 whenever the system is being reset as for example during a power up or initialization process. The NERSET signal is fed to the various shift registers used throughout the master I/O interface 4 and is likewise fed to the microprocessor 300 after the power supplies have settled during an initial power-on operation. In effect, this reset signal is derived from the power normal signal along line 316 of FIG. 3.

The NMEMWRITE-TS and NMEMREAD-TS signals are effectively the memory read and memory write signals utilized in the Intel 8080 CPU during the status portion of the machine cycle. The memory read information is effectively the D7 status bit whereas the memory write signal is effectively D1.multidot.D4. The microprocessor 300 is utilized in a memory mapped I/O architecture such that all I/O considered in the memory address space of the CPU.

The NWR-TS signal is the not write signal from the microprocessor 300. The NINTAIO-TS signal is the not interrupt acknowledge signal derived from the DO status bit of the status word for the master microprocessor clocked by the microprocessor phase 1 clock (PH1) and enabled by SYNC. The SYNC signal is generated by the microprocessor at the beginning of each machine cycle and is used to synchronize the master I/O interface and peripheral circuits. The NREADYEN-TS (not ready enable) signal is derived from the microprocessor and indicates that the address lines have settled on the master system bus and the read signal to the CPU may be generated if desired. The NDBIN-TS signal is derived from outputs of the microprocessor and indicates that the master data bus is in the data input mode.

Master I/O Interface

The master I/O interface 4 comprises an ACB register 422, MCB register 416 and SDO register 418. These three registers are shown in greater detail in FIG. 8 wherein the ACB register 422 is fabricated, for example, by means of the series combination of an eight bit register 850 and a four bit register 852. The four bit register output line 854 is connected to the serial input line of the eight bit register 850 so that an effective twelve bit parallel input/serial output register may be formed. In effect, only ten bits of this effective twelve bit register are utilized consistent with the area command byte length as shown in FIG. 5. By way of example, the eight bit shift register may be model No. 74166 (Texas Instrument SN 74166) and the four bit register may be model No. 74194. The various clock signals and strobe signals utilized to operate the shift registers are derived from logic circuitry to be discussed hereinbelow. Effectively, however, registers 850 and 852 are operated to parallel load data from the MCB register 416 and to serially shift this data out along the master data out line 425. The Area Command Byte and Data Out Byte are encoded by phase encoder 840 comprising exclusive OR gate 842 and inverter 844. The clock input to exclusive OR gate 842 is the area shift clock pulse from clock generator 426. The data is phase encoded to minimize adverse temperature effects and noise on the fiber optic link, driers and receivers. As a result of the phase encoding, a transmitted logical 1 is in phase with the area shift clock whereas a logical 0 is out of phase.

The MCB register 416 is also shown in FIG. 8 to comprise two four bit shift registers 856 and 858, each, for example, model 74194 and operable in a parallel in/parallel out mode. The outputs of shift registers 856 and 858 are shown connected to various input lines of the ACB shift registers 850 and 852. The inputs for the MCB register 416 are the data lines D0-D7 from the master data bus 414 (via puffers of FIG. 7). The parallel in/parallel out operation of the four bit shift registers 856
and 858 is achieved by holding the mode control lines S0 and S1 to a logical "1" state by means of a conventional pull-up resistor network (indicated in the drawing by +V) which is also utilized to maintain the clear (CLR) input high (logical "1"). Consequently, input data is fed to the output lines of shift registers 856 and 858 upon a positive transition (low to high) of the input clock signal "NLDMCB".

The SDO register 418 is also shown in FIG. 8 to consist of an eight bit shift register 860, model No. 74166, operable in a parallel load/serial output mode. The output of shift register 860 is fed to the input of four bit shift register 852. The various clock signals utilized to load and shift the ACB register 422, MCB register 416 and SDO register 418 are explained more fully below. It may be seen however, that bits D0-D7 from the master data bus 414 are loaded into the MCB register 416
and are subsequently parallel loaded into the ACB register 422. With reference to eight bit register 850 of the ACB register 422, the start transmission (ST) bit of shift register 850 is loaded with a high or logical 1 signal from a pull up network into bit position zero. The following six data bits in shift register 850 are loaded from the MCB four bit shift registers 856 and 858. Specifically, the Byte Address bits C1-C3 and the Channel Select bits CS1-CS3 are connected to the inputs of the eight bit shift register 850. A parity signal is also shown fed to an input of eight bit register 850 and derived from a parity generator set forth hereinbelow. The parity bit position occupies the seventh bit position in the ACB register. The eighth bit position is the reserve command bit presently not utilized and is supplied by the four bit register 858 of the MCB register 416 into register 852. The ninth bit position of the ACB register is the "R/D" bit which designates the read (R) or duplex (D) mode of transmission.

It may similarly be seen that the input of the SDO register 418 is simply the data bits D0-D7 from the master data bus 414. The clock inputs to the eight bit register 860 ensure that the SDO register captures the Data Out Byte forming the second word of the transmission sequence whereas the first word or Area Command Byte is captured first by the MCB register 416 and subsequently loaded into the ACB register 422. The serial input terminal S1 of the SDO register 418 is grounded such that bit zero's are serially loaded and shifted into the SDO register during a serial shift operation. Consequently, when the SDO output data byte is shifted into the ACB register 422, the SDO register 418 will simultaneously be loaded with zero's.

The loading and shifting of shift register 860 is controlled, in part, by means of logic circuit 862 which comprises inverter 864, NAND gate 866 and NOR gate 868 as shown.

On the input side for receiving data from the various area controllers, the master I/O interface 4 comprises a multiplexer 406, SDI register 410 and CCB register 412. These elements are shown in greater detail in FIG. 9. The data-in lines from the area controllers are first buffered in buffer 870 (model No. 8097) and fed to an OR gate 404 (FIG. 4) consisting of NOR gates 872 and 874 having outputs connected to the input of a NAND gate 876. The output of NAND gate 876 is termed "AOREDDATA" indicating that it is the area "ORed" data, and this signal is fed as one input to multiplexer 406. Additional inputs to the multiplexers 406 are supplied from the individual area data lines and are identified as "ADATAIN1" through "ADATAIN6". Four additional inputs to the multiplexer 406 are shown. One input is simply the master data out MDO signal from the master data out line 425 via 430 which is utilized for turn-around testing, and the remaining three inputs to multiplexer 406 serve as a mode selective code for multiplexer 406. These three bits are simply the Receiver Control bits RC1-RC3 defined in Table 4. In normal operation these bits are 0 and the "ORed" data is selected. The multiplexer 406 may for example be model No. 74151 wherein the strobe signal is grounded and the inverted output data terminal w is utilized.

The output of multiplexer 406 appears on line 878 and is designated "NSDATAIN", the not selected data in signal. The NSDATAIN signal is inverted by means of NOR gate 880 conditioned by a load delay "LDDLY" signal to be explained more fully below. The selected data input signal, SDATAIN, is fed to the input of SDI register 410 illustrated in FIG. 9 as an eight bit shift register 882. Register 882 may, for example, be model No. 74164 utilized in two modes: a serial in/serial out mode and a serial in/parallel output mode as required. Eight bit register 882 outputs data to the CCB register 412 which comprises two additional eight bit registers 884 and 886, each for example, model No. 74164. The outputs of eight bit register 882 of SDI register 410 are designated SDI-0 through SDI-7 indicative of the eight serial data-in bits. Likewise, CCB register 412 has outputs indicated as CCB0 through CCB9 corresponding to the ten bits in the Area Command Byte. Effectively, the CCB register is utilized during turn-around operations to check the bits in the ACB register 422. Consequently, the CCB register 412 is designed to be ten bits long. The CCB register 412 is also utilized as a counter for designating the end of a simplex or duplex transmission as explained more fully below. The loading and shifting of the SDI register 410 and CCB register 412 are controlled, in part, by means of the logic circuit 888. This circuit comprises a NAND gate 890 which is utilized to clock the eight bit registers 884 and 886. Logic circuit 888 additionally comprises serially connected NAND gates 892 and 894 and inverter 896 which are utilized to reset the eight bit registers 882, 884 and 886.

It is seen that the overall structure of the master I/O interface 4 permits the utilization of a relatively simple dedicated hardward interface which is both interruptable and restartable and able to handle all of the I/O communication between the master and remote units. With particular reference to Table 1, it is seen that a single dedicated address may perform two functions which are distinct from one another depending upon whether the address is associated with a read or write function of the master microprocessor. The memory mapped or extended I/O operation of the master microprocessor 300 treats these dedicated addresses as memory addresses. Status lines on the master microprocessor are fed to decoding circuitry described in detail below which enable proper read or write treatment of the data appearing on the data lines. The single master I/O interface is utilized to communicated with all area controllers. In order to properly handle interrupts, the contents of the MCB register
416 may be stored upon receiving an interrupt so that the stored contents may be reinserted into the MCB register after the interrupt has been service. In this manner communications may be restarted between the master and area units. A specific example of utilizing the instructions in Table 1 is given below.

If data is to be output to be designated remote controller, a write function is made to address EDFC (LOAD MCB). If an interrupt is now received the master microprocessor performs a read function to the same address, namely, address EDFC, to store the contents of the MCB register. After servicing the interrupt the MCB is again loaded followed by load of the SDO register and start transmission, e.g. write to address EDFB. The insuing duplex mode may be used, for example, during psuedo-interrupt operation. After the SDO register has been loaded any further interrupts will not effect output data transmission inasmuch as such transmission is independent of the master microprocessor. The separate hardware implementation of setting the R/D bit relieves the master microprocessor in controlling the serial data out sequence and thus frees it to perform other tasks.

During a data read operation it is also possible to receive interrupts. A write to address EDFA (read only mode) may be performed to request data from a remote controller. Prior to receiving the information from the remote controller (which may take, for example, on the order of some 20 microseconds), an interrupt may be received so that the master microprocessor will not have time to wait for and store the contents of the SDI register 410. The requested data is simply not received although, again, the contents of the MCB register 416 are saved so that the request may be repeated after servicing the interrupt. During servicing of the interrupt routine different command bytes and data bytes would have been loaded into the MCB and SDO registers respectively. Upon transmitting data from the SDO register, however, zero's are serially loaded therein so that the SDO register is always zeroed after the output data byte is transmitted. Consequently, the reloading of the MCB register is combined in one operation with a start transmission as is done in the write function to address EDFA. Zero data in the SDO register will not adversely effect an area controller particularly inasmuch as the R/D bit is set to the simplex mode.

The reading of the SDI register may be effected by two different read statments to addresses EDFB amd EDFA respectively. The read to the address EDFB initiates the READ SDI AND START I/O instruction which may be utilized for reading the SDI register and automatically requesting an additional input of the same data. This read function is most useful for filtering noisy source information from the remote controllers. A simple reading of the SDI register may be effected utilizng the read function to the address EDFA.

Parity Generator

The parity generator 420 of FIG. 4 is further illustrated in FIG. 10 and is seen to comprise an odd/even parity generator 900, exclusive OR gate 901 and a D-type flip-flop 902. The odd/even parity generator 900 may be, for example, model No.
74180, and provides an output signal along its even sum output line 904. The even sum parity is computed over the input lines 903-910. Line 903 is fed by the R/D signal and is a logical 1 for a duplex mode transmission and a logical 0 for a simplex or read only transmission. Lines 904-906 are fed by bits C1-C3 respectively from the Byte Address portion of the MCB register (outputs of four bit register 856) and input lines 907-909 are fed from the Channel Select bits CS1-CS3 of the MCB register (outputs of four bit register 858). Input line 910 to the odd/even parity generator 900 is supplied by the RC (reserve command) signal from the MCB register 416. The output 904 of the odd/even parity generator 900 is conditioned upon the PARITY FLP (parity flip) signal fed along line 911 to the even input terminal of generator 900 and the logical inverse of this signal which is fed via the exclusive OR gate 901 to the odd input terminal of the generator 900. The second input of the exclusive OR gate is tied to a high voltage or logical 1 signal so that the odd and even inputs to parity generator 900 will always be inverse of one another. The parity flip signal along line 911 is derived from the Status Write Register as will be explained more fully below. The inputs to flip-flop 902 are effectively decodes of the address byte A0-A15 inasmuch as they depend upon whether the transmitted signal is an input only or an input/output transmission. These decode signals are set forth in further discussion below. The output of the parity generator 420 along line 904 is fed as one input to the eight bit shift register 850 of the ACB register 422.

Clock Generator

The clock generator 426 of FIG. 4 is shown in detail in FIG. 11. Two MOS level 2.5 MHz clock signals are supplied from the clock oscillator 310 of the master controller 2 and utilized to operate the master microprocessor 300. Two additional TTL
2.5 MHz clock signals are also provided by oscillator 310 and are designated NPH2-I0 along line 950 and NPH1-I0 along line 952. Each clock signal is fed into a high power driver 954 and 956 which may be, for example, model No. 74H40 so that 2.5 MHz clock signals PH2 and PH1 are provided along lines 958 and 960 respectively. Clock generator 426 is further seen to comprise a dividing network 962 which divides down the 2.5 MHz PH1 clock signal into a 1.25 MHz signal designated "NSHFTCLK" on line 964
and a 1.25 MHz clock signal "SHFTCLK" on line 966. The dividing network 962 comprises a flip-flop 968 (model No. 7474) and two high power drivers 970 and 972 (model No. 74H40). The NSHFTCLK signal along line 964 is fed to NAND gate 974 providing an output clock signal ASHFTCLK corresponding to the area shift clock signal along line 428 (see FIG. 4).

The clock generator 426 further comprises a four bit shift register 976 (model No. 74194 operated with S0 and S1 mode control inputs high) which is clocked by the PH1 signal along line 960 and provides output clock signals synchronized to the PH1
clock and labeled SYNCD, SYNCD1 and SYNCD2 as shown. Additionally, the four bit shift register 976 provides a SHFTCLKDLY signal which is simply a delayed version of the area shift clock signal, ASHFTCLK from line 428. The SYNC signal input to the four bit shift register 976 is derived from the master controller 2 as per FIG. 7. This SYNC signal is tied to the falling edge of the PH2 clock signal in the master microprocessor 300, and the shift register 976 is effective to synchronize this SYNC signal to the PH1 clock. The various outputs of the four bit shift register 976 are utilized for timing and control purposes as explained further below.

The SHFTCLKDLY output signal of the four bit shift register 976 is fed to an inverter 978, NAND gate 980 (conditioned by the ASHFTCLK signal from line 428) to the restart signal of a four bit counter 982 (model No. 74161). The output of counter
982 is utilized to provide a NCLKFT signal along line 984 via an inverted output thereof. The inverse of this signal, namely, the CLKFT signal is the clock fault signal listed in Table 2 and forms part of a Master Status Read byte which is returned to the master microprocessor 300 in response to a memory read to address X 'EDF9'. Consequently, the four bit counter 982 in combination with a memory status read instruction is utilized to determine if the shift clock signal ASHFTCLK (of line 428) is being transmitted to the area controllers.

Shift Controls

The control logic 424 (FIG. 4) is utilized to control the shifting of the input data through the SDI register 410 and CCB register 412. The control logic utilized to accomplish the shifting is shown in detail in FIG. 12 and comprises a four bit shift register 1000 and a second four bit register 1002 (both model No. 74194 for example). These shift registers are utilized as simple flip-flops and the mode control inputs S1 and S0 are tied to logical 1. Consequently, data which appears on the input lines of these registers is fed to the output on the rising edge of the clock signal. Register 1000 is clocked by the PH2 clock signal and produces a F1 signal output whereas register 1002 is clocked by the SHFTCLK signal from line 966 of clock generator 426 (see FIG. 11) and produces a F2 output signal. A number of different clock and control signals are generated by means of the shift control logic of FIG. 12 and these signals are utilized in controlling and clocking the SDI register 410, CCB register 412, SDO register 418 and ACB register 422.

FIG. 12 shows the interconnection of the registers 1000 and 1002 utilizing a NAND gate 1004, NOR gate 1006, inverters 1008, 1010, 1012 and 1014, NOR gate 1016, AND gate 1018, NAND gate 1020 and NAND gate 1022. It may be seen that the shift control logic of FIG. 12 has effectively three control input signals and two external clock signals utilized for its operation. Two of the control signals are the ST or start transmission and SYNC D. The ST signal is fed to the upper input of NAND gate
1004 and results from a decode of the Area Command Byte stored in the ACB register 422. The SYNC D signal is the second input to NAND gate 1004 and is generated from register 976 of the clock generator 426 of FIG. 11. A third input to the shift control logic of FIG. 12 is the CCB0 bit of the eight bit shift register 886 forming part of the CCB register 412 (see FIG. 9). The CCB0 signal is fed along line 1028 to the upper input of NAND gate 1020. The two clock signals are the PH2 clock and SHFTCLK clock. Utilizing the ST, SYNCD and CCB signals, as well as the PH2 and SHFTCLK clock signals, the shift control logic generates a number of control and timing signals as set forth in the timing charts of FIG. 13.

FIG. 13 itself illustrates a functional timing chart for a "LOAD SDO AND START TRANSMISSION" instruction. The graphs in FIG. 13 are drawn beginning at the last machine cycle of the instruction so that the address has already been fetched from memory by the CPU, and the master controller 2 is now beginning to initiate a memory write instruction. In FIG. 13, for example, graphs (a) and (b) represent the two phase clock signals PH1 and PH2 each at 2.5 MHz from the master controller 2. Graph (c) is the SHFTCLK, or shift clock pulse of 1.25 MHz from the clock generator 426. Graph (f) illustrates the SYNCD pulse which is seen tied to the rising edge of PH1. Graphs (n) and (o) represent signals F1 and F2 as outputs from registers 1000 and
1002 respectively. Registers 1000 and 1002 operate as pairs of flip-flops to synchronize the F2 signal with the rising edge of the SHFTCLK signal. The rising edge of F2 is utilized to generate HOLD, HLDDLY, LOAD, and LDDLY signals which are in turn utilized to shift data in the SDI register 410, CCB register 412 as well as various of the output registers. Consequently, it is essential that the rising edge of signal F2 be synchronized with the rising edge of the shift clock signal SHFTCLK. Inasmuch as the shift clock signal is in itself divided down from the PH1 clock signal it is necessary to insure that F2 is synchronized to the rising edge of the shift clock, SHFTCLK signal, as opposed to the falling edge. Consequently, NAND gate 1022, NOR gate 1006, and inverter 1014 insure that F1 will not reset until after F2 is set. Essentially, F1 is set by a logical 1 provided from NOR gate 1006 which results from the simultaneous occurrence of a start transmission, ST, pulse and the SYNCD pulse. F1 remains set even after the SYNCD pulse goes low inasmuch as F2 is not yet set so that its output is low. The low F2 signal is inverted via inverter 1014 and fed as a high to the upper input of NAND gate 1022. The lower input of NAND gate
1022 is also high inasmuch as F1 is now set. Consequently, after F1 has set and prior to the setting of F2, NAND gate 1022 provides a low output which keeps signal SF1 on input line 1024 to register 1000 as a logical 1. This condition remains until F2
is itself set during an upward transition of the SHFTCLK signal as the clock input to register (flip-flop) 1002. Once F2 is set the upper input of NAND gate 1022 goes low providing a high at its output which is fed via NOR gate 1006 to reset the signal SF1 which resets register 1000 on the next upward transition of PH2. As a result, signal F2 is synchronized to the rising edge of the shift clock signal (SHFTCLK).

The setting of signal F2 to a logical 1 produces a high for the SHOLD signal (set hold) at the output of AND gate 1018, e.g. see graph (p). Consequently, F2 and SHOLD are synchronized to transition from a low to a high state at the same time, namely, on the rising edge of the shift clock pulse SHFTCLK. AND gate 1018 has an upper input fed by the output of NAND gate 1020. The upper input of NAND gate 1020 is fed from the CCB0 bit of register 886 via a line 1028. This bit is a 0 after a power-up transition and will remain 0 until the end of a transmission wherein it will transition to a high level. In fact, a marker 1 bit initiated by LDDLY signal to NOR gate 880 (FIG. 9A) is shifted through registers 882 and 884 into registers 886. The appearance of the 1 in bit CCB0 is used to mark the end of a transmission. The initial 0 value of CCB0 insures that the output of NAND gate 1020 is a 1 so that the output of AND gate 1018 will transition to a high value upon the logical high appearing at the lower input thereto. The SHOLD signal is seen to provide an input to register 1002 providing a HOLD signal on the next rising edge of clock SHFTCLK. The HOLD signal is in turn fed back to an input of register 1002 to provide a LOAD signal at the output thereof on the next shift clock pulse (see graphs (c), (q) and (s) of FIG. 13). Both the HOLD and LOAD signals are in turn fed to register 1000 and are utilized to provide hold delay (HLDDLY) and load delay (LDDLY) signals upon a positive transition of the PH2 clock signal (see graphs (b), (r) and (t) of FIG. 13).

The relationship of F1 to the HOLD, LOAD, HOLD DELAY and LOAD DELAY signals is clearly seen in the graphs (n) through (t) of FIG. 13. It is noted that the HOLD and LOAD signals are each tied to the rising edge of the shift clock pulse whereas the HLDDY and LDDLY signals are tied to the rising edge of PH2 which immediately follows the rising edge of the shift clock pulse. The hold delay and load delay signals are utilized in FIG. 9 to operate the loading and shifting of the SDI register 410
and CCB register 412 as explained more fully below.

FIGS. 14A and 14B illustrate additional logic circuitry utilized to provide further clock signals used to control the shift registers of the master I/O interface 4. FIG. 14A details the generation of the clock signal CCB1+2+3 and comprises a NOR gate 1040 and inverter 1042. The CCB1+2+3 clock signal is essentially conditioned by bits 1 or 2 or 3 of the CCB register 412 identified as bits CCB1, CCB2 and CCB3 respectively. When any one of these bits is a logical 1, a logical 0 is generated at the output of NOR gate 1040 and consequently the output of inverter 1042 goes high. The CCB1+2+3 clock signal is fed as an input to register 1002 of FIG. 12 and generates a "DISSDICLK" (disable SDI clock) signal on the rising edge of the shift clock pulse (SHFTCLK). The DISSDICLK signal is in turn fed to an input of register 1000 and is utilized to generate a "DISSDICKDLY" or delayed DISSDICLK signal on the rising edge of PH2. The DISSDICLKDLY pulse is utilized in FIG. 14B to disable the CLKSDI pulse (by keeping it high) which clocks the DSI register 410 (eight bit shift register 882 of FIG. 9) during a master turnaround test mode of operation.

As seen in FIG. 14B, the CLKSDI clock signal for shifting the SDI register is supplied by the output of an OR gate 1050 which has a lower input fed by a CLK CCB/ACB clock signal and an upper input fed by a "DSCLK" signal from an AND gate 1052. The lower input of AND gate 1052 is fed from the DSISDICKDLY signal from register 1000 (FIG. 12) initially generated from the CCB1+2+3 signal of FIG. 14A. The upper input of AND gate 1052 is fed by the output of a NAND gate 1054 whose inputs are tied to the receiver control bits RC1-RC3 of Tables 3 and 4. The output of NAND gate 1054 will be a logical 1 (normal ORed area data operation) unless the receiver control bits are all in a logical 1 state indicating a turn-around test mode of operation. Consequently, during a normal operation in which the data from the area controllers is wire ORed or in which a particular area controller is selected, the upper input to AND gate 1052 will be a logical 1. As a result, the output of AND gate 1052 will be
1 after DISSDICLDDLY goes high thereby inhibiting further transitions of CLKSDI, thus stopping the SDI shift.

The reason for providing a separate CLKSDI pulse to SDI register 410 is simply that the amount of shifting required for the master turn-around test mode of operation is different (larger) than the amount required during normal operations when data is received from the area controllers (see FIG. 6). If in fact the turn-around mode is utilized, then the upper input of AND gate 1052 is low (FIG. 14B) so that the output of AND gate 1052 is low and the SDI register clock is the same as the CLK CCB/ACB clock. In this case, the turn-around bit stream will be shifted through the CCB and SDI registers stopping when CCB0 goes to a logical 1. If, however, the normal mode of operation is utilized, then the output of NAND gate 1054 is high and DISSDICLKDLY (which depends upon CCB1+2+3) will be high whenever a logical 1 is in CCB1 or CCB2 or CCB3 thereby producing a logical 1 at the output of AND gate 1052. Thus, CLKSDI cannot go from low to high but is held at a high state effectively disabling the clock pulse to SDI three SHFTCLK pulses sooner than in turn-around mode. The result, however, is that the Data-In Byte from the selected area controller is now present in bits SDI0-SDI7 as desired at the end of a transmission.

Address Decoder

The address decoder which forms part of the control logic 424 of FIG. 4 is illustrated in detail in FIG. 15. Effectively, incoming address lines are decoded to ascertain whether the master I/O interface 4 is required to participate in data control for the instruction being executed. The address range specifically reserved for the master I/O interface and its I/O operations as well as its status read and write operations are HEX addresses EDFC-EDF8 (Table 1). If the address bus contains an address within this range the address decoder will provide an output signal which will permit the appropriate read or write operation to take place within the master I/O interface 4.

The address decoder comprises NAND gates 1072 and 1074 having the respective address line inputs as shown and providing a logical 0 output only if all of the respective inputs are a logical 1. The address decode range is determined by means of the NAND gates 1072-1074 as well as NOR gate 1078. If the decode address is that of the master I/O interface 4 then the output of NOR gate 1078 goes to a logical 1 represented by a high for the signal AHERE. The AHERE signal is then utilized to provide a NREADY-TS signal to the master microprocessor 300 of the master controller 2. This signal is effectively the "READY" signal for the CPU indicating that data in the input registers (such as the SDI register 410) is ready to be read by the master microprocessor 300. The NREADY-TS signal is conditioned by logic circuit 1080 comprising NOR gate 1082, AND gate 1086, NAND gate 1088, NAND gate 1090 and tri-state driver 1092. Input to NOR gate 1082 is provided by the NMEMREAD and NMEMWRITE signals from the master controller 2 and are effectively the memory read and memory write signals provided during a status indication along the data lines of the master microprocessor 300. The output of NOR gate 1082 is provided to the lower input of AND gate
1086 whose upper input is fed by a signal from NOR gate 1078 indicating that the address is that of the master I/O interface 4. A true output of AND gate 1086 is indicative of a memory cycle to an address allocated to the master I/O interface 4, and this output is fed as an upper input to the three input NAND gate 1088. The second two inputs to NAND gate 1088 correspond to the ready enable signal from the master controller 2 (FIG. 7) and a power normal signal from the power supply 312 (FIG. 3). These two signals, the ready enable signal and power normal signal are also utilized together with the interrupt acknowledge-I/O signal, INTAIO (FIG. 7) as inputs to NAND gate 1090. NAND gate 1090 controls tri-state driver 1092 which is tied to the output of a second tri-state driver 1094 supplying the NREADY-TS signal to the master microprocessor 300. A logical high on the inverted input pin to the tri-state driver effects a high impedance output of the driver, and a 0 on the inverted input pin will enable the output of the driver to logically follow the input signal. Logic circuit 1080 consequently insures that the ready signal sent to the master microprocessor 300 occurs only if power is stabilized (power normal signal true) and the master I/O interface 4 has been properly addressed and received both the ready enable signal and the interrupt acknowledge-I/O signal from the master microprocessor 300.

The register decoder is illustrated in FIG. 16 and also forms part of the control logic 424 of FIG. 4. The register decoder is utilized to provide control signals indicative of an address read or address write instruction involving the master I/O interface 4. These control signals are fed to control the loading and shifting of the various registers of FIGS. 8, 9, 10 and 12.

The address decoder of FIG. 16 is seen to comprise NAND gates 1120-1126, inverters 1128 and 1130, NOR gates 1132-1136, OR gates 1138 and 1140 and demultiplexer 1142. The demultiplexer 1142 may be, for example, model No. 74155 and is effectively two demultiplexers, each being a one line-to-four line decoder. The upper input line carrying signal NENLD (not enable load) is passed to one of the selected upper four output lines, and the second input line carrying the NENRD (not enable read) signal is used to feed one of the lower four output lines. The particular output line is governed by the select inputs which are connected to the address bits AO1 and AO0 of the address bus (via buffers of FIG. 7). The demultiplexer is seen to discriminate between two types of signals, those involving memory read functions and those involving memory write functions. In both cases, the memory read and memory write signals are conditioned by the AHERE signal indicative of a master I/O interface address provided from NOR gate 1078 of FIG. 15. The upper three outputs of the demultiplexer 1142 are generated as decodes for the instructions LOAD SDO AND START TRANSMISSION, LOAD MCB AND START TRANSMISSION and WRITE STATUS. The lower four output signals from the demultiplexer 1142 are generated as decodes for the instructions READ CCB, READ STATUS, READ SDI, and READ SDI AND START TRANSMISSION. In reference to Table 1, the above enumerated seven instructions leave only two address decodes undetermined. These instructions are the READ MCB instruction and the LOAD MCB instruction. Decodes for these instructions are provided by NAND gates 1125 and 1126 respectively. It is noted that one input to each of these NAND gates is supplied by the address line A02 and the other input is provided by the respective read enable or load enable (write enable) signal from inverters 1128 and 1130 respectively.

The ST pulse is generated at the output of NOR gate 1134 and is generated as a consequence of either of three signals being low as follows: (1) NLDSDO+ST, the not LOAD SDO AND START TRANSMISSION, (2) NLDMCB+ST, the not LOAD MCB AND START TRANSMISSION, and (3) NRDSDI+ST, the not READ SDI AND START TRANSMISSION. Consequently, whenever an instruction involving a start transmission is executed the ST signal goes high and the signal is utilized as an input to NAND gate 1004 as seen above in FIG. 12 to initiate the control and clocking of the input and output registers of the master I/O interface 4. Other control signals are generated by the register decoder of FIG. 16. These signals include the not load SDO signal, NLDSDO, fed from OR gate 1138 to the lower input of NOR gate 868 of logic circuit 862 (FIG. 8), and the not load MCB signal NLDMCB from OR gate 1140 fed to the clock input of registers 856 and 858 of MCB register 416 (FIG. 8). NRDMCB (not read MCB) and NLDSTAT (not load status) are also generated in FIG. 16 and these signals are used in status read and write circuitry as set forth hereinafter.

Status Input and Output Control

The master I/O interface 4 may be utilized to provide status information to the master microprocessor 300 and additionally to write certain status data for controlling the operation of the MACS system. FIG. 17 illustrates a status write register
1150 which comprises two four bit shift registers (model No. 74194) utilized to store status bytes from the master data bus 414. Bits D7-D4 are fed to four bit register 1152 and bits D3-D0 are fed to four bit register 1154. Each register is clocked to load data bits D0-D7 from the data bus by means of the NLDSTAT signal (the load status signal) coming from NOR gate 1136 of the register decoder shown in FIG. 16. The select terminals S0 and S1 of each of the registers 1152 and 1154 are maintained at a logical 1 level so that data on the output lines follows the input line data on a positive transition of the clock pulse. Each register 1152 and 1154 is reset initially by the NRESET signal during a power-up sequence. The output of registers 1152 and
1154 are seen to correspond to Table 3 wherein the various status write bits are defined. The CLKEN signal along line 1156 is fed to NAND gate 974 of FIG. 11 and inhibits the area shift clock signal ASHFTCLK along line 428 to the area controllers if CLKEN is a logical 0.

Receiver control bits RC3-RC1 are provided on output lines 1158a-c of registers 1152 and 1154, and are fed to the register select inputs of multiplexer 406 of FIG. 9. The signal CFOK along line 1160 and MTOK along line 1162 are used in area controller and master controller diagnostic tests and are fed to power LED displays on a control panel (not shown) to provide the operator with an indication of a successful diagnostic test as controlled by the diagnostic software. The parity flip (PARITYFLP) signal along line 911 is fed to an input of odd/even parity generator 900 of FIG. 10 as set forth above. The values in registers 1152 and 1154 drive the output lines until these registers are reset when the NRESET pulse goes to 0 or until a new Status Write Byte is generated along the data lines D0-D7 and loaded into the status write register via the NLDSTAT decode from the write status instruction.

The status read function is implemented by means of an input multiplexer and control logic as shown in FIG. 18. In addition to status information, the input multiplexer and control logic of FIG. 18 is used to effect the reading of the MCB register 416, SDI register 410 and CCB register 412. FIG. 18 illustrates an input multiplexer 1170 coupled to control logic 1172 and tri-state driver arrays 1174 and 1176. The output of each tri-state driver array is connected directly to the tri-state master data bus as indicated by data lines DO-TS through D7-TS. The input multiplexer 1170 essentially comprises eight separate multiplexers, each a four-to-one data selector designated 1184a-1184h. The eight data selectors may be implemented by four model no. 74153 multiplexers operable with the input strobe lines tied to ground and the input select terminals connected to the control logic 1172 via lines 1180 and 1182. Line 1180 controls the select A multiplexer input whereas line 1182 is connected to the select B input. Data selector 1184a has four inputs indentified as RC (reserve command), CLKFT, SDI-7 and CCB9. These four inputs correspond to (1) the reserve command bit of the MCB register (see FIGS. 5 and 8); (2) the CLKFT bit of the Status Read Byte (see TABLE 2) derived from line 984a of the clock generator 426 of FIG. 11; (3) the SDI-7 or seventh bit of the SDI register 410; and (4) CCB9 or the ninth bit of the CCB register 412. In a similar fashion data selector 1184b has four input signals corresponding to bit CS3 of the MCB register, clock signal ASHFTCLK (area shift clock) from line 428 of the clock generator, SDI6 data bit from the SDI register and CCB8 data bit from the CCB register. Similarly labeled lines are shown for the remaining data selectors 1184c-1184h so that the groups of lines allow an input read operation from the MCB register, status read operation, SDI register and CCB register repsectively.

Control logic 1172 comprises NOR gates 1190 and 1192 and NAND gates 1194 and 1196. NOR gate 1190 provides an output decode for the select A terminal of the multiplexers 1178 whereas NOR gate 1192 provides the select B input signal. The input data enable function is provided by the NENINDATA signal as an output