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United States Patent
4162536
Morley
July 24, 1979
Title
Digital input/output system and method
Abstract
A parallel process controller capable of expandable, parallel operating multi-function control of processes. The process controller comprises programmable command memory modules, data memory modules, an input/output system, a programming panel, and a high speed data bus (N-bus). The input/output system comprises input/output channels for intercommunication between the process controller and the external world. This intercommunication is repetitively updated for each input/output channel in an error-free manner that operates autonomously with respect to the remainder of the process controller. Each input/output channel incorporates a first dedicated area of a dedicated data memory module in which information is read and a second dedicated area of the data memory module in which information is written. The information read from the first dedicated area is transferred to external devices via a local modem-remote modem combination. Likewise, data written into the second dedicated area of the dedicated data memory module is transferred from the external device via the same remote modem-local modem combination.
Inventors:
Morley; Richard E.
(Mason,
NH
)
Assignee:
Gould Inc., Modicon Div.
(Rolling Meadows,
IL
)
Appl. No.:
873407
Filed:
January 30, 1978
Current U.S. Class:
714/18
714/822
Field of Search:
364/2MSFile,9MSFile 340/146.1BA
U.S. Patent Documents
3805234
April 1974
Masters
3910322
October 1975
Hardesty, Jr. et al.
Primary Examiner:
Shaw; Gareth D.
Assistant Examiner:
Bartz; C. T.
Attorney, Agent or Firm:
Mattern, Ware, Davis & Stoltz
Parent Case Text
This is a division of application Ser. No. 646,412 filed Jan. 2, 1976, now abandoned.
Claims
Having described the invention, what is claimed is:
1. A method of sending selected output data from a local location to a remote location and sending selected input data from the remote location to the local location, comprising the steps of:
(1) the local location selecting and sending output data to the remote location;
(2) the remote location receiving and echoing back to the local location the output data sent in step 1;
(3) the local location receiving and error-checking the echoed selected output data with that sent in step 1;
(4) if an error is detected in step 3, returning to step 1;
(5) if no error is detected in step 3, the local location generating and sending to the remote location a first signal indicating desired selected input data;
(6) the remote location receiving and echoing the received first signal to the local location;
(7) the remote location obtaining the desired selected input data;
(8) the local location receiving the echoed first signal and error-checking it with the first signal sent in step 5;
(9) if an error is detected in step 8, returning to step 5;
(10) if no error is detected in step 8, assuming at the local location that a successful transfer of output data from the local location to the remote location has occurred;
(11) the local location generating and sending a second signal to the remote location, the second signal requesting transferral of the input data obtained in step 7;
(12) the remote location receiving the second signal and sending to the local location the desired selected input data obtained in step 7;
(13) the local location receiving and storing the requested input data;
(14) the local location generating and sending a third signal requesting the transferral of the same input data requested in step 11 to the remote location;
(15) the remote location receiving the third signal and echoing back the desired selected input data to the local location;
(16) the local location receiving and storing the desired selected input data sent in step 15 and error-checking this data with that received in step 13;
(17) if an error is detected in step 16, the local location substituting the data received in step 16 for that received in step 13 and returning to step 14; and
(18) if no error is detected in step 16, the local location assuming a successful transfer of input data has occurred from the remote location to the local location and returning to step 1.
2. A method of sending data as defined in claim 1, wherein the local location at step 1 further generates a fourth signal indicating whether the output data there sent has been previously sent to the remote location and wherein the remote location generates a fifth signal along with the input data sent to the local location in step 12, the fifth signal indicating whether the desired selected input data has been previously sent to the local location.
3. A method of sending data as defined in claim 2, wherein the remote location obtains desired selected input data from the remote external world and obtains this data by generating a data request signal informing the remote external world to load data into a data buffer associated with the remote location.
4. A method of sending data as defined in claim 3, wherein no new input data is requested from the remote external world after receipt by the remote location of the second signal.
5. A method of sending data as defined in claim 4, wherein the local location communicates with a local external world and wherein the local location obtains the selected output data from the local external world and transfers to the local external world received selected input data from the remote external world.
6. A method of sending data as defined in claim 5, wherein the fourth signal is communicated from the remote location to the remote external world along with the output data received from the local location so as to indicate to the remote external world the status of the output data and further wherein the fifth signal is communicated from the local location to the local external world to indicate the status of the communicated input data received from the remote location.
7. A method of sending data as defined in claim 6, wherein the communicating of output data from the local external world to the local location and of input data from the local location to the local external world occurs for only a short predetermined length of time during which no transferral of data or signals from the local location to the remote location or from the remote location to the local location occurs.
8. A method of sending data as defined in claim 7, wherein the transferral of output data from the local external world to the local location and input data from the local location to the local external world occurs after step 18 but before returning to step 1.
9. A method of sending data as defined in claim 3, wherein the local location communicates with a local external world and wherein the local location obtains the selected output data from the local external world and transfers to the local external world received selected input data from the remote external world.
10. A method of sending data as defined in claim 9, wherein the fourth signal is communicated from the remote location to the remote external world along with the output data received from the local location so as to indicate to the remote external world the status of the output data and further wherein the fifth signal is communicated from the local location to the local external world to indicate the status of the communicated input data received from the remote location.
11. A method of sending data as defined in claim 10, wherein the communicating of output data from the local external world to the local location and of input data from the local location to the local external world occurs for only a short predetermined length of time during which no transferral of data or signals from the local location to the remote location or from the remote location to the local location occurs.
12. A method of sending data as defined in claim 11, wherein the transferral of output data from the local external world to the local location and input data from the local location to the local external world occurs after step 18 but before returning to step 1.
13. A method of sending selected output data from a local location to a remote location and sending selected input data from the remote location to the local location, for use of the output data by the remote external world and for use of the input data by the local external world comprising the steps of:
(1) the local location selecting and obtaining output data from the local external world;
(2) the local location entering a data output mode by generating a first header (H.phi.) including "output new word" data indicating whether the obtained output data from the local external world is new data;
(3) the local location sending the first header with the selected output data to the remote location;
(4) the remote location receiving and storing the selected output data and at least a portion of the first header including the "output new word" data and the selected output data;
(5) the remote location echoing the first header and the selected output data received in step 4 back to the local location;
(6) the local location receiving and error checking the echoed first header and echoed selected output data respectively with the first header and selected output data sent to the remote location in step 3;
(7) if an error is detected in step 6, returning to step 3;
(8) if no error is detected in step 6, the local location entering the output verify mode by generating a second header (H1) including data representing addressable desired input data to be sent from the remote location to the local location;
(9) the local location sending the second header to the remote location;
(10) the remote location receiving the second header and then allowing the stored output data and status of the "output new word" data received in step 4 to be used by the remote external world, the remote location storing at least the portion of the second header representing the address of the desired input data and obtaining from the remote external world the data at the desired address;
(11) the remote location echoing the received second header to the local location;
(12) the local location receiving the echoed second header and error checking it with the second header sent to the remote location in step 9;
(13) if an error is detected in step 12, returning to step 9;
(14) if no error is detected in step 12, assuming at the local location that a successful transfer of output data from the local location to the remote location has occurred and the local location entering the data input mode by generating a third header (H2);
(15) the local location sending the third header to the remote location;
(16) the remote location receiving the third header and echoing back to the local location at least the desired input data obtained from the remote external world in step 10 along with "input new word" data indicating whether the obtained input data from the remote external world is new;
(17) the local location receiving and storing the requested input data and the "input new word" data;
(18) the local location entering the data input verify mode by generating a fourth header (H3);
(19) the local location sending at least the fourth header to the remote location;
(20) the remote location receiving the fourth header;
(21) the remote location echoing back at least a portion of the fourth header to the local location along with the desired selected input data and the "new input word" data;
(22) the local location receiving and storing the desired selected input data and the "new input word" data sent in step 21 and error checking these data respectively with the data received in step 17;
(23) if an error is detected in step 22, the local location regarding the data received in step 22 as that received in step 17 and returning to step 18; and
(24) if no error is detected in step 22, the local location assuming a successful transfer of data has occurred from the remote location to the local location and allowing the local external world to use the input data and "new input word" data stored in step 22, and returning to step 1;
whereby output data is obtained from the local external world and is error-free transferred from the local location to the remote location for use by the remote external world with data indicating the newness of the output data and whereby input data is obtained from the remote external world and is error-free transferred from the remote location to the local location for use by the local external world with data indicating the newness of the input data.
14. A method of sending data as defined in claim 13, wherein the input data and output data respectively comprise P and Q addressable lines of data, where P and Q are positive integers.
15. A method of sending data as defined in claim 14, wherein the output data and input data comprise addressable lines of data which are sequentially and repetitively transferred according to steps 1-24.
16. A method of sending data as defined in claim 15, wherein the lines of output data and input data comprise an invariant number of binary bits.
17. A method of sending data as defined in claim 16, wherein the first, second, third and fourth headers each comprise a fixed number of binary bits.
18. A method of sending data as defined in claim 17, wherein each header precedes any output data or input data associated therewith.
19. A method of sending data as defined in claim 18, wherein arbitrary data is generated by the local location along with the third header (H2) and fourth header (H3) and wherein said arbitrary data is sent to the remote location with the third header and fourth header respectively.
20. A method of sending data as defined in claim 19, wherein the echoing of data from the remote location to the local location occurs while the remote location is receiving data from the local location.
21. A method of sending data as defined in claim 14, wherein the input data, output data, and first, second, third and fourth headers comprise binary bits.
22. A method of sending data as defined in claim 21, wherein the local location at step 1 repetitively sequentially selects one of the Q addressable output data lines and wherein the local location at step 8 repetitively sequentially selects one of the P addressable input data lines.
23. A method of sending data as defined in claim 22, wherein the first, second, third and fourth headers comprise at least 16 digital bits, with at least one bit for the state of the "output new word" data or "input new word" data, at least one bit for the complement of the "output new word" data or "input new word" data, at least four bits for the line number of the selected input data line or of the selected output data line, at least four bits for the complement of the line number of the selected input data line or of the selected output data line, at least two bits for a code representing the first, second, third or fourth header, at least two bits for the complement of the header code, and at least one synchronization bit.
24. A method of sending data as defined in claim 14, wherein the local location at step 1 repetitively sequentially selects one of the Q addressable output data lines and wherein the local location at step 8 repetitively sequentially selects one of the P addressable input data lines.
25. A method of sending data as defined in claim 14, wherein integer P equals integer Q.
26. A method of sending data as defined in claim 13, wherein at step 10 the remote location error-checks the received second header and only allows the stored output data received in step 4 to be used by the remote external world if no error is detected in the second header.
27. A method of sending data as defined in claim 26, wherein at step 10 the remote location generates a "data valid" signal when no error is detected in the second header so as to allow the stored output data received in step 4 to be used by the remote external world.
28. A method of sending data as defined in claim 26, wherein at step 10 the remote location obtains data from the external remote world by setting a request new input data signal and wherein this signal is cleared at the remote location in step
16.
29. A method of sending data as defined in claim 13, wherein the echoing of data from the remote location to the local location occurs while the remote location is receiving data from the local location.
30. A method of sending output data from a local location to a remote location and sending input data from a remote location to a local location, for use of the output data by the external remote world and for use of the input data by the external local world, comprising the steps of:
(1) the local location selecting and obtaining output data from the local external world;
(2) the local location generating a first header (H.phi.);
(3) the local location sending the first header with the output data to the remote location;
(4) the remote location receiving the first header and output data and storing at least a portion of the output data;
(5) the remote location echoing the first header and the output data received in step 4 back to the local location;
(6) the local location receiving the echoed first header and output data and error-checking this data respectively with the first header and output data sent in step 3;
(7) if an error is detected in step 6 returning to step 3;
(8) if no error is detected in step 6, the local location generating a second header (H1) including data representing the location of input data to be sent from the remote location to the local location;
(9) the local location sending the second header to the remote location;
(10) the remote location receiving the second header, allowing the stored output data received in step 4 to be used by the remote external world, and obtaining and storing from the remote external world input data represented by at least a portion of the second header;
(11) the remote location echoing the received second header to the local location;
(12) the local location receiving the second header and error-checking it with that sent in step 9;
(13) if an error is detected in step 12 returning to step 9;
(14) if no error is detected in step 12 assuming at the local location that a successful transfer of output data from the local location to the remote location has occurred and generating a third header (H2);
(15) the local location sending the third header to the remote location;
(16) the remote location receiving the third header and echoing back to the local location at least a portion of the received third header and sending the input data represented by at least a portion of the second header obtained fromthe remote external world in step 10 to the local location;
(17) the local location receiving and storing the input data;
(18) the local location generating a fourth header (H3);
(19) the local location sending at least the fourth header to the remote location;
(20) the remote location receiving the fourth header;
(21) the remote location echoing back at least a portion of the fourth header to the local location along with input data represented by at least a portion of the second header;
(22) the local location receiving and storing the input data sent in step 21;
(23) the local location error-checking the input data received in step 22 with that received in step 17;
(24) if an error is detected in step 23, the local location substituting the received input data in step 22 for that received in step 17 and returning to step 18; and
(25) if no error is detected in step 23, the local location assuming a successful transfer has occurred of input data from the remote location to the local location and allowing the local external world to use the input data stored in step 22.
31. A method of sending output data and input data defined in claim 30, wherein the output data and input data comprise addressable lines of data which are sequentially and repetitively transferred according to steps 1-25.
32. A method of sending output data and input data as defined in claim 31, wherein the lines of output data and input data comprise an invariant number of binary bits.
33. A method of sending output data and input data as defined in claim 32, wherein the generating of the first header (H.phi.) includes the generation of "output new word" data representing the first transferral of output data from the local location to the remote location and wherein the remote location at step 17 in addition to echoing back at least a portion of the received third header and sending the desired input data obtained from the remote external world in step 10 further generates and sends "input new word" data representing the first sending of this particular input data to the local location and wherein the remote location allows the remote external world to sense the "output new word" data so as to inform the remote external world that the associated output data is new output data and wherein the local location allows the local external world to sense the "input new word" data so as to inform the local external world that the received input data is new.
34. A method of sending output data and input data as defined in claim 33, wherein the remote location allows the stored output data received in step 4 to be used by the remote external world in step 10 by generating a "data valid" signal at the remote location.
35. A method of sending output data and input data as defined in claim 30, wherein the first, second, third and fourth headers each comprise a fixed number of binary bits.
36. A method of sending output data and input data as defined in claim 35, wherein each header precedes any output data or input data associated therewith.
37. A method of sending output data and input data as defined in claim 36, wherein arbitrary data is generated by the local location along with the third header (H2) and fourth header (H3) and wherein said arbitrary data is sent to the remote location with the third header and fourth header respectively.
38. A method of sending output data and input data as defined in claim 37, wherein the output data and input data comprise an equal number of binary bits and wherein the arbitrary data generated with the second header (H1) and third header (H2) comprise binary bits equal in number to the output data and input data.
39. A method of sending output data and input data as defined in claim 38, wherein the echoing of data from the remote location to the local location occurs while the remote location is receiving data from the local location.
40. A method of sending output data and input data as defined in claim 30, wherein the echoing of data from the remote location to the local location occurs while the remote location is receiving data from the local location.
41. An input/output system for transferring information to and from a remote external device comprising:
(A) an input/output memory for storage of input data received from the remote external device and output data for transferral to the remote external device;
(B) at least one input/output channel interconnected with said input/output memory for receiving from the external device input data and for transferring to the external device output data, said input/output channel incorporating:
(1) a local modem having,
(a) header generating means for generating signals representing the current operating state of the input/output channel,
(b) signal transferring means for receiving and transferring the output data to the remote external device and for receiving and transferring input data received from the remote external device to the iput/output memory, and
(c) error-checking means for insuring the proper transferral and receipt of output data and input data to and from the remote external device;
(2) data communications means interconnected with the local modem for transferring output data and for receipt of input data; and
(3) a remote modem having,
(a) means for receiving header signals and output data transferred by the local modem through the data communication means to the remote modem and for transferral of this output data to the remote external device when verification of error-free transferral of said output data is ascertained,
(b) means for receiving input data from the remote external device, and
(c) signal transferring means for transferring input data and echoing of received output data and header signals to the local modem,
wherein the header generator means of the local modem generates a first header (H.phi.), said header transferred with output data received from the input/output memory to the remote modem, said remote modem receiving and storing at least a portion of the transferred output data and echoing back at least a portion of the first header and transferred output data back to the local modem, the error-checking means of the local modem comparing the received header against that transferred and the received output data with that transferred by the local modem, and again transferring the first header with the same output data if any error is detected between the echoed first header or echoed output data with that transferred by the local modem to the remote modem, and if no error is detected, the header generator means generating a second header (H1) including data representing the location of the desired input data to be obtained by the remote modem from the remote device, the remote modem receiving the incoming second header with the data representing the address of desired input data, the signal transferring means allowing the received output data to be transferred to the remote external device upon receipt of the second header, and the signal transferring means echoing back the second header to the local modem, the error-checking means of the local modem comparing the received second header with the second header sent to the remote modem and if an error is detected causing the signal transferring means of the local modem to re-transfer the second header to the remote modem, and if no error is detected assuming that a successful transfer of output data has occurred, the local modem then entering a data input cycle by generating a third header (H2) with data representing the location of desired input data sent with the second header, the remote modem receiving the third header and echoing back to the local modem the third header along with the specified input data, the local modem receiving the third header and the input data and storing the input data, the local modem generating a fourth header (H3) with data requesting the same input data specified in the second header, the remote modem receiving the fourth header and echoing back at least a portion of the fourth header with the data located in the specified location, the local modem error-checking the fourth header and input data respectively with the fourth header transferred by the local modem to the remote modem and with the input data received immediately prior to the presently received input data and if any error is detected in either the fourth header or the input data respectively with the fourth header transferred to the remote modem or with the previously received input data, causing the most recently received input data to be stored by the local modem and again generating and sending the fourth header to the remote modem, and if no error is detected in either the fourth header or the received input data, assuming that a successful transferral of input data has occurred and allowing the input/output memory to obtain the latest received input data from the local modem.
42. An input/output system as defined in claim 41, wherein the input data comprises P lines of data and the output data comprises Q lines of data, P and Q being positive integers and wherein the local modem sequentially transfers the Q output lines to the remote modem and wherein the local modem header generator means in at least the second header includes data representing the sequential locations of the P input lines and wherein the local modem sequentially and repetitively transfers the Q output lines to the remote modem and sequentially requests the receipt of the P input lines from the remote modem.
43. An input/output system as defined in claim 42, wherein P and Q are the same integer.
44. An input/output system as defined in claim 43, wherein the input data and output data both comprise an equal and invariant number of binary bits.
45. An input/output system as defined in claim 44, further comprising:
(C) means for generating a repetitive timing and control signal communicating with the input/output channel for causing data to be transferred to and from the input/output channel and the input/output memory for a short predetermined length of time after receipt of said timing and control signal other than when the input/output memory is communicating with the input/output channel, wherein the input/output memory may be accessed by the local external world at all times other than such short predetermined length of time when the input/output memory is communicating with the input/output channel.
46. An input/output system as defined in claim 45, wherein the local modem header generator means further generates arbitrary data along with the third and fourth headers for transferral to the remote modem.
47. An input/output system as defined in claim 46, wherein the arbitrary data generated by the local modem header generator means along with the third and fourth headers each comprise an invariant number of binary bits equal to the number of binary bits associated with the input data and output data.
48. An input/output system as defined in claim 47, wherein the remote modem signal transferring means echoes the header and data to the local modem while the remote modem is in the process of receiving the header and data.
49. An input/output system as defined in claim 41, wherein the remote modem signal transferring means echoes the header and data to the local modem while the remote modem is in the process of receiving the header and data.
50. An input/output system comprising:
(A) an input/output memory for the storage and receipt of input data and output data; and
(B) at least one input/output channel interconnected with the input/output memory for transferring output data from the input/output memory and for receiving input data for storage by the input/output memory, the input/output channel incorporating:
(1) a local modem having,
(a) means for selecting and receiving output data from the input/output memory,
(b) means for generating header signals indicating the state of data transferral to and from the local modem,
(c) data transferring and receiving means for transferring the output data and header signals and for receiving the input data and header signals, and
(d) error-checking means for insuring the proper transferral and receipt of output data and input data to and from the local modem;
(2) data communication means interconnected with the local modem for transferring from the local modem header signals and output data and for receiving at the local modem header signals and input data; and
(3) a remote modem having,
(a) means for receiving output data and header signals from the local modem through the data communication means, and
(b) data transferring means for echoing received output data and header signals and for transferring input data and header signals to the local modem through the data communication means;
wherein, (1) the local modem sends selected output data to the remote modem; (2) the remote modem receives and echoes back to the local modem the output data; (3) the local modem receives and error-checks the echoed selected output data with that sent in step 1; (4) if an error is detected in step 3, the local modem returning to step 1; (5) if no error is detected in step 3, the local modem generating and sending to the remote modem a first header signal indicating desired selected input data; (6) the remote modem receiving and echoing the received first header signal to the local modem; (7) the remote modem obtaining the desired selected input data from the remote external world; (8) the local modem receiving the echoed first header signal and error-checking it with the first header signal sent in step 5; (9) if an error is detected in step 8, returning to step 5; (10) if no error is detected in step 8, assuming at the local modem that a successful transfer of output data from the local modem to the remote modem has occurred; (11) the local modem generating and sending a second header signal to the remote modem, the second header signal requesting transferral of the input data obtained in step 7; (12) the remote modem receiving the second header signal and sending to the local modem the desired selected input data obtained in step 7; (13) the local modem receiving and storing the requested input data; (14) the local modem generating and sending to the remote modem a third header signal requesting the transferral of the same input data requested in step 11; (15) the remote modem receiving the third header signal and echoing back the desired selected input data to the local modem; (16) the local modem receiving and storing the desired selected input sent in step 15 and error-checking this data with that received in step 13; (17) if an error is detected in step 16, the local modem substituting the data received in step 16 for that received in step 13 and returning to step 14; and (18) if no error is detected in step 16, the local modem assuming a successful transfer of input data has occurred from the remote modem to the local modem and returning to step 1.
51. An input/output system as defined in claim 50, wherein the local modem header generating means further comprises means at step 1, for generating a "new output" signal indicating whether the output data there sent has been previously sent to the remote modem.
52. An input/output system as defined in claim 51, wherein the remote modem further comprises a data buffer communicating with the data receiving means and data transfer means, and wherein the remote modem further comprises means for obtaining the desired selected input data from a remote external world by generating a data request signal informing the remote external world to load data into the data buffer.
53. An input/output system as defined in claim 52, wherein the input/output memory communicates with a local external world and wherein the input/output memory obtains the selected output data from the local external world and transfers to the local external world received selected input data from the remote external world.
54. An input/output system as defined in claim 53, further comprising first means for communicating the "new output" signal from the remote modem to the remote external world along with the output data received from the local modem so as to indicate to the remote external world the status of the output data and further comprising second means for communicating the "new input" signal from the input/output memory to the local external world to indicate the status of the input data received from the remote modem.
55. An input/output system as defined in claim 54, further comprising:
(A) means for generating a repetitive timing and control signal communicating with the input/output channel causing data to be transferred to and from the input/output channel and the input/output memory for a short predetermined length of time after receipt of the timing and control signal other than when the input/output memory is communicating with the input/output channel, wherein the input/output memory may be accessed by the local external world at all times other than such short predetermined length of time when the input/output memory is communicating with the input/output channel.
56. An input/output system for transferring information to and from the remote external world and local external world comprising:
(A) an input/output memory for the storage and receipt of input data as P input lines from the remote external world and output data as Q output lines from the local external world, P and Q being positive integers, the memory having means for generating "new output word" data indicating the newness status of an output data line, the "new output word" data having a first state when the output data line is first received by the memory and having a second state after the output data line is transferred from the memory; and
(B) at least one input/output channel interconnected with said input/output memory for processing, isolating and receiving from the remote external world P lines of input data and transferring to the remote external world Q lines of output data, said input/output channel incorporating:
(1) a local modem having,
(a) means for sequentially receiving, processing and isolating the Q output data lines of the input/output memory,
(b) header generator means for generating header data, including the "new output word" data, representing the current operating state of the input/output channel,
(c) data transferring and receiving means for transferring the processed and isolated Q output data lines and the header data, and for receiving the P input data lines and header data, and
(d) error-checking means for insuring the proper transferral and receipt of output data and input data to and from the remote external world;
(2) data communications means interconnected with the local modem for transferring from the local modem and receiving at the local modem data including the transferral of header data, and Q output data lines and for receiving header data, and P input data lines; and
(3) a remote modem having,
(a) means for receiving, processing and isolating data transferred by the local modem through the data communications means to said remote modem and transferral of each of the Q output lines of isolated and processed data to the remote external world when verification of error-free transferral of each output data line is ascertained,
(b) a header data storage, decoding, and error-checking means for storing the transferred header data and for error-checking the contents of the header data,
(c) means for sequentially receiving, processing and isolating the P input data lines from the external remote world,
(d) means for generating a "data valid" signal and for generating and inserting into a header data a "new input word" data indicating the newness status of an input data line, having a first state when an input data line is first received by the remote modem from the remote external world and having a second state after the input data line is transferred to the local modem; and
(e) data transferring means for echoing the received Q output data lines and header data to the local modem and for transferring the P input data lines received from the external remote world and header data to the local modem after a "data valid" signal is generated;
wherein the header generator means of the local modem initiates an output transferral state by generating a first header data (H.phi.) including the "new output word" data from the input/output memory representing the newness status of the output data line, the header data transferred with the selected line of output data to the remote modem, the remote modem transferring means echoing the transferred line of output data back to the local modem along with the first header data, the error-checking means of the local modem comparing the received header data against that transferred and the received line of output data with that transferred, and if an error is detected causing the retransferral of the first header data and output data line to the remote modem, and if no error is detected the header generator means generating a second header data (H1) including an input line number associated with one of the P input data lines to be transferred by the remote modem to the local modem, the remote modem receiving and decoding the incoming second header data and if no error is detected in the second header generating a "data valid" signal allowing the transferral of the received output data to the remote external world, the remote modem data transferring means echoing back the second header data to the local modem, the error-checking means of the local modem comparing the received second header data with the second header data sent to the remote modem and if an error is detected causing the local modem to re-transfer the second header data to the remote modem, and if no error is detected assuming that a successful transferral of the selected Q output data line has occurred, the local modem header generator means then generating a third header data (H2) including the input data line number previously sent to the remote modem, the local modem transferring means transferring the third header data to the remote modem, the remote modem decoding this third header data and transferring the selected P input data line obtained from the remote external world to the local modem along with the third header data including the "new input word" data where it is stored by the local modem data transferring and receiving means, the local modem entering a data input verify state by the header generator means then generating a fourth header data (H3), the local modem transferring means transferring the fourth header data to the remote modem, the remote modem decoding the fourth header data and reloading the selected input data line from the remote external world and transferring it back to the local modem along with the fourth header data with the "new input word" data, the error-checking means of the local modem comparing the received selected P input data line with that previously received with the third header data and, if no error is detected, transferring the input data line from the local modem to the input/output memory and the local modem then incrementing to the next sequential output data line and returning to the output transferral state, and if an error is detected causing a re-transferral of the fourth header data to the remote modem and consequently causing the remote modem to re-transfer the selected input data line to the local modem until such time that the local modem error-checking means obtains an error-free transferral of the input data line; whereby the input/output channel continuously transfers Q output data lines from the local modem to the remote modem with error-checking thereof for transferral to the remote external world and transfers P input data lines from the remote modem to the local modem with error-checking thereof for transferral to the input/output memory and thus to the local external world.
57. An input/output system as defined in claim 56, further comprising:
(C) means for generating a repetitive timing and control signal communicating with the input/output channel for causing information to be transferred to and from an input/output channel and the input/output memory for a short predetermined length of time after receipt of the timing and control signal other than when the input/output memory is communicating with the input/output channel, whereby said input/output memory may be accessed at all times by the local external world other than said short predetermined length of time when the input/output memory is communicating with the input/output channel.
58. An input/output system as defined in claim 57, wherein the data communications means comprises a coaxial cable.
59. An input/output system as defined in claim 58, wherein the "data valid" signal is cleared by the remote modem after receipt of the first header data.
Description
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
This invention relates to process controllers, and in particular to parallel process controllers.
2. DESCRIPTION OF THE PRIOR ART
The use of control systems in industry and commerce is pervasive. Such control systems are typically used in chemical processing, textile processing, steel manufacture, weighing systems, and virtually any industrial manufacturing process. Originally, such control systems depended upon timely human decisions and intervention for proper operation. However, control systems that operate independently of human response have recently appeared. These control systems have typically relied on predetermined limits, sequences, and actions in order to properly control the system. Thus, the tools of the control engineer have progressed from simple human intervention to relays, to simple sequences, and finally, in the recent past, to programmable controllers; such as the Models 084, 184 and 284 of the present Modicon Corporation of Andover, Massachusetts. The advent of programmable controllers was a powerful new tool for the control engineer, for it allowed him or her to produce a control program that effectively simulated the logic functions of hard wired relays.
The use of relay logic was a natural first step for the control engineer to take. Also, the use of sequencers, or stepping switches, to make relay logic cyclicable and repetitive was a logical extension of hard wired relay logic. Thus, the introduction of programmable controllers that operated in relay logic fashion and were programmable in a relay ladder diagram format was a natural; albeit highly innovative, progression of the control engineering art.
However, at this point the logical development of tools for the control enginner broke down. The industry's acceptance of programmable controllers as a working tool led to the desire to assign greater and more complex control tasks to these controllers. Some of these tasks have been met in part by adding to programmable controllers the ability to perform non-relay logic functions such as data transfer operations as enumerated in U.S. Pat. No. 3,940,233, issued Dec. 30, 1975, assigned to the Modicon Corporation, and incorporated herein by reference.
However, although the programmable controllers may be improved to allow some data transfer capability, the programmable controllers do not have the speed nor the capability to rapidly perform many such data transfer operations without lengthening the execution time of the relay logic lines of the programmable controller.
An alternative to the programmable controller having such added functions was found to be the mini-computer, which is capable of performing far more complex tasks than a programmable controller. However, mini-computers have the significant drawback of requiring a programmer to define its operations. Thus, the control engineer could no longer speak to his equipment directly, because the mini-computer did not comprehend relay logic. The mini-computer spoke computer language, or assembly language, or some interpretive language like Fortran, and the control engineer typically did not speak these languages.
Thus, this more powerful tool for the control engineer required an interpreter between it and the control engineer. Furthermore, the larger the computer, the greater the interpreter's skill required to program the computer.
In using a mini-computer to perform control functions for industrial control systems, the control engineer would design his system and tell the program what he wanted the mini-computer to do. Consequently, a new language was necessary which was considered a comprise between the control engineer and the programmer. The control engineer put his control system's request into a new language, and the programmer converted it into computer language. Consequently, there were mistakes and mistaken interpretations due to the extra man between the control engineer and the system to be controlled. The resultant misunderstandings and re-education by both the control engineer and the programmer resulted in an inefficient control system with major economic drawbacks. Thus even though with the use of a mini-computer it was possible to perform more complicated tasks than previously performable by simple programmable controllers, the development and debugging of software for the mini-computer, as well as the interfacing hardware necessary between the mini-computer and the system to be controlled, made such a mini-computer system an order or magnitude more expensive and time consuming to implement than programmable controllers.
Also, today's control system problems have become more difficult due to the large control problems encountered in many large industrial complexes. Some control engineers have used multiple service programmable controllers to tackle such large control system's problems. Others have used the general purpose computer directly through a variety of general and special interface boxes. Finally, there is an increasing trend toward the development of special languages for a dedicated mini-computer. Various suppliers have developed dedicated programming languages for specific market segments. However, there seems to be little commonality between these programming languages.
The control engineers that have attempted to use computers have suffered through the development time and expense of generating original software for the computers. Furthermore, they have the continuing problem of implementing changes in the process, or changes in the control technique that require alteration of the software. Thus, even though the computer is programmed to perform a control task, it still requires a programmer to make every change in the program performing that task. Even minor changes in the process require a programmer's assistance in reinstructing the computer.
Furthermore, the dedicated computers being applied through interpretive programming language are not free of problems. Computers are not generally variable in size to match a given job, which results in excess capacity and expense in those situations where the job is small, or complicated interconnections between two or more computers if the control task is large. In addition, the reliability of the computer creates a maintenance problem, since computers generally are intended to be used in the computer room environment and not in the hard-hat environment of industrial process control.
Clearly then, the ideal solution to the problem of control system implementation is a special purpose machine that communicates in a language understandable by the control engineer, that is expandable to fit the desired control system, and that can withstand the industrial environment. Furthermore such a machine must be reliable and be equipped with input/output capability that will operate the relay valves and motors found in industrial process control systems. Such a machine must give the control engineer the enlarged and expandable data base that the current programmable controllers lack, and eliminate the need of the programmer intermediary used with mini-computers and computers.
The present parallel process controller is this solution. It comprises command memory modules, data memory modules, an input/output system, a programming panel, and a high speed N-bus (data bus) for accomplishing any desired control task. The control engineer simply instructs the command memory modules through the interconnectable programming panel what he desires to be performed. The control engineer does not have to tell the process controller how to perform what he desires because the command memory modules incorporate the necessary hardware for solving the instructions selected by the control engineer.
Since each command memory module is a physically separable item, they may be added to the process controller to adequately fit the size of a particular control task. Furthermore, since each command memory module acts autonomously from the other command memory modules, and since each command module solves its selected instructions in a short, fixed, length of time, the entire process controller, regardless of the overall complexity of the entire control task, performs this control task in a parallel fashion. That is, the system response time is not a function of the complexity of the control task.
The programming panel not only allows the control engineer to instruct the command modules, but also allows the control engineer to monitor and troubleshoot the entire process controller. A discrete, simple, user oriented language is used, therefore not requiring the control engineer to understand computer language. Furthermore, all information displays are decimal, not requiring the control engineer to know and understand other numeric systems.
The present invention also incorporates data memory modules which allow expansion of the data base to fit a particular control task. In addition, the input/output system of the present invention provides high speed, error-free transfer of information from the process under control to the process controller, as well as the transferral of industrial compatible signals to operate relays, valves, and motors ordinarily found on equipment in the control process.
The parallel process controller can also serve as a master control over a number of programmable controllers that interface with the process under control. Here, the process controller of the present invention forms the hierarchical control needed for controlling complex processes.
SUMMARY OF THE INVENTION
The parallel process controller (PPC or machine) of the present invention is an expandable, parallel operating multi-function controller designed specifically for industrial process control. It consists of three basic sections, the command memory modules (CM), the data memory modules (DM), and the input/output system (I/O). Each CM and DM is packaged in a self-contained module, and a high speed N-bus allows interconnection of from 1 to 10 CM's with from 0 to 2 DM's. Internally, the I/O is regarded as additional memory. The PPC is programmed and monitored through a programming panel, which functions through a dedicated channel in the I/O. The programming panel can display the contents of each command memory and data memory, one line at a time. A line is the basic information entity in the PPC. The programming panel also allows an operator to instruct the PPC to perform functions which are part of its repertoire. Power for the parallel process controller is available in incremental blocks, to match the number of CM's and DM's employed.
The PPC will interface with peripherals which operate in ASCII format. Printers, certain CRT's, teletypewriters and other peripheral devices are usable with the PPC. The three basic building blocks of the parallel process controller, the CM, DM, and I/O, are organized around the high speed N-bus and communicate to each other via this bus.
The command memory module is the active element of the parallel process controller. It contains the functional equivalent of a central processing unit as well as memory for lines of instruction for the PPC. Additionally, the CM has as part of its hardware the circuitry to carry out certain special functions. These include calculations, data or instruction transfers, timing and counting, and arithmetic testing and logic. A command memory operates autonomously, without regard for other CM's. It is the equivalent of a micro-processor with memory but without I/O. While major differences in implementation exist between a general purpose processor and the command memory, their results, for those functions which the PPC is built to perform, are the same with one significant exception. The present process controller operates as a parallel processor, while a computer is a series processor. In the process control field, the present command memory represents a departure from conventional process controller design, combining as it does the processor with its own dedicated memory and allowing the resultant device to step through 200 pre-programmed lines of instructions. The advantages of the present invention's use of command memory modules over conventional process controllers for process control applications are:
1. a large reference data base;
2. designed-in hardware commands;
3. faster operation;
4. the ability to operate up to ten CM's in parallel;
5. the range of peripherals available; and
6. possibility of interaction with supervisory general purpose computers.
The advantages of the command memory over general purpose computers are:
1. the hardwired commands (no software generation required).
2. the parallel operation of up to 10 CM's;
3. the optimized handling of the eighty bit line;
4. the ruggedized construction; and
5. the RFI shielding;
The data memory module is the data storage element of the parallel process controller. The data memory is optional and the PPC can function without the data memory by using a scratchpad memory and live storage area in the command memory. For applications in which the storage available in the CM is not large enough, from one to two DM's may be included in the system. CM's share the N-bus sequentially and during its bus access time, any CM may address, read, or write in any DM location. Information stored by one CM at a certain DM location can be referenced, destroyed, or changed by any other CM. This multiple DM access is the only means of CM to CM communication.
The input/output system (I/O) of the parallel process controller consists of from one to three 80 line I/O memories (200 lines maximum are used), from two to ten pairs of local and remote modems, and an indeterminate number of terminal boxes. Each of the ten remote modems performs multiplexing on the equivalent of 640 input and 640 output terminals, for a total capacity of up to 6400 input points and 6400 output points. Sixty-four (64) bit datum words or 80 bit statement words are assembled in the remote modem. These words are created by any device desiring to communicate with the PPC, including the programming panel, peripheral devices such as printers, CRT's, teletypewriters, and mass storage units, and input and output signal conditioning cards.
The line is the basic unit of information and instruction within the parallel process controller. It is 80 bits long and is the functional equivalent of the word in a mini-computer. However, because the minicomputer word length is typically 12
or 16 bits, the 80 bit line in the PPC is more powerful than a word or instruction in the mini-computer. The line is broken into five 16-bit segments, called registers, and each register is given a name and has a specific function in the operation of the PPC. The number assigned to the line describes its geographical location within the parallel process controller. Each command memory has locations for 1000 lines and is assigned numbers from 000 to 999. Line numbers 1000 through 1999 are reserved for memory locations within the I/O system of the PPC. Line numbers 2000 through 9999, in blocks of 4000 numbers, are reserved for the data memory modules.
An instruction register tells whether the line is an instruction (to be carried out) or a datum (to be processed as information); and if it is an instruction, what the instruction is.
A reference register tells the controller whether the condition reference is AC (transitional) or DC (direct), where the condition reference is stored, the relationship to the reference (true, false, true-to-false transition, or false-to-true transition), and the type of reference (coil, ready, stepper, or transformer, explained infra). This register is similar in operation to the first register of an electrical circuit line disclosed in U.S. Pat. No. 3,686,639, entitled "Digital Computer-Industrial Controller System and Apparatus;" assigned to Modicom Corporation, of Andover, Massachusetts; and hereby incorporated by reference.
A third register, called the A register can refer only to the command memory in which it is located. It can contain a relay type element, and a four digit number. The number can be local data, or it can be the address of another line within the same CM where data may be obtained. The latter type of number is designated remote data. A fourth register, called the B register can refer to any line of memory in the entire machine. It can contain a relay type element and a four digit number, and the four digit number is always an address.
For all arithmetic operations, the A and B registers are operated on, and the result is stored in the fifth register, known as the C register.
The C register, as the A register can only refer to lines of memory within the CM in which it is located. It also can contain a relay type element and a four digit number. The number can be data (local) or it can be the address of data within the CM (remote).
All communication to the PPC is performed through the line. The programming panel can address any line within the PPC and operate on that line alone. Data from I/O modules is grouped into lines before it is transmitted to the I/O memory, where it is stored as discrete lines. Information is stored in the data memory in complete 80-bit lines.
The operation of the programming panel including the "trace" and "scroll" features (discussed infra) and the electronic implementation of the programming panel is set forth in significant part in U.S. Pat. No. 3,944,984, issued Mar. 16, 1976, and assigned to Modicon Corporation, of Andover, Massachusetts. In addition, U.S. Pat. No. 3,686,639, entitled "Digital Computer-Industrial Controller System and Apparatus," issued Aug. 22, 1972, and U.S. Pat. No. 3,930,233, entitled "Data Transfer and Manipulation Apparatus for Industrial Controllers," issued Dec. 30, 1975, both assigned to the Modicon Corporation, also discuss the electronic implementation of programming panels similar to the programming panel utilized in the present invention. These patents are hereby incorporated by reference.
There are two status bits associated with each line within the PPC. They are included as part of the 80 bits of the line itself within the instruction register and are addressable using the same number as the line number. The first bit is designated Ready (D) which generally refers to the truth of the reference condition, or if the instruction is a multiscan instruction, to the truth of the reference condition after a suitable delay to allow the instruction to be completed. Ready can be either a steady state or a pulse reference. The second bit is designated Coil or Koil (K) and can be defined for many lines as the logical truth of the line.
Each PPC command memory contains a large number of hardwired instructions that can be used repeatedly by the control engineer to set up and solve process problems. These instructions require only a single line of CM space to implement, and during programming, only the selection of a single pushbutton switch to request. First is the relay logic line, which is analogous to the logic line disclosed in U.S. Pat. No. 3,686,639, supra, as well as the logic line used by the Model 084 and 184
programmable controllers of the Modicon Corporation, Andover, Massachusetts. The selection of the relay switch sets up the R, A, B, and C registers to accept logic element type inputs and reference locations similar to the Modicon model 084 and 184
programmable controllers.
Beyond simple relay logic lines, the PPC will perform arithmetic calculations, tests, counts, timing, transfers, and conversion of data from one format to another. Each of these functions can be performed locally (where the A & C registers contain data) or remotely (where the A & C registers contain the addresses of data stored elsewhere).
The parallel process controller of the present invention can also control a number of external programmable controllers which in turn control a desired process. Here the present invention forms the apex of a hierarchical control system. Alternatively, the programmable controllers can act as remote data concentrators for efficient data transfer to the I/O system of the present invention. In either mode as well as in the earlier mentioned direct control of the desired process, the present parallel process controller provides a means for controlling extremely complicated processes capable of being implemented by control engineers without the need of computer specialists.
OBJECTS OF THE INVENTION
Therefore, it is a principal object of the present invention to provide a process controller that is capable of parallel operation of a plurality of central processing units so as to implement industrial process control of varying complexity;
Another object of the present invention is to provide a parallel process controller of the above description having an invariant response time regardless of the complexity or size of the industrial process being controlled;
A further object of the present invention is to provide a parallel process controller comprising command memory modules corresponding to individual central processing units which are expandable in number, that communicate with an expandable number of data memory modules for the storage of data, and an input/output system for communication between the parallel process controller and a plurality of interconnected external devices;
A still further object of the present invention is to provide a parallel process controller of the above description capable of parallel, supervisory control of a plurality of programmable controllers;
Another object of the present invention is to provide a parallel process controller of the above description having an interconnectable programming panel for monitoring, programming, and displaying instructions executed by the parallel process controller;
An additional object of the present invention is to provide a parallel process controller of the above description wherein the instructions programmed by the programming panel are of a simple format thereby allowing an operator unskilled in computer programming language to effectively implement a desired industrial process control;
A further object of the present invention is to provide a parallel process controller of the above description wherein the instructions entered on the programming panel correspond to lines having a fixed size which are capable of representing the complete repertoire of instructions solvable by the parallel process controller, including calculation, data and instruction transfers, timing and counting, arithmetic testing and logic, and wherein said lines may alternatively represent data in one of a variety of formats;
An additional object of the present invention is to provide a parallel process controller of the above description wherein data manipulations involving data of varying format is solved by the process controller without special instructions or alterations of the instructions by the user;
A further object of the present invention is to provide a parallel process controller of the above description wherein the programming panel is able to monitor the lines stored in the command memory modules and data memory modules, to scroll through consecutively higher or lower numbered lines, and to trace into instruction lines to which a previously displayed instruction line refers;
A still further object of the present invention is to provide a parallel process controller of the above description wherein the input/output system performs error free communication with a plurality of external devices and operates asynchronously with respect to the remainder of the parallel process controller;
An additional object of the present invention is to provide a parallel process controller of the above description wherein each command memory module is repetitively sequentially interconnected with the data memory modules and input/output system for a set predetermined length of time so that the command memory modules are capable of communication between each other via the data memory modules;
A further object of the present invention is to provide a parallel process controller of the above description wherein the programming panel incorporates a cathode ray tube (CRT) display for illustrating the particular instruction line presently being monitored or programmed by the user wherein a plurality of keys on the programming panel are capable of selecting the complete repertoire of instructions solvable by the parallel process controller;
A still further object of the present invention is to provide a parallel process controller of the above description having an input/output system that is capable of communication with a plurality of external devices including programmable controllers, over long distances while maintaining error free transmittal of information to and from the parallel process controller;
Other objects of the present invention will in part be obvious and will in part appear hereinafter.
THE DRAWINGS
For a further understanding of the nature and objects of the invention, reference should be had to the following detailed description taken in connection with the accompanying drawings in which:
FIG. 1 is an overall block diagram of the parallel process controller of the present invention;
FIG. 2 is a perspective view of the parallel process controller of FIG. 1;
FIG. 3 is an overall block diagram of the input/output system and the interconnection of this system to the command memory modules and data memory modules of the parallel process controller of FIG. 1, and to interconnected external devices;
FIG. 4 is a schematic representation of a programmed line utilized in the parallel process controller of FIG. 1, illustrating the five registers comprising a line as well as the information represented by each of these registers;
FIG. 5 is an overall block diagram of the interconnections between the command memory modules, data memory modules, input/output channels, and the general timing and control unit of the parallel process controller of FIG. 1;
FIG. 6 is an overall block diagram of a command memory module of the parallel process controller of FIG. 1;
FIG. 7 is a schematic representation of the line memory addresses utilized in a command memory module of the parallel process controller of FIG. 1;
FIG. 8 is a schematic representation of the line addresses utilized in the I/O system of the parallel process controller of FIG. 1;
FIG. 9 is a schematic representation of a typical program line utilized in the parallel process controller of FIG. 1, similar to the typical line shown in FIG. 4 but showing in more detail the information entered into the instruction register of the programmed line;
FIG. 10 is a schematic illustration of the information entered into the registers of a program line of the parallel process controller of FIG. 1, illustrating the condition references and output conditions of a typical programmed line;
FIG. 11 is a schematic representation of "stepper" lines utilized in the command memory modules of the parallel process controller of FIG. 1;
FIG. 12 in a schematic representation of "input transformer" lines utilized in command memory modules of the parallel process controller of FIG. 1;
FIG. 13 is a schematic representation of "output transformer" lines utilized in command memory modules of the parallel process controller of FIG. 1;
FIG. 14 is a schematic representation of the general line format used for different instructions solvable by the command memory modules of the parallel process controller of FIG. 1;
FIG. 15 is a schematic representation of the general statement formats used by the command memory modules of the parallel process controller of FIG. 1;
FIG. 15A is a schematic representation of the instruction and reference registers of an instruction line utilized by the command memory modules of the parallel process controller of FIG. 1, illustrating the coding format for these instruction registers as well as the contact specifications used by the reference register;
FIG. 15B is a schematic representation of the coding format of an instruction register of an instruction line utilized in command memory modules of the parallel process controller of FIG. 1;
FIG. 15C illustrates the coding format for the reference, A, B, and C nodes of a logical statement utilized by the parallel process controller of FIG. 1;
FIG. 16, comprising FIGS. 16A through 16SSF are a series of diagrammatic representations of the complete instruction set of statement lines solvable by the parallel process controller of FIG. 1, as well as conversion from datum lines of one data format to a datum line of another data format or from a statement line to a datum line;
FIG. 17 is a timing chart illustrating the calculation timing for execution of arithmetic statements by the command memory modules of the parallel process controller of FIG. 1;
FIG. 18 is a timing diagram for conducting multi-sweep execution of multiply and divide statements by the command memory modules of the parallel process controller of FIG. 1;
FIG. 19 is a timing diagram of the execution by the command memory modules of compare, match and test instructions;
FIG. 20 is a timing diagram for execution of count statements by the command memory modules;
FIG. 21 is an overall flow diagram utilized by the command memory modules of the parallel process controller of FIG. 1;
FIG. 22 is an overall block diagram of the processor used in the command memory modules of the parallel process controller of FIG. 1;
FIG. 23 is an overall block diagram of a typical data memory module utilized by the parallel process controller of FIG. 1;
FIG. 24 is a detailed block diagram of a typical data memory module of the parallel process controller of FIG. 1;
FIG. 25 is a detailed timing chart illustrating the execution of functions of a typical data memory module of the parallel process controller of FIG. 1;
FIG. 26 is a block diagram of a section of I/O memory of a particular I/O channel as well as the local modem accompanying this I/O channel of the parallel process controller of FIG. 1;
FIG. 27 is an overall block diagram of the I/O system of the parallel process controller of FIG. 1;
FIG. 28 is a schematic representation of the module assignments for the complete I/O system of the parallel process controller of FIG. 1;
FIG. 29 is a schematic representation of the line addresses utilized by the I/O system of the parallel process controller of FIG. 1;
FIG. 30 is a timing chart illustrating the data rates and minimum bandwidths required by an I/O channel of the I/O system;
FIG. 31 is a timing diagram illustrating the various timing states for the transmittal and receipt of information via the I/O system of the parallel process controller of FIG. 1;
FIG. 32 is a timing chart illustrating the "header" transferral utilized by the I/O system of the parallel process controller of FIG. 1;
FIG. 33 is an overall block diagram of a typical I/O channel of the I/O system;
FIG. 34 is a schematic representation of the I/O status word coding utilized by the I/O system of the parallel process controller of FIG. 1;
FIG. 35 is a diagrammatic representation of the utilization of the parallel process controller of FIG. 1 with interconnected external programmable controllers so as to form a hierarchical parallel process controller for complex processes;
FIG. 36 is an overall block diagram of the general timing and control unit of the parallel process controller of FIG. 1;
FIG. 37 is a diagrammatic representation of the power and bus interconnections of the parallel process controller of FIG. 1;
FIG. 38 is a detailed block diagram of the general timing and control unit of the parallel process controller of FIG. 1;
FIG. 39 is a schematic representation of the system status word coding utilized by the general timing and control unit of the parallel process controller of FIG. 1;
FIG. 40 is an overall block diagram and timing chart analysis of the N-bus utilized in the parallel process controller of FIG. 1;
FIG. 41A is a block diagram of the command memory module bus logic utilized by the parallel process controller of FIG. 1;
FIG. 41B is a timing chart of the command memory bus logic illustrated in FIG. 41A;
FIG. 42A is an overall block diagram of the data memory bus logic utilized by the parallel process controller of FIG. 1;
FIG. 42B is a timing chart of the data memory bus logic illustrated in FIG. 42A;
FIG. 43A is a schematic representation of the N-bus of the parallel process controller of FIG. 1;
FIG. 43B is a timing analysis for the skew rate of the N-bus illustrated in FIG. 43A;
FIG. 44 is a timing chart representing the transferral of information on the N-bus of FIG. 43A;
FIG. 45 is a partially cutaway perspective view of the parallel process controller of FIG. 1 illustrating the insertion of module frames into the main assembly enclosure of the parallel process controller;
FIG. 46 is a partially cutaway side elevational view of the main assembly enclosure illustrated in FIG. 2 of the parallel process controller of FIG. 1;
FIG. 47A is a perspective view of a typical card frame for enclosing a printed circuit card on which one of the modules of the parallel process controller of FIG. 1 is enclosed;
FIG. 47B is a partially cutaway side elevational view of the frame illustrated in FIG. 47A;
FIG. 48A is a perspective view of the frame illustrated in FIG. 47A without the insertion of the printed circuit card illustrated in FIG. 47A;
FIG. 48B is a partially cutaway side elevational view of the frame illustrated in FIG. 48A;
FIG. 48C is a top plan view of the frame illustrated in FIGS. 48A and 48B;
FIG. 49 is a perspective view of the radio frequency interference shield utilized in the main assembly enclosure illustrated in FIGS. 2 and 46;
FIG. 50 is a block diagram of the input filter unit and power supply system utilized by the parallel process controller of FIG. 1;
FIG. 51 is a top plan view of one version of the programming panel utilized by the parallel process controller of FIG. 1;
FIG. 52 is a perspective view of a cathode ray tube embodiment of the programming panel utilized by the parallel process controller of FIG. 1.
FIG. 53 is a diagrammatic representation of the system configuration describing a typical process to be controlled;
FIGS. 54A-54C are diagrammatic representations of a ladder block diagram for the process illustrated in FIG. 53;
FIG. 55 is a diagram showing and explaining the notations used in FIGS. 54A-54C;
FIGS. 56A-56D is a diagrammatic representation of a ladder program listing based on the ladder block diagrams of FIGS. 54A-54C; and
FIG. 56 is a diagram showing how FIGS. 56A-56D are put together.
GLOSSARY NOTE
A glossary of frequently used terms in the description of the present invention is enclosed and labeled Table 14.
DETAILED DESCRIPTION
As best seen in FIGS. 1 and 2, a parallel process controller (also designated PPC or machine) 10 performs as a soft-wired control system for industrial applications. The physical hardware it replaces is inherently continuous and parallel, a network of discrete acquisition, processing, and control elements. In the past, minicomputers have been used to replace such control systems with varying degrees of success. Since a computer is a sequential processing device, executing one instruction at a time, implementation of a control system requires careful consideration of performance under all system conditions. For example, sampling rates may vary with processing load, causing "crosstalk" between seemingly independent parts of a system. Multilevel interrupt systems and supervisory executive routines are often used to solve such problems. In general, however, minicomputer systems tend to be tailored to each process through a massive programming effort by programming specialists and to contain time and memory-consuming overhead to "match" the sequential machine to the parallel process.
The present parallel process controller avoids these problems by strict, hardware-controlled "parallel processing." The PPC has no "instructions" in the minicomputer sense. Instead, it is programmed by "Lines," each of which is a stand-alone processing or storage element. Interrelation of these lines is controlled by referencing, corresponding to wiring or interconnection of the elements. The reader familiar with programmable logic controllers may note that this programming technique has been successfully used in programmable controllers, such as the Models 084, 184 and 284 of the Modicon Corporation, Andover, Mass.
A processing line, called a statement may be a four-term Boolean or relay ladder line as in a programmable logic controller, or it may perform an arithmetic or other calculation when activated by a discrete reference condition (called a "coil"). Each statement has at least one condition reference input and one coil output. Other features, which permit flexible system programming are detailed infra, as are the various types of statements. A storage line, called a Datum, may also be programmed. This is simply a place in which to store data associated with the process. A command memory 12 is the device which stores and executes user lines. Lines contained in a command memory are continuously active with respect to their control relationships. A network of up to 200 active lines may exist within a single command memory module. The control relationships of the command memory lines are emulated, and all processing takes place at the invariant rate of 100 times per second. Internally, the command memory processes lines in numerical order, so that multi-step processes may be performed in a single 10 millisecond scan in most instances. Parallel processing capability may be expanded by connecting several command memories to a PPC system.
A general timing and control unit (GTCU) 14 generates all signals necessary for the sharing of an N-bus 16 by command memories as well as system synchronization and refreshing of semiconducor data memories. It also provides power regulation and control signals to a power supply system 34.
The PPC system comprises one or more command memories as processing elements. All control systems, however, require input/output capability. In addition, provision must be made for data and program storage capability, and for intercommunication among command memories. The N-bus 16 provides an electrical pathway over which command memory statements can have access to common input, output, and data storage units.
Optional data memory modules 18 for storing up to 4000 lines each are available in the parallel process controller. Statements contained in data memories are not active but may be moved into command memories under program control as required. Stored data may also be manipulated by the command memories and storage locations can be used as a means of communication between individual command memories as well as for bulk data storage. All data memories are accessible to all command memories via the N-bus.
Command memory access to the outside world is provided via the input/output (I/O) system 20. All command memories can access I/O locations via the N-bus. The I/O unit appears as a set of data lines containing a one-for-one mapping of outside world information. Multiplexing/demultiplexing hardware transfers information between these lines and up to 10 remote locations at the rate of 125 times a second. Both refreshing and error-correction are automatic and continuous and do not require program intervention. As best seen in FIG. 3, an I/O memory 22 has output addresses that are read/write and can thus be used as "data memory" addresses for scratchpad and for inter-command memory buffering purposes.
As best seen in FIG. 1, the command memory modules 12 are interconnected via the N-bus 16. Up to ten command memories are time division-multiplexed on the N-bus so that each, in turn, has control of the bus. Up to two 40-line and one 20-line I/O memories and up to two 4000-line data memories service the bus at all times since one and only one location in all of these memories may be accessed at any instant. Command and data memory numbers are selected by a thumbwheel switch 24 on each module. The input/output system is expandable from a basic I/O memory unit with two channels 26 and 27 optionally expandable to four channels 26, 27, 28 and 29. Up to two addtional I/O memory units 23 and 25 each carrying either two or four channels may be added, up to a maximum of ten channels (Channels 4-9). Each I/O channel communicates with a remote modem 30 located up to three thousand feet from the PPC and connected via CATV cable. Up to ten 64-bit lines of input and ten 64-bit lines of output may be further demultiplexed at the remote location. In some equipment, these lines are grouped into ten I/O "ports" 32, each consisting of one input and one output location. Discrete digital, alphanumeric, and programming devices are connected at these points. Direct programming and memory loading devices are restricted to I/O Channel 0, ports .phi. and 1. Indirect loading may be implemented via user commands or other lines.
As best seen in FIGS. 1 and 2, an expandable power supply system 34 powers the PPC system and provides, with associated filter circuitry 164, isolation from power line transients. A battery power backup system 19, couples with the power supply system to provide data and system protection in the event of power loss.
The parallel process controller is programmed as a collection of statements (and datums) entered by a programming panel 36 or other loading device. The following procedure is employed:
A. describe the process. This can be in any descriptive format familiar to the user, but should indicate signal flow from input to output. Electrical elementary diagram format is also useful.
B. assign outputs. This fixes output statement line numbers where discrete outputs are required.
C. assign inputs and data storage locations.
D. create the program using the PPC set of 41 statement types (discussed infra). This should closely follow the original descriptive diagrams.
E. debug. Individual conditions can be exercised using the programming panel disable feature (described infra) so that portions of the system can be disconnected and debugged individually.
The above procedure is followed for each command memory program. The following items are typically considered:
1. Command memory programs do not inherently interact. One may not reference another directly.
2. Lines are solved in numerical sequence.
3. Command memories operate in synchronism on a line-by-line basis.
4. Only lines 0-199 of each CM (discussed infra) are executed although other lines may contain statements. (The scratchpad area and transformer area (infra) each contain 40 lines.)
5. Data written into data memory by one command memory "move out" statement (discussed infra) may be immediately read by another command memory of higher number on the same time or by any CM on the second subsequent line.
6. The number of lines effectively "swept" by a command memory may be increased by application of block and line move in and move out statements (discussed infra), with attendant reduction of sweep speed.
An example of an instruction line 38 is given in FIG. 4. This illustrates some of the information contained in a typical line. Further details are found infra relating to the command memory. The following features should be noted:
(a) Line number region 61 specifies the location of the line in one of ten CM's, in DM or in I/O.
(b) Line type register (instruction or I register) 40 specified characteristics of the line.
(c) Registers 42 contain data and/or references associated with the line.
COMMAND MEMORY
Function
As best seen in FIGS. 1 and 5, the command memory (CM) is the basic functional unit of the parallel process controller. Its purpose is to memorize user statements and datums descriptive of the process to be controlled and to continuously process these lines to produce the desired control relationships. The command memory is one of up to ten identical parallel central processing units in the PPC system. The command memory can contain a maximum of 200 active user lines, each of which may function as a statement (processing element) or may contain data. In addition, a user scratchpad area is available which generally is used to contain data. Auxiliary features are provided within each command memory to facilitate logical bit manipulation and discrete input/output.
A command memory contains all storage and functional elements required to process user statements. Access to input/output circuitry and data storage (data memory modules 18) is facilitated by connection to the N-bus 16. Timing and synchronization signals from the GTCU 14 via the N-bus maintain line-by-line lock-step synchronism between all command memories with the PPC system. Each time all 200 active lines are processed is defined as one "scan". Externally supplied power is required to support the command memories.
BASIC ARCHITECTURE
FIG. 6 illustrates the basic elements of the command memory.
MC Memory
A large semiconductor memory 46 contains 200 user lines 48, up to 40 scratchpad lines 50, and up to 40 special lines 51 (discussed infra). This memory includes additional storage capacity for partially processed results of lines requiring multiscan processing operation and for special "transformer" lines.
Processor
A second major element of the command memory is the processor 52. This processing element consists of an array of storage registers 54, arithmetic and logical elements 56, and a control read-only-memory (ROM) 58 which directs register transfer paths and sequential state progression. In general, such an array can be considered as an instruction sequence required to interpret and process statements and data in the main memory.
BUS INTERFACE
For access to externally located data and input/output the microprocessor 56 is provided with an interface 60 to the N-bus 16. Because of bus timing constraints, the bus controller 60 is somewhat independent of the microprocessor during a bus data exchange.
For each of the 200 user lines 48 being processed, several references to internal memory 50, a single read access from the N-bus, and a single write access to the N-bus may be made within each 40 microsecond bus multiplexing period.
"Run" Light
An internal self-test function is implemented in the command memory processor 52 to provide maintenance and protective information. Successful completion of a routine designed to exercise a maximum number of circuit elements and data paths causes recycling of a "watchdog timer" circuit within micro-processor 56. Failure to retrigger the device within a 20 millisecond period causes shutdown of the bus interface communication and of the "RUN" indicator 62.
Over-Temperature Sensor
An over-temperature sensor 64 monitors ambient temperature in the command memory module. An over-temperature condition is signalled to the N-bus 16 for maintenance purposes, but does not affect operation of the processor or memory. Over-temperature conditions can be logically sensed by user programs as part of system status information (line address 1200 of the PPC - general timing and control unit 14) should programmed response to this condition be required.
Instructions
The following section sets forth the addressing rules and instruction set of the parallel process controller 10, and presents in detail the internal data formats and the behavior of each line for both application and microprogram design.
Addressing; General
As best seen in the system memory diagram of FIG. 5 illustrating the relationship of address space within the PPC 10, the command memories are time-multiplexed on the N-bus 16 so that each, in turn, has access to the address field consisting of the I/O system 22 and data memories 18. A command memory may reference its internally stored data and conditions freely but may only make limited references to I/O 22 and data memory locations within data memories 18.
Internal Lines
Internal locations addressable by a command memory are illustrated in FIG. 7. Line storage locations are divided into three types: first, 200 active lines 48 for scanning and processing by the command memory processor 52; (see FIG. 6); second,
40 scratchpad lines 50 available for storage; and third, 40 special lines 51 (of which 12 are used) for performing translation between data and conditions. These lines augment bit manipulation capability, discussed infra.
Conditions
Statements within the active line area 48 are activated and controlled by condition references.
Ready (D)
Each line within the active area produces a "Ready" or a D-condition 65 which signifies that the operation specified by an active statement is "ready;" i.e., that the statement has completed the most recently initiated action. This condition is true for one scan each time the action is completed.
Coil or Koil (K)
A set of "coils" or K-condition references 66 are provided. These conditions represent the logical result or status of any line within the command memory.
Stepper (S)
As best seen in FIGS. 7 and 11, four "steppers" 68 are provided in each command memory. Each stepper is a special line location and generates 100 "sequence" conditions. A stepper is generally used to activate functions in a sequential fashion. A stepper is roughly equivalent to a rotary switch; i.e., one and only one condition out of each set of 100 conditions may be true at any one time. Table 1 explains the addressing scheme of the steppers.
Input (E)
Each command memory is provided with four special line locations which function as input transformers 70. Each transformer produces a mapping of any line stored at that location such that each bit of the line is referencable as an E-condition. Each of the input transformer words thus produces a set of 64 E-condition references.
TABLE 1 __________________________________________________________________________ Input Transformer (see FIGS. 7 and 12) Bits 0 - 63 deposited into line 910 become "coils" E0/0/ - E63 Bits 0 - 63 deposited into line 911 become "coils" 064 -
127 Bits 0 - 63 deposited into line 912 become "coils" 128 - 191 Bits 0 - 63 deposited into line 913 become "coils" #192 - E255 Output Transformer (see FIGS. 7 and 13) K coils K000 - K063 generated by line 0 - 63 are stored in line 920 bits 0 - 63 K coils K064-K127 generated by lines 64-127 are stored in line 921 bits 0-63 K coils K128-K191 generated by lines 128-191 are stored in line 922 bits 0-63 K coils K192-K199 generated by lines 192-199 are stored in line 923 bits 0-7 Bits 8 - 63 of line 923 are zero Stepper (see FIGS. 7 and 11) Numerical value 1-99 deposited into line 900 becomes one of coils S000-S099 Numerical value 0-99 deposited into line 901 becomes one of coils S100-S199 Numerical value 0-99 deposited into line 902
becomes one of coils S200-S299 Numerical value 0-99 deposited into line 903 becomes one of coils S300-S399 __________________________________________________________________________
The input transformer may be thought of as a method of converting discrete input information into individually referencable "coils." Table 1 explains the addressing scheme of the E-conditions.
Output Transformers
As best seen in FIGS. 7 and 13, a set of output transformers 72 map the first 200 K coils 66 into special line locations in a process which is essentially the inverse of the input transformer 70. Four such transformers are provided, each of which maps 64 K-conditions in numerical sequence (up to 199). These transformers provide the fundamental method for communicating discrete information between a command memory and output points. The set of input and output transformers allows discrete bit exchange between command memories within the PPC system using intermediate locations within data memory modules. Table 1 explains the addressing scheme of the K-conditions.
I/O Addressing
Input/output addresses of the I/O system 20 are illustrated in FIG. 8. All input/output locations are referenced by all command memories at PPC line addresses 1000 to 1999. These are ten I/O channels (see FIG. 5). Each channel output section
74 is referenced as 10 consecutive line locations in the address range 1000 through 1099 and each channel input section 76 is referenced as 10 line locations in the address range 1100 through 1199.
One hundred words of I/O channel status conditions 78 are available at address locations 1300 to 1399, one word for each line of data, ten for each channel. Bits contained within each word signify the new word status of an individual subchannel (line), and also information concerning the status of channel hardware (carrier, error). The bit test instruction (to be described infra) permits the status bits to be used to implement programmed control of I/O devices when required. Output addresses may be written and read for use as storage locations. Line 1200 contains system power status information and is physically located in the GTCU 14.
TYPES OF COMMAND MEMORY LINES
Format
Command memory lines may be classified into three types: statements, datums, and dedicated lines. As best seen in FIG. 9, each line consists of an 80-bit word which is divided into two portions. The first portion is a 16 bit line type or I register 40 containing a description or specification of the line and its status. The remainder of the line consists of four 16-bit registers 42 designated R, A, B, and C, which generally contain the working information associated with the line.
I-Register; Status Bits
A status portion 80 of the I-register is dynamic. It contains the coil (K) 66 and ready (D) 65 status bits, which are updated each time the line is processed. It also contains the enable 82 and suspend 83 bits. The enable bit allows a programming panel operator to cause a line to be disabled so that the associated coil and ready conditions can be forced to a known status during debugging operations. The suspend bit allows the programming panel 36 (see FIG. 1) to inhibit all processing of the line. In addition, a previous sample 84 of the reference node calculation (if the line is a statement, see FIG. 4) is stored in the status portion of the I-register so that reference node state transition may be detected (for AC or transitional referencing). For timed count statements (discussed infra), the history of a prior request for counting is also stored.
I-Register; Description Code
A description portion 85 of the I-register specifies whether the line is a statement or a datum. When a line is a datum, R, A, B, and C registers 42 are taken together as data in the format specified by the description code. If the line is a statement, registers R, A, B, and C take on specific meaning as will be detailed in the following sections.
Statements; R-Register
FIG. 10 and Table 2 illustrate characteristics which are common to all statements.
TABLE 2 ______________________________________ REGISTERS: I-Register defines Instruction. R Register activates process (condition reference). A,B,C Registers define data or conditions asso- ciated with process. D (Ready) indicates True when result of process is ready (available). D lasts for one sweep EACH TIME process is completed. K (Coil) indicates logical result of process (as required). REFERENCES: The R Register may make DC (static) or AC (transi- tional) references to conditions in a command memory. Other logical nodes may make DC references only. Any logical node may make DC references only. Any logical node may make inverted reference (True When referenced condition is false). Conditions referenced may be Coil (K), Done (D), Input (E), or Sequence Step (S). ______________________________________
The reference (R) register of a statement causes transmission of a true (logical one) condition if the specified reference conditions are met. (Registers performing logical condition solutions are referred to as "nodes"). The R-node may refer to any internal D, K, E (input transformer bit; see FIG. 7), or S (output transformer bit; see FIG. 7) condition in either inverted or noninverted sense. The result of this reference may be taken as a static (DC) or transitional (AC) condition. If transitional, a false-to-true transition causes an output lasting for one sweep.
When a transitional (AC) reference is made, the result (R-node) output will be true whenever the referenced condition is sensed as true on the current sweep and was sensed as false on the previous sweep. An inverted transitional reference is true when the referenced condition is false on the current sweep and was true on the previous sweep.
Statement; Ready Condition (D)
For every statement, a true output from the R-node ultimately causes a D or ready condition 65 to occur. In most lines, the D condition coincides with the truth of the R-node (since processing of the statement occurs within the same sweep time as the detection of the referenced condition). In multi-sweep statements, (such as multiply and divide), the D condition does not occur until the completion of the calculation which may not occur for several sweeps. When a calculation is in progress, the line will not respond to a new R-node truth (DC) or transition (AC).
Statement; A, B, C, Registers, and Coil (K)
The process initiated by a true condition of the R-node commonly uses data or references supplied by the A, B, and C registers. Certain statements deposit information in the C register and most produce a logical result represented by the K coil
66.
SPECIAL LINES
Stepper Lines
FIGS. 7 and 11 and Table 3 illustrate in more detail the action of a stepper line 68. A stepper location can contain a full 80 bit line, but any value placed in the data area in excess of the maximum step number (99) causes all referenced conditions for the associated stepper to be false.
Input and Output Transformer Lines
Input transformers are illustrated in FIGS. 7 and 12 and Table 4 and output transformers are illustrated in FIGS. 7 and 13 and Table 5. These figures and tables are largely self-explanatory. It should be noted that combinations of stepper lines with input and output transformers, plus bit test and move statements (disclosed infra) permit rather flexible input/output, sequential state, shift register, and sequencer type process-control implementations. An input transformer location is a general purpose "scratchpad" register and therefore can contain a K or coil bit 66.
Statement Classification and Terminology
The various classes of statements are illustrated in relay ladder diagram symbology in FIG. 14. These may be generally classified as data manipulation statements, logical statements, and count statements. Any logical node in an instruction refers only to a condition; however, registers within data manipulation statements often contain or refer to data.
TABLE 3 ______________________________________ DESCRIPTION: CM lines 900-903 form four steppers. The decimal (BCD) contents of each "stepper" location is referenceable by active CM lines (0-199) as a set of 100 discrete conditions (coils) as shown above. At most, one condition in each set may be true at any time. If the contents of the stepper (L) .gtoreq. 10.sup.2, all conditions are false; If (L) = 0, the "Home" condition is true. If (L) = 1, "step 1" is true, etc. Stepper locations are "scratch-pad" to the CM and therefore may store a full 80 bits. Thus, associated coils (K900-K903) are also referenceable. RULE: Step S X Y Z is true when contents of Line 90X = YZ, where YZ = 00, 01, 02, 03, --- 99, and X = 0, 1, 2,
3 SXYZ = 0 for contents of line 90X .gtoreq. 10.sup.2. ______________________________________
TABLE 4 ______________________________________ DESCRIPTION: CM lines 910 - 913 form four input trans- formers. Each bit in the data area composed of the R, A, B, and C, Registers is ref- erenceable as a Condition (Coil) by any active line in the CM (lines 0-199). Loca- tions 910-913 appear as "scratch-pad" to the CM and are therefore full 80 bit locations. Thus, Coil conditions K910, K911, K912 and K913 are also referenceable. In general, these locations are treated as binary data. RULE: Line 91X, bit YZ corresponds to E coil 64 X + YZ where X = 0, 1, 2, 3 and YZ = 1, 2, 3, ______________________________________
TABLE 5 ______________________________________ DESCRIPTION: CM lines 920-923 form an image of CM active and scratch-pad lines, 64 per location. This map is useful for CM-to- output and CM-to-CM communication. Out- put transformer lines are updated con- tinuously. They are initialized to zero prior to the first sweep on power-up. NOTE: Bits in the output transformers correspond to K condition (Coils) 0-199 on an instantaneous basis. RULE: Line 92X, bit YZ contains K coil 64X + YZ where X = 0, 1, 2, 3; YZ = 1, 2, 3, OUTPUT CONDITIONS: K923 are False RESTRICTIONS: If a CM statement (other than move in or move out line) deposits into line920-923, data will not be written, and map content will not be affected. Warning: Move in or move out line may cause data type to change, thus defeating this protection. ______________________________________
If a register within a statement contains data used in creating the result of the instruction, it is called local data; however, if the register contains a reference to data (i.e., the location in a memory location where data resides), it is called remote. Whenever a data reference is remote, only the B register can specify a data location external to the command memory; that is, the A and C registers can only specify data locations within the particular command memory.
Line Coding
FIG. 15 illustrates the coding format of the various line types. A statement contains decimal data expressed in binary coded decimal data (BCD); one four-digit quantity to each register as shown. A datum is expressed in either BCD or 8-bit coded digits. Whenever a data manipulation is performed between lines having data of varying formats, conversion between formats is automatic. When a statement is referenced as data, the content of the C register is used regardless of the actual significance of this information. Modification of the C register of a "logic" statement is prevented by hardware. In a numeric manipulation, nondecimal values contained in referenced data registers produce meaningless results. Binary (discrete) data is used primarily for condition and input/output manipulation
Details of the I and R register coding formats are shown in FIGS. 15A, 15B, and 15C. As shown in these figures, the operation code (opcode) designating the type of line selected is stored in the first 10 bits of the I register. A summary of these opcodes is given in Table 5A for both hexidecimal and octal numbering systems. Bit 10 of the I register is the "suspend" bit, discussed infra, while bit 11 is the "enable" bit, discussed infra. The remaining four bits of the I register store information relating to the D and K conditions, and the prior state of the D condition.
As best seen in FIG. 15A, the R register stores information relating to the desired contact specifications which activates the R register and the line depending on the state of the selected K, E, D, or S condition of the reference line. These four R register contact specifications are: (1) normal static true 41; (2) static false 43; (3) false-to-true transition (AC leading edge) 45; and true-to-false transition (AC falling edge). The normal static true contact specification activates the R register if the selected reference condition (D, K, E, or S condition of the referenced line) is presently true. Conversely, the static false specification activates the R register if the reference condition is presently false. The AC leading edge specification activates the R register if the selected reference condition was false during the last sweep or scan and is presently true; while the AC falling edge activates the R register if the selected reference condition was true and is presently false.
TABLE 5A ______________________________________ SUMMARY OF OPCODES OPCODES LOCAL REMOTE* FUNCTION HEX OCT HEX OCT ______________________________________ BIN DATA 0/0/0/ 0/0/0/0/ N.A. NO STORE BIN DATA 0/10/ 0/0/20/ N.A. BCD DATA 0/20/
0/0/40/ N.A. ASCII DATA 0/30/ 0/0/60/ N.A. ADD 0/40/ 0/10/0/ 0/50/ 0/120 SUB 0/41 0/10/1 0/51 0/121 MUL 0/42 0/10/2 0/52 0/122 DIV 0/43 0/10/3 0/53 0/123 COMP 0/44 0/10/4 0/54 0/124 MATCH 0/45 0/10/5 0/55 0/125 TEST 0/46 0/10/6 0/56 0/126 GET DATA 0/87 0/207 0/97 0/227 PUT DATA 0188 0/210 0/98 0/230/ GET LINE 0/89 0/211 0/99 0/231 PUT LINE 0/8A 0/212 0/9A 0/232 BLOCK GET 0/AE 0/256 0/BE 0/276 COUNT REF 0/AB 0/253 0/BB 0/273 TMR SEC 1AB 0/653 1BB 0/673 TMR 0/.1 SEC 2AB 1253 2BB 1273 TMR .0/1 SEC 3AB 1653 3BB 1673 BIT TEST 0/CC 0/314 0/DC 0/334 PARALYZE 0/AD 0/255 0/BD 0/275 RELAY 0/E0/ 0/340/ 0/FO 0/360/ MULT IN PROG. 0/60/ 0/140/ 0/70 0/160/ DIVD IN PROG 0/61 0/160/ 0/71 0/161 XFX SPARES : XXE XXF ______________________________________ *REMOTE = LOCAL + 0/10/.sub.16
Example of R register references are shown in FIG. 10. The reference line number is stored in bits 0-11 of the R register.
As best seen in FIG. 15C, for logical statement lines the A, B, and C registers refer to desired reference line conditions, specifying the D, E, S, or K conditions. These conditions are sensed as well as the contact specification--"and" 49, "and not" 51, "or" 53, and "or not" 59--that activate the particular A, B, or C node depending on the state of the referenced D, E, S, or K condition. It should be noted that certain nodes of counter, bit test and suspend lines also use the contact specification shown in FIG. 15C for some of the A, B, C nodes. The R node of a logical statement is analogous to the R register of any other type of statement (see FIG. 15B).
DETAILS OF THE INSTRUCTION SET
FIGS. 16A through 16SS and corresponding Tables 7A through 7XX form a detailed description of each statement and a description of the datum. Table 6 is a summary of this instruction or statement set. Some additional explanation follows.
Calculate (FIGS. 16A-16H, Table 7A-7H)
Calculate instructions (+, -, .times., -) deal with positive integers only. The result of the subtract statement is magnitude, with the coil (K) representing sign. For add, multiply and divide statements, the coil represents overflow or exceeding of data limits. Multiply and divide statements also place restrictions on the magnitude of the multiplier, multiplicand, and divisor as detailed in the figures.
Data Transfer and Move In, Move Out Line Transfer FIGS. 16O-16AA, Tables 7O-82AA
These statements are used for moving single datums, tables of data, or instruction sequences between locations within the PPC system. Two classes of move in and move out statements are provided. "Move in data" and "move out data" can move the data areas of lines only, with appropriate format conversion. The "move in" line and "move out" line statements are primarily for program loading, and must be used judiciously. These statements move entire lines without modification. In all move in and move out statements, the C register represents an "index" or "offset," allowing the instruction to point to any one of a number of locations within a table.
TABLE 6 ______________________________________ STATEMENT SET AND DATUM SUMMARY ______________________________________ Statement Local Remote (FIG. 16-) (FIG. 16-) (Table 7-) (Table 7-) Arithmetic Add A B Subtract C D Multiply E F Divide G H Compare I J Match K L Test M N Data Transfer Move In O P Move Out Q R Pack S T Unpack U V FIFO W Line Transfer Move In X Y Move Out Z AA Move In Block BB CC Move Out Block DD EE Suspend FF GG Count Preset Count HH II Up/Down Count JJ KK Timer .01 sec HH II Timer .1 sec HH II Timer 1 sec HH II Bit Oriented Bit Manipulate LL MM Bit Match NN OO Bit Shift PP QQ Logic RR Datum FIG. 16- Table 7- DIS to BCD and BCD to DIS SS SS DIS, BCD or DNS to ASCII SS and SSA SS ASCII to BCD or DIS SS and SSB SS Statement to ASCII SS and SSC SS Statement to BCD or DIS SS and SSD SS ASCII to Statement SS and SSE SS BCD, DIS, or DNS to Statement SS and SSF SS Logic to any other Line Type -- SS ______________________________________
TABLE 7A __________________________________________________________________________ STATEMENT: ADD LOCAL OPERATION: If R is True, A + (B).fwdarw.C Note 1. The sum A+ (B) is calculated modulo 10.sup.4 and deposited into the C Register 2. (B) is the data content of Line B located in CM, I/O, or DM RESTRICTIONS: A is BCD, 0.ltoreq.A<10.sup.4 B is BCD, 0.ltoreq.B<10.sup.4 C is BCD, 0.ltoreq.C<10.sup.4 INPUT CONDITIONS: R=DXXX, Where 0.ltoreq.XXX<10.sup.3 KXXX, EXXX, or SXXX R is normal or inverted, AC or DC OUTPUT CONDITIONS: K: is true if A+ (B).gtoreq.10.sup.4 and D is true D: (Data Ready) is true if R is true TIMING: Solved each sweep. __________________________________________________________________________
TABLE 7B __________________________________________________________________________ STATEMENT: ADD REMOTE __________________________________________________________________________ OPERATION: If R is True, (A) + (B) .fwdarw. (C) Note 1. The Data content of Line A plus the Data Content of Line B is deposited in the Data area of Line C. 2. The sum is calculated modulo 10.sup.16. 3. The sum is deposited according to Line C Data area modulus. 4. Lines A and C are in CM. Line B is in CM, DM, or I/O. RESTRICTIONS: A is BCD; 0 .ltoreq. A < 10.sup.3 (CM only) B is BCD; 0 .ltoreq. B < 10.sup.4 (CM, I/O, or DM) C is BCD; 0 .ltoreq. C < 10.sup.3 (CM only) INPUT CONDITIONS: R = D,E,K, or SXXX; normal or inverted, DC or AC where 0
.ltoreq. XXX < 10.sup.3 OUTPUT CONDITIONS: K : (Data out of limits) is true if sum .gtoreq. data area modulus of line C D : (Data Ready) is true if R is true TIMING: Solved each sweep. __________________________________________________________________________
TABLE 7C ______________________________________ STATEMENT: SUBTRACT LOCAL ______________________________________ OPERATION: If R is true .vertline.A-(B).vertline. .fwdarw. C Note 1. The difference of the data portion of l