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United States Patent
3905023
Perpiglia
September 9, 1975
Title
Large scale multi-level information processing system employing improved failsaft techniques
Abstract
A multiprogrammed multiprocessing information processing system having independently operating computing, input/output, and memory modules through an exchange, and interacting with a multi-level operating system designed to automatically makes optimum use of all system resources by controlling system resources and by scheduling jobs in the multiprogramming mix of the processing system. In operation, the operating system insures that all system resources are automatically allocated to meet the needs of the programs introduced into the system as well as insuring the continuous and automatic reassignment of resources, the initiation of new jobs, and the monitoring of their performance. System reliability is achieved by the incorporation of error detection circuit throughout the system, by single-bit correction of errors in memory, by recording errors for software analysis and by modularization and redundacy of critical elements.
Inventors:
Perpiglia; Frank Joseph
(Springfield,
PA
)
Assignee:
Burroughs Corporation
(Detroit,
MI
)
Appl. No.:
388551
Filed:
August 15, 1973
Current U.S. Class:
714/6
Field of Search:
340/172.5 235/153AK
U.S. Patent Documents
3266020
August 1966
Cheney et al.
3319226
May 1967
Mott et al.
3416139
December 1968
Marx
3548382
December 1970
Lichty et al.
3566357
February 1971
Ling
3623011
November 1971
Baynard, Jr. et al.
3760365
September 1972
Kurtzberg et al.
3787816
January 1974
Hauck et al.
3787818
January 1974
Arnold et al.
3792448
February 1974
Bennett et al.
R27703
July 1973
Stafford et al.
Primary Examiner:
Shaw; Gareth D.
Assistant Examiner:
Nusbaum; Mark Edward
Attorney, Agent or Firm:
Chung; Edmund M. Feeney, Jr.; Edward J. Peterson; Kevin R.
Claims
What is claimed is:
1. A multi-processing modular data processing system including a plurality of peripheral devices comprising:
a plurality of memory modules interconnected by a memory bus to provide a multi-accessable main memory for said system, each of said plurality of memory modules including a memory control unit and at least one memory storage unit, each of said memory control units being connected to said memory bus and including means for detecting errors in the transfer of information between said memory bus and said memory storage unit;
a plurality of central processing modules, each of said plurality of central processing modules including a program control section and a storage section, each of said storage sections being connected to said memory bus and including means for indicating malfunctions internal to said respective processing module and errors related to information transfer between said respective processing module and said main memory;
a plurality of input/output modules, each of said input/output modules including a memory interface unit and a translator unit, said memory interface unit of each of said plurality of input/output modules being connected to said memory bus, said translator unit of each of said plurality of input/output modules being connected to said program control section of each of said processing modules for receiving control information and including means for detecting and reporting malfunctions internal to said respective input/output module and errors related to information transfers between said respective input/output module and said plurality of peripheral devices;
a maintenance bus coupled to each of said memory control units of said plurality of memory modules and to each of said storage sections of said plurality of central processing modules and to each of said memory interface units of said plurality of input/output modules; and
maintenance diagnostic means coupled to said maintenance bus for off-line testing of each of said plurality of said central processing modules, each of said plurality of input/output modules, and said memory control units of each of said plurality of memory modules;
2. The data processing system of claim 1 wherein said memory control unit further includes:
means for correcting all single-bit errors in information received from said at least one memory storage unit associated with said memory control unit before said transfer of information to said memory bus.
Description
TABLE OF CONTENTS
Abstract of the Disclosure
Background of the Invention
Summary of the Invention
Brief Description of the Drawing
General Description of the System
Detailed Description of the Invention
A. central Processor
B. communications Unit
C. input/Output Subsystem
D. memory Subsystem
E. maintenance Diagnostic Unit
F. multi-Level Operating System
This invention relates to an information processing system and more particularly to a multi-level processing system and a management control subsystem for the multi-level processing system.
BACKGROUND OF THE INVENTION
In early multi-processor information processing systems, one processor and only one processor could be designated as a control or master processor. One of the functions of this master processor was the control of the servicing of the interrupts by the modules of the information processing system. In operation, each processor in a multi-processing system may be executing a different program and therefore one processor could be executing a high level priority program and another, a low level priority program. When an interrupt, such as from an input device, is requested, and assume for purposes of discussion the first processor has been designated the master or control processor, and that the request had a lower priority than the priority of the high level program being executed by the first processor, the first processor would continue executing its program until completed before the interrupting program would be executed. Obviously, it is quite possible that the interrupting program could be of a much higher level priority than a low level priority program being executed by a second processor in the system. Priority then, in these prior art systems, was determined strictly by the relationship of the interrupting request to the program being executed by the processor designated the control processor.
On the other hand, without a central control of interrupts and masking, each processor must form its own accepting or rejecting of a task assignment. Thus, in the prior art, a central interrupt directory was provided, but in order to remit a processor to control or inhibit interrupt, the processor must be contacted, at which time, the processor must determine if the priority of the interrupt is high enough to warrant an interruption. Thus, means were provided in the prior art for permitting each processor in a multi-processing system to become a control processor thereby affording more efficient servicing of communication requests having a priority greater than the program being executed. This capability was usually provided in a central system controller for masking or disabling the interruption of the processor performing a program that is of a higher level than the program requested by an interrupting module and permitting the interruption of a processor executing a program which is of a lower level than the program requested by the interrupting module. In these multi-processor systems, it was common for the several data processors to share the same memory and the same input/output devices; however, one processor was still required for processing the master control program and allocating specific operations to one or more associated "slave" processors. In such an arrangement, all executive functions were performed by the master or control processor and all of the other processors operated merely as peripheral extensions of the master or control processor. However, to provide a completely modular system in the prior art in which a number of processes may be incorporated into the system, the hardware implementation of each processor was of necessity identical. This dictated that each processor in the system had equal capability of handling all programs including the master control program which was responsible for the job of scheduling and resource allocation for the system.
Present day large scale data processing systems find many applications for multi-programming including concurrent batch processing, real time processing, and time sharing. In order to accommodate a variety of such unrelated jobs or tasks, prior art systems have been provided with operataing systems or control programs which supervise such activities as task sequencing, storage allocation, and the like. Also provided as part of the operating system are the various compilers or language translators which permit the programmer, without knowledge of the circuit characteristics of the system, to employ a variety of programming languages. In the prior art systems, each of the one or more data processors alternately executed successive portions of the plurality of user programs. In such a system, a data processor assigned to execute a particular user program continued until the program either voluntarily relinquished control of the data processor or was involuntarily interrupted. A program relinquished control when it could not continue until after the occurrence of some future event, such as the receipt of input data or when it terminated. The released processor was immediately assigned to execute another waiting and ready program, either commencing initial execution of a new program, or the execution of a program from its point of relinquishment or interruption. The processor again continued this program in execution until a new point wherein the program relinquished the processor or the program was interrupted. Meanwhile, the voluntarily relinquishing programs stand by, awaiting the occurrences of their respective required events, whereupon they can become candidates for further execution. The interrupted programs, on the other hand, usually are immediate candidates for execution, but must wait assignment of a data processor according to a predetermined rule designed to maintain maximum system efficiency.
Viewing a program as comprising a series of instructions for directing the assigned data processor to execute in sequence the individual steps necessary to perform a particular data processing operation. The data processor communicates with the working store of the system to retrieve from respective cells thereof, each instruction to be executed and data items to be processed and to store therein data items which have been processed. Most of the instructions comprise an order portion denoting the type of operation the data processor must execute and an address portion representing the location of a cell in working storage from which the data item is to be retrieved for processing or into which a processed data item is to be inserted. Moreover, the data processor supplies an address representation to denote the cell from which the next instruction is to be obtained. Because the retrieval and storage time of working storage must be very short for compatibility with the very rapid rate of instruction execution of the modern data processor, the cost of working storage capacity is relatively great. Therefore, in the prior art, economics limited the size of the fast operating working store and, accordingly, the number of programs and quantity of information it could store at a particular time. To alleviate this problem in the prior art supplemental storage was provided for holding all user programs received from input devices and awaiting scheduling for execution, user program "libraries," and data files. This supplemental storage was provided by mass quantities of relatively inexpensive and slow "auxiliary storage." Ordinarily, the auxiliary store is coupled for communication with the working store to provide programs and information to the working store as they are required for processing. Additionally, the auxiliary store relieves working storage of processed data, providing temporary storage prior to transmittal of the processed data to an output device.
To make multi-programming and multi-processing a reality, a system must be capable of dynamically controlling its own resources and the scheduling of its jobs or tasks and it must be capable of processing a number of jobs concurrently in less time than it takes to process the same jobs serially. To implement multi-programming, a management control subsystem including a group of management control programs, program parts, and sub routines is required for exercising supervisory control over the data processing system. The group of management control programs, program parts, and subroutines is termed an "operating system." The primary purpose of the operating system is to maintain the user program in efficient concurrent execution by effective allocation of the limited system resources to the programs, these resources including the data processors, memory storage, and input and output equipment.
It should be noted that the type of task or jobs for which the system is to be used will affect the operating system which in turn affects the design of the system itself. If the system is designed to be job oriented then the supervisory program is geared to execute an incoming stream of programs and its associated input data. On the other hand, if the system is designed for real-time or time sharing operations, the supervisory program uses incoming pieces of data as being required to be routed to the number of processing programs. Moreover when the system is designed for time sharing, protection of different programs and related resources becomes important.
Although a single processor system may be multi-program, a greater degree of flexibility is achieved from a multi-processing system where a number of separate processes may be assigned to a plurality of processors. Examples of such multi-processing systems are disclosed in the Anderson et al, U.S. Pat. No. 3,419,849 and Lynch et al, U.S. Pat. No. 3,411,139. A central processor of the type employed in the Lynch et al patent is disclosed in Barnes et al, U.S. Pat. No.
3,401,376. Each of the above-mentioned patents is assigned to the assignee of the present invention.
The above-described systems employed operating systems which were designed for multi-processing systems. A particular distinction of the instant invention is that the processor modules employ circuitry to evaluate system instructions at a faster speed than previously accomplished. Traditionally, data or central processors have had their frequency set according to the longest propagation paths which existed in the logic. Most often, this critical path was the adder mechanism or the communications system with main memory. Obviously, every other logic path in the processor was shorter than this critical path and in many cases, such as simple register movements, the operations are executed at a rate above the basic clock frequency. Since the operand adder or main memory interface accounts for a small percentage of the operation time, a central processor of the prior art, as a whole, had rather poor efficiency.
Another factor which plays an important role in processing speed is the inherent limitations of single work referencing of main memory. These limitations are a particular deterrent in an environment where memory referencing is accomplished on a "need then demand" basis. This technique, though simple to mechanize, tends to force operations toward a serial nature.
In present day data processing systems it is particularly advantageous to have system programs, such as service programs, which are recursive or reentrant in nature. Furthermore, it is advantageous that such recursiveness exist in a hierarchy of levels and not just one level. Additionally, it is advantageous and even necessary that certain of the system programs as well as the user program must be protected in memory from unwarranted entry by unrelated processes being executed elsewhere in the same system. Still another characteristic which is advantageous is that of providing functions common to various source languages which functions are implemented in circuitry where possible to provide faster execution times.
More importantly, present day large scale information processing systems must be reliable not only in terms of accuracy but also in terms of dependability. Therefore, it is desirable to have a system which is very reliable and, secondly, a system which as a whole can continue to function despite failures in individual modules of the system.
It is therefore an object of the present invention to provide an improved information processing system for such diverse applications as time sharing, scientific problem solving, and other data processing tasks.
It is a further object of the present invention to provide a data processing system having a high degree of modularity which is capable of concurrent computation at a plurality of processing levels.
It is a further object of the present invention to provide a data processing system which is reliable and includes fail-soft capability.
SUMMARY OF THE INVENTION
The foregoing objects are achieved according to the instant invention by providing an information processing system which can be tailored to the processing needs of a user by arranging central processor modules, input/output modules and memory modules on an electronic grid or exchange under the management of a multi-level operating system or master control program which maximizes system throughput through the controlled interaction of independently operating computing, input/output, and memory modules through the exchange. The multi-level operating system makes multiprocessing and multiprogramming both functional and practical by dynamically controlling system resources and by scheduling jobs in the multiprogramming mix. Improved speed and reliability of instruction execution is achieved by reducing or masking the overhead associated with reference to memory by freeing the central processor from concern with input/output operations, and by employing fail-soft measures that minimize system degradation.
The three main sections of the central processor modules are designed for independent and parallel operation thus enabling a speeding up of arithmetic computations and data maniplations and the overlapping of these computations and manipulations with memory references. Also included in the central processor module are high-speed integrated circuit local memories which permit multiword transfers between a central processor module and the system's main memory and makes possible the anticipation of the need for program and data words, thereby reducing and at times virtually eliminating the time spent waiting for the completion of transfers to and from main memory.
Greater accessability to main memory to all users by reducing memory access times for each user is achieved by the four-way interleaving of addresses in main memory and the capability for phased multiword transfers of information to and from main memory in bursts of up to four words.
In further accord with the present invention, all input/output operations are asynchronously performed by the input/output module independent of the central processor module, which is therefore freed to perform other useful work.
Confidence in the reliability of system hardware through graceful degradation or fail-soft is provided by the ability of the multi-level operating system to dynamically and automatically reconfigure the modules of the system to exclude a faulty one, and by the use of separate power supplies and redundant regulators for each module. Modular design and redundant buses are also a fail-soft feature of the instant invention. Incorporated in all major modules of the system are error detection and reporting circuits, which provide the multi-level operating system with information to perform fail-soft analysis and dynamic reconfiguration of the system resources. The memory modules, however, are provided with single-bit error correction capability independent of the multi-level operating system.
The multi-level operating system of the instant invention may be viewed as comprising a base level and N successive levels. The base level, which is defined as the kernel, is the nucleus of the operating system, and provides the sole interface between system software and system hardware, as well as the operating environment for the next level, which is or are the control program(s). A control program, which operates under control of the kernel, is delegated by the kernel many tasks of program supervision, system supervision, and input/output control, and in turn provides the operating environment for user or application programs. Thus, in general, a process at each level of the operating system is responsible for the processes it creates at the next higher level and for no others. The reliability of the system is thus, in part, achieved through the isolation of control programs' environments, since the kernel acts as the interface between a control program and the system hardware. Under control of the kernel, it is thus possible to execute concurrently several control programs, each tailored to support a particular type of application, be it batch work, testing of hardware modules, or time sharing.
Other objects, features and advantages of the subject invention are presented in the following detailed description of the preferred embodiments and illustrated in the accompanying drawings, wherein:
FIG. 1 depicts the general configuration of the subject invention;
FIGS. 2A and 2B comprise a general block diagram of a system of the instant invention;
FIGS. 3A and 3B comprise a more detailed block diagram of the system shown in FIG. 2;
FIG. 4 is a simplified block diagram of a central processor module of the instant invention;
FIG. 5 is a functional block diagram of a stack buffer employed in the central processor module of FIG. 4;
FIG. 6 is a functional block diagram of the stack buffer and a stack memory area employed in the central processor module of FIG. 4;
FIG. 7 is a functional diagram of a stack buffer operation;
FIG. 8 is a generalized functional diagram of a buffer system of the instant invention;
FIG. 9 is a generalized block diagram of a communications unit employed in the central processor module of FIG. 4;
FIG. 10 is a representation of the format of a fail register for the central processor module of FIG. 4;
FIG. 11 is a simplified block diagram of the system of the instant invention;
FIg. 12 is a diagram showing the modular organization of an input/output module of the instant invention;
FIG. 13 depicts a general configuration of an input/output subsystem of the instant invention;
FIG. 14 is a diagram showing the information transfer rates for the input/output module of FIG. 12;
FIG. 15A and 15B comprise a functional block diagram of a job map for the input/output module of FIG. 12;
FIG. 16 is a representation of the format of a Home address control word as employed with the instant invention;
FIG. 17 is a representation of the format of a unit table control word as employed with the instant invention;
FIG. 18 is a representation of the format of an input/output queue head control word as employed with the instant invention;
FIG. 19 is a representation of the format of an input/output queue tail control word as employed with the instant invention;
FIG. 20 is a representation of the format of an status queue header control word as employed with the instant invention;
FIG. 21 is a representation of the format of an input/output control block as employed with the instant invention;
FIG. 22 is a representation of the format of an input/output control word as employed with the instant invention;
FIG. 23 is a diagram showing the functional areas of the input/output module of FIG. 12;
FIG. 24 is a basic block diagram of the input/output module of FIG. 12;
FIG. 25 is a functional block diagram of typical data transfer classification for the input/output module of FIG. 12;
FIG. 26 is a functional block diagram of the typical input/output interface with the central processor module of FIG. 4 and main memory of the system of FIG. 2;
FIG. 27 is a functional block diagram showing the data/error detection flow of the input/output module of FIG. 12;
FIGS. 28A and 28B comprise a functional block diagram showing input/output module path redundancy;
FIG. 29 is a diagram showing the modularity of a memory subsystem of the system of FIG. 2;
FIG. 30 is a functional diagram showing the data word transfer between memory and a user of memory;
FIG. 31 is a representation of the interface between a memory storage unit, a memory control module and a requesting unit;
FIG. 32 is a simplified block diagram of a memory control module of the instant invention;
FIGS. 33A and 33B comprise a detailed block diagram of a memory control module of the instant invention;
FIG. 34 is a representation of the signal interface between a memory control module and a requesting unit;
FIG. 35 is a diagram showing the function logic for error detection and correction in a memory module of the instant invention;
FIG. 36 is a representation of the data and control interface between a memory control module and a memory storage unit;
FIG. 37 is a diagram showing interlacing of memory storage units of the instant invention;
FIGS. 38A and 38B comprise a block diagram of a memory storage unit of the instant invention;
FIG. 39 is a timing diagram for a memory logic module of the instant invention;
FIG. 40 is a timing diagram for a memory storage module of the instant invention;
FIG. 41 is a block diagram for the clock system of the instant invention;
FIG. 42 is a simplified block diagram of the multi-level operating system of the instant invention;
FIG. 43 is a representation of the format of the fail register for the input/output module of FIG. 12.
GENERAL DESCRIPTION OF THE SYSTEM
The information processing system of the instant invention is a large scale, truly general purpose, balanced, flexible, modular multi-programming and multi-processing computer system that is suitable for such diverse applications as time-sharing, scientific problem solving, and business data processing. The system of the instant invention is designed to handle complex data structures and sophisticated program structures dictated both by higher level languages presently in use and by the requirements of advanced problems and is designed to manage efficiently the massive on-line and archival storage requirements of large data bases, and to accommodate vast networks of data communications devices.
The system of the instant invention is a very fast, modular parallel processing system with exceptional versitility and configuration, and can be tailored to the processing needs of a user by arranging central processor modules, input/output modules, and memory modules on an electronic grid, or exchange in a variety of ways depending upon the exact needs of the user. If the high performance and adaptability of the system of the instant invention could be attributed to a single factor, it would be to the balance attained by means of the controlled interraction of independently operating computing, input/output and memory modules through the exchange. With this arrangement, which will be described in detail, the throughput of the instant system as a whole is maximized, and the performance of no single element of the system is maximized to the neglect or detriment of the others.
The key to the efficient and balanced use of the system of the instant invention is the multi-level operating system, a unique executive software operating system that automatically makes optimum use of all the resources of the system. It is this operating system, which will be described in detail, that makes multi-processing and multi-programming both functional and practical by dynamically controlling the system resources and by scheduling jobs or tasks in the multi-programming mix. In operation, the multi-level operating system allocates system resources to meet the needs of the program introduced into the processing system. It continually and automatically reassigns resources, starts jobs, and monitors their performance.
Further implications of the modularity and flexibility of the system of the instant invention are its expandability (the capacity to add hardware modules without reprogramming) and its increased reliability is achieved by the use of fail-soft techniques that (in addition to providing for error detection and error correction, redundancy of data paths, and independence and redundancy of power supplies) excludes faulty modules from the system and permit processing to continue (again, without reprogramming) even with the temporarily reduced configuration.
Even though the system of the instant invention is a very large and immensely complicated and thus able to perform complex computations, the system is, nevertheless, comprehensible to the persons who use it: programming is accomplished only in higher level, problem-oriented languages (COBOL, ALGOL, FORTRAN, PL/I, and ESPOL); the control language used in entering jobs into the system is a simple, free-form English-like language; and the messages that pass between the system and the operator are brief, clear and easy to learn.
Although the balanced use of the principal components of the system as a whole under the control and coordination of the multi-level operating system is the key to the high throughput of the system, the high performance of the system is in large part achieved by improving the speed of execution of instructions, by reducing or masking the overhead associated with references to memory, by freeing the central processor modules from concern with input/output operations, and by employing fail-soft measures that minimize system degradation. Moreover, the system main-frame hardware has been designed and built strictly according to stringent circuit and wiring rules and proven design and packaging techniques well known in the art. This factor and the incorporation of monolithic integrated circuits in the processing elements, permits the system to perform consistently at high operating frequencies.
The fail-soft features of the system of the instant invention are designed to keep the system running 100 percent of the time, minimize system degradation, and to provide the user with tools for performing his own data recovery. These goals are achieved by a unique combination of hardware and software throughout the system. In the instant invention, the system is maintained operational by the higher reliability of the system hardware, by the incorporation of error detection circuits throughout the system, by single-bit error correction of errors in memory, by recording erros for software analysis, by modular design, by use of separate power supplies and redundant regulators for each module, by use of redundant busses, and by the ability of the multi-level operating system to reconfigure the modules of the system to temporarily exclude a faulty module. In short, the detection and reporting of errors is accomplished by hardware, analysis of errors is performed by software, and the reconfiguration of the system is accomplished dynamically by multi-level operation. Because of the modularity of power supplies and the use of redundant regulated supplies for critical voltages, the impact of a malfunctioning voltage supply is minimized and does not result in a catastrophic failure.
Minimization of system degradation is achieved by providing diagnostic programs and equipment for rapidly identifying and repairing faults and for reestablishing confidence in a repaired module before it is returned to the user's system. The diagnostic portion of the multi-level operating system is designed to identify a faulty module, and by the use of a maintenance diagnostic unit of the instant invention, a fault in any main frame module or in a disk file optimizer is narrowed to a single clock period and to a flip-flop and its associated logic circuit. Finally, by the use of a card tester on the maintenance diagnostic unit, the faulty integrated circuit chip can be identified.
To provide the user with tools for performing his own data recovery the system of the instant invention is designed with such features as installation allocated disk, protected disk files, duplicate files, and fault statements in the higher level programming languages used on the system. Installation allocated disks permits the user to specify the physical allocation of his critical disk files in order to facilitate the maintenance and reconstruction of these files. Protected disk files permit the user to gain access to the last portion of valid data written in a file before an unexpected system halt. The use of duplicate disk files is to avoid the problem of fatal disk file errors. The multi-level operating system of the instant invention maintains more than one copy of each disk file row, and, if access cannot be gained to a record, an attempt is made to gain access to the copy of the record. By the use of fault statements, the user can stipulate the action to be taken by his program in case certain errors occur.
Physically the components of the system of the instant invention falls into three categories. The first category includes the central components of the system, namely, the central processor modules 20, the input/output modules 10, the memory modules 30a, which collectively comprise main memory 30, the maintenance diagnostic units 26, and the operators console (not shown), see FIG. 1. The second category includes the peripheral controls 38 and exchanges, the disk file optimizer 40, the data communications processor 36, see FIG. 2, and AC power supplies.
The third category includes standard peripheral devices that are joined in the central system by means of the standard peripheral controls, adaptors, and exchanges and standard remote devices that are joined to the central system by means of line adaptors and the data communications processors 36.
The arrangement of the components of these three categories into a system and the size of the system depends on the application and workload of the user. In the following paragraphs, the maximum and the typical configuration with full fail-soft capabilities will be described.
The theoretical maximum configuration of the system of the instant invention is shown in FIG. 2. As many as eight memory modules 30a may be arranged on an exchange with a combined total of up to eight requestors of memories 30a, i.e., central processor modules 20 and input/output modules 10. Any single requestor of memory may address and gain access to the entire content of the high speed main memory 30. A maintenance bus 32 is provided to service the controls for the memory modules 30a, the central processor modules 20, the input/output modules 10, and the disk file optimizers 40. Either one or two maintenance diagnostic units 26 may be placed on the maintenance bus 32. At a rate of up to 6.75 million bytes per second, a single input/output module 10 is capable of transferring data simultaneously between main memory 30 and 28 peripheral controls 38 (including eight high speed controls) and between main memory 30 and as many as four data communications processors 36. It is also capable of handling as many as four disk file optimizers 40 (devices that are used in improving the rate of transfer of data between main memory 30 and disk files). In the preferred embodiment, the number of high speed, medium speed, and low speed peripheral devices that may be attached through controls and exchanges to a single input/output module 10 or that may be included in the input/output subsystem is 255. For purposes of discussion, each card reader, pseudo reader card punch, line printer, tape reader, paper tape punch, operator's display terminal, and free-standing magnetic tape unit; each station on a magnetic tape cluster; and each electronic unit in a disk file subsystem is considered a device. By suitable cross connections through exchanges, it is possible to establish pathways between disk files, disk packs, or magnetic tape units in more than one input/output module 10, hence, these peripheral devices can be shared by all of the input/output modules 10 in the system.
Among the peripheral devices available are disk files and disk file memory modules that constitute a virtual memory which in effect greatly expands the storage capacity of the main memory 30 of the system; see FIG. 3, these modules, which are interfaced with the input/output module 10 through controls are as follows: (1) head-pertrack-disk file optimizers 40 to form optimized-access memory banks capable of storing some 450 million to 8 billion 8-bit bytes information per input/output module
10 and whose access time is in effect in the range of 2 to 6 milliseconds or four to ten milliseconds; (2) head-per-track disk file modules that are combined (without the control of the optimizer) into random access memory banks of from 15 million to 16
billion 8-bit bytes per input/output module 10 and whose average access time is 20 to 35 milliseconds; (3) disk pack memory modules that are combined into random access memory banks with a capacity of from 121 million to many billions of 8-bit bytes of storage per input/output module 10 and whose average access time is 30 milliseconds.
Besides the 255 peripheral devices that may be included in an input/output subsystem, there is a vast network of remote terminals, remote controllers, and remote computers that can be accommodated by the up to 1,024 remote lines serviced by the four programmable data communications processors 36 that can be controlled by a single input/output module 10. Normally, each line handles a number of remote devices, and, naturally, systems that have more than one input/output module 10 can have more than one data communications network. The maximum number of data communications processors 36 that can be included in the system of the instant invention is 28, (seven input/output modules).
The power, speed, flexibility and reliability of which the system of the instant invention is capable are fully realized in a configuration that includes two central processor modules 20, two input/output modules 10, four memory modules 30a, one maintenance diagnostic unit 26, and its associated magnetic tape unit 35, and two operator's consoles 27 (one per IOM). Besides these central components, this typical fail-soft configuration must include two disk file memory subsystems (one for each input/output module 10) or a single disk file subsystem that is shared by means of exchanges by the two input/output modules 10, peripheral controls 38, and AC power cabinets. Naturally, a complement of peripheral devices and their controls and exchanges, data communications processors 36, and remote devices suited to the application and workload of the system is also required. A system of the proportions described above incorporates fully the fail-soft features of the system of the instant invention and takes complete advantage of its capabilities of handling 4-word transfers of data to and from main memory 30.
The following paragraphs provide a description of the principal components and functional subsystems that, under the control of the multi-level operating system of the instant invention and arranged in the configuration suited to the particular data processing needs, comprise the preferred embodiment of the information processing system of the instant invention. These components and subsystems are the central processor modules 20, the input/output subsystem, the memory subsystem, the maintenance diagnostic unit 26, the operator's console (not shown), the disk file subsystem, the data communication subsystem, and the power subsystem.
DETAILED DESCRIPTION OF THE INVENTION
A. Central Processor
The computational element of the system is the central processor module 20. In the preferred embodiment the central processor module 20 has a 16 mHz clock rate. There are three major, independent, asynchronously operating sections of the central processor module 20, namely, the program section 42, the execution section 44, and the storage section 46, see FIG. 4. Communication between these sections is carried out by means of queues of operations. Because of the parallelism of the central processor module 20, arithmetic computations and data manipulations, the calculation of addresses, and the transferring of data to and from memory may go on at the same time.
Briefly, the program section 42 performs instruction decoding operations of object code strings and absolute address calculations, the execution section 44 performs all arithmetic and logical data manipulation operations, and the storage section
46 performs all storage related functions. The general interconnections and data flow between these three sections is shown in FIG. 4. As discussed, communications between the sections is established by operating queues.
The program section 42 includes a program buffer 48 and program barrel 54, a program control unit 56, a fault control logic 58 and an address unit 60. The program section 42 is responsible for extracting each instruction from the program code string and initiating processing of the instructions. The program section 42 also controls and responds to the fault interrupt system, which will be described later. The primary responsibility of the program section 42 is to separate the object code string into operations which are then placed in the appropriate queues for the execution section 44. A few instructions are operated entirely by the program section 42, such as an unconditional branch, and others are executed in part.
In the preferred embodiment, Polish notation is used as the base for the system's ALGOL compilation algorithm. In compiler translation, the source expression is examined one symbol at a time with a left to right scan and is combined into logical entities. As each logical entity is examined, a specific procedure is followed so that the Polish notation expression is constructed in its finalized form with one scan of the source expression. When the program is compiled, the computational part of the source program will be converted into a machine language string of instructions. An example of this is the source language plus sign (+) which will be directly replaced by the machine language ADD instruction. The language string, resembling a Polish notation string, will be referred to as the program code string. This code string will be divided into two or more variable sized segments, according to the structure of the program. Program segments are normally stored on disk files. When a program is executed, program segments are made present in memory as needed. Because such program segments cannot be modified, a single copy of a program segment in memory may be used for several concurrent executions of the same program; thus, the program code string is often described as "re-entrant" or "recursive."
As mentioned earlier, a program code string may be divided into two or more program segments. For each program segment, there is a single segment descriptor, which defines the length and location of the program segment. The segment descriptors are stored in a special stack known as the segment dictionary. Thus, each job is associated not only with one job stack, but also with one segment dictionary stack. In addition, the multi-level operating system of the instant invention has its own stack and segment dictionary. Within the job stack, a Program Control Word (PCW) is provided for each point of entry into a segment of code. The program control word (PCW) provides an index, not only into the segment dictionary to locate the proper segment descriptor, but also into the program segment itself to locate the proper program word and syllable.
The constants and variables of a program are assigned locations within the "stack" of a program when it is compiled. The stack can be thought of as analogous to a physical stack with the last item placed on top of the stack. When items are removed (one at a time) from the stack, the item on the top of the stack is the first item to be removed. The item at the bottom of the stack remains at the bottom of the stack until all other items have been removed from the stack. The stack not only provides an easily manageable means for keeping a dynamic history of the program as it is being processed, but also lends itself to the use of program code strings based on Polish notation.
In the preferred embodiment, when a job is activated, two top-of-stack locations (A & B), see FIG. 5, are linked to the job's stack. This linkage is established by a stack-pointer register (S) 63, which contains the memory address of the last word placed in the stack. The two top-of-stack (TOS) locations (A & B) extend the stack to provide quick access for data manipulation. Data is brought into the stack through the top-of-stack locations in such a manner that the last operand placed into the stack is the first to be extracted. Total capacity of the top-of-stack location (A & B) is two operands. Loading a third operand into the top-of-stack locations causes the first operand to be pushed from the top-of-stack locations into the stack. The stack-pointer register (S) 63 is incremented by one before a word is placed into the stack and is decremented by one after a word is withdrawn from the stack and placed into the top-of-stack location. As a result, the S register 63 continually points to the last word placed into the job's stack.
In the preferred embodiment, a job's stack is bounded, for memory protection, by two registers; the Base-of-Stack register (BOSR) 65 and the Limit-of-Stack register (LOSR) 67. The contents of the BOSR register 65 defines the base of the stack, and the contents of the LOSR register 67 defines the upper limit of the stack. The job is interrupted if the S register 63 is set to the value, contained in either the LOSR register 67 or the BOSR register 65.
The contents of the top-of-stack location are maintained automatically by the central processor 20 to meet the requirements of the current operator. If the current operator requires data transfer into the stack, the top-of-stack locations receive the incoming data, and the surplus contents, if any, of the top-of-stack locations are pushed into the stack. Words are brought out of the stack into the top-of-stack locations. These words are used by the operators which require the presence of data in the top-of-stack locations. These operators, however, do not explicitly move data into the stack.
In the preferred embodiment each top-of-stack location (A & B) can accommodate two memory words. For single precision operations, location A will contain one single precision operand and location B will contain the other single precision operand. However, calling a double precision operand into either of the top-of-stack locations (A & B) will cause both halves of the double precision operand to be loaded into the A or B location. The first word is loaded into the top-of-stack and its associated tag bits are checked. If the value of the tag bits indicate double precision, the second half of the operand is loaded into the second half of the top-of-stack location. Double precision operands revert to single words when they are pushed down into the stack (the most significant half of the operand is pushed down first). The process is reversed when a double precision operand is returned from the stack of the top-of-stack locations. That is, the least significant half of the double precision operand is popped up first and the tag is discovered to have a value of two, causing the most significant half of the operand to also be popped into the top-of-stack.
In the preferred embodiment, stack implementation includes a 32-word stack buffer 50, which permits a portion of an active stack to be contained in IC memory locations within the central processor modules 20. This stack buffer 50, see FIG. 6, may contain information which has not yet been written to core or main memory 30, as well as copies of words which are resident in core or main memory. Stack buffer 50 permits a portion of the stack to be held local within the central processor module
20, to provide quick access for stack manipulation by the execution section 44 of the central processor module 20.
In addition to the portion of the stack held local in the stack buffer 50, certain other data from the stack may be contained in a local memory within the central processor module 20. This local memory, the associate memory of memory 52, is used to capture data fetched by the program unit look ahead which is not resident in the stack buffer. Although an active stack may be contained partly in the stack buffer 50 within the central processor module 20 and partly in core memory, the stack buffer
50 is purged whenever the stack becomes inactive (when a move-to-stack operation takes place). This purging of the stack buffer 50 causes the unique data within the stack buffer 50 to be copied to core memory.
One very important aspect of the system of the instant invention is the retention of the dynamic history for the program being processed. Two lists of program history are maintained in the system's stack, the addressing environment list and the stack history list. Both of these lists are dynamic, varying as the job proceeds along different program paths with varying sets of data. The two lists grow and contract in accordance with the procedural depth of the program. Both of these lists are generated automatically by the system hardware.
Turning now to the execution section of the central processor 20, the execution section 44 includes an execution unit 62 and the execution unit input queues 64. The execution section 44 is responsible for all data and control manipulations involving the stack. The execution section 44 performs all arithmetic and logical operations as well as stack related control functions. The execution section 44 is driven in an orderly manner from a first-in first-out list of operations placed in its operator queue by the program section 42.
The storage section 46 includes a storage unit 66, the stack buffer unit 50, the associative memory 52, and a communications unit 68. The storage section 46 is responsible for all storage related functions. Some of the storage section's duties are implied, such as maintaining the stack buffer 50, but most operations are explicit in that they result directly from the processing of program code. Implicit operations for storage section 46 are placed in the input queue 70 of the storage unit 66
by either the program section 42 or the execution section 44. It is the responsibility of the storage section 46 to determine if an address reference points to local storage or main memory 30 in which case, a main memory cycle is necessary.
These major sections are subdivided into units which operate relatively independently. The program control unit 56 of the program section 42 is an asynchronously functioning unit of logic intended to maintain the program buffer 48, and separate the object code into operations which are placed in the appropriate queues of the execution unit queues 64 for execution. The organization of the program control unit 56 is such that multiple syllable operators that overlap word boundaries in the program buffer 48 do not cause additional overhead. Branch points which happen to be within the buffer 48 are detected automatically and that code is entered without program fetch from the main memory 30.
In the preferred embodiment, the program buffer 48 of the program section 42 of a central processor module 20 is an array of IC memory chips which provides a total local memory capacity of 32 words of 60 bits each. The actual physical configuration is two memories of 16 words each. As shown in FIG. 4, these two memory divisions are interleaved such that all odd words from main memory 30 are stored in one division and all even words in another. Each division is further divided into four segments, zero through three. The buffer is loaded in segments of four words per main memory reference. The algorithm for loading the program buffer 48 is based on anticipation rather than waiting until the buffer 48 is empty, so that full advantage is taken of the natural idle time on the main memory bus 47, as shown in FIG. 2. As the words are brought in, they are alternately placed in the odd and even divisions of the program buffer 48. Each word brought in has parity checked on all
51 bits. As each word is placed into the program buffer 48, parity is generated and stored on each syllable; thus, regardless of the number of syllables for a given instruction or its route through the central processor 20, its integrity is maintained by parity on each individual syllable.
The address computation unit 60 of the program section 42 includes the logic necessary for the calculation of absolute addresses. This unit has a storage area of 48 words by 20 bits. The storage area is provided with input and output registers, of which the output register is used to buffer registers during an adder/comparator cycle so that a storage cycle may occur simultaneously. The input register of the storage area is used to buffer data for a write cycle so that the controlling logic can release immediately instead of waiting for the storage cycle to complete. This input register also serves to hold a value for the adder/comparator, for subsequent calculations such as found in string processing (e.g., index plus constant plus base). All write cycles into the storage area of the address computation unit 60 are controlled by the execution section 44, but read cycles for the purpose of address computation can be initiated from either the execution section 44 or the program section 42
of a central processor module 20. Separate read registers are provided for these two sections, and a priority resolver settles any conflicts. It should be noted that the address computation unit 60 is not directly in the pipeline and is therefore not queue driven. As previously mentioned, the address computation unit 60 is autonomous only to the extent that a write cycle to the IC memory of a central processor module 20 need only be initiated and not completely controlled by the initiating logic.
The fault control unit 58 of the program section 42 is designed to aid in the general maintenance, and error recovery under the guidance of the fail-soft portion of the multi-level operating system of the instant invention. Error recovery is aided by a system of multiple levels of control states coupled with alternate stack and display zero capabilities. The fault control unit 58 includes a fault condition register which records system interrupts and conditions the central processor 20 to take the necessary action in order to handle these interrupts. This register records both operator dependent and operator independent interrupts.
The execution unit 62 of the execution section 44 of a central processor module 20 is the final stop in the processing pipeline. The great majority of instructions are not completed until the execution unit 62 is reached. The execution unit 62
is the only unit in the processor 20 which operates on value data. It also has some control word formation and address calculation responsibilities. This unit includes the two top-of-stack registers A and B and may temporarily store parts of character strings on which it is operating. The execution unit 62 like the program control unit 56 is queue driven. All operations and operator associated data are placed into the queue of the execution unit 62 by the program control unit 56. The value data inputs are supplied by the storage control unit 66 of the storage section 46. Responsibility for the write control into the queue is shared by the program and storage units. Reading of information from the queue is the sole responsibility of the execution unit 62. The status of the input queue is monitored, for obvious reasons, by the program section 42 in order to detect queue full, and queue empty when unit synchronization is necessary. A queue input register is provided to allow the transmitting unit to release as soon as the register is loaded. The actual write cycle initiates after the loading of the queue input register. In the preferred embodiment, the queue is implemented by memory chips thus affording simultaneous read and write operations.
The storage unit 66 of the storage section 46 of the central processor module 20 includes the logic necessary to control all references to main memory 30. Main memory references can be initiated independent of the program operator function or as a direct result of operator execution. The independent operations are the control of the program buffer 48, the associative memory 52 and the stack buffer 50. The references to main memory 30 which are a direct result of operator execution are presented to the storage control unit 66 through its operation queue 70. The actual operations in the queue are placed there by the program control unit 56 as the program is phased. The addresses pertinent to an operation are placed in a queue by either program control, or by the execution section 44.
The storage control unit 70 is responsible for monitoring stack functions to determine if they are within the limits established by the Base-Of-Stack register (BOSR) 65 and the Limit-Of-Stack register (LOSR) 67. In checking these limits, the storage control unit 66 must take into account the number of locals so that bounds detection is not after the fact.
The input queue is controlled essentially by all of the sub-sections of the central processor 20. The program control unit 56 also provides the operator. The address can be calculated by either the program control unit 56 or by the execution unit 62 and data for store functions is always taken from the execution unit 62. When a reference is determined to be "not local" the storage control unit 66 initiates a reference to main memory 30. In the event that anything out of the ordinary occurs during a main memory fetch reference, the storage unit 66 initiates an orderly termination and passes the data and sufficient control information to describe the problem to the execution unit 62 through the unit's input queue 64. It is necessary that reaction to irregularities be deferred by the storage unit 66 since on fetch functions this unit may be ahead of the actual execution point. The execution unit 62 is the section of the central processor 20 which actually defines the point of execution for the program, therefore nothing that unexpectedly changes the order of the program may be allowed to take place until the associated operator reaches the top of the execution queue 64. For store functions, the execution unit 62 and the storage unit
66 are already in sync and fault reaction takes place immediately.
In the preferred embodiment, the storage control unit 66 is capable of overlapping operations within its unit. This situation occurs whenever a reference to main memory 30 is initiated. When the communication unit 68 of the storage section 46
is handling an external reference, the storage unit 66 can go on to the next entry in its input queue 70. If in the event that an operation references a variable that is local to the stack buffer 50 or associative memory 52, then the local reference is completed in parallel with the main memory reference. The overlap is not restricted to one operation. The storage unit 66 is free to process operations out of its input queue 70 for as long as possible or until the external reference is completed. The benefit of this overlap comes from the fact that most references to variables used in constructing a Terminal descriptor are local. Then, although the item referenced by the Terminal descriptor is external (data array in particular), the time spent in main memory 30 is effectively masked by subsequent descriptor construction.
The program buffer 48 of the program section 42 is a 32-word area of local processor memory used to capture a portion of the executing program's object code. Since a program buffer 48 is up-dated in multi-word segments, full advantage is taken of the phased memory system. In the preferred embodiment, object code averages 3.5 instructions per program word so that a good deal of program logic will be resident to the program buffer 48. The buffer "window" tends to slide over the object code string to entirely capture program loops; hence, in most cases, branching may take place without a main memory reference for the new program word.
The stack buffer 50 is an area of memory assigned to a job to provide storage for basic program and data references. The stack also provides temporary storage for data and job history. When a job is activated, a linkage between its stack and the top-of-stack registers (A & B) is established by the stack pointer register (S) 63, which contains the memory address of the last word placed in the stack. The stack buffer serves to extend the stack memory area into the processor local IC memory and to provide quick access for stack manipulation by the execution unit 62, see FIG. 6. The primary purpose of the stack buffer 50 is to hold, locally, a portion of the stack environment in any of 32 IC memory locations. The addressing scheme in this local memory is organized in a wrap-around fashion. Data is brought into the stack in such a manner that the last operand placed in the stack is the first to be extracted. As previously discussed, after the two top-of-stack registers (A & B) are filled, loading a third operand into the top-of-stack causes the first to be pushed into the stack buffer 50. As entries are pushed into the stack buffer 50, and when saturation is attained, a segment of the buffer entries is autonomously moved into main memory 30 so that the stack buffer 50 maintains the top area of the stack memory area. Any stack adjustment to main memory 30 is always accomplished in multi-word segments in order to take full advantage of the phased memory system. This "window" of stack entries tends to capture the current addressing environment of the executing program stack. In the instant invention, the stack buffer 50 can be directly addressed within limits, as if it were actually an area of main memory 30. The direct addressing of the stack buffer 50 action is transparent to the programmer. Therefore, knowledge of this action is not necessary for the programmer.
As shown in FIG. 7, the main memory address of the top-of-stack buffer 50 or newest entry is contained in the stack top register(s) 63. The main memory address at the bottom of the stack buffer 50 is contained in the stack limit register (SLR) or in some cases, in the stack address register (SAR). After the central processor module 20 is assigned to a job stack, the top four words of the stack memory area are transferred from main memory 30 to the stack buffer 50. Subsequent stack expansions and local data references are executed entirely within this buffer 50. When the stack buffer becomes full, a four word segment is transferred to main memory 30 thus taking full advantage of the phased memory system. Stack cutbacks, resulting in the stack becoming empty cause the next four word segment of the main memory stack to be brought into the stack buffer 50 and the address registers up-dated accordingly. The stack buffer 50 can be thought of as a "window" of stack entries which slide along the main memory stack as the job stack changes in size, so that it always includes some portion of the top area of the stack. This type of buffer structure is especially effective in a procedure or subroutine organized environment. In order to reduce conflicts and prevent possible destruction of valid shared data in main memory 30, only those variables which have been pushed into the stack buffer 50 from the top of stack registers (A & B) are sent to main memory 30. This would occur during a purge or a buffer segment move. The job of keeping track of this boundary of new data is accomplished by holding the absolute address of the variable that has not yet been sent to main memory 30 in the stack link register (SLR). As the stack buffer 50 slides along the main memory stack, it tends to hold variables that have not yet been placed into memory 30, new data and entries that are copies of the main memory stack. Because of this action, the stack address register (SAR) is utilized whenever the buffer
50 contains both new and copied data. The stack address register (SAR) always includes the absolute address of the deepest stack entry in the buffer 50. In order to transfer entries between the stack buffer 50 and main memory 30, stack buffer addresses corresponding to the main memory addresses in the S register 63 and the stack address register (SAR) must be maintained. The IC memory locations used for this purpose are the BTP and TPP registers, shown in FIG. 7, which store the stack buffer addresses of the oldest and newest entries, respectively. Because the stack buffer uses a wrap-around addressing scheme, the BTP and TPP registers serve mainly as pointers for absolute value is unimportant. The TPP, BTP, S, SAR and SLR registers are used to align the stack buffer "window" along the main memory stack as shown in FIG. 7. FIG. 7 illustrates a situation where the central processor 20 has just changed to another stack to resume execution. The filling of the stack buffer 50 has just begun with the transfer of the top four word block from the main memory stack. Execution is continuing as indicated by the new entries formed in the stack buffer 50. Additional area for stack expansion must be created when the stack buffer 50 is full. When this situation arises, the stack address register (SAR) is incremented by four and the stack link register (SLR) now represents the lead address of the variable which must be moved to main memory 30. At the completion of the operation, the stack link register (SRL) is equal to the stack address register (SAR).
It is sometimes necessary to automatically purge the stack buffer 50. When purging, all variables within the buffer 50 and above the SLR setting are transferred to main memory 30. With the appropriate instruction, the purging of the stack buffer 50 occurs before the actual lock reference to main memory 30. This insures that the contents of the stack buffer 50 are copied into main memory and therefore available to another processor. A purge operation concludes with the SLR set equal to the contents of the S register 63 incremented by one, which indicates that the entire contents of the local buffer are copies of main memory.
The associative memory 52 is a general data buffer implemented to provide fast access to frequently used variables and descriptors which are outside the area contained in the stack buffer 50. In the preferred embodiment, the associative buffer or memory 52 is a processor IC memory comprising sixteen words of 78 bits. Each word is composed of 51 bits of data and tag, a parity bit, 20 bits of main memory address, two bits of residue on the address, and four spare bits. The associative memory
52, see FIG. 8, is loaded with any item referenced by an IRW (indirect reference word) unless the item is a double precision operand or another IRW. Such entries include data descriptors, step index words, and single precision operands. The data descriptors retained may include dope vector entries such as those used in multi-dimensional and segmented array implementation. When such items, requested by either the program control unit 56 or the execution unit 62 are brought into the communication unit 68, they are copied along with their main memory address into the associative memory 52. A future reference to the item may find it still resident in the associative memory 52, and thus can eliminate a reference to main memory 30. After the associative memory 52 is full, the oldest resident entry is overwritten each time a new item is brought into the associative memory 52. When an item has been overwritten it is reentered into the associative memory 52 on the next reference to the item, so that frequently used items tend to be available in the current contents of the associative memory 52.
When information is to be stored in a main memory address currently available in the associative memory 52, the data in that associative memory location are up-dated along with the data in the main memory location. Therefore, valid entries in the associative memory 52 are current copies of the associated items in main memory 30. Any store operation performed by the storage control unit 66 is executed to main memory 30 as well as to local areas if applicable. Since stores always up-date the contents of main memory 30, the contents of the associative memory 52 never need to be overidden into main memory 30. After successful completion of the local memory store, the execution unit 62 may continue to execute operators in its queue, even though the store to main memory 30 is not complete. This is possible because conflicts such as protected writes and accidental procedure entries will not have been detected on the store to local memory. The hardware can invalidate all information in the associative buffer 52 when necessary, such as when entering the multi-level operating system for reallocation. A record is maintained of the validity of each word in the associative buffer 52. When information is requested from main memory 30, a check is made under control of the storage control unit 66 to determine if the requested information is currently contained in either the stack buffer 50 or the associative memory 52. This action of local detection occurs as an operator and address are removed from the storage unit input queue 70. In the event that a reference is found in both the associative memory 52 and the stack buffer 50, the stack buffer 50 is given preference since it conceivably could be a latter copy of that reference which was created by a series of functions causing push-down operations.
COMMUNICATIONS UNIT
The communications unit (CU) 68 provides the interface between the central processor module 20 and main memory 30. All main memory accesses are performed by this unit. Requests for memory operations are made to the CU 68 by the program buffer
48, the storage unit 66, and the stack buffer 50. Information fetched by the CU 68 from main memory 30 is forwarded to the execution units 62, the stack buffer 50, the associative memory 52, or, for program code, to the program buffer 48.
Access to the CU 68 is granted to the requesting CPM units on a priority basis. First priority is given to the stack buffer 50, because the execution unit 62 is waiting for the results of any request made by the stack buffer 50. The stack buffer requests are made when performing a stack-buffer fill, empty, or purge operation. The storage unit 66 has second priority as the execution units 62 may be waiting for the results of a storage unit request. The program buffer requests have third priority as these requests are made in anticipation of the actual need for additional program code.
The major logic elements of the communications unit as shown in FIG. 9, include input (IN) and output (OP) registers 302, 304 respectively, the communications address (CA) register 306, the communications length (CLN) registers 308, the remember-suspend (RS) register 310, the fail (FL) registers 70 and the control logic. The fail register 70 while assessible to the communication unit 68 is used by the fault control logic 58 of the CPM 20 and will be described later.
On single-word memory operations, the absolute memory address of the operation is contained in the CA register 306. For multi-word operations, the starting address is in the CA register 306 and the number of words to be fetched or stored is in the CLN register 308. During the operation, both the address and the word count are adjusted for each word fetched or stored. In the preferred embodiment, program code is fetched in eight-word blocks, which requires two four-word fetches (if the memory configuration allows four-word phasing). If, at the end of the first four-word fetch of program code, a higher priority request has been made for CU use, the current memory address and word length are transferred to the remember-suspend register 310 for temporary storage. Then the second four-word fetch is delayed until after the higher-priority request has been serviced. When no other requests are pending, the RS register 310 contents are loaded back into the CA register 306 and CLN register 308 and the fetching of code is resumed.
When access to main memory 30 is required, the CU control logic compares the six most significant bits of the address in the CA register 306 with the limits established for each memory control module (which will be described later) and selects the appropriate module. Then, the starting address and other control information for the operation are sent to the selected module in a memory control word. The control word is assembled in the input register 302, then transferred to the output register 304 and is sent to the addressed memory control module. The receipt of the control word is acknowledged by the memory control module.
For fetch operations, the memory control module notifies the CU 68 that access has been granted by sending a data-present (DAP) signal and the requested data to the CU 68. The data is received by the IN register 302 and is subsequently forwarded to the program buffer 48, the stack buffer 50, the associative memory 52, or the EWR, as appropriate.
Data for store operation is received by the CU 68 from either the storage unit data queue or the stack buffer 50. Data for store operations is buffered in the IN register 302 until the CU 68 gains memory access. Following the transfer of the control word and the acknowledgment of the receipt of this word, the selected memory control module informs the CU 68 of access by sending a send-data signal to the CU 68. On obtaining access the CU 68 transfers the data into the output register 304 and the word is then sent to the selected memory control module.
To further aid in understanding the physical and conceptual design of the central processor module 20, some of the basic operational concepts of the central processor module 20 are presented.
In the preferred embodiment, the central processor module 20 is designed as a pipeline processing unit. Therefore, each processing station may be operating simultaneously on a different task. As any instruction is passed through the processing pipeline, successive operations are performed by the various processing stations until the instruction is fully executed.
In general, the program operators in the program code string are fetched from memory 30 in multi-word segments and placed in the program buffer 48. The operators are extracted one at a time by the program control unit 56 and each is separated into one or more micro-operators, which are queued for processing by the execution unit 62. The program control unit 56 determines what data will be required for execution of the micro-operator and requests this data for the storage unit 66. For literal values, which are contained in the code string, the program control unit 56 extracts the data and forwards it directly to the execution unit 62. Therefore, as the execution unit 62 processes the micro-operators, the required data is usually instantly available, allowing the execution unit 62 to perform the required processing without delay. Results derived by the execution unit 62 may either be stored in one of the local memory areas or may be sent through the storage unit 66 and the communications unit 68 to main memory 30. By using this pipeline technique, relatively low speed processing is achieved without compromising equipment reliability.
To further increase processing speed, extensive use has been made of buffer memory areas contained within the processor 20. These local memory areas, which have already been described, are used to store program code, a portion of the active program stack, and frequently referenced variables.
In the preferred embodiment, the utilization in the central processor module 20 of special high-speed integrated circuit (IC) memories for the program buffer 48, the stack buffer 50, and the associative buffer 52, reduces and at times virtually eliminates the time spent waiting for the completion of transfers of data to and from main memory 30. Because these buffers are filled autonomously (two or four words at a time, depending upon configuration of the main memory 30, on the principle of anticipation rather than that of need followed by demand), the replenishment of their contents takes full advantage of normal main memory idle time. Program buffer 48 provides local storage for up to thirty-two 60-bit program words and permits tight loop capture of program loops of 32 words or less. A loop once in the buffer may be extracted repeatedly without further fetching of program words from main memory 30. The 32 word stack buffer 50 provides local storage for (and hence quick access too) descriptors, variables, and control words at the top of the stack of a job that is being executed. The associative data buffer 52, which is composed of 16 78-bit words, provides local high speed storage for the operands of a job that are most often used but that are not close enough to the top of the stack to be placed in the stack buffer 50.
The stack structure of the system of the instant invention is not merely a software fabrication imposed upon congenial hardware. Rather, the hardware mechanism for structuring and manipulating the stack is intrinsic to the central processor module 20. This hardware stack mechanism makes possible the control of subordinate routines, communications between processes, and the servicing of interrupts to be treated in a uniform and efficient way.
Memory protection (preventing a program's gaining access to or altering data not assigned to it) is achieved by a combination of hardware and software mechanisms. The hardware mechanisms include automatic detection of a program's attempt to index beyond an assigned data area and the use of control bits which are set by software and which prevent the user's program from changing program words, data descriptors, segment descriptors, memory links, indirect reference words (IRW), control words, and tables of the software operating system.
The operators of the central processor module 20 act upon vectors, entire words, characters, groups of bits, and single bits. The same set of operators is used in performing both single-precision and double-precision arithmetic.
Interrupt conditions detected by the central processor module 20, and input/output module 10, or by a control module of a memory module 30a are processed by the central processor module 20, which prepares the stack for entry into the interrupt-handling procedure of the multi-level operating system, places the needed parameters in the stack, and causes entry into the interrupt-handling procedure of the operating system. Thus, by automatically discontinuing (either temporarily or permanently, depending upon the interrupt condition) the process being executed at the time the interrupt condition occurs, the system is able to deal with nearly every condition (both normal and abnormal) that may arise in a multiprogramming, multiprocessing environment.
In a preferred embodiment, the central processor module 20 operates in either of two states, namely, the control state which is used only by the multi-level operating system, or the normal state, which is used by both user programs and the multi-level operating system. The interrupt-handling procedure of the multi-level operating system is always executed in the control state. The differences between the two states are that in the control state the processing of interrupt conditions arising outside the central processor module 20 (external interrupts) is inhibited whereas in the normal state, it is not so inhibited and that in the control state the central processor 20 may execute privileged instructions that may not be executed in the normal state by the central processor 20.
In addition to the two states, the central processor module 20 can operate in any one of five interrupt modes, namely, the normal mode (CMO), the control mode 1 (CM1), control mode 2 (CM2), control mode (CM3), and control mode 4 (CM4).
Utilization of residual checking in all arithmetic operations and of parity checking in data transfers greatly facilitates the detection of errors within the central processor 20. If a failure occurs with the central processor module 20, a processor internal interrupt is produced and the cause of failure is denoted by the contents of a fail register 70 of the processor module 20.
The fail register (FR) 70, see FIG. 10, is physically located in the communications unit 68 of the central processor module 20 and is used to provide additional information concerning processor internal and memory related error conditions.
The fail register (FR) 70 may be considered as comprised of three parts: a part concerning errors which are internal to the central processor module 20, a part concerning errors which are memory-related, and a single bit indicating continuability after alarm interrupts. Each of these parts is independently set by the fault control logic 58 of the central processor module 20: the three parts are read and cleared (read destructive) as one. If more than one interrupt affecting one of the three parts of the register 70 occurs before the register is read and cleared, the part is completely overwritten with the information about the most recent interrupt. In a system which includes more than one control processor module 20, any or all of the central processor modules 20 may operate in control state or normal state, as well as in any of the interrupt modes.
The individual sections of the CPM Fail register 70 are used as follows: the processor internal error section is used for all processor internal errors (processor internal memory related errors use the memory related section as well). The memory related section is also used for memory parity, Memory Fail 1, and invalid access errors, but only when parameter P2 is not used, in which case P2 will be all zeros. The memory related section is also used for all Memory Fail 2 interrupts. The continuability bit is only applicable to Alarm interrupts. The Memory Fail 1 and 2 interrupts will be discussed in detail later.
In addition to the above interrupt conditions, the memory portion of the fail register 70 also reports an interrupt recovery routine by a control module portion of a memory module 30a which will be described later. When an interrupt condition is detected, a bit assigned to designate that condition is set in the 27 bit fail register 70. However, the indication of the error is queued with the operand, and the central processor module 20 is not interrupted until after the affected operation is completed by the execution unit 44.
Errors which are internal to a central processor module 20 are described by the setting of the CPM Fail Register 70. Error conditions reported include: parity, residue, continuity, and decoding errors in the execution unit; and queue overwrite, residue error in the address unit; internal error in the program unit, and memory error on protected store.
The processor internal portion of the fail register 70 reports parity, residue, continuity and decoding errors. The memory related portion of fail register 70 reports a number of different types of interrupt conditions. An interface error detected during an operation between the communication unit 68 and the other sections of the central processor 20 are reported to the fail register 70 as well as a parity error detected during an access to main memory 30. Also reported by the fail register 70 is the interrupt condition which exists when an address does not exist in main memory 30 and when a memory time out occurred in the central processor 20.
The central processor module 20 operates in normal mode (CMO) until an interrupt condition is detected. The first three control modes (CM1, CM2, CM3) allow for recursive attempts to enter the hardware interrupt routine (the fault control logic
58 of the central processor module 20). Control mode 4 (CM4) indicates that these attempts were not successful. There is no direct connection between the states of operation and the modes of operation of the CPM 20. The CPM 20 may be in any of the four interrupt modes while either in control state or in normal state.
INPUT/OUTPUT SUBSYSTEM
Turning now to the input/output subsystem of the instant invention. The primary function of the input/output subsystem is to control and buffer the transfer of fixed-length data fields between main memory 30 (level-1) and the storage media of peripheral devices (level-3) of the information processing system. The peripheral devices are the media through which the system user communicates with the system. In the system of the instant invention, the peripheral devices operate independently of the central processor module 20 but always under control of the multi-level operating system through the input/output subsystem. The input/output subsystem includes one or more input/output modules 10, which is referred to as the IOM, and one or more peripheral control cabinets 39, see FIGS. 2 and 11. The input/output subsystem as an entity is interfaced directly with the level-1 and the level-3 storage systems and indirectly, by way of the level-1 subsystem with the central processor module 20. Within limitations, the number of input/output modules 10 and the number of peripheral control cabinets 39 within an input/output subsystem is dependent upon the user's requirements. The limitations are (a) that the combined total number of central processor modules 20 and input/output modules 10 in a system may not exceed eight and (b) a maximum of 28 peripheral controllers 38 may be connected to a single input/output module 10.
In the preferred embodiment the modularity concept applied to the design of the input/output module 10 provides an efficient, economic match to the user's system requirement. The modularity concept primarily concerns interface capability, and in particular, the peripheral interface capability provided by the data service subsections. These subsections are asynchronous and provide distinct peripheral connectivity capabilities. This uniqueness, derived from the asynchronous nature of the modular subsections, is a fail-soft advantage. Data-service failures are limited to a specific interface area, and thus allow the remaining interface capabilities to continue in service. The modularity concept has also permitted the use of additional data buffering within selected subsections on a device-speed basis. This use of buffering enables the faster peripheral devices of the system to communicate with main memory 30 in a faster multiple-word-mode using the phased memory transfer capability of the system. This efficient match of device rate to memory produces a higher input/output module 10 transfer rate.
Modularity in the input/output module 10 is achieved by use of the adapters, see FIG. 12. The respective adapters are defined below. The PC adapter A (PC/ADP-A) provides 10 peripheral controller (PC) channel capability to the first PCC 39, and ready line capability for three exchanges. The PC adapter B (PC-ADP-B) provides 10 peripheral controller channel capability to the second PCC 39 and ready line capability for four exchanges. The disc file controller adapter A (DFC/ADP-A) provides four disc-file-controller (DFC) channel capability to the first PCC 39 dedicated to disc controllers only. The disc file controller adapter B (DFC-ADP-B) provides four disc-file-controller channel capability to the second PCC 39 dedicated to disc controllers only. The scan bus adapter (SC/ADP) provides scan-bus capability to the input/output module 10 for driving the data communications processor (DCP) 36 and the disc file optimizer (DFO) 40. The disc-file-optimizer adapter (DFO/ADP) provides two disc file optimizer (DFO) channel capability. The datacomm processor adapter A (DCP/ADP-S) provides one data communications processor (DCP) channel capability for the first data communication processor 36. The datacomm processor adaptor B (DCP/ADP-B) provides one DCP capability per adapter (three used for the DCP's 2, 3, and 4). The memory bus adapter (MB/ADP) provides the input/output module capability for operating with a second group of eight memories. The switch interlock adapter A (SWI/ADP-A) provides capability for operation with two memory modules 30a. (Two used for the first four memory modules 30a). The switch interlock adapter B (SWI/ADP-B) provides capability for operation with two memory modules 30a. (Used for all additional memory modules
30a).
The modularity provided in the design of input/output module 10 of the instant invention allows the input/output subsystem to include a variety of IOM/PCC combinations, and therefore allows interface with the peripheral devices in a multitude of configurations. An example of the possible types of interface connections between the input/output subsystems of the instant invention and peripheral devices is shown in FIG. 10. As illustrated, the input/output subsystem may be connected with the peripheral devices through owned and/or shared exchanges, and/or directly with the peripheral devices.
Characteristically, the input/output module 10 is designed to provide the system user with maximum throughput and flexibility while requiring a minimum of central processor overhead. The input/output module 10 is characterized by its ability to operate asynchronously with the central processor 20 in the initiation, servicing, and termination of the device transfers. The base for this asynchronous mode is the request "map" concept. In essence, the input/output module 10 is queue driven from a map of I/O requests that reside in main memory 30. In requesting an input/output operation, the central processor module 20 alters the map in main memory 30 only to the extent of its interest to enter a request. The input/output module 10 later "trails" the same central processor path in recognizing and initiating the input/output request. Since main memory 30 (where the map resides) is a shared resource in the preferred embodiment, the central processor 20 and the input/output modules 10 may asynchronously access and process the map. Once the input/output module 10 is initiated, the central processor module 20 continues to process, queues new requests, processes, etc., such that the input/output module transfer times to and from devices are asynchronous and do not involve central processor cycles. To efficiently accomplish this task, the input/output module 10 of the instant invention includes a special purpose, hardwired multi-processor that services the map. In addition to this basic overlap advantage, the input/output module 10 further increases system throughput by a variety of techniques. For example, by reducing system processor overhead by handling real time interactive loops (for example, the DFO 40) directly without system intervention, or reducing system processor overhead by handling device termination cycles can increase throughput. Or partitioning the servicing of the data transfers into the input/output module 10 subsections designed to specifically handle the four principle classes of data throughput, which are the batch (line-printer, card reader, etc.), high speed (disc files), data communication (data communication processors 36), and real time interactive (disc file optimizers 40) can increase system throughput. Each subsection is completely independent and operates asynchronously with other subsections. They are unique and are buffered to match their device class thereby allowing an input/output module 10 to efficiently run to the throughput capability of a memory port of the memory subsystem. Increased througput is also achieved by allowing the input/output module 10 to select a transfer path for a device as the path becomes available (referred to as deferred binding).
As shown in FIG. 13, maximum throughput can be realized only if the binding of a data path between an input/output module 10 and a device is delayed until the device is ready to initiate the job. For instance, if device D2 is to be initiated, the path required to connect a process with D2 involves selecting between two input/output subsystems (I/O subsystem 1 and 2) and between channels (A and B or C and D) within each input/output subsystem. If the path is pre-selected programmatically, the situation can develop in which the device is free but the pre-selected path is not. Thus, execution of a request would be unnecessarily delayed if an alternate path did not in fact exist.
Delay-binding the path programatically generally requires that the central processor module 20, which initiated the job, be involved in the operation until the actual device initiated is accomplished. Since this reduces the parallelism of both central processing and the input/output subsystems, it is more efficient to have the input/output modules 10 manage the path selection. The total system-processor time required to accomplish an I/O operation is thus limited to the amount of time required for a central processor module 20 to construct and queue an input/output request in the level-1 memory. Once queued, I/O requests will be serviced by an input/output module 10 independent of any central processor module 20 involvement, as soon as a path to the selected device becomes available.
To enable central processor modules 20 to queue I/O requests and the input/output modules 10 to select paths and service requests, a list of unit table (UT) words (which describe the channels to be used for I/O requests) and a table of the I/O control block (IOCB) base address pointers (Queue-Header and Queue Trail Tables) must be loaded into the level-1 memory at initialized (cold start) time. These tables allow each input/output module 10 to be aware of the devices it can service and the order or priority of exchange devices, and is the mechanism used by the central processor modules 20 to queue requests. When a request is processed (or the start I/O process) requires that a transfer of data be made by an input/output module 10, the central processor module 20 is required to perform the following operations: (a) construct either single or multiple requests which explicitly define the operation(s) required to complete the job; (b) store the request in level-1 memory, and (c) inform the input/output modules capable of servicing the job requests of the level-1 locations at which the requests are stored.
The requests are then left in level-1 memory until an input/output module 10 is read to service them. All requests for I/O are made at what is termed the home address (HA) level. That is, each processor requesting to execute I/O must specify a unit designate (UD) number for use as an index into the unit table (UT). The unit table is then used with the UD number to queue the request for the requested device. Upon completion of each I/O request, the state of either the IOCB software attention bit or of a status queue header (SOH) interrupt bit determines whether the input/output modules notify the central processor 20 of the terminated status. Thus, once the request has been queued, system software will be free to perform other tasks while waiting for the completion of the I/O request(s).
In the preferred embodiment, the transfer rate of the input/output module 10 is dependent upon the modular configuration of the input/output module 10 and the system memory speeds. FIG. 14 indicates the composition of the transfer rate for an input/output module 10 with all the previously described modularity adapters included, using a phased 1.5 micro second cycle memory system. A diagram of an input/output subsystem map (IOSM) 312 required for the I/O subsystem configuration represented in FIG. 13 is shown in FIG. 15. As shown in FIG. 15, the IOSM 312 is comprised of a home address (HA) 314, a unit table (UT) 316, a QUEUE table which is defined by a head 318 and tail 320, (IOQH, IOQP), the status queue header (SQH) 322, and an input/output control block (IOCB) 324. The following paragraphs will be devoted to a description of these elements.
The HA 314 is a basic software-constructed word used for communications with an input/output module 10. The HA 314 includes basic I/O instruction fields which, when decoded, condition the IOM logic to initiate the IOM operations. The HA word is stored in a level-1 memory address location. The fields of the HA word are shown in FIG. 16, and defined in Table 1.
TABLE 1 __________________________________________________________________________ HOME ADDRESS FIELD DEFINITION Bit(s) Function __________________________________________________________________________ Parity (51) Provides odd parity for the word being transferred. Tag (50-48) Denotes word as being a single (000) precision word. Lock (47) When set, by software indicates the HA words are available for IOM use. Resets when IOM services HA words. Bits (46 thru 44) Not used. Controls (43 thru 40) Defines the Control Codes of the HA word. Bits (39 thru 36) Not used Unit Designate (UD) (35 A unique 8-bit code-used with the UT base address thru 28) to index and lock fetch from level-1 memory the UT word for the device to be started, and used with the QH base address to unlock fetch from level-1 memory the QH word, which points to the IOCB base address Channel Number (27 thru Identifies one of the 32 possible IOM channels. 23) Bits (22-20) Not used. Ha,SQ,UT, or QH (19 thru Used to establish a new base address or during a 0) cold-start operation to transfer to the IOM the following base addresses: All 4 registers are capable of being changed by an instruction after the system is initialized. a. HA --
20-bit basic address obtained through a cold-start operation. b. UT -- a 20-bit address indicating the base address of the UT. c. SQ -- a 20-bit address which points to a status queue header (SQH). The SQH consists of the head and tail address of the status queue. d. QH -- a 20-bit address indicating the base address of the IO Queue Table and is added to 256 to point to the IO Queue Tail. __________________________________________________________________________
A UT word is required for each peripheral device (maximum of 255 devices) in the I/O subsystem. Each UT word is the main element used by the IOM 10 to serve as I/O requests. Each UT word for an exchange includes pointers to the first unit designate (FUD) and the next unit designate (NUD) numbers and its associated channel-number-base-address listing for the device type used for the I/O request. The various fields in the UT shown in FIG. 17 and defined in Table 2.
The formats and definition of the input/output queue head (IOQH) and the input/output queue trail (IOQT) are given in FIGS. 18 and 19 and in Tables 3 and 4, respectively.
A status queue (SQ) is a queue comprised of terminated IOCB's which have been linked together by a IOM 10. When a request is terminated, the IOM 10 that executed the IOCB inserts the termination status into the fifth word field of the IOCB. The IOCB is then unlinked from the unit queue and linked to the SQ. If the software attention bit in the input/output control word (IOCW) is set (set by software) or if the interrupt bit in the SQH is set at the same time that the IOCB is being linked to the SQ, a channel interrupt signal is sent by the IOM 10 to the central processor 20. When a non-channel-related error is detected, the IOM 10 sends an IOM error interrupt signal to the central processor 20 and not the channel interrupt.
TABLE 2 __________________________________________________________________________ UNIT TABLE WORD DEFINITION Bit(s) Function __________________________________________________________________________ Parity (51) Provides odd parity for the word being transferred. Tag (50 thru 48) Denotes word as being a single (000) precision word. Lock (LK) (47) When set, indicates the UT word is being operated on. Magnetic Tape (MGT) (46) When set, indicates this job request is for a magnetic tape. (set by software.) Disk Pack (DSPK) (45) When set, indicates this job request is for a disk pack. (Set by software.) Bits (44 thru 40) Not used. Disk File Optimizer (DFO) When set, indicates unit is under control of a (39) DFO. A ring walk will not be performed with this bit set. (Set by software.) Exchange (EX) (38) When set, indicates the unit is connected to an exchange. A ring walk will be performed (if the job bit is set) with this bit set. (Set by software.) Not used if bit 39
is set. Job (JB) (37) When set, indicates that all channels associated with this request were busy, and when a channel becomes free and no further request are queued for that device, this job is to be done. (Set by IOM.) Used only with exch. devices (Bit 38=1) Not used with DFO (Bit 39.) Busy (BZ) (36) When set, indicates that this unit is busy. (Set by IOM.) *First Unit Designate Points to the First Unit Designate Number (FUD) (35 thru 28) connected to the exchange. Channel Number Base For units not on an exchange, the number of the Address (27 thru 23) channel to which this unit is connected. For units on an exchange, the lowest numbered channel to which the exchange is connected. *Last Channel on Exchange Indicates the 2
least significant bits of the (LCEX) (22 and 21) last channel number of the exchange, for the device to be used. Bits 20 thru 17 Not used. Last (LST) (16) When set, indicates this is the last Unit Designate on the exchange. *Next Unit Designate Points to the Next Unit Designate number (NUD) (15 thru 8) connected to the exchange. Channel Used (7 thru 3) These bits specify the channel that was used to service the device. (Set by IOM.) Bits (2 thru 0) Not used. __________________________________________________________________________ *These apply only to exchange devices.
TABLE 3 ______________________________________ QUEUE HEAD (IOQH) Bit(s) Function ______________________________________ Parity (51) Provides odd parity for the word being transferred. Tags (50-48) Denotes word as being a single precision word. (000) (47-20) For Software use only.) (19-0) Address of 1st IOCB. (If 19-0) are zero dur- ing a start I/O operation, an Illegal condition exists and a fail word is sent to the status Queue. ______________________________________
TABLE 4 ______________________________________ QUEUE TAIL (IOQT) Bit(s) Function ______________________________________ Parity (51) Provides odd parity for the word being transferred. Tags (50-48) Denotes word being a single precision word. (000) (47-20) For software use only. (19-0) Address of last IOCB. ______________________________________
A status queue header (SQH), see FIG. 20, is assigned to each IOM 10 that is addressed by an SQ register 326 of the IOM 10. The SQH serves as the monitor of the SQ and is used by the IOM 10 to build and access the queue. When a request terminates, the SQH is locked-fetched and tested for a null condition (bit 41 reset). If a null condition is detected, the address of the terminated IOCB is stored in both the head and tail fields of the SQH and the null bit is set. If the null bit is detected set, then the address of the terminated IOCB is inserted into the next link (NL) field of the last terminated IOCB and is also inserted into the trail address field of the SQH. The various fields of the SQH word are defined in Table 5.
In the preferred embodiment an IOCB as shown in FIG. 21, is a block of six (or more) 51-bit words. These words are used to initiate requests for service (IOCW) and to relate requests for service, linking of requests, and requests termination statuses. When a request is terminated, the section of the input/output module 10 would perform the request inserts and insert a request termination bit into an active channel stack (ACS). The input/output module 10 that executed the IOCB then fetches the appropriate result descriptor information from the IOM 10, uses the result descriptor information to form a result descriptor (RD) word and stores the RD word in the sixth word field in the IOCB. The terminated IOCB is then linked to the status queue (SQ). To complete the termination, the queue head (QH) and queue tail (QT) of the QH table are nulled (set to zero) if this were the last request from this unit, and the UT word for the device is stored unlocked. If there are more requests, the address of the next IOCB is inserted into the QH. The control is then passed to the I/O start logic to initiate the next request. The various fields of the IOCB are defined in Table 6. Finally, the IOCW which is illustrated in FIG. 22, is the fourth word in the IOCB. The input/output control word (IOCW) includes the standard control field (SCF) which includes information useful to the data service sections (such as a memory protect bit, a memory inhibit bit, and a software tension bit of the IOM
10). The various fields of the IOCW are defined in Table 7.
TABLE 5 __________________________________________________________________________ STATUS QUEUE HEADER Bit(s) Function __________________________________________________________________________ Parity (51) Provides odd parity for the word being transferred. Tag (50 thru 48) Denotes word as being a single (000) precision word. Lock (LK) (47) When set, indicates the SQH word is being operated on. Bit (46) Not used. Change (45) Notifies softward, when set, that a status change vector has occurred. CPM Number (44 thru 42) Points to the CPM that will be interrupted by either channel interrupt or error interrupt. Null (41) When a 0, indicates that the queue is empty; when a 1, indicates terminated jobs are under queue. Interrupt (40) When set, (set by software) indicates that the CPM number field shall be interrupted upon job termination. (Reset by IOM) Head (39 thru 20) A 20-bit address pointing to the IOCB of the first device terminated. (Not used if bit 41 =
0) Tail (19 thru 0) A 20-bit address pointing to the IOCB of the last device terminated. (Not used if bit 41 = 0) __________________________________________________________________________
Turning now to a general functional description of the input/output module 10, the input/output module and associated peripheral control cabinets 39 are employed to control the transfer data between the level-1 storage media and all peripheral units, independent of central processors 20. The input/output modules 10 receive instructions from the central processors 20, and in conjunction with the associated peripheral controllers 38, execute these instructions. At the completion of a data transfer, the input/output module 10 generates terminate instructions and stores terminate information in a designated stack area located in the input/output module 10. In the preferred embodiment, each input/output module 10 is capable of processing up to 28 simultaneous input/output (I/O) operations from up to 28 peripheral controls (PC's) 38, and can accommodate a combined maximum of 255 peripheral device, four (4) data communications processors 36, and four disc file optimizers (DFO's) 40. Physically each input/output module 10 can be considered as divided into the following six functional areas, see FIG. 23; (1) the translator 72; (2) the memory interface unit (MIU) 74; (3) the scan interface (SCI) 76; (4) the data communications processor memory interface (DCI) 78; (5) the peripheral control interface (PCI) 80; and the disc file interface (DFI) 82.
TABLE 6 __________________________________________________________________________ IOCB Word Field Function __________________________________________________________________________ IOLINKAGE (NL) Level-1 address of the next IOCB queued for this device (bits 0-19). SIDELINK Link to another job in this side chain; may or may not be for the same unit. Contains: a. Tag-unused b. Unit Designate for which that next IOCB is to be queued (bits 40 thru 47) c. Address of next IOCB in side chain (bits 20 thru 39) d. Bits 8 thru 19 -- unused e. IOM mask (bits 0 thru 7) -- identifies which IOM's could perform the side-linked job Buffer Descriptor This is a data descriptor which points to the bufer, and contains: a. Area Base Address (bits 0 thru 19) -- this 20-bit address points to the level-1 location at which the buffer associated with this device can be found. b. Buffer Length (bits 20 thru 39) -- specifies the buffer length (in words) in main memory. IOCW This word field defines the I/O job for the PCI or DFI portion of the IOM. For a detailed description of the format and definition of the IOCW contents, refer to figure 9-7 and to table 9-7. CDL This word field will contain the Channel Designate -- level (CDL) information word which will be transferred to the channel selected for the operation. IORD Termination (normal or error) of the operation causes the IOM to transfer into this word field Result Descriptor (RD) information. __________________________________________________________________________ NOTE: Translator Adds (Area Base Address + Buff Length) for final address
TABLE 7 __________________________________________________________________________ IOCW Bit(s) Function __________________________________________________________________________ The various fields of the IOCW are defined as follows: Parity (51) Provides odd parity for the word being transferred. Tag (50 thru 48) Denotes word as being a single (000) precision word. ASCII (ASC) (47) When set, indicates that ASCII translation is required. Link (LK) (46) When set, indicates that a link to another IOCW is required. (The address of the new IOCW is stored in bits 0 thru 19). Software Attention (SA) When set, indicates that the IOM will interrupt (45) the CPM on the channel interrupt line at the time the IOCB is being linked into the status queue (SQ). Input/Output (I/O) (44) When set, indicates that the transfer is to be an input operation. When reset, indicates that the transfer is to be an output operation. Memory Inhibit (MINH) When set, indicates that data will not be (43) transferred to/from memory. Translate (TRA) (42) When set, indicates that internal IOM translation is needed. Frame Length (FML) (41) When set, indicates that the frame length is to be 8-bits. When reset, indicates that the frame length is to be 6-bits. Memory Protect (MP) (40) When set, indicates that the level-1 memory will not store into a location during a write operation and will send a fail signal when a memory word contains bit 48 = 1. Backward/Forward (B/F) When set, indicates a backward operation on a (39) tape unit. When reset, indicates a forward operation on a tape unit. Tag Control (TCTL) (37 Indicate the following: and 36) 37 36 0 0 Store single precision tags 1 1 Store double precision tags 0 1
Store program tags 1 0 Tag field transfer (35 thru 0) Not used. __________________________________________________________________________
The translator 72 is a special purpose processor capable of performing specific hardwired micro-sequences. It is the mechanism of the input/output module 10 that services I/O requests, generates the request descriptors required to initiate peripheral devices, and reports request termination and failure status conditions to the central processor 20. The operation of the translator is keyed to respond to certain declared flag conditions.
The memory interface unit (MIU) 74 performs all level-1 to level-3 data transfers between the input/output module 10 and a maximum of eight system level-1 memory controllers (MCM's). The MIU 74 detects level-1 memory error conditions, and reports them to the requesting functional unit of the input/output module 10 and to the translator 72 when applicable. The memory interface unit 74 manages level-1 memory access requests by the functional units of the input/output module 10 on a preassigned priority basis. First priority is given to data service requests while second priority is given to data communications processor interface requests. Third priority is given to translator requests.
The scan interface unit (SCI) 76, which includes the data communications processor memory interface (DCI) 78, includes the storage and controls required for providing scan bus 79 for communicating with four data communications processors (DCP's)
36 and four disc file optimizers (DFO's) 40. The scan bus 79 to the four DFO's 40 is shared between two input/output modules 10. The translator 72 initiates scan operations by transmitting a scan control word to the scan interface unit (SCI) 76. If a scan-out is required, the translator 72 is notified by completion of scan operations by the scan interface unit 86. If a scan-in is the operation completed, the translator 72 loads the scan-in information in the register denominated the B register in the translator 72. If an error is detected by the scan interface unit 76, the error information from the scan interface unit 76 is loaded into a register denominated the F register of the translator 72. The errors detected by the scan interface unit are Not Ready error, which occurs when a disc file optimizer 40 or a data communications processor 36 addressed by the scan bus 79 does not respond with a ready signal within 3 micro seconds, and a Module Error which occurs when a disc file optimizer 40
or a data communications processor 36 addressed by the scan but 79 detects an error on a scan-out or a scan-in operation.
The data communications processor memory interface (DCI) 78, which is part of the SCI 76, includes a storage capability and the controls required to interface with the memory busses 47 of four data communication processors (DCP's) 36. The memory transfer operations performed include: (a) Fetch (one word); (b) store with flashback (one word); and (c) protected store with flashback (one word). All errors detected by the DCI 78 or the memory interface unit 74 for a DCI memory request are translated to the data communications processor 36 that initiated the memory request.
The peripheral control interface (PCI) 80 enables the input/output module 10 to interface with from one to twenty peripheral controllers (PC's) 38 and coordinate data transfers between these controllers and the memory interface unit (MIU) 74 as directed by the translator 72. In the preferred embodiment, each peripheral controller (PC) 38 requires a one microsecond service cycle to transfer data. By means of overlapping service cycles and by use of local memory windows (a one-clock period during which a particular operatio