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United States Patent Application
20040027854
Kind Code
A1
Iwata, Yoshihisa ; et al.
February 12, 2004
Magnetic random access memory
Abstract
Setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write bit line sink signal on the basis of the setting data. The current waveform of the write word/bit line current is controlled for each chip or memory cell array.
Inventors:
Iwata; Yoshihisa
(Yokohama-shi, JP)
, Nakajima; Kentaro
(Tokyo, JP
)
Correspondence Name and Address:
1940 DUKE STREET
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
ALEXANDRIA
VA
22314
US
Series Code:
438015
Filed:
May 15, 2003
U.S. Current Class:
365/158
U.S. Class at Publication:
365/158
Intern'l Class:
G11C 011/14
Claims
What is claimed is:
1. A writing method of a magnetic random access memory, comprising: causing a first magnetic field parallel to a hard-axis to act on a magnetoresistive element having an easy-axis and the hard-axis; and causing a second magnetic field which is weaker than the first magnetic field and parallel to the hard-axis and a third magnetic field parallel to the easy-axis to simultaneously act on the magnetoresistive element.
2. A method according to claim 1, wherein the first and second magnetic fields continuously act on the magnetoresistive element.
3. A method according to claim 1, wherein a change from the first magnetic field to the second magnetic field is done to change an intensity of the magnetic field in an analog manner.
4. A method according to claim 1, wherein a change from the first magnetic field to the second magnetic field is done to change an intensity of the magnetic field in a digital manner.
5. A method according to claim 1, wherein the first and second magnetic fields are generated by a first write current which flows in a direction parallel to the easy-axis, and the third magnetic field is generated by a second write current which flows in a direction parallel to the hard-axis.
6. A method according to claim 5, wherein the first and second magnetic fields are obtained by temporally changing a current value of the first write current.
7. A method according to claim 1, wherein a direction of the third magnetic field is determined by a value of write data for the magnetoresistive element.
8. A writing method of a magnetic random access memory, comprising: causing a first magnetic field parallel to a hard-axis and a second magnetic field parallel to an easy-axis to simultaneously act on a magnetoresistive element having the easy-axis and hard-axis; and causing a third magnetic field which is stronger than the second magnetic field and parallel to the easy-axis to act on the magnetoresistive element.
9. A method according to claim 8, wherein the second and third magnetic fields continuously act on the magnetoresistive element.
10. A method according to claim 8, wherein a change from the second magnetic field to the third magnetic field is done to change an intensity of the magnetic field in an analog manner.
11. A method according to claim 8, wherein a change from the second magnetic field to the third magnetic field is done to change an intensity of the magnetic field in a digital manner.
12. A method according to claim 8, wherein the first magnetic field is generated by a first write current which flows in a direction parallel to the easy-axis, and the second and third magnetic fields are generated by a second write current which flows in a direction parallel to the hard-axis.
13. A method according to claim 12, wherein the second and third magnetic fields are obtained by temporally changing a current value of the second write current.
14. A method according to claim 8, wherein directions of the second and third magnetic fields are determined by a value of write data for the magnetoresistive element.
15. A writing method of a magnetic random access memory, comprising: causing a first magnetic field parallel to a hard-axis to act on a magnetoresistive element having an easy-axis and the hard-axis; causing a second magnetic field parallel to the hard-axis and a third magnetic field parallel to the easy-axis to simultaneously act on the magnetoresistive element; and causing a fourth magnetic field parallel to the easy-axis to act on the magnetoresistive element.
16. A method according to claim 15, wherein the first and second magnetic fields have the same intensity and continuously act on the magnetoresistive element.
17. A method according to claim 15, wherein the third and fourth magnetic fields have the same intensity and continuously act on the magnetoresistive element.
18. A method according to claim 15, wherein the second magnetic field is weaker than the first magnetic field, and the first and second magnetic fields continuously act on the magnetoresistive element.
19. A method according to claim 18, wherein a change from the first magnetic field to the second magnetic field is done to change an intensity of the magnetic field in an analog manner.
20. A method according to claim 18, wherein a change from the first magnetic field to the second magnetic field is done to change an intensity of the magnetic field in a digital manner.
21. A method according to claim 15, wherein the fourth magnetic field is stronger than the third magnetic field, and the third and fourth magnetic fields continuously act on the magnetoresistive element.
22. A method according to claim 21, wherein a change from the third magnetic field to the fourth magnetic field is done to change an intensity of the magnetic field in an analog manner.
23. A method according to claim 18, wherein a change from the third magnetic field to the fourth magnetic field is done to change an intensity of the magnetic field in a digital manner.
24. A method according to claim 15, wherein the first and second magnetic fields are generated by a first write current which flows in a direction parallel to the easy-axis, and the third and fourth magnetic fields are generated by a second write current which flows in a direction parallel to the hard-axis.
25. A method according to claim 15, wherein directions of the third and fourth magnetic fields are determined by a value of write data for the magnetoresistive element.
26. A writing method of a magnetic random access memory, comprising: causing a first magnetic field parallel to a hard-axis and a second magnetic field parallel to an easy-axis to simultaneously act on a magnetoresistive element having the easy-axis and hard-axis; causing a third magnetic field parallel to the hard-axis and a fourth magnetic field which is stronger than the second magnetic field and parallel to the easy-axis to simultaneously act on the magnetoresistive element; and causing a fifth magnetic field which is weaker than the third magnetic field and parallel to the hard-axis and a sixth magnetic field parallel to the easy-axis to simultaneously act on the magnetoresistive element.
27. A method according to claim 26, wherein the first and third magnetic fields have the same intensity.
28. A method according to claim 26, wherein the third magnetic field is weaker than the first magnetic field.
29. A method according to claim 28, wherein a change from the first magnetic field to the third magnetic field and a change from the third magnetic field to the fifth magnetic field are done to change an intensity of the magnetic field in an analog manner.
30. A method according to claim 28, wherein a change from the first magnetic field to the third magnetic field and a change from the third magnetic field to the fifth magnetic field are done to change an intensity of the magnetic field in a digital manner.
31. A method according to claim 26, wherein the first, third, and fifth magnetic fields continuously act on the magnetoresistive element.
32. A method according to claim 26, wherein the fourth and sixth magnetic fields have the same intensity.
33. A method according to claim 26, wherein the sixth magnetic field is stronger than the fourth magnetic field.
34. A method according to claim 33, wherein a change from the second magnetic field to the fourth magnetic field and a change from the fourth magnetic field to the sixth magnetic field are done to change an intensity of the magnetic field in an analog manner.
35. A method according to claim 33, wherein a change from the second magnetic field to the fourth magnetic field and a change from the fourth magnetic field to the sixth magnetic field are done to change an intensity of the magnetic field in a digital manner.
36. A method according to claim 26, wherein the second, fourth, and sixth magnetic fields continuously act on the magnetoresistive element.
37. A method according to claim 26, wherein the first, third, and fifth magnetic fields are generated by a first write current which flows in a direction parallel to the easy-axis, and the second, fourth, and sixth magnetic fields are generated by a second write current which flows in a direction parallel to the hard-axis.
38. A method according to claim 26, wherein directions of the, second, fourth, and sixth magnetic fields are determined by a value of write data for the magnetoresistive element.
39. A writing method of a magnetic random access memory, comprising: applying a first current to a first wiring running along a direction parallel to an easy magnetization axis; and simultaneously applying a second current being weaker than the first current to the first wiring and a third current to a second wiring along a direction parallel to a hard magnetization axis, wherein a magnetic tunnel junction cell is arranged between the first wiring and the second wiring.
40. A writing method of a magnetic random access memory, comprising: simultaneously applying a first current to a first wiring running along a direction parallel to an easy magnetization axis and a second current to a second wiring running along a direction parallel to a hard magnetization axis; and applying a third current being stronger than the second current to the second wiring, wherein a magnetic tunnel junction cell is arranged between the first wiring and the second wiring.
41. A writing method of a magnetic random access memory, comprising: applying a first current to a first wiring running along a direction parallel to an easy magnetization axis; simultaneously applying a second current to the first wiring and a third current to a second wiring along a direction parallel to a hard magnetization axis; and applying a fourth current to the second wiring, wherein a magnetic tunnel junction cell is arranged between the first wiring and the second wiring.
42. A writing method of a magnetic random access memory, comprising: simultaneously applying a first current to a first wiring running along a direction parallel to an easy magnetization axis and a second current to a second wiring running along a direction parallel to a hard magnetization axis; simultaneously applying a third current to the first wiring and a fourth current being stronger than the second current to the second wiring; and simultaneously applying a fifth current being weaker than the third current to the first wiring and a sixth current to the second wiring, wherein a magnetic tunnel junction cell is arranged between the first wiring and the second wiring.
43. A magnetic random access memory comprising: first and second write lines which cross each other; a magnetoresistive element arranged at an intersection between the first and second write lines; a first driver to supply a first write current to the first write line; a second driver to supply a second write current to the second write line; a setting circuit in which first setting data to control the first write current and second setting data to control the second write current are registered; and a current waveform control circuit which controls operation of the first driver depending on the first setting data and controls operation of the second driver depending on the second setting data.
44. A memory according to claim 43, further comprising a first sinker which absorbs the first write current, and a second sinker which absorbs the second write current, and wherein the current waveform control circuit controls operation of the first and second sinkers.
45. A memory according to claim 44, wherein the current waveform control circuit ends the operation of the first driver and then ends the operation of the first sinker.
46. A memory according to claim 44, wherein the current waveform control circuit ends the operation of the second driver and then ends the operation of the second sinker.
47. A memory according to claim 43, wherein the first setting data is data which determines a supply/cutoff timing of the first write current for the first write line.
48. A memory according to claim 47, wherein the current waveform control circuit has a plurality of delay circuits having different delay times, selects one of the plurality of delay circuits on the basis of the first setting data and causes the selected delay circuit to delay a write signal which instructs a start/end of write operation by a predetermined time, thereby determining the supply/cutoff timing of the first write current.
49. A memory according to claim 43, wherein the second setting data is data which determines a supply/cutoff timing of the second write current for the second write line.
50. A memory according to claim 49, wherein the current waveform control circuit has a plurality of delay circuits having different delay times, selects one of the plurality of delay circuits on the basis of the second setting data and causes the selected delay circuit to delay a write signal which instructs a start/end of write operation by a predetermined time, thereby determining the supply/cutoff timing of the second write current.
51. A memory according to claim 49, wherein a direction of the second write current changes depending on a value of write data, and the supply/cutoff timing of the second write current changes in accordance with the direction of the second write current.
52. A memory according to claim 49, wherein a direction of the second write current changes depending on a value of write data, and the supply/cutoff timing of the second write current is constant independently of the direction of the second write current.
53. A memory according to claim 43, wherein the first setting data is data which determines a current waveform of the first write current for the first write line.
54. A memory according to claim 53, wherein the first driver has a plurality of current sources, and the current waveform control circuit controls operations of the plurality of current sources on the basis of the first setting data to determine the current waveform of the first write current.
55. A memory according to claim 54, wherein the current waveform control circuit has a plurality of waveform generation circuits corresponding to the plurality of current sources, the plurality of waveform generation circuits outputting a plurality of pulse signals which control the operations of the plurality of current sources on the basis of the first setting data.
56. A memory according to claim 53, wherein the first driver has a plurality of current sources, the current waveform control circuit determines timings of operations of the plurality of current sources, and the first setting data determines presence/absence of the operations of the plurality of current sources.
57. A memory according to claim 56, wherein the current waveform control circuit has a plurality of waveform generation circuits corresponding to the plurality of current sources, the plurality of waveform generation circuits outputting a plurality of pulse signals which determine the timings of the operations of the plurality of current sources.
58. A memory according to claim 54 or 56, wherein the plurality of current sources have the same current supply capability.
59. A memory according to claim 54 or 56, wherein the plurality of current sources have different current supply capabilities.
60. A memory according to claim 43, wherein the second setting data is data which determines a current waveform of the second write current for the second write line.
61. A memory according to claim 60, wherein the second driver has a plurality of current sources, and the current waveform control circuit controls operations of the plurality of current sources on the basis of the second setting data to determine the current waveform of the second write current.
62. A memory according to claim 61, wherein the current waveform control circuit has a plurality of waveform generation circuits corresponding to the plurality of current sources, the plurality of waveform generation circuits outputting a plurality of pulse signals which control the operations of the plurality of current sources on the basis of the second setting data.
63. A memory according to claim 60, wherein the second driver has a plurality of current sources, the current waveform control circuit determines timings of operations of the plurality of current sources, and the second setting data determines presence/absence of the operations of the plurality of current sources.
64. A memory according to claim 63, wherein the current waveform control circuit has a plurality of waveform generation circuits corresponding to the plurality of current sources, the plurality of waveform generation circuits outputting a plurality of pulse signals which determine the timings of the operations of the plurality of current sources.
65. A memory according to claim 61 or 63, wherein the plurality of current sources have the same current supply capability.
66. A memory according to claim 61 or 63, wherein the plurality of current sources have different current supply capabilities.
67. A memory according to claim 60, wherein a direction of the second write current changes in accordance with a value of write data, and a current waveform of the second write current changes in accordance with the direction of the second write current.
68. A memory according to claim 60, wherein a direction of the second write current changes in accordance with a value of write data, and a current waveform of the second write current is kept unchanged independently of the direction of the second write current.
69. A memory according to claim 43, wherein the setting circuit has an output circuit which outputs the first and second setting data in normal operation and a transfer circuit which transfers, in place of the first and second setting data, first and second test data which control the first and second write currents in test operation.
70. A memory according to claim 43, wherein the setting circuit has a storage element to semipermanently store the first and second setting data.
71. A memory according to claim 70, wherein the storage element is a laser blow fuse.
72. A memory according to claim 70, wherein the storage element is a magnetoresistive element.
73. A memory according to claim 70, wherein the storage element is an antifuse which stores data on the basis of presence/absence of breakdown of a tunneling barrier of a magnetoresistive element.
74. A memory according to claim 73, further comprising a circuit which electrically programs the first and second setting data in the antifuse.
75. A memory according to claim 43, wherein the magnetoresistive element has an easy-axis and a hard-axis, the easy-axis being parallel to a direction in which the first write line runs, and the hard-axis being parallel to a direction in which the second write line runs.
76. A memory according to claim 43, wherein the first write line is a write word line, and the second write line is a write bit line.
77. A memory according to claim 43, wherein the magnetoresistive element is a tunnel magnetoresistive element having two ferromagnetic layers and a tunneling barrier layer inserted between the two ferromagnetic layers.
78. A magnetic random access memory comprising: a plurality of first write lines; a plurality of second write lines which cross the plurality of first write lines; a plurality of magnetoresistive elements arranged at intersections between the plurality of first write lines and the plurality of second write lines; a plurality of first drivers corresponding to the plurality of first write lines; a plurality of second drivers corresponding to the plurality of second write lines; a setting circuit in which first setting data to control a first write current flowing to the plurality of first write lines and second setting data to control a second write current flowing to the plurality of second write lines are registered; and a current waveform control circuit which controls operations of the plurality of first drivers depending on the first setting data and controls operations of the plurality of second drivers depending on the second setting data.
79. A memory according to claim 78, wherein the first setting data is data which controls a supply/cutoff timing or current waveform of the first write current for all the plurality of first write lines, and the second setting data is data which controls a supply/cutoff timing or current waveform of the second write current for all the plurality of second write lines.
80. A memory according to claim 78, wherein the first setting data is data which controls a supply/cutoff timing or current waveform of the first write current individually for each of the plurality of first write lines, and the second setting data is data which controls a supply/cutoff timing or current waveform of the second write current individually for each of the plurality of second write lines.
81. A memory according to claim 78, wherein a direction of the second write current changes in accordance with a value of write data, and a supply/cutoff timing or current waveform of the second write current changes in accordance with the direction of the second write current.
82. A memory according to claim 78, wherein a direction of the second write current changes in accordance with a value of write data, and a supply/cutoff timing or current waveform of the second write current is constant independently of the direction of the second write current.
83. A memory according to claim 78, wherein when the plurality of first write lines, the plurality of second write lines, the plurality of magnetoresistive elements, the plurality of first drivers, and the plurality of second drivers construct one cell array block, a plurality of cell array blocks are stacked on a semiconductor substrate, and the setting circuit and current waveform control circuit are shared by the plurality of cell array blocks.
84. A memory according to claim 78, wherein when the plurality of first write lines, the plurality of second write lines, the plurality of magnetoresistive elements, the plurality of first drivers, the plurality of second drivers, the setting circuit, and the current waveform control circuit construct one cell array block, a plurality of cell array blocks are stacked on a semiconductor substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-140499, filed May 15, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a magnetic random access memory (MRAM) which stores "1"- and "0"-information using a tunneling magnetoresistive effect.
[0004] 2. Description of the Related Art
[0005] In recent years, many memories which store information by new principles have been proposed. One of them is a memory using the tunneling magnetoresistive (to be referred to as TMR hereinafter) effect proposed by Roy Scheuerlein et al. (e.g., "A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell", ISSCC2000 Technical Digest, p. 128).
[0006] A magnetic random access memory stores "1"- and "0"-information using MTJ (Magnetic Tunnel Junction) elements. An MTJ element has a structure in which an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers), as shown in FIG. 109. Information to be stored in the MTJ element is determined on the basis of whether the magnetizing directions of the two magnetic layers are parallel or antiparallel.
[0007] As shown in FIG. 110, "parallel" means that the two magnetic layers have the same magnetizing direction (magnetizing direction). "Antiparallel" means that the two magnetic layers have opposite magnetizing directions (the arrows indicate the magnetizing directions).
[0008] Normally, an antiferromagnetic layer is arranged on the side of one of the two magnetic layers. The antiferromagnetic layer serves as a member which fixes the magnetizing direction of one magnetic layer and changes only the magnetizing direction of the other magnetic layer, thereby easily rewriting information.
[0009] The magnetic layer whose magnetizing direction is fixed is called a fixed layer or pinning layer. The magnetic layer whose magnetizing direction can freely be changed is called a free layer or storing layer.
[0010] As shown in FIG. 110, when the magnetizing directions of the two magnetic layers are parallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers is minimized. This state is a "1"-state. When the magnetizing directions of the two magnetic layers are antiparallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the MTJ element is maximized. This state is a "0"--state.
[0011] The write operation principle for an MTJ element will be briefly described next with reference to FIG. 111.
[0012] MTJ elements are arranged at the intersections between write word lines and data lines (read/write bit lines) which cross each other. A write is done by supplying a current to each of a write word line and a data line and setting the magnetizing direction of an MTJ element in the parallel or antiparallel state using a magnetic field generated by the currents flowing through the two lines.
[0013] For example, assume that the easy-axis (axis of easy magnetization or easy magnetization axis) of an MTJ element corresponds to the X-direction, a write word line runs in the X-direction, and a data line runs in the Y-direction perpendicular to the X-direction. In the write mode, a current that flows in one direction is supplied to the write word line, and a current that flows in one or the other direction is supplied to the data line in accordance with write data.
[0014] When a current that flows in one direction is supplied to the data line, the magnetizing direction of the MTJ element is set in the parallel state ("1"-state). On the other hand, when a current that flows in the other direction is supplied to the data line, the magnetizing direction of the MTJ element is set in the antiparallel state ("0"-state).
[0015] The magnetizing direction of the MTJ element changes in accordance with the following mechanism.
[0016] As is indicated by the TMR curve in FIG. 112, when a magnetic field Hy is applied in the longitudinal (easy-axis) direction of an MTJ element, the resistance value of the MTJ element changes by, e.g., about 17%. The change ratio, i.e., the ratio of the resistance difference between the anti-parallel state and the parallel state and the resistance of the parallel state is called "MR ratio".
[0017] Note that the MR ratio changes depending on the structure, composition and morphology of the MTJ element. Currently, even an MTJ element with an MR ratio of about 50% is available.
[0018] The synthesized magnetic field of the magnetic field Hy in the easy-axis direction and a magnetic field Hx in the hard-axis (axis of hard magnetization or hard magnetization axis) direction is applied to the MTJ element. As indicated by the solid line in FIG. 113, the intensity of the magnetic field Hy in the easy-axis direction, which is necessary for changing the resistance value of the MTJ element, changes depending on the intensity of the magnetic field Hx in the hard-axis direction. When this phenomenon is used, data can be written in only an MTJ element that is present at the intersection between a selected write word line and a selected data line in memory cells arranged in an array.
[0019] This mechanism will be described in more detail using the asteroid curve shown in FIG. 113.
[0020] An MTJ element has an asteroid curve indicated by, e.g., the solid line in FIG. 113. More specifically, when the intensity of the synthesized magnetic field of the magnetic field Hy in the easy-axis direction and the magnetic field Hx in the hard-axis direction is outside (e.g., at the position indicated by the filled circle) the asteroid curve (solid line), the magnetizing direction of the magnetic layer can be reversed.
[0021] To the contrast, when the intensity of the synthesized magnetic field of the magnetic field Hy in the easy-axis direction and the magnetic field Hx in the hard-axis direction is inside (e.g., at the position indicated by the open circle) the asteroid curve (solid line), the magnetizing direction of the magnetic layer cannot be reversed.
[0022] Hence, when the intensity of the magnetic field Hy in the easy-axis direction and that of the magnetic field Hx in the hard-axis direction are changed to change the position of the intensity of the synthesized magnetic field in the Hx-Hy plane, the data write for the MTJ element can be controlled.
[0023] A read can easily be performed by supplying a current to a selected MTJ element and detecting the resistance value of the MTJ element.
[0024] For example, switch elements are connected in series to the MTJ elements. Only the switch element connected to a selected read word line is turned on to form a current path. Consequently, a current flows to only the selected MTJ element. Hence, data of the MTJ element can be read.
[0025] In the magnetic random access memory, as described above, the data write is executed by, e.g., supplying write currents to a write word line and a data line (read/write bit line) and causing a thus generated synthesized magnetic field to act on an MTJ element.
[0026] In the write operation, it is necessary to always accurately write data in an MTJ element. That is, a stable write characteristics is necessary. Stabilizing the write characteristics is especially important when data (the state of an MTJ element) stored in an MTJ element and write data are different. In such a case, the magnetized state (magnetizing direction) of the storing layer of the MTJ element must be stably inverted.
[0027] Conventionally, as a write method invented from the viewpoint of stabilizing the write characteristics, a method described in, e.g., U.S. Pat. No. 6,081,445 "Method to Write/Read MRAM Arrays" is known.
[0028] In this method, as shown in FIG. 114, first, the magnetic field Hx in the hard-axis direction is caused to act on the MTJ element to align the magnetizing direction at the end portion of the storing layer of the TMR layer to the hard-axis direction ({circle over (1)}). Then, the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element ({circle over (2)}).
[0029] In this method, after a write current flows to the write word line, a write current having a direction corresponding to write data flows to the write bit line. The easy-axis of the MTJ element is set along the direction in which the write word line runs.
[0030] As described above, the magnetic field Hx extending in the hard-axis direction is made to act on the MTJ element before the magnetic field Hy in the easy-axis direction acts on the MTJ element. As a result, the magnetizing direction at the end portion of the storing layer of the MTJ element is aligned to the hard-axis direction (the magnetizing direction is made unstable). This alignment is performed to prevent changes in the direction of magnetization in the end portion of the storing layer of the MTJ element every time data is written. Hence, the data written is not influenced by the data that has been written before. This helps to enhance the reliability of data-writing.
[0031] The inversion of magnetization of the storing layer of the MTJ element starts from the end portion of the storing layer, as shown in FIG. 115. Hence, the intensity of the synthesized magnetic required and the time of applying the magnetic field may change every time data is written, unless the end portion of the storing layer is magnetized in the same direction every time the data-writing starts. The magnetic field Hx extending in the hard-axis direction is made to act on the MTJ element before the magnetic field Hy in the easy-axis direction acts on the MTJ element. In this method, the field Hx is more intense than a magnetic field that should be applied to change the direction of magnetization in the main portion of the storing layer to the hard-axis direction. Thus, the intensity of the field Hx remains unchanged, not influenced by the data that is being written. That is, the field Hx is intense enough to change the direction of magnetization in the end portion of the storing layer, which is more changeable than the direction of magnetization in the main portion. This data-writing method is advantageous in terms of the reproducibility of data, because the magnetic field Hx, which is not influenced by the data being written, can alone determine the direction of magnetization in the end portion.
[0032] U.S. Pat. No. 6,081,445 discloses only that the magnetic field Hx in the hard-axis direction is caused to act on the MTJ element, and then, the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element. In this case, it may be impossible to sufficiently invert the magnetization of the storing layer of the MTJ element. In addition, the magnetizing direction at the end portion of the storing layer of the MTJ element is kept aligned to the hard-axis direction even after the write operation.
BRIEF SUMMARY OF THE INVENTION
[0033] (1) {circle over (1)} A writing method of a magnetic random access memory according to a first aspect of the present invention comprises steps of causing a first magnetic field parallel to a hard-axis to act on a magnetoresistive element having an easy-axis and the hard-axis, and causing a second magnetic field which is weaker than the first magnetic field and parallel to the hard-axis and a third magnetic field parallel to the easy-axis to simultaneously act on the magnetoresistive element.
[0034] {circle over (2)} A writing method of a magnetic random access memory according to a second aspect of the present invention comprises steps of causing a first magnetic field parallel to a hard-axis and a second magnetic field parallel to an easy-axis to simultaneously act on a magnetoresistive element having the easy-axis and hard-axis, and causing a third magnetic field which is stronger than the second magnetic field and parallel to the easy-axis to act on the magnetoresistive element.
[0035] {circle over (3)} A writing method of a magnetic random access memory according to a third aspect of the present invention comprises steps of causing a first magnetic field parallel to a hard-axis to act on a magnetoresistive element having an easy-axis and the hard-axis, causing a second magnetic field parallel to the hard-axis and a third magnetic field parallel to the easy-axis to simultaneously act on the magnetoresistive element, and causing a fourth magnetic field parallel to the easy-axis to act on the magnetoresistive element.
[0036] {circle over (4)} A writing method of a magnetic random access memory according to a fourth aspect of the present invention comprises steps of causing a first magnetic field parallel to a hard-axis and a second magnetic field parallel to an easy-axis to simultaneously act on a magnetoresistive element having the easy-axis and hard-axis, causing a third magnetic field parallel to the hard-axis and a fourth magnetic field which is stronger than the second magnetic field and parallel to the easy-axis to simultaneously act on the magnetoresistive element, and causing a fifth magnetic field which is weaker than the third magnetic field and parallel to the hard-axis and a sixth magnetic field parallel to the easy-axis to simultaneously act on the magnetoresistive element.
[0037] (2) {circle over (1)} A magnetic random access memory according to a first aspect of the present invention comprises first and second write lines which cross each other, a magnetoresistive element arranged at an intersection between the first and second write lines, a first driver to supply a first write current to the first write line, a second driver to supply a second write current to the second write line, a setting circuit in which first setting data to control the first write current and second setting data to control the second write current are registered, and a current waveform control circuit which controls operation of the first driver depending on the first setting data and controls operation of the second driver depending on the second setting data.
[0038] {circle over (2)} A magnetic random access memory according to a second aspect of the present invention comprises a plurality of first write lines, a plurality of second write lines which cross the plurality of first write lines, a plurality of magnetoresistive elements arranged at intersections between the plurality of first write lines and the plurality of second write lines, a plurality of first drivers corresponding to the plurality of first write lines, a plurality of second drivers corresponding to the plurality of second write lines, a setting circuit in which first setting data to control a first write current flowing to the plurality of first write lines and second setting data to control a second write current flowing to the plurality of second write lines are registered, and a current waveform control circuit which controls operations of the plurality of first drivers depending on the first setting data and controls operations of the plurality of second drivers depending on the second setting data.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0039] FIG. 1 is a view showing one step of a write principle according to the first embodiment of the present invention;
[0040] FIG. 2 is a view showing one step of the write principle according to the first embodiment of the present invention;
[0041] FIG. 3 is a flow chart showing all steps of the write principle according to the first embodiment of the present invention;
[0042] FIG. 4 is a view showing one step of a write principle according to the second embodiment of the present invention;
[0043] FIG. 5 is a view showing one step of the write principle according to the second embodiment of the present invention;
[0044] FIG. 6 is a view showing one step of the write principle according to the second embodiment of the present invention;
[0045] FIG. 7 is a flow chart showing all steps of the write principle according to the second embodiment of the present invention;
[0046] FIG. 8 is a view showing one step of a write principle according to the third embodiment of the present invention;
[0047] FIG. 9 is a view showing one step of the write principle according to the third embodiment of the present invention;
[0048] FIG. 10 is a view showing one step of the write principle according to the third embodiment of the present invention;
[0049] FIG. 11 is a flow chart showing all steps of the write principle according to the third embodiment of the present invention;
[0050] FIG. 12 is a view showing one step of a write principle according to the fourth embodiment of the present invention;
[0051] FIG. 13 is a view showing one step of the write principle according to the fourth embodiment of the present invention;
[0052] FIG. 14 is a view showing one step of the write principle according to the fourth embodiment of the present invention;
[0053] FIG. 15 is a flow chart showing all steps of the write principle according to the fourth embodiment of the present invention;
[0054] FIG. 16 is a view showing one step of a write principle according to the fifth embodiment of the present invention;
[0055] FIG. 17 is a view showing one step of the write principle according to the fifth embodiment of the present invention;
[0056] FIG. 18 is a flow chart showing all steps of the write principle according to the fifth embodiment of the present invention;
[0057] FIG. 19 is a view showing one step of a write principle according to the sixth embodiment of the present invention;
[0058] FIG. 20 is a view showing one step of the write principle according to the sixth embodiment of the present invention;
[0059] FIG. 21 is a view showing one step of the write principle according to the sixth embodiment of the present invention;
[0060] FIG. 22 is a flow chart showing all steps of the write principle according to the sixth embodiment of the present invention;
[0061] FIG. 23 is a view showing one step of a write principle according to the seventh embodiment of the present invention;
[0062] FIG. 24 is a view showing one step of the write principle according to the seventh embodiment of the present invention;
[0063] FIG. 25 is a view showing one step of the write principle according to the seventh embodiment of the present invention;
[0064] FIG. 26 is a flow chart showing all steps of the write principle according to the seventh embodiment of the present invention;
[0065] FIG. 27 is a view showing one step of a write principle according to the eighth embodiment of the present invention;
[0066] FIG. 28 is a view showing one step of the write principle according to the eighth embodiment of the present invention;
[0067] FIG. 29 is a view showing one step of the write principle according to the eighth embodiment of the present invention;
[0068] FIG. 30 is a flow chart showing all steps of the write principle according to the eighth embodiment of the present invention;
[0069] FIG. 31 is a view showing a write principle according to the ninth embodiment of the present invention;
[0070] FIG. 32 is a graph showing a change in intensity of a magnetic field in the ninth embodiment;
[0071] FIG. 33 is a flow chart showing all steps of the write principle according to the ninth embodiment of the present invention;
[0072] FIG. 34 is a view showing a write principle according to the 10th embodiment of the present invention;
[0073] FIG. 35 is a graph showing a change in intensity of a magnetic field in the 10th embodiment;
[0074] FIG. 36 is a flow chart showing all steps of the write principle according to the 10th embodiment of the present invention;
[0075] FIG. 37 is a view showing the overall arrangement of an MRAM according to Circuit Example 1 which implements the first to 10th embodiments for each chip or each cell array;
[0076] FIG. 38 is a view showing an example of a write word line driver/sinker according to Circuit Example 1;
[0077] FIG. 39 is a view showing an example of a write bit line driver/sinker according to Circuit Example 1;
[0078] FIG. 40 is a view showing an example of a write current waveform control circuit according to Circuit Example 1;
[0079] FIG. 41 is a view showing an example of a write word line driver/sinker trigger circuit according to Circuit Example 1;
[0080] FIG. 42 is a view showing an example of a write bit line driver/sinker trigger circuit according to Circuit Example 1;
[0081] FIG. 43 is a view showing an example of a setting circuit according to Circuit Example 1;
[0082] FIG. 44 is a view showing an example of a register in the setting circuit according to Circuit Example 1;
[0083] FIG. 45 is a view showing another example of the register in the setting circuit according to Circuit Example 1;
[0084] FIG. 46 is a view showing an example of a Vclamp generation circuit used in Circuit Example 1;
[0085] FIG. 47 is a view showing an example of a decoder in the setting circuit according to Circuit Example 1;
[0086] FIG. 48 is a view showing the overall arrangement of an MRAM according to Circuit Example 2 which implements the first to 10th embodiments for each chip or each cell array;
[0087] FIG. 49 is a view showing an example of a write word line driver/sinker according to Circuit Example 2;
[0088] FIG. 50 is a view showing an example of a write bit line driver/sinker according to Circuit Example 2;
[0089] FIG. 51 is a view showing an example of a write current waveform control circuit according to Circuit Example 2;
[0090] FIG. 52 is a view showing an example of a write word line driver/sinker trigger circuit according to Circuit Example 2;
[0091] FIG. 53 is a view showing an example of a write bit line driver/sinker trigger circuit according to Circuit Example 2;
[0092] FIG. 54 is a view showing an example of a waveform generation circuit used in Circuit Example 2;
[0093] FIG. 55 is a view showing an example of a delay circuit in the waveform generation circuit used in Circuit Example 2;
[0094] FIG. 56 is a view showing an example of a constant current source circuit used in Circuit Example 2;
[0095] FIG. 57 is a waveform chart showing an example of MRAM operation according to Circuit Example 2;
[0096] FIG. 58 is a view showing an example of a setting circuit according to Circuit Example 2;
[0097] FIG. 59 is a view showing an example of a register in the setting circuit according to Circuit Example 2;
[0098] FIG. 60 is a view showing an example of a decoder in the setting circuit according to Circuit Example 2;
[0099] FIG. 61 is a view showing the overall arrangement of an MRAM according to Circuit Example 3 which implements the first to 10th embodiments for each chip or each cell array;
[0100] FIG. 62 is a view showing an example of a write bit line driver/sinker according to Circuit Example 3;
[0101] FIG. 63 is a view showing an example of a write bit line driver/sinker trigger circuit according to Circuit Example 3;
[0102] FIG. 64 is a view showing an example of the write bit line driver/sinker trigger circuit according to Circuit Example 3;
[0103] FIG. 65 is a view showing the overall arrangement of the MRAM according to Circuit Example 1 which implements the first to 10th embodiments for each write word/bit line;
[0104] FIG. 66 is a view showing an example of a write word line driver/sinker according to Circuit Example 1;
[0105] FIG. 67 is a view showing an example of a write bit line driver/sinker according to Circuit Example 1;
[0106] FIG. 68 is a view showing an example of a write current waveform control circuit/setting circuit according to Circuit Example 1;
[0107] FIG. 69 is a view showing an example of the write current waveform control circuit/setting circuit according to Circuit Example 1;
[0108] FIG. 70 is a view showing an example of the write current waveform control circuit/setting circuit according to Circuit Example 1;
[0109] FIG. 71 is a view showing an example of a write word line driver/sinker trigger circuit according to Circuit Example 1;
[0110] FIG. 72 is a view showing an example of a write bit line driver/sinker trigger circuit according to Circuit Example 1;
[0111] FIG. 73 is a view showing an example of the write bit line driver/sinker trigger circuit according to Circuit Example 1;
[0112] FIG. 74 is a view showing an example of a setting circuit according to Circuit Example 1;
[0113] FIG. 75 is a view showing an example of the setting circuit according to Circuit Example 1;
[0114] FIG. 76 is a view showing an example of the setting circuit according to Circuit Example 1;
[0115] FIG. 77 is a waveform chart showing an example of MRAM operation according to Circuit Example 1;
[0116] FIG. 78 is a waveform chart showing an example of MRAM operation according to Circuit Example 1;
[0117] FIG. 79 is a view showing an example of a write word line driver/sinker trigger circuit according to Circuit Example 2;
[0118] FIG. 80 is a view showing an example of a write bit line driver/sinker trigger circuit according to Circuit Example 2;
[0119] FIG. 81 is a view showing an example of the write bit line driver/sinker trigger circuit according to Circuit Example 2;
[0120] FIG. 82 is a view showing an example of a waveform generation circuit used in Circuit Example 2;
[0121] FIG. 83 is a waveform chart showing the operation waveforms of the waveform generation circuit shown in FIG. 82;
[0122] FIG. 84 is a view showing an example of the waveform generation circuit used in Circuit Example 2;
[0123] FIG. 85 is a waveform chart showing the operation waveforms of the waveform generation circuit shown in FIG. 84;
[0124] FIG. 86 is a view showing an example of the waveform generation circuit used in Circuit Example 2;
[0125] FIG. 87 is a waveform chart showing the operation waveforms of the waveform generation circuit shown in FIG. 86;
[0126] FIG. 88 is a view showing an example of the waveform generation circuit used in Circuit Example 2;
[0127] FIG. 89 is a waveform chart showing the operation waveforms of the waveform generation circuit shown in FIG. 88;
[0128] FIG. 90 is a waveform chart showing an example of MRAM operation according to Circuit Example 2;
[0129] FIG. 91 is a waveform chart showing an example of MRAM operation according to Circuit Example 2;
[0130] FIG. 92 is a view showing an example of a write bit line driver/sinker according to Circuit Example 3;
[0131] FIG. 93 is a view showing an example of a write current waveform control circuit/setting circuit according to Circuit Example 3;
[0132] FIG. 94 is a view showing an example of the write current waveform control circuit/setting circuit according to Circuit Example 3;
[0133] FIG. 95 is a view showing an example of a write bit line driver/sinker according to Circuit Example 4;
[0134] FIG. 96 is a view showing an example of a write current waveform control circuit/setting circuit according to Circuit Example 4;
[0135] FIG. 97 is a view showing an example of the write current waveform control circuit/setting circuit according to Circuit Example 4;
[0136] FIG. 98 is a perspective view showing a schematic arrangement in which a circuit scheme according to the present invention is applied to an MRAM having memory cell arrays stacked in a plurality of stages;
[0137] FIG. 99 is a perspective view showing a schematic arrangement in which a circuit scheme according to the present invention is applied to an MRAM having memory cell arrays stacked in a plurality of stages;
[0138] FIG. 100 is a view showing an example of a write word line driver/sinker applied to the ninth embodiment;
[0139] FIG. 101 is a view showing an example of a write bit line driver/sinker applied to the ninth embodiment;
[0140] FIG. 102 is a view showing an example of a constant current source circuit;
[0141] FIG. 103 is a waveform chart showing the operation waveforms of the circuits shown in FIGS. 100 and 101;
[0142] FIG. 104 is a view showing an example of a write word line driver/sinker applied to the 10th embodiment;
[0143] FIG. 105 is a view showing an example of a write bit line driver/sinker applied to the 10th embodiment;
[0144] FIG. 106 is a view showing an example of a VPGW/VPGB generation circuit;
[0145] FIG. 107 is a view showing an example of a constant current source circuit;
[0146] FIG. 108 is a waveform chart showing the operation waveforms of the circuits shown in FIGS. 104 and 105;
[0147] FIG. 109 is a view showing a structural example of an MTJ element;
[0148] FIG. 110 is a view showing two states of the MTJ element;
[0149] FIG. 111 is a view showing the write operation principle of a magnetic random access memory;
[0150] FIG. 112 is a graph showing a TRM curve;
[0151] FIG. 113 is a view showing an asteroid curve;
[0152] FIG. 114 is a view showing the magnetizing direction of the storing layer of the MTJ element; and
[0153] FIG. 115 is a view showing an example of a conventional write principle.
DETAILED DESCRIPTION OF THE INVENTION
[0154] Magnetic random access memories according to the embodiments of the present invention will be described below in detail with reference to the accompanying drawing.
[0155] 1. Write Principle (Method of Applying Magnetic Field to MTJ Element)
[0156] The write principle for the magnetic random access memories according to the embodiments of the present invention, i.e., a method of applying magnetic fields Hx and Hy to an MTJ element will be described first.
[0157] In the write principle according to the present invention, timings to supply write currents, i.e., timings to apply the magnetic fields Hx and Hy and temporal changes in current values of write currents, i.e., temporal changes in intensities of the magnetic fields Hx and Hy will be examined.
[0158] (1) First Embodiment
[0159] In the write principle of this embodiment, a method of aligning the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction before causing a magnetic field Hy in the easy-axis direction to act on the MTJ element, and a method of, after the magnetic field Hy in the easy-axis direction acts on the MTJ element, stabilizing the magnetic direction at the end portion and the interior of the storing layer of the MTJ element will be proposed.
[0160] A point common to these methods is that the intensity of a magnetic field Hx in the hard-axis direction is temporally changed.
[0161] More specifically, as shown in FIG. 1, before the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the MTJ element to the hard-axis direction is caused to act on the MTJ element to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer to the hard-axis direction ({circle over (1)}).
[0162] Then, as shown in FIG. 2, the magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element to align the magnetizing direction of the MTJ element to the easy-axis direction. At this time, to completely align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the MTJ element to the easy-axis direction, the magnetic field Hx in the hard-axis direction is set to be weaker than that before the magnetic field Hy acts on the MTJ element ({circle over (2)}).
[0163] FIG. 3 simply shows the operation principle of the magnetic random access memory which implements the write principle of the first embodiment.
[0164] The generation timings and intensities of the magnetic fields Hx and Hy are determined on the basis of the current supply timings and magnitudes of write currents to be supplied to a write word line and write bit line, which cross each other. For example, to temporally change the intensity of the magnetic field Hx in the hard-axis direction, the magnitude of the write current to be supplied to the write word line is temporally changed. At this time, assume that the easy-axis of the MTJ element is set along the direction in which the write word line runs.
[0165] First, a write current Ip1 having a predetermined direction is supplied to the write word line. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0166] Then, a write current Ip2 (<Ip1) having a predetermined direction is supplied to the write word line. A write current Ip3 having a direction corresponding to write data is supplied to the write bit line. A synthesized magnetic field Hx+Hy is generated by the write currents Ip2 and Ip3, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST2).
[0167] The change from the write current Ip1 to the write current Ip2
(change of the magnetic field Hx: {circle over (1)}.fwdarw.{circle over (2)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0168] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0169] As described above, in the write principle of this embodiment, before the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic field at the end portion of the storing layer of the MTJ element to the hard-axis direction is caused to act on the MTJ element. In addition, when the magnetic field Hy in the easy-axis direction is to be caused to act on the MTJ element, the magnetic field Hx in the hard-axis direction is set to be weaker than that before the magnetic field Hy is generated.
[0170] Hence, the magnetizing direction of the storing layer of the MTJ element can reliably be reversed, and the write characteristics can improve.
[0171] (2) Second Embodiment
[0172] If the magnetizing direction of the magnetic domains at the end portion of the storing layer of the MTJ element is aligned to the hard-axis direction even after the write operation, as shown in FIG. 95, the magnetizing direction of the magnetic domain at the end portion is perpendicular to the magnetizing direction of the fixed layer of the MTJ element. The MR ratio at this portion is about {fraction (1/2)} that when the magnetized state (the relationship between the magnetizing direction of the fixed layer and that of the storing layer) of the MTJ element is parallel or antiparallel. As a result, the MR ratio of the MTJ element degrades.
[0173] In the write principle of this embodiment, assuming that the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element is aligned to the hard-axis direction by a magnetic field Hx in the hard-axis direction, a method of completely aligning the magnetizing direction of the larger interior portion of the storing layer of the MTJ element to the easy-axis direction by a magnetic field Hy in the easy-axis direction will be proposed.
[0174] The point of this method is that even after the magnetic field Hx in the hard-axis direction is extinguished, the magnetic field Hy in the easy-axis direction is continuously caused to act on the MTJ element.
[0175] More specifically, as shown in FIG. 4, the magnetic field Hx in the hard-axis direction is caused to act on the MTJ element to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the MTJ element to the hard-axis direction ({circle over (1)}).
[0176] Next, as shown in FIG. 5, the magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element. At this time, since the magnetic field Hx in the hard-axis direction is continuously generated, a synthesized magnetic field Hx+Hy acts on the MTJ element ({circle over (2)}).
[0177] After that, as shown in FIG. 6, only the magnetic field Hx in the hard-axis direction is extinguished. That is, since only the magnetic field Hy in the easy-axis direction acts on the MTJ element, the magnetizing direction of the most of the storing layer of the MTJ element completely aligns to the easy-axis direction ({circle over (3)}).
[0178] FIG. 7 simply shows the operation principle of the magnetic random access memory which implements the write principle of the second embodiment.
[0179] The generation/extinction timings of the magnetic fields Hx and Hy are determined on the basis of the supply/cutoff timings of write currents to be supplied to a write word line and write bit line, which cross each other.
[0180] First, a write current Ip1 having a predetermined direction is supplied to the write word line. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0181] Then, while continuously supplying the write current Ip1 to the write word line, a write current Ip2 having a direction corresponding to write data is supplied to the write bit line. The synthesized magnetic field Hx and Hy is generated by the write currents Ip1 and Ip2 (step ST2).
[0182] After that, the write current Ip1 to the write word line is stopped. Only the write current Ip2 to the write bit line is continuously supplied. As a result, the magnetizing direction of the most of the storing layer of the MTJ element is completely aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST3).
[0183] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0184] As described above, in the write principle of this embodiment, even after the magnetic field Hx in the hard-axis direction is extinguished, the magnetic field Hy in the easy-axis direction is continuously caused to act on the MTJ element. Hence, the problem that the magnetizing direction of the interior portion of the storing layer is made unstable is extinguished and prevented, and the most of the storing layer align to the easy-axis direction. Additionally, the magnetizing direction of the storing layer of the MTJ element can reliably be reversed, and the write characteristics can improve.
[0185] (3) Third Embodiment
[0186] In the write principle of this embodiment, assuming that the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element is aligned to the hard-axis direction by a magnetic field Hx in the hard-axis direction, a method of completely aligning the magnetizing direction of the most of the storing layer of the MTJ element to the easy-axis direction by a magnetic field Hy in the easy-axis direction will be proposed.
[0187] The point of this method is that after the magnetic field Hx in the hard-axis direction is extinguished, the magnetic field Hy in the easy-axis direction is continuously caused to act on the MTJ element, and simultaneously, the magnetic field Hy is made stronger than that before the magnetic field Hx is extinguished.
[0188] More specifically, as shown in FIG. 8, the magnetic field Hx in the hard-axis direction is caused to act on the MTJ element to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the MTJ element to the hard-axis direction ({circle over (1)}).
[0189] Next, as shown in FIG. 9, the magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element. At this time, since the magnetic field Hx in the hard-axis direction is continuously generated, a synthesized magnetic field Hx+Hy acts on the MTJ element ({circle over (2)}).
[0190] After that, as shown in FIG. 10, only the magnetic field Hx in the hard-axis direction is extinguished. Only the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element. At this time, the magnetic field Hy is made stronger than that before the magnetic field Hy is extinguished. The magnetizing direction of the most of the storing layer of the MTJ element is completely aligned to the easy-axis direction by the magnetic field Hy ({circle over (3)}).
[0191] FIG. 11 simply shows the operation principle of the magnetic random access memory which implements the write principle of the third embodiment.
[0192] The generation/extinction timings and intensities of the magnetic fields Hx and Hy are determined on the basis of the supply/cutoff timings of write currents to be supplied to a write word line and write bit line, which cross each other.
[0193] First, a write current Ip1 having a predetermined direction is supplied to the write word line. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0194] Then, while continuously supplying the write current Ip1 to the write word line, a write current Ip2 having a direction corresponding to write data is supplied to the write bit line. The synthesized magnetic field Hx and Hy is generated by the write currents Ip1 and Ip2 (step ST2).
[0195] After that, the write current Ip1 to the write word line is stopped. A write current Ip3 (>Ip2) is supplied to the write bit line. As a result, the magnetizing direction of the most of the storing layer of the MTJ element is completely aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST3).
[0196] The change from the write current Ip2 to the write current Ip3
(change of the magnetic field Hy: {circle over (2)}.fwdarw.{circle over (3)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0197] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0198] As described above, in the write principle of this embodiment, even after the magnetic field Hx in the hard-axis direction is extinguished, the magnetic field Hy in the easy-axis direction is continuously caused to act on the MTJ element. In addition, the magnetic field Hy after the magnetic field Hx in the hard-axis direction is extinguished is stronger than that before the magnetic field Hx is extinguished.
[0199] Hence, the problem that the magnetizing direction of the interior portion of the storing layer is made unstable is extinguished and prevented, and the most of the storing layer align to the easy-axis direction. Additionally, the magnetizing direction of the storing layer of the MTJ element can reliably be reversed, and the write characteristics can improve.
[0200] (4) Fourth Embodiment
[0201] In the write principle of this embodiment, a method of aligning the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction before causing a magnetic field Hy in the easy-axis direction to act on the MTJ element, and a method of, after the magnetic field Hy in the easy-axis direction acts on the MTJ element, completely aligning the magnetizing direction of the most of the storing layer of the MTJ element to the easy-axis direction will be proposed.
[0202] The write principle of this embodiment of a combination of the write principle of the first embodiment and that of the third embodiment. The point is that the intensity of a magnetic field Hx in the hard-axis direction and the intensity of the magnetic field Hy in the easy-axis direction are temporally changed, and after the magnetic field Hx in the hard-axis direction is extinguished, the magnetic field Hy in the easy-axis direction is continuously caused to act on the MTJ element.
[0203] More specifically, as shown in FIG. 12, before the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the MTJ element to the hard-axis direction is caused to act on the MTJ element to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer to the hard-axis direction ({circle over (1)}).
[0204] Next, as shown in FIG. 13, the magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element to align the magnetizing direction of the MTJ element to the easy-axis direction. At this time, to completely align the magnetizing direction of the magnetic domain at the end portion of the storing layer of the MTJ element to the easy-axis direction, the magnetic field Hx in the hard-axis direction is set to be weaker than that before the magnetic field Hy acts on the MTJ element ({circle over (2)}).
[0205] After that, as shown in FIG. 14, only the magnetic field Hx in the hard-axis direction is extinguished. Only the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element. At this time, the magnetic field Hy is made stronger than that before the magnetic field Hy is extinguished such that the magnetizing direction of the most of the storing layer of the MTJ element completely aligns to the easy-axis direction ({circle over (3)}).
[0206] FIG. 15 simply shows the operation principle of the magnetic random access memory which implements the write principle of the fourth embodiment.
[0207] First, a write current Ip1 having a predetermined direction is supplied to the write word line. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0208] Then, a write current Ip2 (<Ip1) having a predetermined direction is supplied to the write word line. A write current Ip3 having a direction corresponding to write data is supplied to the write bit line. A synthesized magnetic field Hx+Hy is generated by the write currents Ip2 and Ip3 (step ST2).
[0209] After that, the write current Ip2 to the write word line is stopped. A write current Ip4 (>Ip3) is supplied to the write bit line. As a result, the magnetizing direction of the most of the storing layer of the MTJ element is completely aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST3).
[0210] The change from the write current Ip1 to the write current Ip2
(change of the magnetic field Hx: {circle over (1)}.fwdarw.{circle over (2)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0211] The change from the write current Ip3 to the write current Ip4
(change of the magnetic field Hy: {circle over (2)}.fwdarw.{circle over (3)}) can also be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0212] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0213] As described above, in the write principle of this embodiment, before the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic field at the end portion of the storing layer of the MTJ element to the hard-axis direction is caused to act on the MTJ element. In addition, when the magnetic field Hy in the easy-axis direction is to be caused to act on the MTJ element, the magnetic field Hx in the hard-axis direction is set to be weaker than that before the magnetic field Hy is generated.
[0214] In addition, in the write principle of this embodiment, even after the magnetic field Hx in the hard-axis direction is extinguished, the magnetic field Hy in the easy-axis direction is continuously caused to act on the MTJ element. Furthermore, the magnetic field Hy after the magnetic field Hx in the hard-axis direction is extinguished is larger than that before the magnetic field Hx is extinguished.
[0215] Hence, the problem that the magnetizing direction of the interior portion of the storing layer is made unstable is extinguished and prevented, and the most of the storing layer align to the easy-axis direction. Additionally, the magnetizing direction of the storing layer of the MTJ element can reliably be reversed, and the write characteristics can improve.
[0216] (5) Fifth Embodiment
[0217] In the write principle of this embodiment, a method of simultaneously generating/extinguishing a magnetic field Hx in the hard-axis direction and a magnetic field Hy in the easy-axis direction and also temporally changing the intensity of the magnetic field Hy in the easy-axis direction will be proposed.
[0218] The point of the method of this embodiment is that the magnetic field Hx in the hard-axis direction always has a constant intensity, the magnetic field Hy in the easy-axis direction is set to a small value at the early stage of generation of the magnetic fields Hx and Hy, and then, the magnetic field Hy in the easy-axis direction is changed to a large value.
[0219] More specifically, as shown in FIG. 16, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction is caused to act on the MTJ element. Simultaneously, the small magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element. At this stage, since the MTJ element is largely influenced by the magnetic field Hx, the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction ({circle over (1)}).
[0220] After that, as shown in FIG. 17, the magnetic field Hy in the easy-axis direction is changed to a sufficiently large value to reverse the magnetizing direction of the storing layer of the MTJ element by a synthesized magnetic field Hx+Hy. At this time, the magnetic fields Hx and Hy may have either the same intensity or different intensities ({circle over (2)}).
[0221] FIG. 18 simply shows the operation principle of the magnetic random access memory which implements the write principle of the fifth embodiment.
[0222] First, a write current Ip1 having a predetermined direction is supplied to a write word line. A write current Ip2 having a direction corresponding to write data is supplied to a write bit line. The write current Ip2 has a value much smaller than that of the write current Ip1. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1 having the large value, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0223] After that, a write current Ip3 (>Ip2) having a sufficiently large value is supplied to the write bit line. The synthesized magnetic field Hx+Hy is generated by the write currents Ip1 and Ip3. Consequently, the magnetizing direction of the most of the storing layer of the MTJ element is completely aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST2).
[0224] The change from the write current Ip2 to the write current Ip3
(change of the magnetic field Hy: {circle over (1)}{circle over (2)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0225] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0226] As described above, in the write principle of this embodiment, since the magnetic field Hy in the easy-axis direction is changed stepwise, no large write current need be abruptly supplied to the write bit line to generate the large magnetic field Hy. That is, since the write current (the magnitude of the write current) supplied to the write bit line does not abruptly change, noise due to an inductance component can be reduced.
[0227] (6) Sixth Embodiment
[0228] In the write principle of this embodiment, a method of simultaneously generating/extinguishing a magnetic field Hx in the hard-axis direction and a magnetic field Hy in the easy-axis direction and also temporally changing both the intensities of the magnetic field Hx in the hard-axis direction and the magnetic field Hy in the easy-axis direction will be proposed.
[0229] The point of the method of this embodiment is that at the early stage of generation of the magnetic fields Hx and Hy, the magnetic field Hx in the hard-axis direction is set to a large value while the magnetic field Hy in the easy-axis direction is set to a small value, and then, the magnetic field Hy in the easy-axis direction is changed to a large value while the magnetic field Hx in the hard-axis direction is changed to a small value.
[0230] More specifically, as shown in FIG. 19, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction is caused to act on the MTJ element. Simultaneously, the small magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element. At this stage, since the MTJ element is largely influenced by the magnetic field Hx, the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction ({circle over (1)}).
[0231] After that, as shown in FIG. 20, the magnetic field Hy in the easy-axis direction is changed to a sufficiently large value to reverse the magnetizing direction of the storing layer of the MTJ element by a synthesized magnetic field Hx+Hy. At this time, the magnetic fields Hx and Hy may have either the same intensity or different intensities ({circle over (2)}).
[0232] After that, as shown in FIG. 21, the magnetic field Hx in the hard-axis direction is changed to a sufficiently small value to align the magnetizing direction of the most of the storing layer of the TMR layer to the easy-axis direction by the synthesized magnetic field Hx+Hy ({circle over (3)}).
[0233] FIG. 22 simply shows the operation principle of the magnetic random access memory which implements the write principle of the sixth embodiment.
[0234] First, a write current Ip1 having a predetermined direction is supplied to a write word line. A write current Ip2 having a direction corresponding to write data is supplied to a write bit line. The write current Ip2 has a value much smaller than that of the write current Ip1. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1 having the large value, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0235] Next, when a write current Ip3 (>Ip2) having a sufficiently large value is supplied to the write bit line, the synthesized magnetic field Hx+Hy is generated by the write currents Ip1 and Ip3 (step ST2).
[0236] After that, when a write current Ip4 (<Ip1) having a sufficiently small value is supplied to the write word line, the synthesized magnetic field Hx+Hy is generated by the write currents Ip3
and Ip4 (step ST2). Consequently, the magnetizing direction of the most of the storing layer of the MTJ element completely is aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST3).
[0237] The change from the write current Ip2 to the write current Ip3
(change of the magnetic field Hy: {circle over (1)}{circle over (2)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0238] The change from the write current Ip1 to the write current Ip4
(change of the magnetic field Hx: {circle over (2)}{circle over (3)}) can also be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0239] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0240] As described above, in the write principle of this embodiment, the magnetic field Hx in the hard-axis direction is weakened stepwise, and the magnetic field Hy in the easy-axis direction is strengthened stepwise. For this reason, no large write current need be abruptly supplied to the write word/bit line to generate/extinguish the large magnetic fields Hx and Hy. That is, since the write current (the magnitude of the write current) supplied to the write word/bit line does not abruptly change, noise due to an inductance component can be reduced.
[0241] (7) Seventh Embodiment
[0242] In the write principle of this embodiment, a method of simultaneously generating/extinguishing a magnetic field Hx in the hard-axis direction and a magnetic field Hy in the easy-axis direction and also temporally changing both the intensities of the magnetic field Hx in the hard-axis direction and the magnetic field Hy in the easy-axis direction will be proposed.
[0243] The point of the method of this embodiment is that at the early stage of generation of the magnetic fields Hx and Hy, the magnetic field Hx in the hard-axis direction is set to a sufficiently large value while the magnetic field Hy in the easy-axis direction is set to a small value, then, the magnetic field Hx in the hard-axis direction is changed from the sufficiently large value to a large value while the magnetic field Hy in the easy-axis direction is changed to a large value, and then, the magnetic field Hx in the hard-axis direction is changed to a small value.
[0244] That is, in the write principle of this embodiment, the magnetic field Hx in the hard-axis direction weakens in three steps, and the magnetic field Hy in the easy-axis direction strengthens in two steps.
[0245] More specifically, as shown in FIG. 23, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction is caused to act on the MTJ element. Simultaneously, the small magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element. At this stage, since the MTJ element is largely influenced by the magnetic field Hx, the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction ({circle over (1)}).
[0246] Next, as shown in FIG. 24, the magnetic field Hx in the hard-axis direction is changed from the sufficiently large value to a large value (the magnetic field Hx is slightly weakened). Simultaneously, the magnetic field Hy in the easy-axis direction is changed to a large value. At this time, the magnetic fields Hx and Hy may have either the same intensity or different intensities ({circle over (2)}).
[0247] After that, as shown in FIG. 25, the magnetic field Hx in the hard-axis direction is changed to a sufficiently small value. The magnetizing direction of the most of the storing layer of the TMR layer is completely aligned to the easy-axis direction by a synthesized magnetic field Hx+Hy ({circle over (3)}).
[0248] FIG. 26 simply shows the operation principle of the magnetic random access memory which implements the write principle of the seventh embodiment.
[0249] First, a write current Ip1 having a predetermined direction is supplied to a write word line. A write current Ip2 having a direction corresponding to write data is supplied to a write bit line. The write current Ip2 has a value much smaller than that of the write current Ip1. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1 having the large value, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0250] Next, when a write current Ip3 (<Ip1) is supplied to the write word line, and a write current Ip4 (>Ip2) is supplied to the write bit line, the synthesized magnetic field Hx+Hy is generated by the write currents Ip3 and Ip4 (step ST2).
[0251] After that, when a write current Ip5 (<Ip3) is supplied to the write word line, the synthesized magnetic field Hx+Hy is generated by the write currents Ip4 and Ip5. Consequently, the magnetizing direction of the most of the storing layer of the MTJ element is aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST3).
[0252] The change from the write current Ip1 to the write current Ip3 and the change from the write current Ip3 to the write current Ip5 (change of the magnetic field Hx: {circle over (1)}.fwdarw.{circle over (2)}.fwdarw.{circle over (3)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0253] The change from the write current Ip2 to the write current Ip4
(change of the magnetic field Hy: {circle over (1)}.fwdarw.{circle over (2)}) can also be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0254] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0255] As described above, in the write principle of this embodiment, the magnetic field Hx in the hard-axis direction is weakened in three steps, and the magnetic field Hy in the easy-axis direction is strengthened in two steps. For this reason, no large write current need be abruptly supplied to or cut off from the write word/bit line to generate/extinguish the large magnetic fields Hx and Hy. That is, since the write current (the magnitude of the write current) supplied to the write word/bit line does not abruptly change, noise due to an inductance component can be reduced.
[0256] (8) Eighth Embodiment
[0257] In the write principle of this embodiment, a method of simultaneously generating/extinguishing a magnetic field Hx in the hard-axis direction and a magnetic field Hy in the easy-axis direction and also temporally changing both the intensities of the magnetic field Hx in the hard-axis direction and the magnetic field Hy in the easy-axis direction will be proposed.
[0258] The point of the method of this embodiment is that at the early stage of generation of the magnetic fields Hx and Hy, the magnetic field Hx in the hard-axis direction is set to a sufficiently large value while the magnetic field Hy in the easy-axis direction is set to a small value, then, the magnetic field Hx in the hard-axis direction is changed from the sufficiently large value to a large value while the magnetic field Hy in the easy-axis direction is changed to a large value, and then, the magnetic field Hx in the hard-axis direction is changed to a small value while the magnetic field Hy in the easy-axis direction is changed to a sufficiently large value.
[0259] That is, in the write principle of this embodiment, the magnetic field Hx in the hard-axis direction weakens in three steps, and the magnetic field Hy in the easy-axis direction strengthens in three steps.
[0260] More specifically, as shown in FIG. 27, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction is caused to act on the MTJ element. Simultaneously, the small magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is caused to act on the MTJ element. At this stage, since the MTJ element is largely influenced by the magnetic field Hx, the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction ({circle over (1)}).
[0261] Next, as shown in FIG. 28, the magnetic field Hx in the hard-axis direction is changed from the sufficiently large value to a large value (the magnetic field Hx is slightly weakened). Simultaneously, the magnetic field Hy in the easy-axis direction is changed to a large value. At this time, the magnetic fields Hx and Hy may have either the same intensity or different intensities ({circle over (2)}).
[0262] After that, as shown in FIG. 29, the magnetic field Hx in the hard-axis direction is changed to a sufficiently small value, and the magnetic field Hy in the easy-axis direction is changed from the large value to a sufficiently large value (the magnetic field Hy is further strengthened). Consequently, the magnetizing direction of the most of the storing layer of the TMR layer is aligned to the easy-axis direction by a synthesized magnetic field Hx+Hy ({circle over (3)}).
[0263] FIG. 30 simply shows the operation principle of the magnetic random access memory which implements the write principle of the eighth embodiment.
[0264] First, a write current Ip1 having a predetermined direction is supplied to a write word line. A write current Ip2 having a direction corresponding to write data is supplied to a write bit line. The write current Ip2 has a value much smaller than that of the write current Ip1. The magnetic field Hx in the hard-axis direction is generated by the write current Ip1 having the large value, and the magnetizing direction of the magnetic domain at the end portion of the storing layer of the TMR layer aligns to the hard-axis direction (step ST1).
[0265] Next, when a write current Ip3 (<Ip1) is supplied to the write word line, and a write current Ip4 (>Ip2) is supplied to the write bit line, the synthesized magnetic field Hx+Hy is generated by the write currents Tp3 and Ip4 (step ST2).
[0266] After that, when a write current Ip5 (<Ip3) is supplied to the write word line, and a write current Ip6 (>Ip4) is supplied to the write bit line, the synthesized magnetic field Hx+Hy is generated by the write currents Ip5 and Ip6. Consequently, the magnetizing direction of the most of the storing layer of the MTJ element is aligned to the easy-axis direction by the magnetic field Hy, and the magnetizing direction of the storing layer of the TMR layer is reversed (step ST3).
[0267] The change from the write-current Ip1 to the write current Ip3 and the change from the write current Ip3 to the write current Ip5 (change of the magnetic field Hx: {circle over (1)}.fwdarw.{circle over (2)}.fwdarw.{circle over (3)}) can be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0268] The change from the write current Ip2 to the write current Ip4 and the change from the write current Ip4 to the write current Ip6 (change of the magnetic field Hy: {circle over (1)}.fwdarw.{circle over (2)}.fwdarw.{circle over (3)}) can also be achieved by changing the intensity of the magnetic field in an analog or digital manner.
[0269] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0270] As described above, in the write principle of this embodiment, the magnetic field Hx in the hard-axis direction is weakened in three steps, and the magnetic field Hy in the easy-axis direction is strengthened in three steps. For this reason, no large write current need be abruptly supplied to or cut off from the write word/bit line to generate/extinguish the large magnetic fields Hx and Hy. That is, since the write current (the magnitude of the write current) supplied to the write word/bit line does not abruptly change, noise due to an inductance component can be reduced.
[0271] (9) Ninth Embodiment
[0272] In the write principle of this embodiment, a method of changing the direction and intensity of the synthesized magnetic field Hx+Hy in an analog manner will be proposed.
[0273] The point of the method of this embodiment is that a magnetic field Hx in the hard-axis direction is gradually decreased from a sufficiently large value in an analog manner, and a magnetic field Hy in the easy-axis direction is gradually increased to a sufficiently large value in an analog manner.
[0274] That is, in the write principle of this embodiment, the direction and intensity of the synthesized magnetic field Hx+Hy change in an analog manner.
[0275] More specifically, as shown in FIGS. 31 and 32, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction is caused to act on the MTJ element. While keeping the intensity of the magnetic field Hx at a predetermined level, the magnetic field Hy in the easy-axis direction is caused to act on the MTJ element. The magnetic field Hy gradually increases in an analog manner while the magnetic field Hx has a constant intensity (until time t) ({circle over (1)}).
[0276] At time t, the intensity of the synthesized magnetic field Hx+Hy is maximized. Since the value falls outside the asteroid curve, the magnetizing direction of the storing layer of the MTJ element is reversed.
[0277] After that, as shown in FIGS. 31 and 32, the magnetic field Hx is gradually decreased in an analog manner while keeping the intensity of the magnetic field Hy at a predetermined level ({circle over (2)}).
[0278] A data write is executed by such an analog change in synthesized magnetic field Hx+Hy.
[0279] FIG. 33 simply shows the operation principle of the magnetic random access memory which implements the write principle of the ninth embodiment.
[0280] First, a write current Ip1 having a predetermined direction is supplied to the write word line, and a write current Ip2 having a direction corresponding to write data is supplied to the write bit line. The write current Ip1 maintains a predetermined value. The value of the write current Ip2 gradually increases in an analog manner (step ST1).
[0281] Next, while keeping the value of the write current Ip2 at a predetermined level, the value of the write current Ip1 is gradually decreased in an analog manner (step ST2).
[0282] Since the direction and intensity of the synthesized magnetic field Hx+Hy change in an analog manner, the write can reliably be done.
[0283] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0284] (10) 10th Embodiment
[0285] In the write principle of this embodiment, a method of changing the direction and intensity of the synthesized magnetic field Hx+Hy in an analog manner will be proposed, as in the ninth embodiment.
[0286] The point of the method of this embodiment is that a magnetic field Hx in the hard-axis direction and a magnetic field Hy in the easy-axis direction are changed under a condition that substantially makes the synthesized magnetic field Hx+Hy have a predetermined magnitude, and the direction of the synthesized magnetic field Hx+Hy is changed in an analog manner.
[0287] More specifically, as shown in FIGS. 34 and 35, the magnetic field Hx having an intensity enough to align the magnetizing direction of the magnetic domain at the end portion of the storing layer of an MTJ element to the hard-axis direction is caused to act on the MTJ element. The intensity of the magnetic field Hx is gradually decreased in an analog manner. Simultaneously, the magnetic field Hy in the easy-axis direction, which has a direction corresponding to write data, is gradually increased in an analog manner ({circle over (1)}).
[0288] After that, as shown in FIGS. 34 and 35, the intensity of the magnetic field Hx is further gradually decreased in an analog manner. Simultaneously, the magnetic field Hy in the easy-axis direction is gradually increased in an analog manner ({circle over (2)}).
[0289] A data write is executed by such an analog change in synthesized magnetic field Hx+Hy.
[0290] FIG. 36 simply shows the operation principle of the magnetic random access memory which implements the write principle of the 10th embodiment.
[0291] First, a write current Ip1 having a predetermined direction is supplied to the write word line, and a write current Ip2 having a direction corresponding to write data is supplied to the write bit line. The value of the write current Ip1 is gradually decreased in an analog manner. Simultaneously, the value of the write current Ip2 is gradually increased (step ST1).
[0292] During the write operation, the values of the write current Ip1 and Ip2 may be changed such that, e.g., the intensity of the synthesized magnetic field x+H always substantially keeps a predetermined value. For example, the value of the write current Ip1 (magnetic field Hx) may be set such that it changes by .alpha..multidot.cos t with respect to time t, and the value of the write current Ip2 (magnetic field Hy) may be set such that it changes by .beta..multidot.sin t with respect to time t (.alpha. and .beta. are constants).
[0293] Since the direction of the synthesized magnetic field Hx+Hy changes in an analog manner, the write can reliably be done.
[0294] The circuit scheme to be used to execute this operation principle, i.e., the circuit which determines the timings to supply the write currents to the write word line and write bit line and the magnitudes (waveforms) of the write currents will be described later in detail.
[0295] (11) Others
[0296] The write principle described in each of the first to 10th embodiments is implemented by hardware in the magnetic random access memory (chip or block). A specific write principle may be set for each magnetic random access memory. Alternatively, the write principle and the supply/cutoff timings and magnitudes of the write currents may be set by programming.
[0297] When the write principle and the like are to be set by programming, for example, a laser blow fuse, an MTJ element (MTJ), or an antifuse which breaks the tunneling barrier of an MTJ element can be used as a programming element. The test mode of the magnetic random access memory may include a function of testing the write principle of the synthesized magnetic field.
[0298] A write current is supplied from a driver connected to one end of a write word/bit line and absorbed by a sinker connected to the other end. In cutting off the write current, when the driver function is stopped, and then, the sinker function is stopped after a predetermined time, the potential of the write word/bit line can be completely set to 0V.
[0299] The programming, test mode, and the operation stop timing of the driver/sinker will be described in detail in the following circuit scheme section.
[0300] 2. Circuit Scheme
[0301] Examples of the circuit scheme of a magnetic random access memory which implements the write principle according each of the above-described first to 10th embodiments will be described below.
[0302] (1) Setting for Each Chip or Cell Array
[0303] A circuit which sets the write principle or the supply/cutoff timings and magnitudes of the write currents for each chip or cell array of the magnetic random access memory will be described.
{circle over (1)} CIRCUIT EXAMPLE 1
[0304] Circuit Example 1 is related to a magnetic random access memory which has a function capable of setting the supply/cutoff timing of a write current for a write word/bit line by programming.
[0305] i. Overall Arrangement
[0306] FIG. 37 shows the arrangement of main part of a magnetic random access memory according to Circuit Example 1.
[0307] A magnetic random access memory (MRAM) 11 may construct one memory chip by itself or one block in a chip having a specific function. A memory cell array (data cell) 12 has a function of actually storing data. A reference cell array 13 has a function of setting a criterion to be used to determine the value of read data in read operation.
[0308] A row decoder & driver (row decoder & write word line driver and row decoder & read word line driver) 14 is arranged at one of two X-direction ends of a cell array formed from the memory cell array 12 and reference cell array 13. A write word line sinker 15 is arranged at the other end.
[0309] The row decoder & driver 14 has a function of, e.g., selecting one of a plurality of write word lines on the basis of a row address signal and supplying a write current to the selected write word line in the write operation. The write word line sinker 15 has a function of, e.g., absorbing the write current supplied to the selected write word line in the write operation.
[0310] The row decoder & driver 14 has a function of, e.g., selecting one of a plurality of read word lines (the read word lines may be integrated with the write word lines) on the basis of a row address signal and supplying a read current to the selected read word line in the read operation. A sense amplifier 20 detects, e.g., the read current and determines read data.
[0311] A column decoder & write bit line driver/sinker 16A is arranged at one of two Y-direction ends of the memory cell array 12. A column decoder & write bit line driver/sinker (including a column transfer gate and column decoder) 17A is arranged at the other end.
[0312] The column decoders & write bit line drivers/sinkers 16A and 17A have a function of, e.g., selecting one of a plurality of write bit lines (or data lines) on the basis of a column address signal and supplying a write current having a direction corresponding to write data to the selected write bit line in the write operation. The column transfer gate and column decoder have a function of electrically connecting the data line selected by the column address signal to the sense amplifier 20 in the read operation.
[0313] A reference cell column decoder & write bit line driver/sinker 16B is arranged at one of two Y-direction ends of the reference cell array 13. A reference cell column decoder & write bit line driver/sinker (including a column transfer gate and column decoder)17B is arranged at the other end.
[0314] The reference cell column decoders & write bit line drivers/sinkers 16B and 17B have a function of storing reference data in the reference cell array 13. The column transfer gate and column decoder have a function of reading out the reference data and transferring it to the sense amplifier 20 in the read operation.
[0315] An address receiver 18 receives an address signal and transfers, e.g., a row address signal to the row decoder & driver 14 and a column address signal to the column decoders & write bit line drivers/sinkers 16A and 17A. A data input receiver 19 transfers the write data to the column decoders & write bit line drivers/sinkers 16A and 17A. An output driver 21 outputs the read data detected by the sense amplifier 20 from the magnetic random access memory 11.
[0316] A control circuit 22 receives a /CE (Chip Enable) signal, /WE (Write Enable) signal, and /OE (Output Enable) signal and controls the operation of the magnetic random access memory 11. For example, in the write operation, the control circuit 22 supplies a write signal WRITE to a write current waveform control circuit 24. Upon receiving the write signal WRITE, the write current waveform control circuit 24 determines the supply/cutoff timings and magnitudes (current waveforms) of write currents on the basis of, e.g., setting data that is programmed in a setting circuit 23 in advance.
[0317] More specifically, in the write operation, the write current waveform control circuit 24 supplies a write word line drive signal WWLDRV to the row decoder & driver 14, a write word line sink signal WWLSNK to the write word line sinker 15, and a write bit line drive signal WBLDRV and write bit line sink signal WBLSNK to the column decoders & write bit line drivers/sinkers 16A and 17A.
[0318] In the write operation, for example, the row decoder & driver 14 is set in the operative state when the write word line drive signal WWLDRV is "H". Similarly, the write word line sinker 15 and the column decoders & write bit line drivers/sinkers 16A and 17A are set in the operative state, respectively, when the write word line sink signal WWLSNK, write bit line drive signal WBLDRV, and write bit line sink signal WBLSNK are "H".
[0319] With this arrangement, when the timings to change the write word line drive signal WWLDRV, write word line sink signal WWLSNK, write bit line drive signal WBLDRV, and write bit line sink signal WBLSNK to "H" are controlled by the write current waveform control circuit 24, the supply/cutoff timings of the write currents (application timings of the magnetic fields Hx and Hy) can be determined, and the write principles of the first to 10th embodiments can be implemented.
[0320] As for the absorption timings of the write currents, for example, when the timings to change the sink signals WWLSNK and WBLSNK from "H" to "L" are set after the timings to change the drive signals WWLDRV and WBLDRV from "H" to "L", the potential of the write word/bit line can be completely set to 0V.
[0321] The timings to change the signals WWLDRV, WWLSNK, WBLDRV, and WBLSNK to "H" are determined on the basis of setting data programmed in the setting circuit 23 in advance. For example, a laser blow fuse, an MTJ element (MTJ), or an antifuse which breaks the tunneling barrier of an MTJ element can be used as a programming element.
[0322] In the test mode of the magnetic random access memory, the supply/cutoff timings and magnitudes (current waveforms) of write currents can be determined on the basis of, e.g., setting data input from a data input/output terminal. The setting data may be input from an address terminal.
[0323] Circuit Example 1 of the magnetic random access memory has its characteristic feature mainly in the setting circuit 23 and write current waveform control circuit 24.
[0324] Circuit examples of the setting circuit 23, write current waveform control circuit 24, and drivers/sinkers 14, 15, 16A, and 17A which receive output signals from the write current waveform control circuit 24
will be described below.
[0325] ii. Row Decoder & Write Word Line Driver/Sinker
[0326] FIG. 38 shows a circuit example of the row decoder & write word line driver/sinker.
[0327] The row decoder & write word line driver (for one row) 14 is formed from a NAND gate circuit TND1 and PMOS transistor TP1. The gate of the PMOS transistor TP1 is connected to the output terminal of the NAND gate circuit TND1, the source is connected to a power supply terminal VDD, and the drain is connected to one end of a write word line WWLi (i=1, . . . .)
[0328] The write word line sinker (for one row) 15 is formed from an NMOS transistor TN1. The source of the NMOS transistor TN1 is connected to a ground terminal VSS, and the drain is connected to the other end of the write word line WWLi (i=1, . . . .)
[0329] A row address signal (changes for each row i) formed from a plurality of bits and write word line drive signal WWLDRV are input to the NAND gate circuit TND1. The write word line sink signal WWLSNK is input to the gate of the NMOS transistor TN1.
[0330] In the selected row i, all bits of the row address signal change to "H". For this reason, in the selected row i, when the write word line drive signal WWLDRV changes to "H", the PMOS transistor TP1 is turned on. When the write word line sink signal WWLSNK changes to "H", the NMOS transistor TN1 is turned on.
[0331] When both the PMOS transistor TP1 and the NMOS transistor TN1 are turned on, the write current flows from the row decoder & write word line driver 14 to the write word line sinker 15 through the write word line WWLi.
[0332] According to this row decoder & write word line driver/sinker, when the timings to change the write word line drive signal WWLDRV and write word line sink signal WWLSNK to "H" or "L" are controlled, the timing to supply the write current to the write word line WWLi in the selected row i and the timing to cut off the write current flowing to the write word line WWLi can be controlled.
[0333] When the write word line drive signal WWLDR