Home
Patent Search
IMT Blog
REGISTER
|
SIGN IN
United States Patent Application
20030217346
Kind Code
A1
Teig, Steven ; et al.
November 20, 2003
Method and Apparatus for Quantifying the Quality of Placement Configurations in a Partitioned Region of an Integrated Circuit Layout
Abstract
One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.
Inventors:
Teig; Steven
(Menlo Park, CA)
, Ganley; Joseph L.
(Vienna, VA
)
Correspondence Name and Address:
P O BOX 51860
STATTLER JOHANSEN & ADELI
PALO ALTO
CA
94303
Series Code:
742171
Filed:
December 19, 2000
U.S. Current Class:
716/7
U.S. Class at Publication:
716/7
Intern'l Class:
G06F 009/45;
G06F 017/50
Claims
We claim:
1. For an electronic design automation application, a partitioning method of placing circuit modules in a region of an integrated circuit ("IC") layout, wherein said IC layout includes nets and a plurality of circuit elements, each net representing interconnections between a set of circuit elements in the IC layout, the method comprising: a) defining a plurality of partitioning lines that divide the IC region into several sub-regions; b) identifying the set of sub-regions containing the circuit elements of a net, said set of sub-regions representing the net's configuration with respect to the defined partitioning lines; wherein a connection graph models the net's configuration with respect to the defined partitioning lines; said connection graph having an edge that is completely or partially diagonal; and c) identifying an attribute of the connection graph.
2. The method of claim 1, wherein the connection graph provides a topology of interconnect lines that connect the sub-regions that contain the net's circuit elements.
3. The method of claim 1, wherein said attribute is the length of the connection graph.
4. The method of claim 1, wherein said attribute is the number of bends in the connection graph.
5. The method of claim 1, wherein said attribute is information about the connection graph intersecting the partitioning lines.
6. The method of claim 1 further comprising identifying a second attribute of the connection graph.
7. The method of claim 1 wherein identifying the attribute comprises: a) constructing the connection graph after identifying the set of sub-regions containing the net's circuit elements; b) measuring the attribute of the constructed connection graph.
8. The method of claim 1 wherein a data structure stores attributes of all connection graphs that model all potential net configurations with respect to the partitioning lines, wherein identifying the attribute of the connection graphs comprises retrieving said attribute from the data structure.
9. The method of claim 8 wherein retrieving said attribute comprises retrieving the attribute by using the identified set of sub-regions.
10. The method of claim 1 further comprising calculating the cost of a placement layout within the region from the identified connection-graph attribute.
11. The method of claim 1 further comprising: a) changing the position of a circuit element of the net from one sub-region to another; b) identify a new set of sub-regions that contain the circuit elements of the net, said new set of sub-regions representing the net's new configuration with respect to the defined partitioning lines; wherein a new connection graph models the net's configuration with respect to the defined partitioning lines; said new connection graph having an edge that is completely or partially diagonal; c) identifying an attribute of the new connection graph.
12. The method of claim further comprising: a) for each particular net that has a circuit element in said region, identifying the set of sub-regions containing the circuit elements of the particular net, said set of sub-regions representing the particular net's configuration with respect to the defined partitioning lines; wherein a connection graph models the particular net's configuration with respect to the defined partitioning lines; identifying an attribute of the connection graph; wherein some of the connection graphs have an edge that is completely or partially diagonal; b) calculating a cost of an initial placement configuration within the region by using the identified attributes.
13. The method of claim 12 further comprising modifying the placement configuration in the IC regions to optimize the placement cost.
14. The method of claim 13 further comprising: a) after optimizing the placement configuration within the region, defining a second plurality of partitioning lines that divide one of said sub-regions into smaller sub-regions; b) for each particular net that has a circuit element in said divided sub-region, identifying the set of smaller sub-regions containing the circuit elements of the particular net, said set of smaller sub-regions representing the particular net's configuration with respect to the second partitioning lines; wherein a connection graph models the particular net's configuration with respect to the second partitioning lines; identifying an attribute of the connection graph; wherein some of the connection graphs have an edge that is completely or partially diagonal; b) calculating a cost of an initial placement configuration within the divided sub-region by using the identified attributes.
15. The method of claim 1, wherein the region is the entire IC layout.
16. The method of claim 1, wherein the region is a portion of the IC layout.
17. The method of claim 1, wherein the partitioning lines are intersecting lines that define a partitioning grid.
18. The method of claim 1, wherein the intersecting partitioning lines are N horizontal and M vertical lines that divide the IC region into (N+1)(M+1) sub-regions, where N and M can equal any integer.
19. For an electronic design automation ("EDA") application that performs a placement process, a method of pre-computing costs of placements of circuit modules in regions of integrated circuit ("IC") layouts, the method comprising: a) defining a partitioning grid with N number of slots, said partitioning grid for partitioning a region of an IC layout into N sub-regions during the placement process of the EDA application; b) for each particular grouping of slots of said grid, constructing a connection graph that models the topology of interconnect lines needed to connect said particular group of slots; c) computing an attribute of each of the constructed connection graphs; d) storing said attribute in a data structure.
20. The method of claim 19 wherein computing an attribute of each connection graph comprises calculating the length of each graph.
21. The method of claim 19 wherein computing an attribute of each connection graph comprises calculating a bend-value of each graph.
22. The method of claim 21 wherein the bend-value of a graph specifies the number of diagonal bends of the graph.
23. The method of claim 19 further comprising defining a plurality of wiring paths within said grid, wherein computing an attribute of each connection graph comprises identifying the wiring paths used by each graph.
24. The method of claim 19 further comprising defining a plurality of edges within said grid, wherein computing an attribute of each connection graph comprises identifying the edges intersected by each graph.
25. The method of claim 19 further comprising computing a second attribute of each of the constructed connection graphs;
26. The method of claim 19 wherein said constructed connection graphs are constructed based on a first wiring model, the method further comprising: a) for each particular grouping of slots of said grid, constructing, based on a second wiring model, a connection graph that models the topology of interconnect lines needed to connect said particular group of slots; b) computing an attribute of each of the connection graphs that are constructed based on the second wiring model; and c) storing said attribute in a data structure.
27. The method of claim 26 wherein the first wiring model is the octagonal wiring model, and the second wiring model is the hexagonal wiring model.
Description
BACKGROUND OF THE INVENTION
[0001] An integrated circuit ("IC") is a semiconductor device that includes many electronic components (e.g., transistors, resistors, diodes, etc.). These components are often interconnected to form multiple circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC. The electronic and circuit components of IC's are jointly referred to below as "components."
[0002] An IC also includes multiple layers of metal and/or polysilicon wiring (collectively referred to below as "metal layers") that interconnect its electronic and circuit components. For instance, many IC's are currently fabricated with five metal layers. In theory, the wiring on the metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-angle wiring is commonly referred to as Euclidean wiring. In practice, however, each metal layer typically has a preferred wiring direction, and the preferred direction alternates between successive metal layers. Many IC's use the Manhattan wiring model, which specifies alternating layers of preferred-direction horizontal and vertical wiring. In this wiring model, the majority of the wires can only make 90.degree. turns. However, occasional diagonal jogs are sometimes allowed on the preferred horizontal and vertical layers.
[0003] Design engineers design IC's by transforming circuit description of the IC's into geometric descriptions, called layouts. To create layouts, design engineers typically use electronic design automation ("EDA") applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts.
[0004] EDA applications create layouts by using geometric shapes that represent different materials and devices on IC's. For instance, EDA tools commonly use rectangular lines to represent the wire segments that interconnect the IC components. These tools also represent electronic and circuit IC components as geometric objects with varying shapes and sizes. For the sake of simplifying the discussion, these geometric objects are shown as rectangular blocks in this document.
[0005] Also, in this document, the phrase "circuit module" refers to the geometric representation of an electronic or circuit IC component by an EDA application. EDA applications typically illustrate circuit modules with pins on their sides. These pins connect to the interconnect lines.
[0006] A net is typically defined as a collection of pins that need to be electrically connected. A list of all or some of the nets in a layout is referred to as a net list. In other words, a net list specifies a group of nets, which, in turn, specify the interconnections between a set of pins.
[0007] FIG. 1 illustrates an example of an IC layout 100. This layout includes five circuit modules 105, 110, 115, 120, and 125 with pins 130-160. Four interconnect lines 165-180 connect these modules through their pins. In addition, three nets specify the interconnection between the pins. Specifically, pins 135, 145, and 160 define a three-pin net, while pins 130 and 155, and pins 140 and 150 respectively define two two-pin nets. As shown in FIG. 1, a circuit module (such as 105) can have multiple pins on multiple nets.
[0008] The IC design process entails various operations. Some of the physical-design operations that EDA applications commonly perform to obtain the IC layouts are: (1) circuit partitioning, which partitions a circuit if the circuit is too large for a single chip; (2) floor planning, which finds the alignment and relative orientation of the circuit modules; (3) placement, which determines more precisely the positions of the circuit modules; (4) routing, which completes the interconnects between the circuit modules; (5) compaction, which compresses the layout to decrease the total IC area; and (6) verification, which checks the layout to ensure that it meets design and functional requirements.
[0009] Placement is a key operation in the physical design cycle. It is the process of arranging the circuit modules on a layout, in order to achieve certain objectives, such as reducing layout area, wirelength, wire congestion, etc. A poor placement configuration not only can consume a large area, but it also can make routing difficult and result in poor performance.
[0010] Numerous EDA placers have been proposed to date. Certain placers are constrained-optimization placers, which (1) use cost-calculating functions to generate placement scores (i.e., placement costs) that quantify the quality of placement configurations, and (2) use optimization algorithms to modify iteratively the placement configurations to improve the placement scores generated by the cost-calculating functions.
[0011] A constrained-optimization placer typically receives (1) a list of circuit modules, (2) an initial placement configuration for these modules, and (3) a net list that specifies the interconnections between the modules. The initial placement configuration can be random (i.e., all the modules can be positioned randomly). Alternatively, the initial configuration can be partially or completely specified by a previous physical-design operation, such as the floor planning.
[0012] A constrained-optimization placer then uses a cost-calculating function to measure the quality of the initial placement configuration. The cost function generates a metric score that is indicative of the placement quality. Different cost-calculating functions measure different placement metrics. For instance, as further described below, some functions measure wirelength (e.g., measure each net's minimum spanning tree, Steiner tree, or bounding-box perimeter, etc.), while others measure congestion (e.g., measure number of nets intersected by cut lines).
[0013] After calculating the metric cost of the initial placement configuration, a constrained-optimization placer uses an optimization algorithm to modify iteratively the placement configuration to improve the placement score generated by its cost-calculating function. Different optimization techniques modify the placement configuration differently. For instance, at each iteration, some techniques move one circuit module, others swap two modules, and yet others move a number of related modules. Also, at each iteration, some optimization techniques (e.g., KLFM and tabu search algorithms) search for the best move, while others (e.g., simulated annealing and local optimization) select random moves. In addition, some techniques (e.g., simulated annealing) accept moves that make the metric score worse, whereas others (e.g., local optimization) do not.
[0014] Five types of constrained-optimization placement techniques are described below.
[0015] A. Min-Cut Bipartitioning
[0016] Some placers use min-cut bipartitioning. This technique uses horizontal and vertical cut lines to partition the IC layout recursively into successive pairs of regions. At each level of the recursion, this technique then moves the circuit modules between the regions at that level, in order to reduce the number of nets intersected by the cut line for that level. By minimizing the net-cut cost at each level of the recursion, these techniques reduce the wire congestion across the cut lines.
[0017] FIGS. 2 and 3 illustrate one example of min-cut bipartitioning. FIG. 2 illustrates an IC layout 200 that is partitioned initially in two regions 210 and 215 by a vertical cut line 205. After defining this initial cut line, the min-cut bipartitioning method calculates the number of nets that are intersected by this cut line. This number is indicative of the wire congestion about this cut line. An optimization algorithm (such as KLFM) is then used to modify the initial placement iteratively (i.e., to move the circuit modules iteratively), in order to minimize the net-cut cost across the initial cut line 205.
[0018] Once the congestion across the initial cut line is minimized, the min-cut bipartitioning method is applied recursively to the two regions created by the initial cut line, and then it is applied to the resulting regions created by the succeeding cut lines, and so on. FIG. 3
illustrates the IC layout 200 after it has been recursively partitioned by seven cut lines 205 and 220-245.
[0019] B. Semi-Perimeter Method
[0020] The semi-perimeter method is another cost-calculating function used by some constrained-optimization techniques. This method quickly generates an estimate of the wirelength cost of a placement. For each net, this method typically (1) finds the smallest bounding-box rectangle that encloses all the net's pins, and (2) computes half the perimeter of this bounding rectangle.
[0021] FIG. 4 illustrates a bounding box 400 for a net that contains pins 135, 145, and 160 of FIG. 1. The computed semi-perimeter value of this box 400 equals the sum of its width 405 and height 410. This computed semi-perimeter value provides a lower bound estimate on the amount of wire required to route a net.
[0022] The semi-perimeter method sums the semi-perimeter values of all the bounding rectangles of all the nets to obtain an estimated wirelength cost for a placement configuration. An optimization technique can then be used to modify iteratively the placement configuration to reduce this wirelength cost estimate, and thereby obtain an acceptable placement configuration.
[0023] C. Minimum Spanning Tree
[0024] To estimate the wirelength cost of placement configurations, some constrained-optimization placement techniques compute and add the length of the rectilinear minimum spanning tree ("RMST") for each net. A net's RMST is typically defined as a tree that connects (i.e., spans) the net's pins through the shortest Manhattan wiring route that only branches at the pin locations.
[0025] More specifically, the RMST for an N-pin net includes (1) N nodes (also called points or vertices) corresponding to the N pins, and (2) N-1
edges that connect its N nodes. In addition, the edges of the RMST are either horizontal or vertical, and these edges start and end at one of the N nodes of the tree. FIG. 5 illustrates a RMST 505 for the net that contains pins 135, 145, and 160 of FIG. 1.
[0026] The sum of the length of the RMST for each net provides an estimate of the wirelength cost of a placement. An optimization algorithm can then be used to modify iteratively the placement configuration to minimize this wirelength cost.
[0027] D. Steiner Tree
[0028] Rectilinear Steiner trees are another type of tree structure that constrained-optimization placement techniques generate to estimate the wirelength cost of placement configurations. Rectilinear Steiner trees are similar to RMST's except that Steiner trees do not restrict branching to only pin locations. In rectilinear Steiner trees, a horizontal or vertical edge can branch from a point on an edge that connects two other net pins.
[0029] To construct a Steiner tree for an N-pin net, additional points, called Steiner points, are typically added to the net. If R Steiner points are added to the net, the rectilinear Steiner tree for the N-pin net is the RMST on the N+R points. FIG. 6 illustrates a Steiner tree 605
for the net that contains pins 135, 145, and 160 of FIG. 1. In this example, the Steiner point that has been added is point 610.
[0030] Heuristic techniques are often used to select the R Steiner points and construct the Steiner tree, since these problems cannot be solved in polynomial time. A heuristic technique is a clever algorithm that only searches inside a subspace of the total search space for a good rather than the best solution that satisfies all design constraints.
[0031] Hence, to get an estimate of the wirelength cost of a placement, some constrained-optimization placement techniques use heuristic approximations to identify rectilinear Steiner trees for the nets. The sum of the length of the heuristic Steiner trees for all the nets provides an estimate of the wirelength cost of a placement. An optimization algorithm can then be used to modify iteratively the placement configuration to minimize this wirelength cost.
[0032] E. Recursive Grid Partitioning
[0033] Recursive grid partitioning is another technique for calculating the wirelength cost of placement configurations. A recursive-grid-partitioning placer typically uses sets of crossing horizontal and vertical lines to divide an IC layout recursively into several sub-regions. At each recursion level, the placer then uses an optimization algorithm to move the circuit modules between the sub-regions defined at that recursion level, in order to reduce the wirelength cost. After minimizing the wirelength cost at a particular recursion level, the placer recursively partitions that level's sub-regions that meet certain criteria, in order to optimize further the wirelength cost within those partitioned sub-regions.
[0034] FIGS. 7 and 8 illustrate two examples of this technique. In FIG. 7, an IC layout 700 is recursively divided into quadrisections (i.e., into four regions). Under this approach, minimum spanning trees are typically used to estimate the wirelength cost for connecting modules in different quadrisections.
[0035] FIG. 8 illustrates recursively dividing an IC layout 800 into nine regions. This style of partitioning is sometimes referred to as "sharp" partitioning. For this type of partitioning, Steiner trees are typically used to estimate the wirelength cost for connecting modules in different regions.
[0036] The above-described placement techniques do not consider diagonal wiring in calculating their placement-configuration cost. Hence, when diagonal routes are selected for the interconnect lines, these techniques result in poor placement configurations, which inefficiently consume the layout area, utilize too much wire, and/or have poor wire congestions. Consequently, there is a need in the art for placers that consider diagonal wiring in calculating their placement-configuration costs.
SUMMARY OF THE INVENTION
[0037] Some embodiments of the invention use a recursive partitioning method to place circuit elements in an IC layout. This method starts each time it receives the coordinates for a region of the IC layout. The received region can be the entire IC layout, or a portion of this layout. In some embodiments, this method also receives a net list that specifies all the net's that have circuit elements (e.g., have pins or circuit modules) in the received IC region. In other embodiments, the method receives a list of all the circuit elements (e.g., a list of all pins or circuit modules) in the received IC region, and from this list the method identifies the nets that have circuit elements in the received IC region.
[0038] This method initially defines a number of partitioning lines that divide the received IC region into several sub-regions (also called slots). In some embodiments, the partitioning lines are intersecting cut lines that define a partitioning grid. In some of these embodiments, the intersecting partitioning lines are N horizontal and M vertical lines that divide the received IC region into (N+1)(M+1) sub-regions, where N and M can equal any integer.
[0039] After defining the partitioning lines, the placement method identifies, for each received or identified net, the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for each net represents the net's configuration with respect to the defined partitioning lines.
[0040] Next, for each received or identified net, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.
[0041] Different embodiments identify different attributes of a net's connection graph. The attributes can include the length of the connection graph, the number of bends in the connection graph, the probability of the connection graph intersecting the partitioning lines, etc. Also, some embodiments might just identify one attribute (e.g., length) of each net's connection graph, while other embodiments might identify several attributes (e.g., length and number of bends) of each net's connection graph.
[0042] In some embodiments, the placement method identifies the attribute or attributes of each net's connection graph by constructing this connection graph in real-time and quantifying its attribute or attributes during or after the construction of the graph. However, other embodiments identify the attributes of the connection graphs in a different manner. Before the placement method starts, these embodiments (1) construct the connection graphs for each possible net configuration with respect to the partitioning lines, and (2) pre-tabulate the attributes of the connection graphs in memory. Some embodiments might pre-tabulate the multiple attributes of the connection graphs. Also, some embodiments might pre-tabulate attributes of connection graphs that are based on different wiring models. During placement, these pre-tabulating embodiments then retrieve, for each identified net configuration, the attribute or attributes of the connection graph associated with the identified net configuration from memory.
[0043] The placement method calculates the cost of the placement layout within the received region from the identified connection-graph attributes. For instance, when the identified attribute is the length of the graphs, some embodiments calculate the cost of a placement configuration within the received IC region, by combining (e.g., summing, multiplying, etc.) the length of the graphs, associated with the net configurations, within the received region. Alternatively, when the identified attributes are the length and bend-count of the graphs, some embodiments calculate the placement cost by generating a weighted sum of the length and bend-count.
[0044] Next, the placement method uses an optimization algorithm that iteratively modifies the placement configuration in the received IC regions, in order to improve the placement cost. Different embodiments of the invention use different optimization techniques, such as annealing, local optimization, KLFM, tabu search, etc.
[0045] After each iterative modification during optimization, the placement configuration is re-calculated by repeating the cost-calculating operations described above for all the nets or for just the nets on which the moved circuit element or elements reside. After optimizing the placement configuration within a received region, the placement method recursively performs the above-described partitioning and optimization operations on each sub-region defined that meets one or more criteria. For instance, some embodiments recursively perform the partitioning and optimization operations on each sub-region that contains more than a specified number of circuit elements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0046] The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.
[0047] FIG. 1 illustrates an example of an IC layout.
[0048] FIG. 2 illustrates an IC layout that is partitioned initially in two regions by a vertical cut line.
[0049] FIG. 3 illustrates the IC layout of FIG. 2 after it has been recursively partitioned by seven cut lines.
[0050] FIG. 4 illustrates a bounding box for a net that contains pins 135, 145, and 160 of FIG. 1.
[0051] FIG. 5 illustrates a RMST for the net that contains pins 135, 145, and 160 of FIG. 1.
[0052] FIG. 6 illustrates a Steiner tree for the net that contains pins 135, 145, and 160 of FIG. 1.
[0053] FIG. 7 illustrates an IC layout that is recursively divided into quadrisections.
[0054] FIG. 8 illustrates an IC layout that is recursively divided into nine regions.
[0055] FIG. 9 illustrates the wiring architecture of an IC layout that not only uses diagonal lines, but also uses horizontal and vertical lines.
[0056] FIG. 10 illustrates one manner of implementing the wiring architecture illustrated in FIG. 9.
[0057] FIG. 11 presents a process that conceptually illustrates the operational flow of a placer that utilizes the recursive grid partitioning technique of some embodiments of the invention.
[0058] FIG. 12 illustrates an IC layout that has been divided into sixteen sub-regions by sets of three horizontal and vertical partitioning lines.
[0059] FIGS. 13-15 illustrate three optimal Steiner trees for a net illustrated in FIG. 12.
[0060] FIG. 16 presents an example of a bounding-box for two nodes two nodes of a connection graph.
[0061] FIG. 17 illustrates a process that (1) identifies a bounding box for two nodes of a connection tree, and (2) computes the shortest distance between the two nodes.
[0062] FIG. 18 illustrates a process that constructs Steiner trees for each possible net configuration with respect to a partitioning grid, and stores the length and bend-count of each constructed Steiner tree in a data structure.
[0063] FIG. 19 pictorially illustrates sixteen Steiner-tree nodes for sixteen slots created by a 4-by-4 partitioning grid.
[0064] FIG. 20 illustrates one possible node configuration.
[0065] FIG. 21 illustrates the process for selecting potential Steiner nodes.
[0066] FIG. 22 illustrates a process used construct minimum spanning trees.
[0067] FIG. 23 illustrates an example of a MST that has horizontal, vertical, and diagonal edges.
[0068] FIG. 24 illustrates 42 edges defined in a 4.times.4 grid.
[0069] FIG. 25 illustrates 42 directed-wiring paths across the 42 edges of FIG. 24.
[0070] FIG. 26 illustrates path-usage counts for the trees illustrated in FIGS. 13-15.
[0071] FIG. 27 illustrates path-usage probabilities for the trees illustrated in FIGS. 13-15.
[0072] FIG. 28 illustrates edge-intersect counts for the trees illustrated in FIGS. 13-15.
[0073] FIG. 29 illustrates edge-intersect probabilities for the trees illustrated in FIGS. 13-15.
[0074] FIG. 30 illustrates a process that constructs one or more optimal Steiner trees for each possible net configuration with respect to a partitioning grid, and computes and stores path count and probability information.
[0075] FIG. 31 illustrates a process for calculating the count and path-usage probabilities resulting from the Steiner trees selected by the process of FIG. 30.
[0076] FIG. 32 illustrates a process that pre-tabulates the length, bend-count, and path-usage values of Steiner trees that model possible net configurations within a partitioning grid.
[0077] FIG. 33 illustrates a process that pre-tabulates one or more Steiner tree attributes for several different wiring models.
[0078] FIG. 34 illustrates the software architecture of a placer used in some embodiments of the invention.
[0079] FIG. 35 illustrates an IC layout that is recursively divided into sets of 16 sub-regions.
[0080] FIG. 36 illustrates the data structure for a net list.
[0081] FIG. 37 illustrates the data structure for a net.
[0082] FIG. 38 illustrates the data structure of a circuit module.
[0083] FIG. 39 presents a graph that illustrates the hierarchy of slots defined by the recursor.
[0084] FIG. 40 presents a data structure for a slot.
[0085] FIG. 41 illustrates a process performed by a recursor of FIG. 34.
[0086] FIG. 42 illustrates a process performed by an initializer of FIG. 34.
[0087] FIG. 43 illustrates a global path-usage data structure that stores the sum of all the path-usage values over all the nets.
[0088] FIG. 44 illustrates an IC layout that has been partitioned into sixteen slots.
[0089] FIG. 45 illustrates a process for generating propagated configuration codes.
[0090] FIG. 46 illustrates a process that generates total configuration codes.
[0091] FIG. 47 illustrates one example of a simulated annealing process.
[0092] FIG. 48 illustrates a process that a costs estimator performs.
[0093] FIG. 49 illustrates a process that a mover performs.
[0094] FIG. 50 illustrates a computer system used by some embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0095] The invention is directed towards recursive partitioning placement method and apparatus. In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.
[0096] Several embodiments of the invention's recursive partitioning technique are described below. However, before discussing these embodiments, several diagonal wiring architectures that can be used in conjunction with these embodiments are described in Section I.
[0097] I. Diagonal Wiring Architecture
[0098] Some embodiments of the invention calculate the cost of placement configurations for IC layouts that have diagonal interconnect lines (i.e., diagonal wiring). In some of these embodiments, the IC layouts not only have diagonal interconnect lines, but also have horizontal and vertical interconnect lines.
[0099] As used in this document, an interconnect line is "diagonal" if it forms an angle other than zero or ninety degrees with respect to the layout boundary. On the other hand, an interconnect line is "horizontal" or "vertical" if it forms an angle of 0.degree. or 90.degree. with respect to one of the sides of the layout.
[0100] FIG. 9 illustrates the wiring architecture (i.e., the interconnect-line architecture) of an IC layout 900 that utilizes horizontal, vertical, and 45.degree. diagonal interconnect lines. In this document, this architecture is referred to as the octagonal wiring model, in order to convey that an interconnect line can traverse in eight separate directions from any given point.
[0101] The horizontal lines 905 are the lines that are parallel (i.e., are at 0.degree.) to the x-axis, which is defined to be parallel to the width 910 of the layout. The vertical lines 915 are parallel to the y-axis, which is defined to be parallel to the height 920 of the layout. In other words, the vertical interconnect lines 915 are perpendicular (i.e., are at 90.degree.) to the width of the IC layout. In this architecture, one set 925 of diagonal lines are at +45.degree. with respect to the width of the IC layout, while another set 930 are at -45.degree. with respect to the width of the IC layout.
[0102] FIG. 10 illustrates one manner of implementing the wiring architecture illustrated in FIG. 9 on an IC. Specifically, FIG. 10
illustrates five metal layers for an IC. The first three layers 1005-1015
are Manhattan layers. In other words, the preferred direction for the wiring in these layers is either the horizontal direction or the vertical direction. The preferred wiring direction in the first three layers typically alternates so that no two consecutive layers have the same direction wiring. However, in some cases, the wiring in consecutive layers is in the same direction.
[0103] The next two layers 1020 and 1025 are diagonal layers. The preferred direction for the wiring in the diagonal layers is .+-.45.degree.. Also, as in the first three layers, the wiring directions in the fourth and fifth layer are typically orthogonal (i.e., one layer is +45.degree. and the other is -45.degree.), although they do not have to be.
[0104] Even though some embodiments of the invention are described below to work with IC layouts that utilize the above-described octagonal wiring model, one of ordinary skill will understand that the invention can be used with any wiring model. For instance, the invention can be used with wiring architectures that are strictly diagonal (i.e., that do not have horizontal and vertical preferred direction wiring).
[0105] Also, some embodiments are used with non -45.degree. diagonal wiring. For example, some embodiments are used with IC layouts that have horizontal, vertical, and .+-.120.degree. diagonal interconnect lines. In this document, such a wiring architecture is referred to as the hexagonal wiring model, in order to convey that an interconnect line can traverse in six separate directions from any given point.
[0106] II. Conceptual Flow
[0107] FIG. 11 conceptually illustrates the operational flow of a placement-process 1100 of some embodiments of the invention. This process starts each time it receives the coordinates for a region of the IC layout. The received region can be the entire IC layout, or a portion of this layout.
[0108] In some embodiments, this process also receives a net list that specifies all the net's that have circuit elements in the received IC region. In other embodiments, the process receives a list of all the circuit elements in the received IC region, and from this list identifies the nets that have circuit elements in the received IC region.
[0109] Each received or identified net has several circuit elements associated with it (i.e., each net is defined to include several circuit elements). In some embodiments, the circuit elements associated with the nets are the pins of the circuit modules in the IC layout. However, in the embodiments described below, the circuit elements are the circuit modules. Some of these embodiments treat the circuit modules as the net circuit elements and obviate the need to distinguish between the different pin locations, by assuming that the pins of each module are all located at uniform locations (e.g., located at the origin of the modules).
[0110] Also, in some embodiment, the locations of the circuit elements in the received IC region define a placement configuration within this region. In some embodiments, the initial circuit-element positions before the process 1100 starts are random. Alternatively, some embodiments use a previous physical-design operation, such as the floor planning, to partially or completely specify the initial positions of these elements. Still other embodiments use another placer to specify the initial positions of the circuit elements in the received IC region, and then use process 1100 to optimize the placement configuration for a wiring architecture that uses diagonal wiring.
[0111] As shown in FIG. 11, the process 1100 initially defines (at 1105) partitioning lines that divide the received IC region into several sub-regions (also called slots). In the embodiments described below, the partitioning lines are intersecting lines that define a partitioning grid. In some of these embodiments, the intersecting partitioning lines are N horizontal and M vertical lines that divide the received IC region into (N+1)(M+1) sub-regions, where N and M can equal any integer. For instance, these horizontal and vertical lines divide the received IC region into (1) four sections when N and M equal 1, (2) nine sections when N and M equal 2, (3) sixteen sections when N and M equal 3, or (4) twenty sections when either N or M equals 4 and the other equals 5.
[0112] FIG. 12 illustrates an IC layout 1200 that has been divided into sixteen sub-regions by sets of three horizontal and vertical partitioning lines. This figure also shows a net 1205 that includes five circuit modules 1210, 1215, 1220, 1225, and 1230, which fall into four of the sixteen sub-regions. These four sub-regions are slots 1, 2, 8, and 9.
[0113] After defining the partitioning grid at 1105, the process identifies (at 1110), for each received or identified net, the set of sub-regions (i.e., the set of slots) that contain the circuit modules of that net. The identified set of sub-regions for each net represents the net's configuration with respect to the defined grid.
[0114] For each received or identified net, the process next identifies (at 1115) attribute or attributes of a connection graph that models the net's configuration with respect to the grid. Specifically, for each net, the connection graph provides a topology of interconnect lines that connect the slots that contain the net's circuit modules.
[0115] To model each net's configuration with respect to the grid, each slot that contains one or more of the net's circuit modules is treated as a node (also called a vertex or point) of the connection graph. The nodes of the graph are then connected by edges (also called lines). According to some embodiments of the invention, the connection graph can have edges that are completely or partially diagonal.
[0116] At 1115, different embodiments identify different attributes of a net's connection graph. The attributes can include the length of the connection graph, the number of bends in the connection graph, the probability of the connection graph intersecting the partitioning lines, etc. Also, at 1115, some embodiments might just identify one attribute (e.g., length) of each net's connection graph, while other embodiments might identify several attributes (e.g., length and number of bends) of each net's connection graph.
[0117] For each net, some embodiments use a Steiner tree as the connection graph that connects the slots containing the net's circuit modules. FIGS. 13-15 illustrate three optimal Steiner trees 1305, 1405, and 1505 for the net 1205 in FIG. 12. These Steiner trees all have the same length. One of these trees (1305) has a Steiner node (1320). In addition, each of these trees has at least one edge that is partially diagonal. In these examples, the diagonal edges are at 45.degree. degrees with respect to the layout boundary. When the octagonal wiring model is used, the length of these Steiner trees is an approximation of the interconnect-line length necessary for net 1205 at the current partitioning grid level.
[0118] In some embodiments, the process identifies (at 1115) the attribute or attributes of each net's connection graph by constructing this connection graph in real-time and quantifying its attribute or attributes during or after the construction of the graph. However, the embodiments described below identify the attributes of the connection graphs in a different manner. Before the process 1100 starts, these embodiments (1) construct the connection graphs for each possible net configuration with respect to the partitioning grid, and (2) pre-tabulate the attributes of the connection graphs in memory. During placement, these pre-tabulating embodiments then retrieve (at 1115) the attribute or attributes of the connection graph of each identified net configuration from memory.
[0119] Some embodiments might pre-tabulate multiple attributes of the connection graphs (such as length, number of bends, probabilities for intersecting partitioning lines, etc.). Also, some embodiments might pre-tabulate attributes of connection graphs that are based on different wiring models. Section III below explains several processes for pre-tabulating different attributes of Steiner trees for different wiring architectures.
[0120] At 1120, the process 1100 uses the attributes identified at 1115 to calculate the cost of the placement layout within the received region. For instance, when the process identifies the probabilities of the partitioning lines being cut, some embodiments compute a congestion cost estimate based on these probabilities. Alternatively, when the identified attribute is the length of the graphs, some embodiments calculate the cost of a placement configuration within the received IC region, by combining (e.g., summing, multiplying, etc.) the length of the graphs associated with the net configurations within the received region.
[0121] Some embodiments calculate the placement cost based on more than one type of attribute for each connection graph. For instance, some embodiments calculate the placement cost of the graphs by combining (e.g., generating a weighted sum of) the length and bend-count of the graphs. Other embodiments might combine these two attributes of a net's connection graph by using as the net's cost the length of the shortest connection graph that has less than a maximum bend count; if all the connection graphs have more than the maximum bend count, some of these embodiments use as the net's cost the length of the shortest connection graph that has less than an incremented maximum bend count.
[0122] Next, at 1125, the process uses an optimization algorithm that iteratively modifies the placement configuration in the received IC regions, in order to improve the placement cost. Different embodiments of the invention use different optimization techniques, such as annealing, local optimization, KLFM, tabu search, etc. Also, different optimization techniques modify the placement configuration differently. For instance, at each iteration, some techniques move one circuit module, others swap two modules, and yet others move several related modules, between the sub-regions defined at 1105. Also, at each iteration, some optimization techniques (e.g., KLFM and tabu search algorithms) search for the best move, while others (e.g., simulated annealing and local optimization) select random moves. In addition, some techniques (e.g., simulated annealing) accept moves that make the metric score worse, whereas others (e.g., local optimization) do not.
[0123] After each iterative modification during optimization, the placement configuration is re-calculated by repeating the cost-calculating operations 1110-1120 for all the nets or for just the nets on which the moved circuit module or modules reside. After optimizing the placement configuration at 1125, the process 1100
recursively performs the partitioning and optimization operations 1105-1125 on each sub-region defined at 1105 that meets one or more criteria. For instance, some embodiments recursively perform the partitioning and optimization operations on each sub-region that contains more than a specified number of circuit modules.
[0124] Some embodiments use different shaped partitioning grids for different levels in the recursion process. Other embodiments use same shaped partitioning grids for all the recursion levels. At each recursion level, these embodiments simply adjust the coordinates of the partitioning grid to match the coordinates of the IC region at that recursion level. Using the same shaped partitioning grids for all the recursion levels has several advantages. For instance, it allows the pre-tabulating embodiments to store only net configuration attributes for one partitioning grid; these attributes can be re-used at all the recursion levels because they can be used to define the relative costs of the net configurations at any one level.
[0125] III. Pre-Tabulating Attributes of Steiner Trees
[0126] FIGS. 16-33 illustrate one manner of pre-tabulating attributes of Steiner trees that model possible net configurations with respect to a partitioning grid.
[0127] A. Pre-Tabulating Length and/or Bend Count
[0128] 1. Calculating the Length of an Interconnect Line Connecting Two Nodes of a Connection Graph, and Detecting a Bend in this Line
[0129] FIGS. 16 and 17 illustrate how some embodiments (1) calculate the length of an interconnect line connecting two nodes of a connection graph, and (2) detect whether this line has a diagonal bend. These embodiments perform these operations by treating the two nodes as opposing corners of a bounding box that has a long side (L) and a short side (S).
[0130] FIG. 16 presents an example of a bounding-box 1605 for two nodes 1635 and 1640. As shown in this figure, the line 1610 traverses the shortest distance between nodes 1635 and 1640 for IC layouts that utilize horizontal, vertical, and diagonal interconnect lines. This line is partially diagonal. Specifically, in this example, one segment 1620 of this line is diagonal, while another segment 1615 is horizontal.
[0131] Equation (A) below provides the distance traversed by line 1610
(i.e., the minimum distance between the nodes 1635 and 1640).
Distance=[L-{S(cos A/sin A)}]+S/sin A (A)
[0132] In this equation, "L" is the box's long side, which in this example is the box's width 1625 along the x-axis, while "S" is the box's short side, which in this example is its height 1630 along the y-axis. Also, in this equation, "A" is the angle that the diagonal segment 1620 makes with respect to the long side of the bounding box.
[0133] In some embodiments, this angle A corresponds to the direction of some of the diagonal interconnect lines in the IC layout. For instance, in some embodiments, the angle A equals 45.degree. when the IC layout uses the octagonal wiring model. In this manner, the diagonal cut 1620
across the bounding box represents a potential diagonal interconnect line that forms the connection between the two nodes.
[0134] Equations (B)-(D) below illustrate how Equation (A) is derived. The length of the line 1610 equals the sum of the lengths of its two segments 1615 and 1620. Equation (B) provides the length of the horizontal segment 1615, while Equation (C) provides the length of the diagonal segment 1620.
Length of 1615=L-(Length of 1620)*(cos A) (B)
Length of 1620=S/sin A (C)
[0135] Equations (B) and (C) can be combined to obtain Equation (D) below, which when simplified provides Equation (A) above. 1 Distance = Length of 1615 + Length of 1620 = L - S / sin A * ( cos A ) + S / sin A ( D )
[0136] When the angle A equals 45.degree., Equation (A) simplifies to Equation (E) below.
Distance=L+S*(sqrt(2)-1) (E)
[0137] When the bounding box has no width or height, then the bounding box is just a line, and the minimum distance between the opposing corners of this line is provided by the box's long (and only) side, which will be a horizontal or vertical line. When the bounding box has equal sized height and width (i.e., when it is a square) and the angle A is 45.degree., a line that is completely diagonal specifies the shortest distance between the box's two opposing corners. When the bounding box has different sized height and width (i.e., when it is a rectangle) and the angle A is 45.degree., a line that has a diagonal bend (i.e., a line that has a diagonal component and a vertical or horizontal component) provides the minimum distance between the opposing corners of this bounding box.
[0138] When the angle A corresponds to the direction of some of the diagonal interconnect lines in the IC layout, the minimum distance computed by Equation (A) is an approximation of the shortest length of wiring required to connect two hypothetical modules or pins represented by the nodes 1635 and 1640. This distance might be shorter than the actual wiring path necessary for connecting the two nodes, as it may not be possible to route the net along line 1610. The distance value computed by Equation (A) simply provides a lower-bound estimate on the interconnect-line length required to connect the two nodes in a wiring architecture that utilizes horizontal, vertical, and diagonal wiring. Some embodiments also use this equation for other arbitrary wiring models. However, some of these embodiments select the angle A among several choices so that the distance quantified by this equation is minimized.
[0139] FIG. 17 illustrates a process 1700 that (1) identifies a bounding box for two nodes of a connection tree, (2) calculates the length of an interconnect line connecting the two nodes based on the bounding box's dimensions and Equation (A), and (3) detects whether the interconnect line has a diagonal bend.
[0140] This process initially (at 1705) determines whether the x-coordinate (X.sub.1) of the first node is greater than the x-coordinate (X.sub.2) of the second node. If so, the process defines (at 1710) the x-coordinate (X.sub.1) of the first node as the maximum x-coordinate (X.sub.Max), and the x-coordinate (X.sub.2) of the second node as the minimum x-coordinate (X.sub.Min). Otherwise, the process defines (at 1715) the x-coordinate (X.sub.2) of the second node as the maximum x-coordinate (X.sub.Max), and the x-coordinate (X.sub.1) of the first node as the minimum x-coordinate (X.sub.Min).
[0141] Next, the process determines (at 1720) whether the y-coordinate (Y.sub.1) of the first node is greater than the y-coordinate (Y.sub.2) of the second node. If so, the process defines (at 1725) the y-coordinate (Y.sub.1) of the first node as the maximum y-coordinate (Y.sub.Max), and the y-coordinate (Y.sub.2) of the second node as the minimum y-coordinate (Y.sub.Min). Otherwise, the process defines (at 1730) the y-coordinate (Y.sub.2) of the second node as the maximum y-coordinate (Y.sub.Max), and the y-coordinate (Y.sub.1) of the first node as the minimum y-coordinate (Y.sub.Min).
[0142] The process then defines (at 1735) the four coordinates of the bounding box as (X.sub.MIN, Y.sub.MIN), (X.sub.MIN, Y.sub.MAX), (X.sub.MAX, Y.sub.MIN), and (X.sub.MAX, Y.sub.MAX). Next, the process determines (at 1740) the bounding-box's width and height. The process determines (1) the width by taken the difference between the box's maximum and minimum x-coordinates, and (2) the height by taking the difference between the box's maximum and minimum y-coordinates. The process then determines (at 1745) whether the computed width is greater than the computed height. If so, the process defines (1750) the width as the long side and the height as the short side. Otherwise, the process defines (at 1755) the width as the short side and the height as the long side.
[0143] After 1750 or 1755, the process then uses (at 1760) the above-described Equation (A) to compute the length of the shortest interconnect line that connects the two nodes. The process then determines whether the interconnect line has a diagonal bend. Even though the process 1700 only counts the diagonal bends, other embodiments count other types of bends (e.g., 90.degree. bends from horizontal to vertical lines), especially when non-octagonal wiring architectures are used.
[0144] To determine whether the interconnect line has a diagonal bend, the process 1700 initially determines (at 1765) whether the long or short side of the computed bounding box equals zero. If so, the interconnect line is a vertical or horizontal line that does not have a diagonal bend, and thereby the process sets (at 1770) the bend value of this line to zero.
[0145] Otherwise, the process determines (at 1775) whether the interconnect line is purely diagonal. When the angle A in Equation (A) is defined to be 45.degree. or less, the process determines whether the interconnect line is purely diagonal by ascertaining whether the arctan of the bounding box's short side divided by its long side equals the angle A. When the angle A in Equation (A) is defined to be more than 45.degree., the process determines whether the interconnect line is purely diagonal by ascertaining whether the arctan of the bounding box's long side divided by its short side equals the angle A.
[0146] If the process determines that the interconnect line is purely diagonal, then the process sets (at 1770) the bend value of this line to zero as this line has no diagonal bend. Otherwise, the interconnect line has a diagonal bend (i.e., it has a diagonal segment and a vertical or horizontal segment), and therefore the process sets (at 1780) the bend value of this line to 1. After 1770 or 1780, the process ends.
[0147] 2. Constructing Steiner Trees for all Possible Net Configurations and Pre-Tabulating Length and/or Bend Count for Each Tree
[0148] FIG. 18 illustrates a process 1800 that (1) constructs Steiner trees for each possible net configuration with respect to a partitioning grid, and (2) stores the length and/or diagonal bend-count of each constructed Steiner tree in a look-up table ("LUT"). This process is performed before the placement process 1100 of FIG. 11, so that the placement process in real-time does not have to construct and measure the length and/or bend-count of the Steiner tree for each net configuration. Instead, after process 1800 pre-tabulates the length and/or bend-count of the Steiner trees that model all possible the net configurations, the placement process 1100 needs only to (1) identify the configuration of each net with respect to the partitioning grid, (2) retrieve stored attributes for the identified-configurations, and (3) calculate the placement cost based on these retrieved attributes.
[0149] As shown in FIG. 18, process 1800 initially starts (at 1805) by defining a Steiner-tree node for each sub-region (also called slot) defined by a particular partitioning grid. FIG. 19 pictorially illustrates sixteen Steiner-tree nodes 1905 for sixteen slots created by a 4-by-4 partitioning grid. These nodes represent all the potential nodes of Steiner trees that model the interconnect topologies of all the net configurations. In FIG. 19, the identified nodes are positioned at the center of each slot. In other embodiments, the nodes can uniformly be defined at other locations in the slots (e.g., can be uniformly positioned at one of the corners of the slots).
[0150] Next, the process 1800 defines (at 1810) a set N of possible node configurations. When the grid partitioning defines Y (e.g., four, nine, sixteen, twenty, etc.) sub-regions, set N includes 2.sup.Y node configurations. After defining the set N of possible node configurations, the process 1800 select (at 1815) one of the possible node configurations N.sub.T from this set. FIG. 20 illustrates one possible configuration, which includes nodes 2010, 2015, 2020, and 2025. This node configuration coincides with the node configuration for the net 1205 illustrated in FIG. 12.
[0151] The process then constructs (at 1820) a minimum spanning tree ("MST") for the node configuration selected at 1815, and computes this tree's length (MST_Cost) and diagonal bend-count (Bend_Cost). The process constructs this minimum spanning tree by using edges that can be completely or partially diagonal. One manner of constructing such a MST and computing its length and bend-count will be described below by reference to FIG. 22.
[0152] After constructing the MST for the selected node configuration, the process 1800 identifies (at 1825) potential Steiner nodes. FIG. 21
illustrates a process 2100 for identifying potential Steiner nodes. This process starts (at 2105) by initializing a set P of potential Steiner nodes equal to all the nodes defined at 1805 that are not part of the node configuration selected at 1815. This process then selects (at 2110) one of the potential Steiner nodes.
[0153] Next, the process 2100 determines (at 2115) whether the node (Q) selected at 2110 is on a shortest path between any two nodes in the selected node configuration. To make this determination, the process determines whether any two nodes (B and C) exit in the node configuration such that the distance between the two nodes (B and C) equals the sum of (1) the distance between the first node (B) and the selected node (Q), and (2) the distance between the second node (C) and the selected node (Q). In some embodiments, the process uses the above-described process 1700 and Equation (A) to calculate the distance between any pair of nodes.
[0154] If the process determines that the node Q selected at 2110 lies on a shortest path between any two nodes in the node configuration, the process keeps (at 2120) the selected node in the set P of potential Steiner nodes, flags this node as a node that it has examined, and transitions to 2130, which is described below. On the other hand, if the selected node (Q) is not on the shortest path between any two nodes in the selected node configuration, the process removes (at 2125) the selected node from the set P of potential Steiner nodes, and transitions to 2130.
[0155] At 2130, the process determines whether it has examined all the nodes in the set of potential Steiner nodes. If not, the process returns to 2110 to select another node in this set so that it can determine at 2115 whether this node is on a shortest path between any two nodes in the selected node configuration. When the process determines (at 2130) that it has examined all the nodes in the set of potential Steiner nodes, it ends.
[0156] FIG. 20 pictorially illustrates the result of performing process 2100 for the node configuration 2005. Specifically, this figure illustrates several potential Steiner nodes 2050, and several non-Steiner nodes 2055. The process 2100 initially defines the set of potential Steiner nodes to include all the nodes 2050 and 2055 that are not in the node configuration 2005. The process then removes the nodes 2055 from this set as these nodes do not lie on the shortest path between any two nodes in the selected node configuration.
[0157] Once the process 1800 performs (at 1825) the process 2100 of FIG. 21 to identify potential Steiner nodes, the process 1800 defines (at 1830) all possible sets of Steiner nodes. Each defined set of Steiner nodes includes one or more of the Steiner nodes identified at 1825. Also, each defined set of Steiner nodes has a maximum size that is two nodes less than the number of nodes in the selected node configuration.
[0158] The process 1800 then selects (at 1835) one of the Steiner-node sets defined at 1830 . The process then (at 1840) (1) constructs a minimum spanning tree (MST) for the nodes in the selected node configuration and the selected Steiner-node set, and (2) computes and stores this MST's length (MST_Cost) and diagonal bend-count (Bend_Cost). The process constructs this MST by using edges that can be completely or partially diagonal. One manner of constructing such a MST and computing its length and bend-count will be described below by reference to FIG. 22.
[0159] Next, the process determines (at 1845) whether, in the Steiner node sets defined at 1830, there are any additional Steiner-node sets that it has not yet examined. If so, the process returns to 1835 to select another Steiner-node set, so that it can construct a MST for the nodes of this set and the nodes in the selected node configuration.
[0160] When the process determines (at 1845) that it has generated MST's of the selected node configuration and each Steiner-node set, the process uses (at 1850) a selection criterion to select one of the MST's generated at 1820 and 1840 as the Steiner tree for the current node configuration (i.e., the node configuration selected at 1815). In different embodiments, the process 1800 uses different selection criteria. For instance, in some embodiments, the process selects (at 1850) the MST with the smallest length (i.e., the MST with the smallest MST_Cost stored at 1820 and 1840 ).
[0161] In other embodiments, the process uses both the length and bend-count values to formulate a selection criterion or criteria. For instance, some embodiments select the shortest MST that has less than a maximum number of bends (e.g., the shortest MST that has less than two diagonal bends). If all the generated MST's have more than the maximum bend count, some of these embodiments select the shortest MST that has less than an incremented maximum bend count (e.g., the shortest MST that has less than three diagonal bends). Yet other embodiments combine each generated MST's length and bend-count (e.g., generate a weighted sum of the MST_Cost and the Bend_Cost) to obtain a combined score, based on which they select one of the MST's.
[0162] The process then stores (at 1855) in a storage structure (such as a LUT) the length (MST_Cost) and bend-count (Bend_Cost) of the Steiner tree identified at 1850. During the placement operation, a placer can then quickly identify the length and bend-count of the Steiner tree for the current node configuration by retrieving the stored length and bend-count from the storage structure.
[0163] The process next determines (at 1860) whether it has examined all the node configurations in the set N defined at 1810. If not, the process returns to 1815 to select unexamined node configuration from this set and then repeat operations 1820-55 to determine and store the Steiner length and bend-count for this node configuration. Otherwise, the process ends.
[0164] FIG. 22 illustrates a process 2200 that the process 1800 of FIG. 18
uses at 1820 and 1840 to construct minimum spanning trees. A minimum spanning tree for a node configuration is a tree that has N-1 edges that connect (i.e., span) the N nodes of the configuration through the shortest route, which only branches (i.e., starts or ends) at the nodes. The length of a MST for a net configuration provides a lower-bound estimate of the amount of wire needed to interconnect the nodes associated with the net configuration.
[0165] In some embodiments of the invention, the edges of the MST's can be horizontal, vertical, or diagonal. The diagonal edges can be completely or partially diagonal. Also, when the IC layouts use diagonal interconnect lines (e.g., .+-.120.degree. interconnect lines), the diagonal edges of the MST's can be in the same direction (e.g., can be in .+-.120.degree. direction) as some of the diagonal interconnect lines in the layout.
[0166] For instance, when the IC layout uses an octagonal wiring model (i.e., uses horizontal, vertical, and 45.degree. diagonal lines), some embodiments construct MST's that have horizontal, vertical, and 45.degree. diagonal edges. FIG. 23 illustrates an example of such a MST. This tree 2305 is the MST of the net that contains pins 135, 145, and 160
of FIG. 1. This tree has two edges 2310 and 2315. The first edge 2310 has a horizontal segment 2320 and a +45.degree. diagonal segment 2325, while the second edge 2315 has a vertical segment 2330 and a -45.degree. diagonal segment 2335.
[0167] By treating the two nodes of each edge of an MST as two opposing corners of a bounding box, the length of each edge can be obtained by using the above-described process 1700 and Equation (A).
Distance=[L-{S(cos A/sin A)}]+S/sin A (A)
[0168] As described above, in this equation, "L" is the box's long side, "S" is the box's short side, and "A" is the angle that the diagonal segment of the edge makes with respect to the long side of the bounding box.
[0169] The process 2200 starts whenever the process 1800 calls it (at 1820
or 1840 ) (1) to construct an MST for a set M of nodes, and (2) to calculate the length and bend-count of this MST. This process initially (at 2205) sets the MST length (MST_Cost) and bend count (Bend_Cost) to zero. Next, the process (at 2210) (1) selects a node from the received set M of nodes as the first node of the spanning tree, and (2) removes this node from this set M.
[0170] The process then defines (at 2215) a remainder set R of nodes equal to the current set M of nodes. At 2220, the process selects a node from the remaining node set R, and removes the selected node from the set of remaining nodes. The process then computes and stores (at 2225) the distance between the node selected at 2220 and each current node of the spanning tree. The distance between the selected node and each node can be traversed by an edge that is completely or partially diagonal. Hence, in some embodiments, the process uses the above-described process 1700
and Equation (A) to compute the minimum distance between the selected node and each node. As mentioned above, the process 1700 not only computes the length of the line that traverses this minimum distance, but also computes the bend value for this line.
[0171] Next, the process determines (at 2230) whether there is any node remaining in set R. If so, the process returns to 2220 to select another node from this set, so that it can compute (at 2225) the distance between this node and the current nodes of the spanning tree. Otherwise, the process (at 2235) identifies the smallest distance recorded at 2225, and identifies the node combination (i.e., the node in set M and the MST's node) that resulted in this distance. The process then (at 2240) (1) adds the identified smallest distance to the MST length (MST_Cost), and (2) increments the MST bend count (Bend_Cost) by the bend value of the line that traverses this distance.
[0172] The process next (at 2245) (1) defines a tree node corresponding to the node identified at 2235, (2) removes the identified node from the node set M, and (3) links the defined tree node to the MST node identified at 2235. The process then determines (at 2250) whether the node set M is empty. If not, the process transitions back to 2215 to identify the next node (in this set M) that is closest to the current nodes of the MST. Otherwise, the process determines that it has constructed the MST for the received set M of nodes, returns the computed MST length (MST_Cost) and bend count (Bend_Cost) for this set, and then ends.
[0173] B. Pre-Tabulating Information About Wiring Directions Used and Edges Intersected by Steiner Trees
[0174] The embodiments described above in Section III.A.2 pre-tabulate length and/or bend-count values of Steiner trees that model net configurations with respect to a partitioning grid. Other embodiments, however, pre-tabulate other attributes of these trees. For instance, some embodiments pre-tabulate information about the directed-wiring paths (also called directed routing or interconnect-line paths) that these trees use in the partitioning grid. As further described below, the stored wiring-path information can be used during placement to quantify wiring congestion (also called routing or interconnect-line congestion) of a particular placement configuration.
[0175] The number of directed-wiring paths in a partitioning grid depends on the wiring model and the number of partitioning lines in the grid. For instance, 42 directed-wiring paths exist when the octagonal wiring architecture is used in combination with a 4.times.4 grid. Specifically, the combination of the octagonal wiring architecture and the 4.times.4
grid results in 42 edges between the slots of the 4.times.4 grid. FIG. 24
illustrates these 42 edges (E1-E42). Orthogonal to each particular edge is a directed-wiring path that specifies the direction of the interconnect lines that connect the two slots abutting the particular edge. As there are 42 edges in a 4.times.4 grid that uses the octagonal wiring model, there are 42 directed-wiring paths in these circumstances. FIG. 25 illustrates the 42 directed-wiring paths (P1-P42) across the 42
edges (E1-E42) of FIG. 24.
[0176] The directed-wiring paths do not necessarily specify the actual routing paths used during routing. For instance, directed-wiring path P28
in FIG. 25 does not necessarily have to specify the one and only routing path between the fifth and sixth slots, as routing paths can traverse the entire length of edge E28. Instead, the directed-wiring paths only specify the direction of the interconnect lines that connect the two slots abutting the particular edge.
[0177] The wiring-path information for each net configuration can be stored as an N-bit string or in an N-entry data structure (e.g., N-entry array), where N is the number of wiring directions that result from a particular combination of partitioning grid and wiring model. For instance, in the example illustrated in FIG. 25, each net configuration's wiring-path information can be stored in a 42-bit string or 42-entry array.
[0178] Different embodiments store different directed-wiring path information. Some embodiments identify only one of routing pattern (e.g., one Steiner tree) for each net configuration. Hence, for each net configuration, these embodiments only store the identity of the directed-wiring paths used by the net configuration's selected routing pattern. For each net configuration, such an identify can be stored as an N-bit string, where each bit in this string corresponds to one of the directed-wiring paths and each particular bit is set when the identified routing pattern uses the directed-wiring path corresponding to the particular bit. For instance, if (1) the routing pattern 1305 of FIG. 13
is selected to connect the node configuration of net 1205 of FIG. 12 and (2) the numbering convention of FIG. 25 is used to number the possible directed-routing paths, the wiring-path information for the selected routing pattern 1305 is a 42-bit string that has its 17.sup.th, 31.sup.st, 32.sup.nd, 36.sup.th, and 40.sup.th bits set (e.g., set to 1) and all the other bits not set (e.g., equal to 0).
[0179] Other embodiments enumerate several routing patterns for each net configuration within the partitioning grid. For instance, some embodiments identify the optimal Steiner trees for each net configuration. It is advantageous to enumerate and store information about all the optimal routing patterns when the exact routing pattern for each net configuration is not selected during placement. In this manner, the placer can account for all the congestion that can potentially result from each net configuration.
[0180] The embodiments that identify several routing patterns for each net configuration can store different types of information about the directed-wiring paths used by these routing patterns. For instance, some of these embodiments count and store the number of times each directed-routing path in the grid is used by the identified optimal trees of each net configuration. For each net configuration, such count information can be stored in an N-entry data structure, where each entry stores the count information for one of the directed-wiring paths.
[0181] For example, as mentioned above, Steiner trees 1305, 1405, and 1505
of FIGS. 13-15 provide the optimal routing patterns for the node configuration of net 1205 of FIG. 12 when the octagonal wiring model is used. As illustrated in FIG. 26, these trees (1) use the directed-wiring paths 17, 31-33, 37, and 41 once, (2) use the directed-wiring paths 14, 27 and 36 twice, and (3) use the directed-wiring path 40 thrice. This count information can be stored in a 42-entry array, where each entry corresponds to one of the wiring paths. In this array, the entries for the 17.sup.th, 31.sup.st-33.sup.rd, 37.sup.th, and 41.sup.st paths are set to 1, the entries for the 14.sup.th, 27.sup.th, and 36.sup.th paths are set to two, the entries for the 40.sup.th path is set to 3, and the entries for all other paths are set to 0.
[0182] Other embodiments do not store the number of times each directed-routing path in the grid is used by the identified trees of each net configuration. For instance, some embodiments store the probability that the identified trees of a net configuration use each directed-routing path. For each directed-routing path, this probability can be obtained by dividing the number of times the identified trees use the directed-routing path by the total number of identified trees.
[0183] By way of example, FIG. 27 illustrates these probabilities for the directed-routing paths used by the Steiner trees 1305, 1405, and 1505 of FIGS. 13-15. These probabilities are obtained by dividing the count information (illustrated in FIG. 26) for these directed-routing paths by 3, which is the number of the identified routing trees. As illustrated in FIG. 27, these probabilities are (1) 0.33 for the directed-wiring paths 17, 31-33, 37, and 41, (2) 0.66 for the directed-wiring paths 14, 27 and 36, (3) 1 for the directed-wiring path 40, and (4) 0 for the remaining directed-wiring paths. This probability information can be stored in a 42-entry array, where each entry corresponds to one of the wiring paths. In this array, the entries for the 17.sup.th, 31.sup.st-33.sup.rd, 37.sup.th, and 41.sup.st paths are set to 0.33, the entries for the 14.sup.th, 27.sup.th, and 36.sup.th paths are set to 0.66, the entries for the 40.sup.th path is set to 1, and the entries for all other paths are set to 0.
[0184] During placement, the placer can calculate congestion cost estimates for different placement configurations by using the pre-tabulated wiring-path information. To calculate such a congestion cost, the placer for each net (1) identifies the net's configuration with respect to the partitioning grid, and then (2) retrieves the pre-tabulated wiring-path information, which includes one value for each wiring path in the grid.
[0185] The placer can generate different congestion cost estimates based on these retrieved values. For instance, in some embodiment, the placer calculates a congestion cost by (1) summing the retrieved values for each particular wiring path over all the nets, (2) squaring this sum, and (3) adding the squared sums of all the wiring paths.
[0186] Equation F illustrates this calculation mathematically. 2 Cost = Path ( nets F ( netconfig , path ) ) 2 ( F )
[0187] In this equation, F(netconfig, path) represents the retrieved value of a particular wiring path for a particular net configuration.
[0188] Other embodiments calculate a congestion cost by (1) summing the retrieved values for each particular wiring path over all the nets, and (2) selecting the maximum sum. Equation G illustrates this calculation mathematically. 3 Cost = max Path ( nets F ( netconfig , path ) ) ( G )
[0189] Yet other embodiments use other approaches to compute placement cost estimates based on the wiring-path values. For instance, instead of summing the retrieved values for each particular wiring path over all the nets, some embodiments might combine these values associated with each wiring path in a different manner (e.g., some might multiply the values associated with each wiring path).
[0190] The above-described embodiments pre-tabulate wiring-path information. Other embodiments, however, pre-tabulate edge-intersect information, instead of wiring-path information. Storing the edge-intersection information is analogous to storing the wiring-path information, since each wiring path is defined across a particular edge, as illustrated by FIGS. 24 and 25.
[0191] Some embodiments identify the edge-intersect information for a net configuration by (1) defining edges in the partitioning grid based on the grid and the wiring model, (2) specifying one or more connection graphs (such as Steiner trees) for each net configuration within the grid, and (3) identifying the edges that the specified graphs intersect.
[0192] As with the wiring-path information, different embodiments store different edge-intersect information. For instance, the embodiments that identify only one routing pattern (e.g., one Steiner tree) for each net configuration, can store for each net configuration the identity of the edges intersected by the net configuration's selected routing pattern. For each net configuration, such an identify can be stored as an N-bit string, where each bit in this string corresponds to one of the edges and each particular bit is set when the identified routing pattern intersects the edge corresponding to the particular bit. For instance, if (1) the routing pattern 1305 of FIG. 13 is selected to connect the node configuration of net 1205 of FIG. 12 and (2) the numbering convention of FIG. 24 is used to number the defined edges in the grid, the edge-intersect information for the selected routing pattern 1305 is a 42-bit string that has its 17.sup.th, 31.sup.st, 32.sup.nd, 36.sup.th, and 40.sup.th bits set (e.g., set to 1) and all the other bits not set (e.g., equal to 0).
[0193] On the other hand, some of the embodiments that enumerate several routing patterns for each net configuration, count and store the number of times each edge is used by the enumerated routing patterns of the net configuration. For each edge, other embodiments store the probability that the enumerated trees for the net configuration intersect the edge. This probability can be obtained by dividing the number of times the identified trees intersect the edge by the total number of identified trees.
[0194] FIGS. 28 and 29 respectively illustrate the count and probability information for the Steiner trees 1305, 1405, and 1505 of FIGS. 13-15
that provide routing patterns for the node configuration of net 1205 of FIG. 12. For each net configuration, the count or probability information can be stored in an N-entry data structure, where N corresponds to the number of edges and each entry stores the count or probability information for one of the edge. In the above-mentioned example, the count information for trees 1305, 1405, and 1505 can be stored in a 42-entry array, with the entries for the 17.sup.th, 31 .sup.st-33.sup.rd, 37.sup.th, and 41.sup.st edges set to 1, the entries for the 14.sup.th, 27.sup.th, and 36.sup.th edges set to two, the entries for the 40.sup.th edge set to 3, and the remaining entries set to 0. Similarly, the probability information for these trees can be stored in a 42-entry array, with entries for the 17.sup.th, 31.sup.st-33.sup.rd, 37.sup.th, and 41.sup.st edges set to 0.33, the entries for the 14.sup.th, 27.sup.th, and 36th edges set to 0.66, the entries for the 40.sup.th edge set to 1, and the entries for the remaining edges set to 0.
[0195] A placer can calculate congestion cost estimates based on the edge-intersection information similarly to how it would calculate such estimates based on the wiring-path information. Specifically, to calculate such a congestion cost, the placer initially for each net (1) identifies the net's configuration with respect to the partitioning grid, and then (2) retrieves the pre-tabulated edge-intersection information, which includes one value for each edge in the grid.
[0196] The placer can then generate different congestion cost estimates based on these retrieved values. For instance, in some embodiment, the placer calculates a congestion cost by (1) summing the retrieved values for each particular edge over all the nets, (2) squaring this sum, and (3) adding the squared sums of all the edges. Equation H illustrates this calculation mathematically. 4 Cost = Edges ( nets F ( netconfig , edge ) ) 2 ( H )
[0197] In this equation, F(netconfig, edge) represents the retrieved value of a particular edge for a particular net configuration.
[0198] Other embodiments calculate a congestion cost by (1) summing the retrieved values for each particular edge over all the nets, and (2) selecting the maximum sum. Equation I illustrates this calculation mathematically. 5 Cost = max edge ( nets F ( netconfig , edge ) ) ( I )
[0199] Yet other embodiments use other approaches to compute placement cost estimates based on the edge-intersect values. For instance, instead of summing the retrieved values for each particular edge over all the nets, some embodiments might combine these values associated with each edge in a different manner (e.g., some might multiply the values associated with each edge).
[0200] FIG. 30 illustrates a process 3000 that (1) constructs one or more optimal Steiner trees for each possible net configuration with respect to a partitioning grid, (2) computes count and probability of the trees using each interconnect-line path in the grid, and (3) stores the computed count and path-usage probabilities in a storage structures (such as a LUT). This process is performed before the placement process 1100 of FIG. 11, so that the placement process in real-time does not have to construct the Steiner trees and determine the path-usage probabilities for each net configuration. Also, as mentioned above, some embodiments define the set of interconnect-line paths in the grid based on the grid and on the wiring model used. For instance, as described above, some embodiments define 42 edges for using the octagonal wiring model in a 4.times.4 grid.
[0201] The process 3000 is identical to process 1800 of FIG. 18, except for two operations 3005 and 3010. Operations 1805-1845 and 1860 of process 3000 are identical to similarly numbered operations 1805-1845 and 1860 of process 1800. Hence, these operations 1805-1845 and 1860 will not be further described below, in order not to obscure the description of the invention with unnecessary detail. It should also be noted that the description of FIGS. 19-22 are equally applicable for the process 3000. For instance, like process 1800, the process 3000 (1) calls process 2100
at 1825 to identify potential Steiner nodes, and (2) calls process 2200
at 1820 and 1840 to construct MST's for particular sets of nodes.
[0202] As mentioned above, one difference between process 1800 and process 3000 is that, unlike the process 1800 that identifies one MST at 1850 as the current node configuration Steiner tree, the process 3000 at 3005
selects one or more of the MST's generated at 1820 or 1840 as the optimal Steiner trees for the current node configuration. The process 3000
selects one or more Steiner trees (at 3005) because it is designed to help enumerate all potential congestion that can result from a particular node configuration.
[0203] This process selects its set of Steiner trees for the current node configuration based on one or more criteria. For instance, in some embodiments, this process selects the shortest MST's as the Steiner trees (i e., the process only uses length as a selection criterion). In other embodiments, this process uses both the length and bend-count of the MST's to select its set of Steiner trees. For example, some embodiments might select the shortest MST's that have less than a pre-specified number of bends as the Steiner trees; if none of the MST's have less than the pre-specified number of bends, these embodiments increment the minimum bend count and then select the shortest MST's with that have less than the incremented pre-specified number of bends.
[0204] After selecting one or more Steiner trees for the current node configuration at 3005, the process 3000 calls (at 3010) a process 3100 of FIG. 31 to calculate the count and path-usage probabilities resulting from the selected Steiner trees. In some embodiments, this process starts when process 3000 calls it at 3010 and supplies it with a set of Steiner trees (i.e., one or more Steiner trees).
[0205] The process 3100 starts by initializing (at 3105) the count values for each path to 0. The process then selects (at 3110) a received Steiner tree, and selects (at 3115) one of the edges in the tree (i.e., selects a pair of linked nodes in the tree, where these nodes were linked at 2245
of FIG. 22). Next, the process retrieves (at 3120) values for possible paths that this tree uses. In some embodiments, the process retrieves these values from a LUT that stores path-usage values for any combination of the tree slot nodes. In other words, this LUT maps the endpoints of each possible tree edge within the grid to a set of path-usage values.
[0206] When the tree edge endpoints are not adjacent (i.e., when the pair of nodes selected at 3115 are not adjacent), more than one optimal route might exist between the endpoints (i.e., between the node pairs). Hence, the path-usage values in the LUT might specify values for multiple optimal routes. Also, in these circumstance, the retrieved usage value for a particular path might be greater than 1 to indicate that more than one optimal route use the particular path to connect the node pairs selected at 3115.
[0207] For example, for the Steiner trees shown in FIGS. 13-15, the process 3000 would identify two sets of node connections as two possible Steiner trees. One set of node connections (e.g., node 1310-node 1315-Steiner node 1320-node 1325-node 1330) represent the Steiner tree 1305 of FIG. 13, while another node connection (e.g., node 1325-node 1310-node 1315-node 1335) could represent either the Steiner tree of FIG. 14 or 15.
[0208] In the first set of nodes representing the Steiner tree 1305 of FIG. 13, only one route exists between any two connected pairs of nodes. Hence, for any pair from this set, the mapping LUT would return a 42
values, with all the values equal to 0 except the value for the path between the selected node pair. This non-zero value would be 1 to indicate that only one route exists between the selected node pair.
[0209] On the other hand, for the second set of nodes representing either Steiner tree 1405 or 1505, two routes exist between nodes 1315 and 1330. The Steiner tree 1405 uses one of these routes, while the Steiner tree 1505 uses the other. For this node pair (i e., for nodes 1315 and 1330) in this node set, the mapping LUT would return 38 path values equal to 0, and 4 path values equal to 1. Two of the four values would correspond to the paths 33 and 36 used by the Steiner tree 1405, while the other two values would correspond to paths 37 and 41 used by Steiner tree 1505.
[0210] As mentioned above, when the path-usage values in the LUT specify values for multiple optimal routes between a selected node pair, and more than one optimal route use a particular path, the mapper stores a path usage-value greater than one for the particular path. For example, when the selected node pairs are the node for slot 1 and the node for slot 14
(according to the numbering convention of FIG. 12), the mapper would store a 2 for the path 27 (i.e., the path between slots 1 and 5), since two of the three optimal routes between nodes 1 and 14 use this path.
[0211] After retrieving values for possible paths that this tree uses, the process increments (at 3125) count of the paths based on the retrieved values. Next, the process determines (at 3130) whether it has examined the last edge of the current tree (i.e., whether it has examined the last linked node pair in the current tree). If not, the process transitions back to 3115 to select the next tree edge (i.e., the next linked node pair) and to repeat 3120 and 3125 for this next tree edge.
[0212] When the process determines (at 3130) that it has examined the last tree edge, it then determines (3135) whether it has examined the last tree supplied by the process 3000. If not, the process returns to 3110 to select another tree and then determine the path-usage for this tree. Otherwise, the process records (at 3140) the usage count for each path. Also, for each particular path, the process (at 3140) (1) divides the usage count by the number of the received trees to obtain the usage probability value of the particular path, and then (2) stores this resulting probability value. The process then ends.
[0213] Although the processes 3000 and 3100 were described above for calculating path-usage counts and probabilities, one of ordinary skill will realize that analogous processes can be used to calculate edge-intersect counts and probabilities. Also, the above-described embodiments calculate and store information about wiring paths used and edge intersected by Steiner trees that have potential diagonal edges. However, one of ordinary skill in will realize that some embodiments calculate and store such path-usage and/or edge-intersect information for any arbitrary connection graphs that model net configurations with respect to the partitioning grid. Also, some embodiments that measure and utilize such path usage and/or edge-intersect information do not use diagonal edges in their Steiner trees or their other arbitrary connection graphs (e.g., only use Manhattan Steiner trees or other Manhattan connection graphs).
[0214] C. Pre-Tabulating Edge-Intersect, Length, and Bend-Count Values for Steiner Trees
[0215] Some embodiments pre-tabulate multiple attributes of the Steiner trees that model the net configurations with respect to the partitioning grid. For instance, FIG. 32 illustrates a process 3200 that pre-tabulates the length, bend-count, and path-usage values of such Steiner trees. This process 3200 is a combination of the process 1800 of FIG. 18 and the process 3000 of FIG. 30. It includes all the operations 1805-1845 of the processes 1800 and 3000, operations 1850 and 1855 of the process 1800, and operations 3005 and 3010 of the process 3000. As these operations were described above, they will not be further described below, in order not to obscure the description of the invention with unnecessary detail. Pre-tabulating the length, bend-count, and path-usage values allows the placer to make placement designs based on any one of these attributes or any combination of these attributes.
[0216] D. Pre-Tabulating Steiner Trees for Different Wiring Models
[0217] Some embodiments of the invention pre-tabulate one or more Steiner tree attributes for several different wiring models. For instance, FIG. 33 illustrates a process 3300 that performs the process 1800, the process 3000, or the process 3200 once (at 3305) for the octagonal wiring model, once (at 3310) for the hexagonal wiring model, and once (at 3315) for the Manhattan wiring model.
[0218] To model all possible net configurations for the octagonal wiring model, this process calculates (at 3305) the length, bend-count, and/or path-usage values of Steiner trees with potential 45.degree. diagonal edges. In other words, at 3305, the process 3300 uses 45.degree. as the angle A in Equation (A) that process 2100 and 2200 of process 1800, process 3000, and process 3200 use.
[0219] To model all possible net configurations for the hexagonal wiring model, this process calculates (at 3310) the length, bend-count, and/or path-usage values of Steiner trees with potential 120.degree. diagonal edges. In other words, at 3310, the process 3300 uses 120.degree. as the angle A in Equation (A) that process 2100 and 2200 of process 1800, process 3000, and process 3200 use.
[0220] To model all possible net configurations for the Manhattan wiring model, these embodiments calculate (at 3315) the length, bend-count, and/or path-usage values of Manhattan Steiner trees. In other words, at 3315, the process 3300 uses 90.degree. as the angle A in Equation (A) that process 2100 and 2200 of process 1800, process 3000, and process 3200 use.
[0221] IV. Recursive 4-by-4 Partitioning
[0222] A. Software Architecture
[0223] FIG. 34 illustrates the software architecture of a placer 3400 of some embodiments of the invention. This software architecture includes several software modules 3405 and several data constructs 3410. The software modules include a recursor 3415, an initializer 3420, an optimizer 3425, a cost estimator 3430, and a mover 3435, while the data constructs 3410 include LUT's 3440, circuit modules 3445, net list 3450, nets 3455, and slots 3460.
[0224] The recursor 3415 defines partitioning grids that recursively divide the IC layout into smaller and smaller sub-regions. In some embodiments, the recursor uses different shaped partitioning grids for different recursion levels. In the embodiments described below, however, the recursor uses the same shaped partitioning grids for all the recursion levels. At each recursion level, the recursor simply adjusts the coordinates of the partitioning grid to match the coordinates of the IC region at that recursion level. Using the same shaped partitioning grids for all the recursion levels has several advantages. For instance, it allows the placer 3400 to use one set of pre-tabulated net-configuration attributes for all the recursion levels, as this set could be used to define the relative costs of the net configurations at any one level.
[0225] In the embodiments described below, the recursor uses 3
evenly-spaced horizontal lines and 3 evenly-spaced vertical lines to recursively divide IC-layout regions into 16 identically-sized sub-regions (i.e., 16 identically-sized slots). FIG. 35 illustrates an IC layout 3505 that is recursively divided into sets of 16 sub-regions. Specifically, the IC layout is divided initially into 16 sub-regions, each of these sub-regions is further divided into 16 smaller sub-regions, and one of the smaller sub-regions 3510 is further sub-divided into 16
sub-regions.
[0226] At each recursion level, the initializer 3420 calculates the placement cost of the initial placement configuration within that level's IC region. The initializer calculates this cost by first calculating initial configuration and balance costs, and then using these costs to calculate the initial placement cost.
[0227] In other words, in the embodiments described below, the placement cost has two components, the configuration cost and the balance cost. The configuration cost is the cost associated with the placement configuration of the nets with respect to that level's partitioning grid. This cost is computed based on attributes (such as wirelength, bend-count, path-usage, edge-intersect, etc.) of connection graphs that model the net configurations. As described below, these attributes are pre-tabulated and stored in LUT's 3440. On the other hand, the balance cost at each recursion level reflects the size of the circuit modules in each sub-region defined by that level's partitioning grid. Hence, by factoring the balance cost, a placer can prevent some sub-regions from being excessively full.
[0228] At each recursion level, the embodiments described below calculate the balance cost based on (1) the capacity of each slot at that level, and (2) the size of circuit modules within each slot. Also, at each recursion level, these embodiments calculate the configurations costs by (1) identifying each net's configuration with respect to that level's partitioning grid, (2) using each net's configuration to retrieve pre-tabulated attributes from the LUT's, and (3) computing a configuration cost based on the retrieved attribute or attributes for the net configurations.
[0229] After the initializer 3420 calculates the placement cost of the initial placement configuration within a recursion level's IC region, the optimizer 3425 then iteratively modifies the placement configuration to improve the placement cost within that region. For each potential move that the optimizer selects, the optimizer uses the cost estimator 3430 to calculate the placement cost of the move.
[0230] The optimizer then analyzes these costs to determine whether to make the move. If it decides to make the move, the optimizer uses the mover 3435 to modify the placement configuration according to the selected move.
[0231] FIGS. 41-49 further describe the software modules 3405. However, before describing these software modules, the data constructs 3410 will be described below by reference to FIGS. 36-40.
[0232] B. Data Constructs
[0233] 1. LUT's
[0234] The LUT's 3440 store placement attributes for all possible net configurations. Specifically, some embodiments store in the LUT's attributes of Steiner trees that model the interconnect topologies of the net configurations (i.e., that model the topologies of the interconnect lines connecting the sub-regions that contain the circuit modules of the nets). In some embodiments of the invention, the Steiner trees have edges that are completely or partially diagonal.
[0235] In the embodiments described below, the LUT's store the length and path-usage values of the Steiner trees for all possible net configurations. Some of these embodiments also consider the bend-count values of the trees during pre-tabulation of the length or path-usage values by using the bend-count values as one of the factors for selecting the trees. Other embodiments, however, store the bend-count values for the trees instead of, or in addition to, the length and path-usage values. Several processes for selecting Steiner trees and pre-tabulating their length, bend-count, and path-usage values were discussed above in Section III. One of ordinary skill will understand that other embodiments also store other attributes of trees.
[0236] Some embodiments calculate the configuration cost of the Steiner trees by combining (e.g., generating a weighted sum of) multiple attributes (e.g., length, bend-count, etc.) of the trees. Such a calculation can be performed during the pre-tabulating process or during the placement process.
[0237] In some embodiments, the placer 3400 can operate with different wiring architectures. In these embodiments, different LUT's can be used to store the configuration attributes for the different wiring models. For instance, when the IC layout uses the octagonal wiring model, one of the LUT's 3440 stores the length, bend-count, and/or path-usage values of Steiner trees that can have 45.degree. diagonal edges. Alternatively, when the IC layout uses the hexagonal wiring model, one of the LUT's stores the length, bend-count, and/or path-usage values of the Steiner trees that can have 120.degree. diagonal edges. One of the LUT's can also store length, bend-count, and/or path-usage values for rectilinear Steiner trees, i.e., Steiner trees that only use horizontal and vertical lines.
[0238] In some embodiments, each LUT is a table of floating point numbers. Each table is indexed by a configuration code. In other words, to retrieve configuration attribute for a particular net configuration, the configuration code for the net configuration is identified, and this configuration code is used to identify the entry in the LUT that stores the net's configuration attribute.
[0239] In the embodiments described below, the configuration code is a 16-bit number, where each bit represents a sub-region defined by the current partitioning grid. Specifically, in some embodiments, each configuration-code bit is set (e.g., equals 1) when the associated net has a circuit module in the sub-region represented by the configuration-code bit, and is not set (e.g., equals 0) when the associated net does not have a circuit module in this sub-region. Also, in these embodiments, there are 2.sup.16 configuration codes that represent the 2.sup.16 possible net configurations.
[0240] 2. Net and Net List
[0241] FIG. 36 illustrates the data structure for a net list 3600. In some embodiments of the invention, each net data structure is a net data object (i.e., an instantiation of a net data class). As shown in FIG. 36, the net list includes several fields 3605. Each field refers (e.g., points) to a net 3610.
[0242] FIG. 37 illustrates the data structure for a net. In some embodiments of the invention, each net data structure is a net data object (i.e., an instantiation of a net data class). Each net data structure 3610 includes a field 3705 that stores the net's configuration code. At each stage in the recursion process, each net's configuration code is a 16-bit number that describes the net's configuration with respect to that stage's partitioning grid.
[0243] Each bit in the configuration code represents one of sixteen sub-regions defined by a partitioning grid. In some embodiments, each configuration-code bit is set to 1 when the associated net has a circuit module in the sub-region represented by the configuration-code bit, and is set to 0 when the associated net does not have a circuit module in this sub-region. For instance, under such an approach, the configuration code is 1100000110000000 for the net 1205 with respect to the partitioning grid 1200 of FIG. 12. This code reflects that this net has circuit modules in the 1, 2, 8, and 9 sub-regions defined by partitioning grid 1200. When a net has no circuit modules within a partitioning grid, the net's code configuration within that grid is represented by a string of 16 zeros. Also, for each partitioning grid, there are 2.sup.16
configuration codes that represent the 2.sup.16 possible net configurations within that grid.
[0244] As shown in FIG. 37, the net data structure 3610 also includes a field 3710 that refers (e.g., points) to a distribution array 3715. At each stage in the recursion process, the distribution array 3715 is defined with respect to the partitioning grid for that stage. This array includes 16 integer entries. Each entry corresponds to a partitioned sub-region defined by the recursor 3415, and specifies the number of the net's circuit modules in its corresponding sub-region. For instance, the distribution array for net 1205 with respect to the partitioning grid 1200 is illustrated below.
Distrib. Array for net 1205=[1, 1, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0]
[0245] As described below by reference to FIG. 42, each time the recursor defines a new partitioning grid that divides a particular IC region into 16 smaller sub-regions, the initializer 3420 (1) records in each net's data structure a configuration code that represents the net's initial configuration within the newly partitioned region, and (2) records in each net's distribution array the count of the net's circuit modules within each of the defined sub-regions. Also, as further described below by reference to FIG. 49, each time the mover 3435 repositions one or more circuit modules of the net, the mover modifies the net's configuration code and its distribution array.
[0246] As shown in FIG. 37, the data structure 3610 of a net also includes one or more fields 3720 that refer (e.g., point) to the data structures of circuit modules on the net.
[0247] 3. Circuit Modules
[0248] FIG. 38 illustrates the data structure of a circuit module. In some embodiments of the invention, each circuit-module data structure is a data object (i.e., an instantiation of a circuit-module class). As shown in this figure, this data structure 3800 includes a field 3805 that specifies the size of the circuit module. It also includes a field 3810
that specifies the position of the circuit module in the IC layout. In some embodiments, the circuit module's position is specified by the x- and y-coordinates of module's origin (e.g., its center). The data structure 3800 also includes one or more fields 3815 that refer (e.g., point) to the data structures of nets on which the circuit module resides.
[0249] The data structure 3800 also includes a field 3820 that specifies the slot (i.e., sub-region) that contains the circuit module. At each stage in the recursion process, the current-slot field 3820 is defined with respect to the partitioning grid for that stage. As further described below by reference to FIG. 42, each time the recursor defines a new partitioning grid that divides a particular IC region into 16 smaller sub-regions, the initializer 3420 identifies the position of each circuit module with respect to the newly defined sub-regions. For each circuit module that falls within one of these sub-regions, the initializer then records the identity of the sub-region that contains the module in the current-slot field 3820 of the circuit module data structure. When a circuit module does not fall within any of the sub-regions defined by a particular partitioning grid, the entry in the current-slot field 3820 is set to a default value (e.g., 0). This default value indicates the circuit module is outside of the current partitioned IC region.
[0250] As further described below by reference to FIGS. 49, each time the mover 3435 repositions a circuit module, the mover ascertains the slot that contains the module after its move, and modifies the current-slot field 3820 to reflect the new location of the circuit module.
[0251] 4. Slot
[0252] At each stage in the recursion process, the recursor 3415 divides a particular IC region into 16 sub-regions or slots. FIG. 39 presents a graph that illustrates the hierarchy of slots (i.e., sub-regions) defined by the recursor. This graph 3900 illustrates two levels 3910 and 3915 of the recursion process. In this graph, each node represents an IC region at a particular stage within the recursion process. Also, in this graph, the root node represents the entire IC layout, while each non-root node represents a portion of the IC layout.
[0253] In a slot-hierarchy graph (such as graph 3900), each node has either 0 child nodes or 16 child nodes. A node has 16 child nodes when the recursor partitions that node's region into 16 sub-regions. Conversely, a node does not have child nodes when its corresponding region is not partitioned.