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United States Patent Application
20030161197
Kind Code
A1
Iwata, Yoshihisa ; et al.
August 28, 2003
Magnetic random access memory
Abstract
A read block is formed from a plurality of MTJ elements arranged in the horizontal direction. One terminal of each MTJ element in the read block is commonly connected. The connection point is directly connected to a read word line without intervening a select switch. The other terminal of each MTJ element is individually connected to a read bit line. The read bit line/write word line is connected to a common data line through a row select switch. The common data line is connected to a read circuit.
Inventors:
Iwata; Yoshihisa
(Yokohama-shi, JP)
, Higashi; Tomoki
(Yokohama-shi, JP
)
Correspondence Name and Address:
1940 DUKE STREET
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
ALEXANDRIA
VA
22314
US
Series Code:
369886
Filed:
February 21, 2003
U.S. Current Class:
365/200
U.S. Class at Publication:
365/200
Intern'l Class:
G11C 007/00
Claims
What is claimed is:
1. A magnetic random access memory comprising: a memory cell array having memory cells using a magnetoresistive effect; a first functional line which runs in a first direction in the memory cell array and is commonly connected to one terminal of each of the memory cells; second functional lines which are arranged in correspondence with the memory cells and run in a second direction perpendicular to the first direction in the memory cell array; and a third functional line which is separated from the memory cells and shared by the memory cells,
2. A memory according to claim 1, wherein the memory cell array is arranged on a semiconductor substrate, and no switch element is present immediately under the memory cell array.
3. A memory according to claim 2, wherein dummy interconnections which do not function as actual interconnections are arranged immediately under the memory cell array.
4. A memory according to claim 3, wherein each of the dummy interconnections has the same structure as that of a gate electrode of a MOS transistor arranged at a peripheral portion of the memory cell array.
5. A memory according to claim 3, wherein the dummy interconnections are arranged equidistantly, periodically, or uniformly as a whole.
6. A memory according to claim 1, wherein the memory cells are arranged on a semiconductor substrate and arrayed in a direction parallel to a surface of the semiconductor substrate.
7. A memory according to claim 6, wherein the memory cells are arrayed in the first direction, and the first and third functional lines run in the first direction in the memory cell array.
8. A memory according to claim 6, wherein when the memory cell array and the first, second, and third functional lines form one memory cell unit, stages of memory cell units are stacked on the semiconductor substrate.
9. A memory according to claim 8, wherein for first and second memory cell units which are adjacent to each other in the memory cell units, the first functional line of the first memory cell unit and the third functional line of the second memory cell unit are integrated as a fourth functional line.
10. A memory according to claim 9, wherein the first memory cell unit is arranged on the second memory cell unit.
11. A memory according to claim 9, further comprising a switch circuit which determines whether the fourth functional line should function as the first functional line of the first memory cell unit or the third functional line of the second memory cell unit.
12. A memory according to claim 9, wherein for first and second memory cell units which are adjacent to each other in the memory cell units, the first functional lines of the first and second memory cell units are integrated as a fifth functional line.
13. A memory according to claim 12, wherein for first and second memory cell units which are adjacent to each other in the memory cell units, the third functional lines of the first and second memory cell units are integrated as a sixth functional line.
14. A memory according to claim 13, wherein each of the memory cells of the first and second memory cell units is formed from a magnetic storage element having a pinning layer whose magnetizing direction is fixed, and the magnetizing direction of the pinning layer of each of the memory cells of the first memory cell unit is different from the magnetizing direction of the pinning layer of each of the memory cells of the second memory cell unit.
15. A memory according to claim 13, wherein each of the memory cells of the first and second memory cell units is formed from a magnetic storage element having a pinning layer whose magnetizing direction is fixed, and the pinning layers of the memory cells of the first and second memory cell units have the same magnetizing direction.
16. A memory according to claim 1, wherein the first functional line and second functional lines are arranged immediately under the memory cells, and the third functional line is arranged immediately on the memory cells.
17. A memory according to claim 16, wherein said one terminal of each of the memory cells corresponds to an upper surface of the memory cell, said other terminal of each of the memory cells corresponds to a lower surface of the memory cell, and the memory cells are arranged symmetrically with respect to the contact plug.
18. A memory according to claim 1, wherein the first functional line and second functional lines are arranged immediately on the memory cells, and the third functional line is arranged immediately under the memory cells.
19. A memory according to claim 18, wherein said one terminal of each of the memory cells corresponds to a lower surface of the memory cell, said other terminal of each of the memory cells corresponds to an upper surface of the memory cell, and the memory cells are arranged symmetrically with respect to the contact plug.
20. A memory according to claim 17 or 19, wherein an electrode is connected to said one terminal of each of the memory cells, and said one terminal of each of the memory cells and the first functional line are connected through a contact plug.
21. A memory according to claim 1, wherein the first functional line functions as a read line to supply a read current to the memory cells.
22. A memory according to claim 21, wherein one end of the first functional line is connected to a ground point through a column select switch.
23. A memory according to claim 21, wherein one end of the first functional line is connected to a bias line which is set to a bias potential.
24. A memory according to claim 1, wherein the second functional lines function as read lines to supply a read current to the memory cells and write lines which generate a magnetic field to write data in the memory cells.
25. A memory according to claim 24, wherein one end of each of the second functional lines is connected to a corresponding one of common lines arranged outside the memory cell array through a corresponding one of row select switches.
26. A memory according to claim 25, wherein the common lines run in the first direction.
27. A memory according to claim 25, wherein one end of each of the common lines is connected to a read circuit.
28. A memory according to claim 25, wherein one end of each of the common lines is connected to a driver, and the other end of each of the second functional lines is connected to a sinker.
29. A memory according to claim 25, wherein a driver is connected between the second functional lines and the row select switches, and a sinker is connected to the other end of each of the second functional lines.
30. A memory according to claim 28 or 29, wherein an axis of easy magnetization of the MTJ elements is set in the second direction.
31. A memory according to claim 24, wherein one end of each of the second functional lines is connected, through a corresponding one of first row select switches, to a corresponding one of first common lines arranged outside the memory cell array, and the other end of each of the second functional lines is connected, through a corresponding one of second row select switches, to a corresponding one of second common lines arranged outside the memory cell array.
32. A memory according to claim 31, wherein the first and second common lines run in the first direction.
33. A memory according to claim 31, wherein one end of each of the first common lines is connected to a read circuit.
34. A memory according to claim 31, wherein one end of each of the first common lines is connected to a first driver/sinker, and one end of each of the second common lines is connected to a second driver/sinker.
35. A memory according to claim 34, wherein an axis of easy magnetization of the MTJ elements is set in the first direction.
36. A memory according to claim 1, wherein the third functional line functions as a write line which generates a magnetic field to write data in the memory cells.
37. A memory according to claim 36, wherein drivers/sinkers are respectively connected to two ends of the third functional line.
38. A memory according to claim 36, wherein a driver is connected to one end of the third functional line, and a sinker is connected to the other end of the third functional line.
39. A memory according to claim 27 or 33, wherein the read circuit is formed from sense amplifiers which are arranged in correspondence with the second functional lines, and output buffers which are arranged in correspondence with the sense amplifiers.
40. A memory according to claim 27 or 33, wherein the read circuit is formed from sense amplifiers which are arranged in correspondence with the second functional lines, an output buffer which outputs data from one of the sense amplifiers, and a selector which is connected between the sense amplifiers and the output buffer.
41. A memory according to claim 39, wherein the sense amplifiers fix potentials of the second functional lines and detect a change in read current flowing through the second functional lines.
42. A memory according to claim 39, wherein the sense amplifiers fix potentials of the second functional lines and detect a change in read current flowing through the second functional lines.
43. A memory according to claim 1, wherein the memory cells form a read block, and data from the memory cells are simultaneously read out.
44. A memory according to claim 1, wherein each of the memory cells is formed from a magnetic storage element including a pinning layer whose magnetizing direction is fixed, a storing layer whose magnetizing direction changes in accordance with write data, and a tunneling barrier layer arranged between the pinning layer and the storing layer.
45. A memory according to claim 1, wherein 2.sup.n (n is a natural number) memory cells are present.
46. A memory according to claim 1, wherein each of the memory cells is formed from an element which stores data using a tunneling magnetoresistive effect.
47. A read method of a magnetic random access memory, comprising: using the method to the magnetic random access memory of claim 1; fixing all the second functional lines of claim 1 to a first potential; setting the first functional line of claim 1 to a second potential different from the second potential; individually supplying a read current to the memory cells of claim 1; and reading out data from the memory cells on the basis of a value of the read current.
48. A write method of a magnetic random access memory, comprising: using the method to the magnetic random access memory of claim 1; supplying a first write current flowing in one direction to one of the second functional lines of claim 1; supplying a second write current having a direction depending on write data to the third functional line of claim 1; and writing the write data in one of the memory cells using a magnetic field generated by the first and second write currents.
49. A write method of a magnetic random access memory, comprising: using the method to the magnetic random access memory of claim 1; supplying a first write current having a direction depending on write data to one of the second functional lines of claim 1; supplying a second write current flowing in one direction to the third functional line of claim 1; and writing the write data in one of the memory cells using a magnetic field generated by the first and second write currents.
50. A manufacturing method of a magnetic random access memory, comprising: a. forming a gate electrode of a MOS transistor in a peripheral circuit region and simultaneously forming, in a memory cell array region, dummy interconnections equidistantly, periodically, or in a layout uniform as a whole; b. forming a first interlayer dielectric film which covers the MOS transistor and dummy interconnections; c. forming a memory cell having a magnetoresistive effect in a surface region of the first interlayer dielectric film in the memory cell array region; and d. forming a second interlayer dielectric film which covers the memory cell.
51. A method according to claim 50, wherein the same steps as the c. and d. steps are repeated after the d. step.
52. A method according to claim 50, further comprising: e. forming a first functional line which is connected to one terminal of the memory cell and runs in a first direction; f. forming a second functional line which is connected to the other terminal of the memory cell and runs in a second direction perpendicular to the first direction; and g. forming a third functional line which is separated from the memory cell by a predetermined distance and generates a magnetic field to write data in the memory cell.
53. A method according to claim 50, wherein the first, second, and third functional lines are formed by a damascene process.
54. A method according to claim 50, wherein the first, second, and third functional lines are formed by steps of forming an interconnection trench, forming a metal layer which completely fills the interconnection trench, and removing the metal layer outside the interconnection trench.
55. A method according to claim 54, further comprising, before formation of the metal layer, a step of forming a barrier metal layer.
56. A method according to claim 55, further comprising before formation of the barrier metal layer, forming a sidewall insulating layer on a sidewall of the interconnection trench, and after removal of the metal layer outside the interconnection trench, forming, only on the metal layer, a cap insulating layer made of the same material as that of the sidewall insulating layer.
57. A method according to claim 56, wherein the sidewall insulating layer and cap insulating layer are made of silicon nitride.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-46964, filed Feb. 22, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a magnetic random access memory (MRAM) which utilizes a magnetoresistive effect.
[0004] 2. Description of the Related Art
[0005] In recent years, many memories which store data by new principles have been proposed. One of them is a magnetic random access memory which utilizies the tunneling magnetoresistive (to be referred to as TMR hereinafter) effect.
[0006] As a proposal for a magnetic random access memory, for example, Roy Scheuerlein et al, "A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell", ISSCC2000
Technical Digest, p. 128 is known.
[0007] A magnetic random access memory stores "1"- and "0"-data using MTJ (Magnetic Tunnel Junction) elements. As the basic structure of a MTJ element, an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers). However, various kinds of MTJ element structures have been proposed to, e.g., optimize the MR (MagnetoResistive) ratio.
[0008] Data stored in the MTJ element is determined on the basis of whether the magnetizing states of the two magnetic layers are parallel or antiparallel. "Parallel" means that the two magnetic layers have the same magnetizing direction. "Antiparallel" means that the two magnetic layers have opposite magnetizing directions.
[0009] Normally, one (fixed layer) of the two magnetic layers has an antiferromagnetic layer. The antiferromagnetic layer serves as a member for fixing the magnetizing direction of the fixed layer. In fact, data ("1" or "0") stored in the MTJ element is determined by the magnetizing direction of the other (free layer) of the two magnetic layers.
[0010] When the magnetizing states in the MTJ element are parallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the MTJ element is minimized. For example, this state is defined as a "1"-state. When the magnetizing states in the MTJ element are antiparallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the MTJ element is maximized. For example, this state is defined as a "0"-state.
[0011] Currently, various kinds of cell array structures have been examined for a magnetic random access memory from the viewpoint of increasing the memory capacity or stabilizing write/read operation.
[0012] For example, currently, a cell array structure in which one memory cell is formed from one MOS transistor and one MTJ element is known. Additionally, a magnetic random access memory which has such a cell array structure and stores 1-bit data using two memory cell arrays so as to realize stable read operation is also known.
[0013] However, in these magnetic random access memories, it is difficult to increase the memory capacity. This is because one MOS transistor corresponds to one MTJ element in these cell array structures.
[0014] As a magnetic random access memory which needs no MOS transistors in the memory cell array, a cross-point cell array structure is conventionally known. A cross-point cell array structure has a simple structure with an MTJ element being arranged at the inter-connection of a word line and a bit line. As a characteristic feature, no select transistor is arranged in the memory cell array.
[0015] According to the cross-point cell array structure, the memory cell size can be reduced because no select MOS transistors are used. As a consequence, the memory capacity can be increased.
[0016] For example, when the minimum size of design rule is defined as "F", the size of a memory cell formed from a select MOS transistor and MTJ element is 8F.sup.2. However, a memory cell including only an MTJ element is 4F.sup.2. That is, the memory cell including only an MTJ element can realize a cell size about 1/2 that of the memory cell formed from a select MOS transistor and MTJ element.
[0017] However, when a magnetic random access memory is formed by employing a cross-point cell array structure, there is posed a problem of breakdown of the insulting layer (tunneling barrier layer) of a TMR (MTJ) element in write operation.
[0018] More specifically, in the cross-point cell array structure, an MTJ element is arranged at the intersection of a word line and a bit line while being in contact with them. Write currents having the same value are supplied to the word line and bit line (the directions of the write currents supplied to the word line and bit line change in accordance with the data value) to generate a magnetic field. The direction of magnetization of the MTJ element arranged between the word line and the bit line is thus determined.
[0019] The word line and bit line have interconnection resistances. The value of the interconnection resistance across the word line and bit line increases as they become long. That is, when the write current is flowing, the potential at a position close to the driver of the word line or bit line is higher than that at a position close to the sinker of the word line or bit line.
[0020] Hence, in write operation, a potential difference may be generated across the MTJ element in accordance with its position. This potential difference may cause voltage stress on the tunneling barrier layer of the MTJ element and then dielectric breakdown of the tunneling barrier layer.
[0021] This problem will be described in detail.
[0022] An MTJ element (worst case) which is arranged at a position closest to a word line driver WD (farthest from a word line sinker WS) and closest to a bit line sinker BS (farthest from a bit line driver BD), as shown in FIG. 107, will be examined.
[0023] The potential at the word-line-side end portion of the MTJ element is, e.g., Vp because the end portion is in contact with the word line at a position closest to the word line driver WD. On the other hand, the potential at the bit-line-side end portion of the MTJ element is, e.g., Vp-.alpha. because the end portion is in contact with the bit line at a position farthest from the bit line driver BD, and a voltage drop occurs due to an interconnection resistance r of the bit line.
[0024] That is, the potential of the bit-line-side end portion of the MTJ element is lower than that of the word-line-side end portion by .alpha.. As a result, the potential difference .alpha. is generated across the MTJ element arranged at the closest to the word line driver WD and bit line sinker BS.
[0025] Assume that dielectric breakdown of the tunneling barrier layer is caused by an electric field more than 10 [MV/cm] at a very high probability.
[0026] When the sheet resistance of the word line and bit line is 100
[m.OMEGA.], and the size of the memory cell array is 1750 (1.75 kilo) cells.times.1750 (1.75 kilo) cells, the interconnection resistance r from one end to the other end of the word line or bit line is as follows.
[0027] In the cross-point cell array structure, memory cells are arranged along the word lines and bit lines from one end to the other end of each of them. When a memory cell has a minimum process size (design rule) in the direction in which the word line or bit line runs, the pitch between the memory cells in that direction is also set to the minimum process size (pitch).
[0028] That is, the length of a word line or bit line corresponds to an array of 1750.times.2 memory cells. Hence, the interconnection resistance r from one end to the other end of the word line or bit line is 350
[.OMEGA.] (when the memory cell array becomes large, the word lines and bit lines become long, and the interconnection resistance r increases).
[0029] When the interconnection resistance r is 350 [.OMEGA.], and a write current Ip is 2 [mA], a potential difference of 0.7 (=0.002.times.350) [V] is generated across each of the word lines and bit lines.
[0030] When the thickness of the tunneling barrier layer of the MTJ element (when the MTJ element has a plurality of tunneling barrier layers, the total thickness of the tunneling barrier layers) is 0.7 [nm], and the potential difference across the MTJ element is 0.7 [V], an electric field of 10 [MV/cm] is generated in the MTJ element.
[0031] To avoid dielectric breakdown of the tunneling barrier layer under the above conditions, the size of one memory cell array surrounded by the word line driver/sinker and bit line driver/sinker must be set to 1.75
kilo.times.1.75 kilo or less.
[0032] As described above, in the cross-point cell array structure, when dielectric breakdown of the tunneling barrier layer of the MTJ element in write operation is taken into consideration, the upper limit of the memory cell array size is determined. Hence, the degree of integration of MTJ elements cannot be sufficiently increased.
[0033] In addition, the write current Ip does not always flow to the word line or bit line. The write current Ip is supplied to the word line or bit line only in the write operation. That is, the potential at a position closest to the word line or bit line sometimes exceeds Vp due to overshoot phenomenon.
[0034] In consideration of this overshoot phenomenon, an electric field more than 10 [MV/cm] may be generated in the MTJ element under the above conditions.
[0035] Assume that the sheet resistance of the word line and bit line, the write current Ip, and the thickness of the tunneling barrier layer are constant. In this case, to avoid probable generation of an electric field more than 10 [MV/cm] in the MTJ element at a high possibility, the memory cell array size must be further reduced to decrease the voltage drop amount due to the interconnection resistance r of the word line or bit line.
[0036] For example, overshoot of the potential on the word line or bit line will be examined under the above conditions. The upper limit size of one memory cell array must be decreased from 3 mega (=1.75
kilo.times.1.75 kilo) to 1.5 mega.
[0037] A clamp circuit which clamps the potential of the word line or bit line may be newly arranged as a peripheral circuit of the memory cell array to prevent the overshoot/undershoot phenomenon.
[0038] In this case, however, the size of the peripheral circuits increases as the clamp circuit is added. In addition, the clamp circuit has a function of suppressing abrupt increase/decrease in potential of the word line or bit line. For this reason, changing the potential of the word line or bit line to Vp takes a long time, resulting in a decrease in write speed.
BRIEF SUMMARY OF THE INVENTION
[0039] A magnetic random access memory according to a first example of the present invention comprises a memory cell array having memory cells which utilizes a magnetoresistive effect, a first functional line which runs in a first direction in the memory cell array and is commonly connected to one terminal of each of the memory cells, second functional lines which are arranged in correspondence with the memory cells and run in a second direction perpendicular to the first direction in the memory cell array, and a third functional line which is separated from the memory cells and shared by the memory cells. The other terminal of each of the memory cells is independently connected to one of the second functional lines, and one terminal of each of the memory cells is directly connected to the first functional line.
[0040] A magnetic random access memory according to a second example of the present invention comprises a memory cell array having a memory cell which utilizes a magnetoresistive effect, a first functional line which runs in a first direction in the memory cell array and is connected to one terminal of the memory cell, a second functional line which runs in a second direction perpendicular to the first direction in the memory cell array and is connected to the other terminal of the memory cell, and a third functional line which is separated from the memory cell and generates a magnetic field to write data in the memory cell. One terminal of the memory cell is directly connected to the first functional line, and the other terminal of the memory cell is directly connected to the second functional line.
[0041] A read method of a magnetic random access memory according to a third example of the present invention comprises fixing all the second functional lines to a first potential, setting the first functional line to a second potential different from the second potential, individually supplying a read current to the memory cells, and reading out data from the memory cells on the basis of a value of the read current.
[0042] A write method of a magnetic random access memory according to a fourth example of the present invention comprises supplying a first write current flowing in one direction to one of the second functional lines, supplying a second write current having a direction depending on write data to the third functional line, and writing the write data in one of the memory cells using a magnetic field generated by the first and second write currents.
[0043] A write method of a magnetic random access memory according to a fifth example of the present invention comprises supplying a first write current having a direction depending on write data to one of the second functional lines, supplying a second write current flowing in one direction to the third functional line, and writing the write data in one of the memory cells using a magnetic field generated by the first and second write currents.
[0044] A manufacturing method of a magnetic random access memory according to a sixth example of the present invention comprises the first step of forming a gate electrode of a MOS transistor in a peripheral circuit region and simultaneously forming, in a memory cell array region, dummy interconnections equidistantly, periodically, or in a layout uniform as a whole, the second step of forming a first interlayer dielectric film which covers the MOS transistor and dummy interconnections, the third step of forming a memory cell having a magnetoresistive effect in a surface region of the first interlayer dielectric film in the memory cell array region, and the fourth step of forming a second interlayer dielectric film which covers the memory cell.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0045] FIG. 1 is a circuit diagram showing a magnetic random access memory according to Structural Example 1 of the present invention;
[0046] FIG. 2 is a sectional view showing Device Structure 1 according to Structural Example 1;
[0047] FIG. 3 is a plan view showing Device Structure 1 according to Structural Example 1;
[0048] FIG. 4 is a sectional view showing Device Structure 2 according to Structural Example 1;
[0049] FIG. 5 is a plan view showing Device Structure 2 according to Structural Example 1;
[0050] FIG. 6 is a plan view showing Device Structure 2 according to Structural Example 1;
[0051] FIG. 7 is a plan view showing Device Structure 2 according to Structural Example 1;
[0052] FIG. 8 is a sectional view showing Device Structure 3 according to Structural Example 1;
[0053] FIG. 9 is a plan view showing Device Structure 3 according to Structural Example 1;
[0054] FIG. 10 is a plan view showing Device Structure 3 according to Structural Example 1;
[0055] FIG. 11 is a plan view showing Device Structure 3 according to Structural Example 1;
[0056] FIG. 12 is a plan view showing Device Structure 3 according to Structural Example 1;
[0057] FIG. 13 is a view showing the outline of a magnetic random access memory according to Structural Example 2 of the present invention;
[0058] FIG. 14 is a sectional view showing Device Structure 1 according to Structural Example 2;
[0059] FIG. 15 is a sectional view showing Device Structure 2 according to Structural Example 2;
[0060] FIG. 16 is a circuit diagram showing a magnetic random access memory according to Structural Example 3 of the present invention;
[0061] FIG. 17 is a circuit diagram showing the magnetic random access memory according to Structural Example 3 of the present invention;
[0062] FIG. 18 is a sectional view showing a device structure according to Structural Example 3;
[0063] FIG. 19 is a plan view showing a device structure according to Structural Example 3;
[0064] FIG. 20 is a plan view showing a device structure according to Structural Example 3;
[0065] FIG. 21 is a plan view showing a device structure according to Structural Example 3;
[0066] FIG. 22 is a plan view showing a device structure according to Structural Example 3;
[0067] FIG. 23 is a plan view showing a device structure according to Structural Example 3;
[0068] FIG. 24 is a circuit diagram showing a magnetic random access memory according to Structural Example 4 of the present invention;
[0069] FIG. 25 is a circuit diagram showing the magnetic random access memory according to Structural Example 4 of the present invention;
[0070] FIG. 26 is a sectional view showing a device structure according to Structural Example 4;
[0071] FIG. 27 is a plan view showing a device structure according to Structural Example 4;
[0072] FIG. 28 is a plan view showing a device structure according to Structural Example 4;
[0073] FIG. 29 is a plan view showing a device structure according to Structural Example 4;
[0074] FIG. 30 is a plan view showing a device structure according to Structural Example 4;
[0075] FIG. 31 is a plan view showing a device structure according to Structural Example 4;
[0076] FIG. 32 is a plan view showing a device structure according to Structural Example 4;
[0077] FIG. 33 is a plan view showing a device structure according to Structural Example 4;
[0078] FIG. 34 is a circuit diagram showing a magnetic random access memory according to Structural Example 5 of the present invention;
[0079] FIG. 35 is a circuit diagram showing the magnetic random access memory according to Structural Example 5 of the present invention;
[0080] FIG. 36 is a sectional view showing a device structure according to Structural Example 5;
[0081] FIG. 37 is a plan view showing a device structure according to Structural Example 5;
[0082] FIG. 38 is a plan view showing a device structure according to Structural Example 5;
[0083] FIG. 39 is a plan view showing a device structure according to Structural Example 5;
[0084] FIG. 40 is a plan view showing a device structure according to Structural Example 5;
[0085] FIG. 41 is a plan view showing a device structure according to Structural Example 5;
[0086] FIG. 42 is a plan view showing a device structure according to Structural Example 5;
[0087] FIG. 43 is a plan view showing a device structure according to Structural Example 5;
[0088] FIG. 44 is a circuit diagram showing a magnetic random access memory according to Structural Example 6 of the present invention;
[0089] FIG. 45 is a circuit diagram showing the magnetic random access memory according to Structural Example 6 of the present invention;
[0090] FIG. 46 is a sectional view showing a device structure according to Structural Example 6;
[0091] FIG. 47 is a plan view showing a device structure according to Structural Example 6;
[0092] FIG. 48 is a plan view showing a device structure according to Structural Example 6;
[0093] FIG. 49 is a plan view showing a device structure according to Structural Example 6;
[0094] FIG. 50 is a plan view showing a device structure according to Structural Example 6;
[0095] FIG. 51 is a plan view showing a device structure according to Structural Example 6;
[0096] FIG. 52 is a plan view showing a device structure according to Structural Example 6;
[0097] FIG. 53 is a circuit diagram showing a magnetic random access memory according to Structural Example 7 of the present invention;
[0098] FIG. 54 is a sectional view showing a device structure according to Structural Example 7;
[0099] FIG. 55 is a plan view showing a device structure according to Structural Example 7;
[0100] FIG. 56 is a plan view showing a device structure according to Structural Example 7;
[0101] FIG. 57 is a plan view showing a device structure according to Structural Example 7;
[0102] FIG. 58 is a circuit diagram showing a magnetic random access memory according to Structural Example 8 of the present invention;
[0103] FIG. 59 is a circuit diagram showing a magnetic random access memory according to Structural Example 9 of the present invention;
[0104] FIG. 60 is a sectional view showing a device structure according to Structural Example 10;
[0105] FIG. 61 is a view showing a structural example of an MTJ element;
[0106] FIG. 62 is a view showing a structural example of the MTJ element;
[0107] FIG. 63 is a view showing a structural example of the MTJ element;
[0108] FIG. 64 is a view showing a circuit example of a write word line driver/sinker;
[0109] FIG. 65 is a view showing a circuit example of the write word line driver/sinker;
[0110] FIG. 66 is a view showing a circuit example of a row decoder;
[0111] FIG. 67 is a view showing a circuit example of a column decoder & read column select line driver;
[0112] FIG. 68 is a view showing a circuit example of a write bit line driver/sinker;
[0113] FIG. 69 is a view showing a circuit example of a write bit line driver/sinker;
[0114] FIG. 70 is a view showing a circuit example of a column decoder & write word line driver/sinker;
[0115] FIG. 71 is a view showing a circuit example of a row decoder;
[0116] FIG. 72 is a view showing a circuit example of a write word line driver;
[0117] FIG. 73 is a view showing a circuit example of a row decoder & read line driver;
[0118] FIG. 74 is a circuit diagram showing a magnetic random access memory according to Structural Example 11 of the present invention;
[0119] FIG. 75 is a view showing a circuit example of a write bit line driver/sinker of FIG. 74;
[0120] FIG. 76 is a view showing a circuit example of a write bit line driver/sinker of FIG. 74;
[0121] FIG. 77 is a view showing a circuit example of a read circuit;
[0122] FIG. 78 is a view showing a circuit example of a read circuit;
[0123] FIG. 79 is a view showing a circuit example of a sense amplifier & bit line bias circuit;
[0124] FIG. 80 is a view showing a circuit example of a sense amplifier;
[0125] FIG. 81 is a view showing a circuit example of a reference potential generation circuit;
[0126] FIG. 82 is a view showing a circuit example of an operational amplifier;
[0127] FIG. 83 is a view showing a circuit example of a sense amplifier & bit line bias circuit;
[0128] FIG. 84 is a view showing MTJ elements arranged symmetrically with respect to a write line;
[0129] FIG. 85 is a view showing MTJ elements arranged symmetrically with respect to a write line;
[0130] FIG. 86 is a view showing MTJ elements arranged symmetrically with respect to a write line;
[0131] FIG. 87 is a view showing MTJ elements arranged symmetrically with respect to a write line;
[0132] FIG. 88 is a view showing MTJ elements arranged symmetrically with respect to a write line;
[0133] FIG. 89 is a view showing MTJ elements arranged symmetrically with respect to a write line;
[0134] FIG. 90 is a view showing a circuit example of a write bit line driver/sinker;
[0135] FIG. 91 is a sectional view showing a device structure to which a manufacturing method according to the example of the present invention is applied;
[0136] FIG. 92 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0137] FIG. 93 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0138] FIG. 94 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0139] FIG. 95 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0140] FIG. 96 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0141] FIG. 97 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0142] FIG. 98 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0143] FIG. 99 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0144] FIG. 100 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0145] FIG. 101 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0146] FIG. 102 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0147] FIG. 103 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0148] FIG. 104 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0149] FIG. 105 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0150] FIG. 106 is a sectional view showing a step in manufacturing according to the example of the present invention;
[0151] FIG. 107 is a view showing a problem of a cross-point cell array structure;
[0152] FIG. 108 is a circuit diagram showing a magnetic random access memory according to Modification example of Structural Example 8;
[0153] FIG. 109 is a circuit diagram showing a magnetic random access memory according to Modification example of Structural Example 8;
[0154] FIG. 110 is a circuit diagram showing a magnetic random access memory according to Modification example of Structural Example 8;
[0155] FIG. 111 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0156] FIG. 112 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0157] FIG. 113 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0158] FIG. 114 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0159] FIG. 115 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0160] FIG. 116 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0161] FIG. 117 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0162] FIG. 118 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0163] FIG. 119 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0164] FIG. 120 is a circuit diagram showing a magnetic random access memory according to Structural Example 12 of the present invention;
[0165] FIG. 121 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0166] FIG. 122 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0167] FIG. 123 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0168] FIG. 124 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0169] FIG. 125 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0170] FIG. 126 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0171] FIG. 127 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0172] FIG. 128 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0173] FIG. 129 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0174] FIG. 130 is a circuit diagram showing a magnetic random access memory according to Structural Example 13 of the present invention;
[0175] FIG. 131 is a circuit diagram showing a magnetic random access memory according to Structural Example 14 of the present invention; and
[0176] FIG. 132 is a circuit diagram showing a magnetic random access memory according to Structural Example 15 of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0177] A magnetic random access memory according to an example of the present invention will be described below in detail with reference to the accompanying drawing.
[0178] 1. Cell Array Structure
[0179] The cell array structure of the magnetic random access memory according to the example of the present invention will be described first.
[0180] As a characteristic feature of the cell array structure according to the example of the present invention, in a cell array structure in which one terminal of each of a plurality of MTJ elements which form a read block is commonly connected, and the other terminal is independently connected to a read bit line, one terminal of each of the plurality of MTJ elements is directly connected to a read word line without intervening a read select switch.
[0181] That is, no read select switch (e.g., a MOS transistor) is arranged in the read block. Consequently, a memory cell array can be formed from only MTJ elements.
[0182] According to this cell array structure, no switch element is arranged in the memory cell array. Hence, the density of MTJ elements can be increased, and the underlying layer of the MTJ elements can be planarized (the magnetoresistive value and MR ratio can be uniformed). In addition, since one of two write lines is separated from MTJ elements, no potential difference is generated across an MTJ element in write operation, unlike a cross-point cell array structure. Hence, the tunneling barrier layer of the MTJ element is not broken.
[0183] (1) Structural Example 1
[0184] In Structural Example 1, one read block is formed from four MTJ elements.
[0185] {circle over (1)} Circuit Structure
[0186] The circuit structure will be described first.
[0187] FIG. 1 shows the main part of a magnetic random access memory according to Structural Example 1 of the present invention.
[0188] A memory cell array 11 has a plurality of MTJ elements 12 arranged in an array in the X- and Y-directions. For example, j MTJ elements 12
are arranged in the X-direction, and 4.times.n MTJ elements 12 are arranged in the Y-direction.
[0189] The four MTJ elements 12 arranged in the Y-direction form one read block BKik (i=1, . . . , j, and k=1, . . . , n). One row is constructed by j read blocks BKik arranged in the X-direction. The memory cell array 11 has n rows. In addition, one column is constructed by n read blocks BKik arranged in the Y-direction. The memory cell array 11 has j columns.
[0190] One terminal of each of the four MTJ elements 12 in the block BKik is commonly connected. The connection point is connected to, e.g., a read word line RWLi (i=1, . . . , j). The read word line RWLi runs in the Y-direction. One read word line RWLi is arranged in one column.
[0191] The MTJ elements 12 in the read blocks BKik arranged in one column are directly connected to the read word lines RWLi (i=1, . . . , j) without intervening read select switches (MOS transistors). One end of each read word line RWLi is connected to a ground point VSS through a column select switch CSW formed from, e.g., a MOS transistor.
[0192] The column select switches CSW are arranged outside the memory cell array 11. Hence, no switch elements (MOS transistors) are arranged in the memory cell array 11.
[0193] The other terminal of each of the four MTJ elements 12 in the read block BKik is independently connected to a corresponding one of read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4. That is, the four read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 are arranged in correspondence with the four MTJ elements 12
in one read block BKik.
[0194] The read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 run in the X-direction. One end of each read bit line is connected to a common data line 30 through a row select switch (MOS transistor) RSW2. The common data line 30 is connected to a read circuit 29B (including, e.g., a sense amplifier, selector, and output buffer).
[0195] For example, as shown in FIGS. 111 and 121, the read bit line is connected to a bias transistor BT which sets the bit line potential to VC.
[0196] A row select line signal RLi (i=1, . . . , n) is input to each row select switch RSW2. Row decoders 25-1, . . . , 25-n output the row select line signals RLi.
[0197] As shown in FIG. 111, the bias transistor BT is a PMOS transistor, when the RLi is input to the bias transistor BT. As shown in FIG. 121, the bias transistor BT is a NMOS transistor, when the inverting signal from RLi is input to the bias transistor BT. Row decoders 25-1, . . . , 25-n output the row select line signals RLi and the inverting signal thereof.
[0198] The read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 run in the X-direction and also function as write word lines WWL4(n-1)+1, WWL4(n-1)+2, WWL4(n-1)+3, and WWL4(n-1)+4, respectively.
[0199] One end of each of the write word lines WWL4(n-1)+1, WWL4(n-1)+2, WWL4(n-1)+3, and WWL4(n-1)+4 is connected to a write word line driver 23A through the row select switches RSW2 and common data line 30. The other end of each write word line is connected to a corresponding one of write word line sinkers 24-1, . . . , 24-n.
[0200] One write bit line WBLi (i=1, . . . , j) which is shared by the four MTJ elements 12 of one read block BKik and run in the Y-direction is arranged near the MTJ elements 12 constituting the read block BKik. One write bit line WBLi is arranged in one column.
[0201] One end of each write bit line WBLi is connected to a circuit block 29A including a column decoder and write bit line driver/sinker. The other end is connected to a circuit block 31 including a column decoder and write bit line driver/sinker.
[0202] In write operation, the circuit blocks 29A and 31 are set in an operative state. A write current flows to the write bit lines WBLi in accordance with write data in a direction toward the circuit block 29A or 31.
[0203] In the write operation, the row decoder 25-n selects one of the plurality of rows on the basis of a row address signal. The write word line driver 23A supplies a write current to the write word lines WWL4(n-1)+1, WWL4(n-1)+2, WWL4(n-1)+3, and WWL4(n-1)+4 in the selected row. The write current is absorbed by the write word line sinker 24-n.
[0204] In read operation, the row decoder 25-n selects one of the plurality of rows on the basis of a row address signal. In the read operation, a column decoder 32 selects one of the plurality of columns on the basis of column address signals CSL1, . . . , CSLj to turn on the column select switch CSW arranged in the selected column.
[0205] In the magnetic random access memory according to Structural Example 1, one terminal of each of the plurality of MTJ elements in a read block is commonly connected. The other terminal is connected to a corresponding one of different read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4.
[0206] Hence, data of the plurality of MTJ elements in one read block can be read at once by one read step.
[0207] The read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 also function as the write word lines WWL4(n-1)+1, WWL4(n-1)+2, WWL4(n-1)+3, and WWL4(n-1)+4, respectively. Since no interconnections which exclusively serve as write word lines need be arranged in the cell array, the cell array structure can be simplified.
[0208] As described above, as the characteristic feature of Structural Example 1, a read block has no read select switch for selecting it. In this case, the read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 in an unselected row are biased to same potential to those in a selected row and the write word line WBLj in an unselected column is set in a floating state.
[0209] For this reason, the read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 in all rows are set to the same potentials.
[0210] In Structural Example 1, in the read operation, for example, the potentials of the read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 in the selected row are fixed to identical values. That is, the potentials of the read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 in the selected row are fixed, and a change in read current flowing to the MTJ elements is detected.
[0211] The circuit (clamp circuit) for fixing the potentials of the read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 in the selected row will be described later in detail in association with a read circuit.
[0212] If the read bit lines RBL4(n-1)+1, RBL4(n-1)+2, RBL4(n-1)+3, and RBL4(n-1)+4 in all rows always have the same potential in the read operation, no sneak current flows between the read bit lines through the plurality of unselected MTJ elements and poses no problem in determining the data value of the selected MTJ element.
[0213] In Structural Example 1, since no read select transistor is arranged in the read block, a current path is formed through the MTJ elements in an unselected block in the read operation. However, the resistance value of the MTJ element is sufficiently large. The read current is much smaller than the write current. Hence, an increase in current consumption poses no serious problem.
[0214] In the write operation, when the write current flows to the write word lines WWL4(n-1)+1, WWL4(n-1)+2, WWL4(n-1)+3, and WWL4(n-1)+4 in the selected row, the read word line RWLi is charged through the MTJ elements in the selected row. The read word line RWLi is in the floating state. Hence, it is only charged. No potential difference is generated across the MTJ element.
[0215] {circle over (2)} Device Structure 1
[0216] Device Structure 1 will be described next.
[0217] [1] Sectional Structure
[0218] FIG. 2 shows Device Structure 1 corresponding to one block of the magnetic random access memory according to Structural Example 1 of the present invention.
[0219] The same reference numerals as in FIG. 1 denote the same elements in FIG. 2 to show the correspondence between the elements.
[0220] A read word line RWL1 running in the Y-direction is formed on a semiconductor substrate 41. No switch element is arranged immediately under the read word line RWL1. Four MTJ elements (Magnetic Tunnel Junction elements) MTJ1, MTJ2, MTJ3, and MTJ4 arrayed in the Y-direction are formed above the read word line RWL1.
[0221] One terminal (upper end in this example) of each of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is commonly connected to an upper electrode 44. A contact plug 42 electrically connects the upper electrode 44 to the read word line RWL1.
[0222] The other terminal (lower end in this example) of each of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is electrically connected to a corresponding one of read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4). The read bit lines RBL1, RBL2, RBL3, and RBL4 run in the X-direction (row direction).
[0223] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are independently connected to the read bit lines RBL1, RBL2, RBL3, and RBL4, respectively. That is, the four read bit lines RBL1, RBL2, RBL3, and RBL4 are arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0224] A write bit line WBL1 is formed above and near the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4. The write bit line WBL1 runs in the Y-direction (column direction).
[0225] In Structural Example 1, one write bit line WBL1 is arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4
which construct a read block. Instead, for example, the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 may be stacked, and four write bit lines may be arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0226] In Structural Example 1, the write bit line WBL1 running in the Y-direction is arranged above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, and the read bit lines RBL1, RBL2, RBL3, and RBL4 running in the X-direction are arranged under the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0227] However, the positional relationship of the write bit line WBL1 and read bit lines RBL1, RBL2, RBL3, and RBL4 with respect to the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is not limited to this.
[0228] For example, the write bit line WBL1 running in the Y-direction may be arranged under the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, and the read bit lines RBL1, RBL2, RBL3, and RBL4 running in the X-direction are arranged above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0229] According to this device structure, the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block are electrically connected to the different read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4), respectively. For this reason, data of the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block can be read at once by one read step.
[0230] One terminal of each of the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block is commonly connected. The connection point is directly connected to the read word line RWL1 without intervening a read select switch. In addition, the write bit line WBL1
running in the Y-direction is shared by the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block. For this reason, the degree of integration of MTJ elements can be increased, and their characteristic can be improved.
[0231] [2] Plane Structure
[0232] FIG. 3 shows the positional relationship between the MTJ elements, the read bit lines (write word lines), and the write bit line in the device structure shown in FIG. 2.
[0233] The upper electrode 44 of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 has, e.g., a rectangular shape and has, as a portion, a contact region for the contact plug.
[0234] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are arranged in the Y-direction. Their axis of easy magnetization (a direction parallel to the long sides of the MTJ elements) is the X-direction. That is, each of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 has a rectangular shape long in the X-direction.
[0235] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are arranged in a region where the write bit line WBL1 and the read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4) cross each other.
[0236] {circle over (3)} Device Structure 2
[0237] Device Structure 2 will be described next.
[0238] [1] Sectional Structure
[0239] FIG. 4 shows Device Structure 2 corresponding to one block of the magnetic random access memory according to Structural Example 1 of the present invention.
[0240] The same reference numerals as in FIG. 1 denote the same elements in FIG. 4 to show the correspondence between the elements.
[0241] The read word line RWL1 running in the Y-direction is formed on the semiconductor substrate 41. No switch element is arranged immediately under the read word line RWL1. The four MTJ elements (Magnetic Tunnel Junction elements) MTJ1, MTJ2, MTJ3, and MTJ4 arrayed in the Y-direction are formed above the read word line RWL1.
[0242] One terminal (upper end in this example) of each of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is commonly connected to the upper electrode 44. The contact plug 42 and a conductive layer 43 electrically connect the upper electrode 44 to the read word line RWL1.
[0243] Device Structure 2 is different from Device Structure 1 in the position where the contact plug 42 is formed. More specifically, in Device Structure 1, the contact plug 42 is formed at an end portion in the Y-direction. In Device Structure 2, the contact plug 42 is arranged at the central portion of the upper electrode 44.
[0244] When the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are uniformly arranged to be symmetrical with respect to the contact plug 42, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0245] The conductive layer 43 may be integrated with the upper electrode 44. That is, the conductive layer 43 and upper electrode 44 may be formed simultaneously using the same material.
[0246] The other terminal (lower end in this example) of each of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is electrically connected to a corresponding one of the read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4). The read bit lines RBL1, RBL2, RBL3, and RBL4 run in the X-direction (row direction).
[0247] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are independently connected to the read bit lines RBL1, RBL2, RBL3, and RBL4, respectively. That is, the four read bit lines RBL1, RBL2, RBL3, and RBL4 are arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0248] The write bit line WBL1 is formed above and near the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4. The write bit line WBL1 runs in the Y-direction (column direction).
[0249] In Structural Example 1, one write bit line WBL1 is arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4
which construct a read block. Instead, for example, the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 may be stacked, and four write bit lines may be arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0250] In Structural Example 1, the write bit line WBL1 running in the Y-direction is arranged above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, and the read bit lines RBL1, RBL2, RBL3, and RBL4 running in the X-direction are arranged under the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0251] However, the positional relationship of the write bit line WBL1 and read bit lines RBL1, RBL2, RBL3, and RBL4 with respect to the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is not limited to this.
[0252] For example, the write bit line WBL1 running in the Y-direction may be arranged under the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, and the read bit lines RBL1, RBL2, RBL3, and RBL4 running in the X-direction are arranged above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0253] According to this device structure, the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block are electrically connected to the different read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4), respectively. For this reason, data of the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block can be read at once by one read step.
[0254] One terminal of each of the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block is commonly connected. The connection point is directly connected to the read word line RWL1 without intervening a read select switch. In addition, the write bit line WBL1
running in the Y-direction is shared by the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block. For this reason, the degree of integration of MTJ elements can be increased, and their characteristic can be improved.
[0255] [2] Plane Structure
[0256] FIGS. 5 to 7 show the layouts of the respective interconnection layers in Device Structure 2 shown in FIG. 4. The section shown in FIG. 4
corresponds to the section taken along a line IV-IV in FIGS. 5 to 7.
[0257] FIG. 5 shows the layout of read word lines.
[0258] The read word lines RWL1 run in the Y-direction. The contact plug 42 is arranged on each read word line RWL1.
[0259] FIG. 6 shows the layout of the read bit lines and MTJ elements.
[0260] The read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4) run in the X-direction. The interval between the read bit lines RBL1, RBL2, RBL3, and RBL4 can be set to, e.g., the minimum size (or design rule) processible by photolithography.
[0261] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are arranged on the read bit lines RBL1, RBL2, RBL3, and RBL4, respectively. The axis of easy magnetization of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, i.e., the direction parallel to the long sides of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is the X-direction.
[0262] The read bit line RBL1 is commonly connected to the MTJ elements MTJ1 arranged in the X-direction. The read bit line RBL2 is commonly connected to the MTJ elements MTJ2 arranged in the X-direction. The read bit line RBL3 is commonly connected to the MTJ elements MTJ3 arranged in the X-direction. The read bit line RBL4 is commonly connected to the MTJ elements MTJ4 arranged in the X-direction.
[0263] The conductive layer 43 is arranged on the contact plug 42.
[0264] FIG. 7 shows the layout of write bit lines.
[0265] The upper electrode 44 having a rectangular pattern is arranged on the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 and conductive layer 43. The upper electrode 44 are in contact with the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 and conductive layer 43.
[0266] The write bit lines WBL1 are arranged immediately on the upper electrodes 44. The write bit lines WBL1 run in the Y-direction.
[0267] {circle over (4)} Device Structure 3
[0268] Device Structure 3 will be described next.
[0269] [1] Sectional Structure
[0270] FIG. 8 shows Device Structure 3 corresponding to one block of the magnetic random access memory according to Structural Example 1 of the present invention.
[0271] The same reference numerals as in FIG. 1 denote the same elements in FIG. 8 to show the correspondence between the elements.
[0272] The write bit line WBL1 running in the Y-direction is formed on the semiconductor substrate 41. No switch element is arranged immediately under the write bit line WBL1. A lower electrode 44 having, e.g., a rectangular pattern is formed above the write bit line WBL1.
[0273] The four MTJ elements (Magnetic Tunnel Junction elements) MTJ1, MTJ2, MTJ3, and MTJ4 arrayed in the Y-direction are formed on the lower electrode 44.
[0274] The read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4) are formed on the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, respectively. The read bit lines RBL1, RBL2, RBL3, and RBL4 are in contact with the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, respectively. The read bit lines RBL1, RBL2, RBL3, and RBL4 run in the X-direction (row direction).
[0275] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are independently connected to the read bit lines RBL1, RBL2, RBL3, and RBL4, respectively. That is, the four read bit lines RBL1, RBL2, RBL3, and RBL4 are arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0276] The contact plug 42 and conductive layer 43 are formed on the lower electrode 44. The contact plug 42 and conductive layer 43 electrically connect the lower electrode 44 to the read word line RWL1.
[0277] The contact plug 42 is arranged at the central portion of the lower electrode 44. When the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are uniformly arranged to be symmetrical with respect to the contact plug 42, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0278] The read word line RWL1 is formed above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4. The read word line RWL1 runs in the Y-direction (column direction).
[0279] In Structural Example 1, one write bit line WBL1 is arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4
which construct a read block. Instead, for example, the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 may be stacked, and four write bit lines may be arranged in correspondence with the four MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0280] In Structural Example 1, the write bit line WBL1 running in the Y-direction is arranged under the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, and the read bit lines RBL1, RBL2, RBL3, and RBL4 running in the X-direction are arranged above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0281] However, the positional relationship of the write bit line WBL1 and read bit lines RBL1, RBL2, RBL3, and RBL4 with respect to the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is not limited to this.
[0282] For example, the write bit line WBL1 running in the Y-direction may be arranged above the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, and the read bit lines RBL1, RBL2, RBL3, and RBL4 running in the X-direction are arranged under the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4.
[0283] According to this device structure, the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block are electrically connected to the different read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4), respectively. For this reason, data of the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block can be read at once by one read step.
[0284] One terminal of each of the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block is commonly connected. The connection point is directly connected to the read word line RWL1 without intervening a read select switch. In addition, the write bit line WBL1
running in the Y-direction is shared by the plurality of MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 in the read block. For this reason, the degree of integration of MTJ elements can be increased, and their characteristic can be improved.
[0285] Furthermore, the contact portion between the lower electrode 44 and the read word line RWL1 is formed in the region between the MTJ elements MTJ1 and MTJ2 and the MTJ elements MTJ3 and MTJ4. When the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 are uniformly arranged to be symmetrical with respect to the contact portion of the lower electrode 44, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0286] [2] Plane Structure
[0287] FIGS. 9 to 12 show the layouts of the respective interconnection layers in Device Structure 3 shown in FIG. 8. The section shown in FIG. 8
corresponds to the section taken along a line VIII-VIII in FIGS. 9 to 12.
[0288] FIG. 9 shows the layout of write bit lines.
[0289] The write bit lines WBL1 run in the Y-direction. The lower electrode 44 having a rectangular shape is arranged on each write bit line WBL1.
[0290] FIG. 10 shows the layout of MTJ elements.
[0291] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 and conductive layer 43
are arranged on the lower electrode 44 having a rectangular pattern.
[0292] The MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 on the lower electrode 44 are arranged in the Y-direction. The axis of easy magnetization of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, i.e., the direction parallel to the long sides of the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4 is the X-direction.
[0293] FIG. 11 shows the layout of read bit lines.
[0294] The read bit lines RBL1, RBL2, RBL3, and RBL4 (write word lines WWL1, WWL2, WWL3, and WWL4) are arranged on the MTJ elements MTJ1, MTJ2, MTJ3, and MTJ4, respectively.
[0295] The read bit lines RBL1, RBL2, RBL3, and RBL4 run in the X-direction. The interval between the read bit lines RBL1, RBL2, RBL3, and RBL4 can be set to, e.g., the minimum size (or design rule) processible by photolithography.
[0296] The read bit line RBL1 is commonly connected to the MTJ elements MTJ1 arranged in the X-direction. The read bit line RBL2 is commonly connected to the MTJ elements MTJ2 arranged in the X-direction. The read bit line RBL3 is commonly connected to the MTJ elements MTJ3 arranged in the X-direction. The read bit line RBL4 is commonly connected to the MTJ elements MTJ4 arranged in the X-direction.
[0297] The contact plug 42 is arranged on the conductive layer 43.
[0298] FIG. 12 shows the layout of read word lines.
[0299] The read word lines RWL1 run in the Y-direction. The read word line RWL1 is in contact with the contact plug 42.
[0300] (2) Structural Example 2
[0301] {circle over (1)} Outline
[0302] FIG. 13 shows the outline of a magnetic random access memory according to Structural Example 2 of the present invention.
[0303] The same reference numerals as in FIG. 1 denote the same elements in FIG. 13 to show the correspondence between the elements.
[0304] As a characteristic feature of Structural Example 2, a plurality of stages of memory cell arrays 11-1, 11-2, . . . , 11-m according to Structural Example 1 are stacked on a semiconductor substrate (chip) 10. Each of the memory cell arrays 11-1, 11-2, . . . , 11-m corresponds to the memory cell array 11 shown in FIG. 1.
[0305] {circle over (2)} Device Structure 1
[0306] In Device Structure 1 of Structural Example 2, a plurality of stages of memory cell arrays in Device Structure 2 (FIG. 4) of Structural Example 1 are stacked.
[0307] FIG. 14 shows Device Structure 1 corresponding to one block of the magnetic random access memory according to Structural Example 2 of the present invention.
[0308] [1] First Stage (Memory Cell Array 11-1)
[0309] A read word line RWL1-1 running in the Y-direction is formed on a semiconductor substrate 41. No switch element is arranged immediately under the read word line RWL1-1. Four MTJ elements (Magnetic Tunnel Junction elements) MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 arrayed in the Y-direction are formed above the read word line RWL1-1.
[0310] One terminal (upper end in this example) of each of the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 is commonly connected to an upper electrode 44-1. A contact plug 42-1 and conductive layer 43-1
electrically connect the upper electrode 44-1 to the read word line RWL1-1.
[0311] The contact plug 42-1 is arranged at the central portion of the upper electrode 44-1. When the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are uniformly arranged to be symmetrical with respect to the contact plug 42-1, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0312] The conductive layer 43-1 may be integrated with the upper electrode 44-1. That is, the conductive layer 43-1 and upper electrode 44-1 may be formed simultaneously using the same material.
[0313] The other terminal (lower end in this example) of each of the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 is electrically connected to a corresponding one of read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1
(write word lines WWL1-1, WWL2-1, WWL3-1, and WWL4-1). The read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 run in the X-direction (row direction).
[0314] The MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are independently connected to the read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1, respectively. That is, the four read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 are arranged in correspondence with the four MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1.
[0315] A write bit line WBL1-1 is formed above and near the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1. The write bit line WBL1-1 runs in the Y-direction (column direction).
[0316] [2] Second Stage (Memory Cell Array 11-2)
[0317] A read word line RWL1-2 running in the Y-direction is formed on the write bit line WBL1-1 in the memory cell array 11-1 of the first stage. Four MTJ elements (Magnetic Tunnel Junction elements) MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 arrayed in the Y-direction are formed above the read word line RWL1-2.
[0318] One terminal (upper end in this example) of each of the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 is commonly connected to an upper electrode 44-2. A contact plug 42-2 and conductive layer 43-2
electrically connect the upper electrode 44-2 to the read word line RWL1-2.
[0319] The contact plug 42-2 is arranged at the central portion of the upper electrode 44-2. When the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are uniformly arranged to be symmetrical with respect to the contact plug 42-2, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0320] The conductive layer 43-2 may be integrated with the upper electrode 44-2. That is, the conductive layer 43-2 and upper electrode 44-2 may be formed simultaneously using the same material.
[0321] The other terminal (lower end in this example) of each of the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 is electrically connected to a corresponding one of read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2
(write word lines WWL1-2, WWL2-2, WWL3-2, and WWL4-2). The read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 run in the X-direction (row direction).
[0322] The MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are independently connected to the read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2, respectively. That is, the four read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 are arranged in correspondence with the four MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2.
[0323] A write bit line WBL1-2 is formed above and near the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2. The write bit line WBL1-2 runs in the Y-direction (column direction).
[0324] [3] Others
[0325] Referring to FIG. 14, the memory cell arrays 11-1 and 11-2
according to Device Structure 2 of the Structural Example 1 are stacked in two stages on the semiconductor substrate 41. In principle, the memory cell arrays may be stacked in three or more stages (there is no upper limit).
[0326] According to Device Structure 1 of Structural Example 2, a plurality of stages of memory cell arrays according to Device Structure 2
of Structural Example 1 are stacked on the semiconductor substrate. For this reason, the density of MTJ elements can be increased.
[0327] {circle over (3)} Device Structure 2
[0328] In Device Structure 2 of Structural Example 2, a plurality of stages of memory cell arrays in Device Structure 3 (FIG. 8) of Structural Example 1 are stacked.
[0329] FIG. 15 shows Device Structure 2 corresponding to one block of the magnetic random access memory according to Structural Example 2 of the present invention.
[0330] [1] First Stage (Memory Cell Array 11-1)
[0331] The write bit line WBL1-1 running in the Y-direction is formed on the semiconductor substrate 41. No switch element is arranged immediately under the write bit line WBL1-1. A lower electrode 44-1 having, e.g., a rectangular pattern is formed above the write bit line WBL1-1.
[0332] The four MTJ elements (Magnetic Tunnel Junction elements) MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 arrayed in the Y-direction are formed on the lower electrode 44-1.
[0333] The read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 (write word lines WWL1-1, WWL2-1, WWL3-1, and WWL4-1) are formed on the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1, respectively. The read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 are in contact with the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1, respectively. The read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 run in the X-direction (row direction).
[0334] The MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are independently connected to the read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1, respectively. That is, the four read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 are arranged in correspondence with the four MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1.
[0335] The contact plug 42-1 and conductive layer 43-1 are formed on the lower electrode 44-1. The contact plug 42-1 and conductive layer 43-1
electrically connect the lower electrode 44-1 to the read word line RWL1-1.
[0336] The contact plug 42-1 is arranged at the central portion of the lower electrode 44-1. When the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are uniformly arranged to be symmetrical with respect to the contact plug 42-1, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0337] The read word line RWL1-1 is formed above the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1. The read word line RWL1-1 runs in the Y-direction (column direction).
[0338] [2] Second Stage (Memory Cell Array 11-2)
[0339] The write bit line WBL1-2 running in the Y-direction is formed on the semiconductor substrate 41. No switch element is arranged immediately under the write bit line WBL1-2. A lower electrode 44-2 having, e.g., a rectangular pattern is formed above the write bit line WBL1-2.
[0340] The four MTJ elements (Magnetic Tunnel Junction elements) MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 arrayed in the Y-direction are formed on the lower electrode 44-2.
[0341] The read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 (write word lines WWL1-2, WWL2-2, WWL3-2, and WWL4-2) are formed on the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2, respectively. The read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 are in contact with the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2, respectively. The read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 run in the X-direction (row direction).
[0342] The MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are independently connected to the read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2, respectively. That is, the four read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 are arranged in correspondence with the four MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2.
[0343] The contact plug 42-2 and conductive layer 43-2 are formed on the lower electrode 44-2. The contact plug 42-2 and conductive layer 43-2
electrically connect the lower electrode 44-2 to the read word line RWL1-2.
[0344] The contact plug 42-2 is arranged at the central portion of the lower electrode 44-2. When the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are uniformly arranged to be symmetrical with respect to the contact plug 42-2, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0345] The read word line RWL1-2 is formed above the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2. The read word line RWL1-2 runs in the Y-direction (column direction).
[0346] [3] Others
[0347] Referring to FIG. 15, the memory cell arrays 11-1 and 11-2
according to Device Structure 3 of the Structural Example 1 are stacked in two stages on the semiconductor substrate 41. In principle, the memory cell arrays may be stacked in three or more stages (there is no upper limit).
[0348] According to Device Structure 2 of Structural Example 2, a plurality of stages of memory cell arrays according to Device Structure 3
of Structural Example 1 are stacked on the semiconductor substrate. For this reason, the density of MTJ elements can be increased.
[0349] (3) Structural Example 3
[0350] {circle over (1)} Outline
[0351] Structural Example 3 is an improvement of Structural Example 2. In Structural Example 2, the plurality of stages of the memory cell arrays 11-1, 11-2, . . . , 11-m according to Structural Example 1 are stacked on the semiconductor substrate (chip).
[0352] Even in Structural Example 3, a plurality of stages of memory cell arrays according to Structural Example 1 are stacked on a semiconductor substrate (chip). In Structural Example 3, the number of interconnections in the memory cell arrays is decreased to planarize the underlying layer of MTJ elements (improve the characteristic of MTJ elements). For this purpose, one interconnection is shared by memory cell arrays of different stages.
[0353] {circle over (2)} Circuit Structure
[0354] In Structural Example 3, in a plurality of stages of memory cell arrays 11-1, 11-2, . . . , 11-m stacked, as shown in FIG. 13, the write bit line of the memory cell array of the lower stage and the read word line of the memory cell array of the upper stage are integrated and shared as one write bit line/read word line.
[0355] FIGS. 16 and 17 show the main part of a magnetic random access memory according to Structural Example 3 of the present invention.
[0356] [1] First Stage (Lower Stage)
[0357] FIG. 16 shows the cell array structure of the first stage of Structural Example 3.
[0358] The memory cell array 11-1 has a plurality of MTJ elements 12
arranged in an array in the X- and Y-directions. For example, j MTJ elements 12 are arranged in the X-direction, and 4.times.n MTJ elements 12 are arranged in the Y-direction.
[0359] The four MTJ elements 12 arranged in the Y-direction form one read block BKik (i=1, . . . , j, and k=1, . . . , n). One row is constructed by j read blocks BKik arranged in the X-direction. The memory cell array 11 has n rows. In addition, one column is constructed by n read blocks BKik arranged in the Y-direction. The memory cell array 11-1 has j columns.
[0360] One terminal of each of the four MTJ elements 12 in the block BKik is commonly connected. The connection point is connected to, e.g., a read word line RWLi-1 (i=1, . . . , j). The read word line RWLi-1 runs in the Y-direction. One read word line RWLi-1 is arranged in one column.
[0361] The MTJ elements 12 in the read blocks BKik arranged in one column are directly connected to the read word lines RWLi-1 (i=1, . . . , j) without intervening read select switches (MOS transistors). One end of each read word line RWLi-1 is connected to a ground point VSS through a column select switch CSW formed from, e.g., a MOS transistor.
[0362] The column select switches CSW are arranged outside the memory cell array 11-1. Hence, no switch elements (MOS transistors) are arranged in the memory cell array 11-1.
[0363] The other terminal of each of the four MTJ elements 12 in the read block BKik is independently connected to a corresponding one of read bit lines RBL{4(n-1)+1}-1, RBL{4(n-1)+2}-1, RBL{4(n-1)+3}-1, and RBL{4(n-1)+4}-1. That is, the four read bit lines RBL{4(n-1)+1}-1, RBL{4(n-1)+2}-1, RBL{4(n-1)+3}-1, and RBL{4(n-1)+4}-1 are arranged in correspondence with the four MTJ elements 12 in one read block BKik.
[0364] The read bit lines RBL{4(n-1)+1}-1, RBL{4(n-1)+2}-1, RBL{4(n-1)+3}-1, and RBL{4(n-1)+4}-1 run in the X-direction. One end of each read bit line is connected to a common data line 30(1) through a row select switch (MOS transistor) RSW2. The common data line 30(1) is connected to a read circuit 29B(1) (including, e.g., a sense amplifier, selector, and output buffer).
[0365] For example, as shown in FIGS. 112 and 122, the read bit line is connected to a bias transistor BT which sets the bit line potential to VC.
[0366] A row select line signal RLi (i=1, . . . , n) is input to each row select switch RSW2. Row decoders 25(1)-1, . . . , 25(1)-n output the row select line signals RLi.
[0367] As shown in FIG. 112, the bias transistor BT is a PMOS transistor, when the RLi is input to the bias transistor BT. As shown in FIG. 122, the bias transistor BT is a NMOS transistor, when the inverting signal from RLi is input to the bias transistor BT. Row decoders 25(1)-1, . . . , 25(1)-n output the row select line signals RLi and the inverting signal thereof.
[0368] The read bit lines RBL{4(n-1)+1}-1, RBL{4(n-1)+2}-1, RBL{4(n-1)+3}-1, and RBL{4(n-1)+4}-1 run in the X-direction and also function as write word lines WWL{4(n-1)+1}-1, WWL{4(n-1)+2}-1, WWL{4(n-1)+3}-1, and WWL{4(n-1)+4}-1, respectively.
[0369] One end of each of the write word lines WWL{4(n-1)+1}-1, WWL{4(n-1)+2}-1, WWL{4(n-1)+3}-1, and WWL{4(n-1)+4}-1 is connected to a write word line driver 23A(1) through the row select switches RSW2 and common data line 30(1). The other end of each write word line is connected to a corresponding one of write word line sinkers 24(1)-1, . . . , 24(1)-n.
[0370] One write bit line WBLi-1 (i=1, . . . , j) which is shared by the four MTJ elements 12 of one read block BKik and run in the Y-direction is arranged near the MTJ elements 12 constituting the read block BKik. One write bit line WBLi-1 is arranged in one column.
[0371] One end of each write bit line WBLi-1 is connected to a circuit block 29A(1) including a column decoder and write bit line driver/sinker through a switching circuit 22. The other end of the write bit line WBLi-1 is connected to a circuit block 31(1) including a column decoder and write bit line driver/sinker through a disconnecting circuit 21.
[0372] The disconnecting circuit 21 and switching circuit 22 are controlled by a memory cell array select signal SEL. In write operation, when the memory cell array 11-1 of the first stage (lower stage) is selected, the switching circuit 22 electrically connects one end of the write bit line WBLi-1 to the circuit block 29A(1). The disconnecting circuit 21 electrically connects the other end of the write bit line WBLi-1 to the circuit block 31(1).
[0373] In the write operation, the circuit blocks 29A(1) and 31(1) are set in an operative state. A write current flows to the write bit lines WBLi-1 in accordance with write data in a direction toward the circuit block 29A(1) or 31(1).
[0374] In the write operation, the row decoder 25(1)-n selects one of the plurality of rows on the basis of a row address signal. The write word line driver 23A(1) supplies a write current to the write word lines WWL{4(n-1)+1}-1, WWL{4(n-1)+2}-1, WWL{4(n-1)+3}-1, and WWL{4(n-1)+4}-1 in the selected row. The write current is absorbed by the write word line sinker 24(1)-n.
[0375] In read operation, the row decoder 25(1)-n selects one of the plurality of rows on the basis of a row address signal. In the read operation, a column decoder 32(1) selects one of the plurality of columns on the basis of column address signals CSL1, . . . , CSLj to turn on the column select switch CSW arranged in the selected column.
[0376] [2] Second Stage (Upper Stage)
[0377] FIG. 17 shows the cell array structure of the second stage of Structural Example 3.
[0378] The memory cell array 11-2 has the plurality of MTJ elements 12
arranged in an array in the X- and Y-directions. For example, j MTJ elements 12 are arranged in the X-direction, and 4.times.n MTJ elements 12 are arranged in the Y-direction.
[0379] The four MTJ elements 12 arranged in the Y-direction form one read block BKik (i=1, . . . , j, and k=1, . . . , n). One row is constructed by j read blocks BKik arranged in the X-direction. The memory cell array 11 has n rows. In addition, one column is constructed by n read blocks BKik arranged in the Y-direction. The memory cell array 11-2 has j columns.
[0380] One terminal of each of the four MTJ elements 12 in the block BKik is commonly connected. The connection point is connected to, e.g., a read word line RWLi-2 (i=1, . . . , j). The read word line RWLi-2 runs in the Y-direction. One read word line RWLi-2 is arranged in one column.
[0381] The MTJ elements 12 in the read blocks BKik arranged in one column are directly connected to the read word lines RWLi-2 (i=1, . . . , j) without intervening read select switches (MOS transistors). One end of each read word line RWLi-2 is connected to the ground point VSS through the column select switch CSW formed from the switching circuit 22 and a MOS transistor.
[0382] The other end of the read word line RWLi-2 is connected to the circuit block 31(1) including a column decoder and write bit line driver/sinker through the disconnecting circuit 21.
[0383] The disconnecting circuit 21, switching circuit 22, and column select switches CSW are arranged outside the memory cell array 11-2. Hence, no switch elements (MOS transistors) are arranged in the memory cell array 11-2.
[0384] The disconnecting circuit 21 and switching circuit 22 are the disconnecting circuit 21 and switching circuit 22 in the cell array structure of the memory cell array of the first stage shown in FIG. 16.
[0385] The disconnecting circuit 21 and switching circuit 22 are controlled by the memory cell array select signal SEL.
[0386] As described above, in the write operation, when the memory cell array 11-1 of the first stage (lower stage) is selected, the switching circuit 22 electrically connects one end of the write bit line WBLi-1 to the circuit block 29A(1). The disconnecting circuit 21 electrically connects the other end of the write bit line WBLi-1 to the circuit block 31(1).
[0387] In the read operation, when the memory cell array 11-2 of the second stage (upper stage) is selected, the switching circuit 22
electrically connects one end of the read word line RWLi-2 to the column select switch CSW. The disconnecting circuit 21 electrically disconnects the other end of the read word line RWLi-2 from the circuit block 31(1).
[0388] The other terminal of each of the four MTJ elements 12 in the read block BKik is independently connected to a corresponding one of read bit lines RBL{4(n-1)+1}-2, RBL{4(n-1)+2}-2, RBL{4(n-1)+3}-2, and RBL{4(n-1)+4}-2. That is, the four read bit lines RBL{4(n-1)+1}-2, RBL{4(n-1)+2}-2, RBL{4(n-1)+3}-2, and RBL{4(n-1)+4}-2 are arranged in correspondence with the four MTJ elements 12 in one read block BKik.
[0389] The read bit lines RBL{4(n-1)+1}-2, RBL{4(n-1)+2}-2, RBL{4(n-1)+3}-2, and RBL{4(n-1)+4}-2 run in the X-direction. One end of each read bit line is connected to a common data line 30(2) through a row select switch (MOS transistor) RSW2. The common data line 30(2) is connected to a read circuit 29B(2) (including, e.g., a sense amplifier, selector, and output buffer).
[0390] For example, as shown in FIGS. 113 and 123, the read bit line is connected to a bias transistor BT which sets the bit line potential to VC.
[0391] A row select line signal RLi (i=1, . . . , n) is input to each row select switch RSW2. Row decoders 25(2)-1, . . . , 25(2)-n output the row select line signals RLi.
[0392] As shown in FIG. 113, the bias transistor BT is a PMOS transistor, when the RLi is input to the bias transistor BT. As shown in FIG. 123, the bias transistor BT is a NMOS transistor, when the inverting signal from RLi is input to the bias transistor BT. Row decoders 25(2)-1, . . . , 25(2)-n output the row select line signals RLi and the inverting signal thereof.
[0393] The read bit lines RBL{4(n-1)+1}-2, RBL{4(n-1)+2}-2, RBL{4(n-1)+3}-2, and RBL{4(n-1)+4}-2 run in the X-direction and also function as write word lines WWL{4(n-1)+1}-2, WWL{4(n-1)+2}-2, WWL{4(n-1)+3}-2, and WWL{4(n-1)+4}-2, respectively.
[0394] One end of each of the write word lines WWL{4(n-1)+1}-2, WWL{4(n-1)+2}-2, WWL{4(n-1)+3}-2, and WWL{4(n-1)+4}-2 is connected to a write word line driver 23A(2) through the row select switches RSW2 and common data line 30(2). The other end of each write word line is connected to a corresponding one of write word line sinkers 24(2)-1, . . . , 24(2)-n.
[0395] One write bit line WBLi-2 (i=1, . . . , j) which is shared by the four MTJ elements 12 of one read block BKik and run in the Y-direction is arranged near the MTJ elements 12 constituting the read block BKik. One write bit line WBLi-2 is arranged in one column.
[0396] One end of each write bit line WBLi-2 is connected to a circuit block 29A(2) including a column decoder and write bit line driver/sinker. The other end of the write bit line WBLi-2 is connected to a circuit block 31(2) including a column decoder and write bit line driver/sinker.
[0397] In the write operation, the circuit blocks 29A(2) and 31(2) are set in an operative state. A write current flows to the write bit lines WBLi-2 in accordance with write data in a direction toward the circuit block 29A(2) or 31(2).
[0398] In the write operation, the row decoder 25(2)-n selects one of the plurality of rows on the basis of a row address signal. The write word line driver 23A(2) supplies a write current to the write word lines WWL{4(n-1)+1}-2, WWL{4(n-1)+2}-2, WWL{4(n-1)+3}-2, and WWL{4(n-1)+4}-2 in the selected row. The write current is absorbed by the write word line sinker 24(2)-n.
[0399] In the read operation, the row decoder 25(2)-n selects one of the plurality of rows on the basis of a row address signal. In the read operation, a column decoder 32(2) selects one of the plurality of columns on the basis of column address signals CSL1, . . . , CSLj to turn on the column select switch CSW arranged in the selected column.
[0400] {circle over (3)} Device Structure (Sectional Structure)
[0401] As a characteristic feature of the device structure of Structural Example 3, in the memory cell array of Device Structure 1 (FIG. 14) of Structural Example 2, a write bit line WBL1-1 of the lower stage (first stage) and a read word line RWL1-2 of the upper stage (second stage) are integrated and shared as one write bit line/read word line WBL1-1/RWL1-2.
[0402] FIG. 18 shows a device structure corresponding to one block of the magnetic random access memory according to Structural Example 3 of the present invention.
[0403] [1] First Stage (Memory Cell Array 11-1)
[0404] The read word line RWL1-1 running in the Y-direction is formed on a semiconductor substrate 41. No switch element is arranged immediately under the read word line RWL1-1. Four MTJ elements (Magnetic Tunnel Junction elements) MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 arrayed in the Y-direction are formed above the read word line RWL1-1.
[0405] One terminal (upper end in this example) of each of the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 is commonly connected to an upper electrode 44-1. A contact plug 42-1 and conductive layer 43-1
electrically connect the upper electrode 44-1 to the read word line RWL1-1.
[0406] The contact plug 42-1 is arranged at the central portion of the upper electrode 44-1. When the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are uniformly arranged to be symmetrical with respect to the contact plug 42-1, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0407] The conductive layer 43-1 may be integrated with the upper electrode 44-1. That is, the conductive layer 43-1 and upper electrode 44-1 may be formed simultaneously using the same material.
[0408] The other terminal (lower end in this example) of each of the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 is electrically connected to a corresponding one of read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1
(write word lines WWL1-1, WWL2-1, WWL3-1, and WWL4-1). The read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 run in the X-direction (row direction).
[0409] The MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are independently connected to the read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1, respectively. That is, the four read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 are arranged in correspondence with the four MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1.
[0410] A write bit line WBL1-1 is formed above and near the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1. The write bit line WBL1-1 runs in the Y-direction (column direction).
[0411] [2] Second Stage (Memory Cell Array 11-2)
[0412] The write bit line WBL1-1 in the memory cell array 11-1 of the first stage also functions as the read word line RWL1-2 in the memory cell array 11-2 of the second stage.
[0413] More specifically, in the write operation, when the memory cell array 11-1 of the first stage is selected, the write bit line/read word line WBL1-1/RWL1-2 are used as the write bit line WBL1-1. In the read operation, when the memory cell array 11-2 of the second stage is selected, the write bit line/read word line WBL1-1/RWL1-2 is used as the read word line RWL1-2.
[0414] Four MTJ elements (Magnetic Tunnel Junction elements) MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 arrayed in the Y-direction are formed above the read word line RWL1-2.
[0415] One terminal (upper end in this example) of each of the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 is commonly connected to an upper electrode 44-2. A contact plug 42-2 and conductive layer 43-2
electrically connect the upper electrode 44-2 to the read word line RWL1-2.
[0416] The contact plug 42-2 is arranged at the central portion of the upper electrode 44-2. When the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are uniformly arranged to be symmetrical with respect to the contact plug 42-2, signal margin in the read operation due to the interconnection resistance or the like can be maximized.
[0417] The conductive layer 43-2 may be integrated with the upper electrode 44-2. That is, the conductive layer 43-2 and upper electrode 44-2 may be formed simultaneously using the same material.
[0418] The other terminal (lower end in this example) of each of the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 is electrically connected to a corresponding one of read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2
(write word lines WWL1-2, WWL2-2, WWL3-2, and WWL4-2). The read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 run in the X-direction (row direction).
[0419] The MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are independently connected to the read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2, respectively. That is, the four read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 are arranged in correspondence with the four MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2.
[0420] A write bit line WBL1-2 is formed above and near the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2. The write bit line WBL1-2 runs in the Y-direction (column direction).
[0421] [3] Others
[0422] In the example shown in FIG. 18, the memory cell arrays 11-1 and 11-2 are stacked in two stages on the semiconductor substrate 41. In principle, the memory cell arrays may be stacked in three or more stages (there is no upper limit).
[0423] According to the device structure of Structural Example 3, the memory cell array 11-1 of the lower stage and the memory cell array 11-2
of the upper stage according to Device Structure 1 of Structural Example 2 share one interconnection. For this reason, the density of MTJ elements can be increased. In addition, the underlying layer of the MTJ elements can be planarized (the characteristic of the MTJ elements can be improved).
[0424] {circle over (4)} Device Structure (Plane Structure)
[0425] FIGS. 19 to 23 show the layouts of the respective interconnection layers in Device Structure 1 shown in FIG. 18. The section shown in FIG. 18 corresponds to the section taken along a line XVIII-XVIII in FIGS. 19
to 23.
[0426] FIG. 19 shows the layout of read word lines of the first stage.
[0427] The read word lines RWL1-1 run in the Y-direction. The contact plug 42-1 is arranged on each read word line RWL1-1.
[0428] FIG. 20 shows the layout of read bit lines of the first stage and MTJ elements of the first stage.
[0429] The read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1 (write word lines WWL1-1, WWL2-1, WWL3-1, and WWL4-1) run in the X-direction. The interval between the read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1
can be set to, e.g., the minimum size (or design rule) processible by photolithography.
[0430] The MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 are arranged on the read bit lines RBL1-1, RBL2-1, RBL3-1, and RBL4-1. The axis of easy magnetization of the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1, i.e., the direction parallel to the long sides of the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 is the X-direction.
[0431] The read bit line RBL1-1 is commonly connected to the MTJ elements MTJ1-1 arranged in the X-direction. The read bit line RBL2-1 is commonly connected to the MTJ elements MTJ2-1 arranged in the X-direction. The read bit line RBL3-1 is commonly connected to the MTJ elements MTJ3-1
arranged in the X-direction. The read bit line RBL4-1 is commonly connected to the MTJ elements MTJ4-1 arranged in the X-direction.
[0432] The conductive layer 43-1 is arranged on the contact plug 42-1.
[0433] FIG. 21 shows the layout of write bit lines of the first stage/read word lines of the second stage.
[0434] The upper electrodes 44-1 each having a rectangular pattern are arranged on the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 and conductive layers 43. The upper electrodes 44-1 are in contact with the MTJ elements MTJ1-1, MTJ2-1, MTJ3-1, and MTJ4-1 and conductive layers 43-1.
[0435] The write bit lines/read word lines WBL1-1/RWL1-2 are arranged immediately on the upper electrodes 44-1. The write bit lines/read word lines WBL1-1/RWL1-2 run in the Y-direction.
[0436] The contact plug 42-2 is arranged on each write bit lines/read word lines WBL1-1/RWL1-2.
[0437] FIG. 22 shows the layout of read bit lines of the second stage and MTJ elements of the second stage.
[0438] The read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2 (write word lines WWL1-2, WWL2-2, WWL3-2, and WWL4-2) run in the X-direction. The interval between the read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2
can be set to, e.g., the minimum size (or design rule) processible by photolithography.
[0439] The MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 are arranged on the read bit lines RBL1-2, RBL2-2, RBL3-2, and RBL4-2. The axis of easy magnetization of the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2, i.e., the direction parallel to the long sides of the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 is the X-direction.
[0440] The read bit line RBL1-2 is commonly connected to the MTJ elements MTJ1-2 arranged in the X-direction. The read bit line RBL2-2 is commonly connected to the MTJ elements MTJ2-2 arranged in the X-direction. The read bit line RBL3-2 is commonly connected to the MTJ elements MTJ3-2
arranged in the X-direction. The read bit line RBL4-2 is commonly connected to the MTJ elements MTJ4-2 arranged in the X-direction.
[0441] The conductive layer 43-2 is arranged on the contact plug 42-2.
[0442] FIG. 23 shows the layout of write bit lines of the second stage.
[0443] The upper electrodes 44-2 each having a rectangular pattern are arranged on the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 and conductive layer 43-2. The upper electrodes 44-2 are in contact with the MTJ elements MTJ1-2, MTJ2-2, MTJ3-2, and MTJ4-2 and conductive layers 43-2.
[0444] The write bit lines WBL1-2 are arranged immediately on the upper electrodes 44-2. The write bit lines WBL1-2 run in the Y-direction.
[0445] (4) Structural Example 4
[0446] {circle over (1)} Outline
[0447] Structural Example 4 is also an improvement of Structural Example 2. In Structural Example 4, a plurality of stages of memory cell arrays are stacked on a semiconductor substrate (chip), and one interconnection is shared by memory cell arrays of different stages, as in Structural Example 3. With this arrangement, the number of interconnections in the memory cell arrays is decreased to planarize the underlying layer of MTJ elements (improve the characteristic of MTJ elements).
[0448] Structural Example 4 is different from Structural Example 3 in the positional relationship of an interconnection to be shared. More specifically, in Structural Example 3, one interconnection is shared as a write bit line of the memory cell array of the lower stage and a read word line of the memory cell array of the upper stage. In Structural Example 4, one interconnection is shared as a read word line of the memory cell array of the lower stage and a write bit line of the memory cell array of the upper stage.
[0449] {circle over (2)} Circuit Structure
[0450] In Structural Example 4, in a plurality of stages of memory cell arrays 11-1, 11-2, . . . , 11-m stacked, the read word line of the memory cell array of the lower stage and the write bit line of the memory cell array of the upper stage are integrated and shared as one write bit line/read word line.
[0451] FIGS. 24 and 25 show the main part of a magnetic random access memory according to Structural Example 4 of the present invention.
[0452] [1] First Stage (Lower Stage)
[0453] FIG. 24 shows the cell array structure of the first stage of Structural Example 4.
[0454] The memory cell array 11-1 has a plurality of MTJ elements 12
arranged in an array in the X- and Y-directions. For example, j MTJ elements 12 are arranged in the X-direction, and 4.times.n MTJ elements 12 are arranged in the Y-direction.
[0455] The four MTJ elements 12 arranged in the Y-direction form one read block BKik (i=1, . . . , j, and k=1, . . . , n). One row is constructed by j read blocks BKik arranged in the X-direction. The memory cell array 11 has n rows. In addition, one column is constructed by n read blocks BKik arranged in the Y-direction. The memory cell array 11-1 has j columns.
[0456] One terminal of each of the four MTJ elements 12 in the block BKik is commonly connected. The connection point is connected to, e.g., a read word line RWLi-1 (i=1, . . . , j). The read word line RWLi-1 runs in the Y-direction. One read word line RWLi-1 is arranged in one column.
[0457] The MTJ elements 12 in the read blocks BKik arranged in one column are directly connected to the read word lines RWLi-1 (i=1, . . . , j) without intervening read select switches (MOS transistors). One end of each read word line RWLi-1 is connected to a ground point VSS through a switching circuit 22 and a column select switch CSW formed from a MOS transistor.
[0458] The other end of the read word line RWLi-1 is connected to a circuit block 31(2) including a column decoder and write bit line driver/sinker through a disconnecting circuit 21.
[0459] The disconnecting circuit 21, switching circuit 22, and column select switches CSW are arranged outside the memory cell array 11-1. Hence, no switch elements (MOS transistors) are arranged in the memory cell array 11-1.
[0460] The disconnecting circuit 21 and switching circuit 22 are controlled by a memory cell array select signal SEL.
[0461] For example, in read operation, when the memory cell array 11-1 of the first stage (lower stage) is selected, the switching circuit 22
electrically connects one end of the read word line RWL