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United States Patent Application
20030135798
Kind Code
A1
Katayama, Yukari ; et al.
July 17, 2003
Optical disk device and data randomizing method for optical disk device
Abstract
A random seed scramble for preventing the deterioration of a medium is applied to the next generation optical disk. A seed is stored to a BIS area. ID or an EDC is checked to hold interchangeability before and after scramble release. When no error is generated in data before the scramble release, it is recognized as an unscrambled disk. In contrast to this, when no error is generated in data after the scramble release, it is recognized as a scrambled disk. An information storing area showing an area to be rewritten by performing the scramble and an area to be rewritten without performing the scramble is arranged.
Inventors:
Katayama; Yukari
(Chigasaki, JP)
, Maeda; Takeshi
(Kokubunji, JP
)
, Miyamoto; Harukazu
(Higashimurayama, JP
)
, Nishiya; Takushi
(Yawata, JP
)
, Kato; Takatoshi
(Yokohama, JP
)
, Taira; Shigeki
(Yokohama, JP
)
, Kawamae; Osamu
(Yokohama, JP
)
, Hoshizawa; Taku
(Kawasaki, JP
)
Correspondence Name and Address:
SUITE 1800 1300 NORTH SEVENTEENTH STREET
ANTONELLI TERRY STOUT AND KRAUS
ARLINGTON
VA
22209
Series Code:
316875
Filed:
December 12, 2002
U.S. Current Class:
714/710
U.S. Class at Publication:
714/710
Intern'l Class:
G11C 029/00
Claims
What is claimed is:
1. An optical disk device using a data randomizing method for generating and writing a seed at a write processing time, and characterized in that said seed is changed to an error correcting code as one code word together with additional information such as a writing position of written data, etc.
2. An optical disk device according to claim 1, wherein one portion of the seed is a rewriting number.
3. An optical disk device according to claim 1, wherein one portion of the seed is a track number or one portion of ID.
4. An optical disk device according to claim 1, wherein plural seeds are prepared in one write processing, and a sequence having preferable characteristics is selected among sequences of run length limit codes made from the plural seeds.
5. An optical disk device according to claim 1, wherein no address information of the data is scrambled.
6. An optical disk device according to claim 1, wherein ID information of the data is checked before scramble release at a regenerating time of the data, and the data are recognized as unscrambled data if there is no error, and the ID information of the data is again checked after descramble processing is terminated if there is an error, and the data are recognized and processed as scrambled data if there is no error.
7. An optical disk device according to claim 1, wherein an inspection using an error detection code of the data is made before scramble release at a regenerating time of the data, and the data are recognized as unscrambled data if there is no error, and the inspection using the error detection code of the data is again made after descramble processing is terminated if there is an error, and the data are recognized and processed as scrambled data if there is no error.
8. An optical disk device according to claim 1, wherein a record is made by using an optical disk medium having an area in which unscrambled data should be recorded, and a scrambled area.
9. A scramble coding method to be executed in a memory device, comprising: a seed selecting step for selecting a seed; and a scramble step for making an accumulative calculation by an exclusive logical sum with respect to data provided by continuously connecting said seed and inputted data of bits each separated by a predetermined bit number.
10. A scramble coding circuit to be executed in a memory device, comprising: seed selecting means for selecting a seed; and scramble means for making an accumulative calculation by an exclusive logical sum with respect to data provided by continuously connecting said seed and inputted data of bits each separated by a predetermined bit number.
11. A scramble decoding method corresponding to the scramble coding method according to claim 9 to be executed in the memory device, and comprising: a descramble step for calculating the exclusive logical sum with respect to the inputted data of bits each separated by a predetermined bit number; and a seed separating step for separating the seed from said descrambled data.
12. A scramble decoding circuit corresponding to the scramble coding circuit according to claim 10 to be executed in the memory device, and comprising: descramble means for calculating the exclusive, logical sum with respect to the inputted data of bits each separated by a predetermined bit number; and seed separating means for separating the seed from said descrambled data.
13. A recording method characterized in that the recording method is constructed by using the scramble coding method according to claim 9.
14. A recorder characterized in that the recorder is constructed by arranging one of means for embodying the scramble coding method according to claim 9, and the scramble coding circuit according to claim 10.
15. A regenerating method characterized in that the regenerating method is constructed by using the scramble decoding method according to claim 11.
16. A recorder characterized in that the recorder is constructed by arranging one of means for embodying the scramble decoding method according to claim 11, and the scramble decoding circuit according to claim 12.
17. A memory medium characterized in that the memory medium stores data recorded by one of the recording method according to claim 13 and the recorder according to claim 14.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a scramble coding-decoding method to be executed in a memory device (particularly an optical disk device such as a DVD, etc.) for recording data to a memory medium (particularly DVD) such as an optical disk, etc. able to rewrite (overwrite and overlap-write) the data, and regenerating the data from such a memory medium, and its circuit. Further, the present invention relates to a recording-regenerating method having such a scramble coding-decoding method or its circuit, and its device (particularly an optical disk device such as a DVD, etc.) Further, the present invention relates to a memory medium (particularly an optical disk medium such as a DVD, etc.) for storing data recorded by such a recording method or its device.
[0002] In a memory device using a rewritable phase changing type optical disk such as a DVD-RAM, data are generally written onto a track of the disk by generating a recording mark by the power of light. Concretely, the data can be recorded by changing a memory layer to one of two states, i.e., a crystal state (recording mark) and a noncrystal state (a portion having no mark) by irradiating the light beam at a high power level sufficient to change the state of the memory layer (film) to the memory medium while this light beam is controlled. Since light reflectivities in the crystal state and the noncrystal state are different from each other, the memory device can regenerate the recorded data by irradiating the light beam to the memory medium and detecting reflected light of the light beam. The light beam is a sufficiently low power level so that no memory device changes the state-of the memory layer. When the same data are recorded many times to the same place of the memory medium by many rewritings, the light beam at the high power level is irradiated to this place in the same situation every time. This causes physical deviation of the memory layer such as the flowage of a substance constituting the memory layer, a change in film thickness, etc. The physical deviation of the memory layer greatly changes its light reflectivity. Therefore, it is difficult to regenerate data with sufficient reliability in the memory device. As this result, it is necessary to limit the number of rewritable times of the memory medium to a small value.
[0003] There is a technique disclosed in Japanese Patent Laid-Open No. 150725/1991 as the technique for solving this problem. In this technique, when data are recorded in the memory device, the data are recorded by shifting the recording place of the data on the memory medium within a predetermined range. Thus, even when the same data are recorded, it is possible to avoid the same data from being recorded in the same place at any time so that the number of recording times of the same data to the same place can be reduced. As this result, the number of rewritable times of the memory medium can be increased. Further, in the DVD-RAM, a so-called groove is formed on the disk, and data density is increased by writing the data to both the groove and a portion (land) constituting no groove.
[0004] In the recording regenerator using the memory medium of a disk type, control for accurately locating a head onto the track is called tracking. In the DVD-RAM, the land and the groove are formed by making a very small vibration called a wobble, and the tracking is performed by utilizing this wobble. However, when the same data are written to an adjacent track, a tracking signal becomes weak. Therefore, a problem exists in that the tracking is easily missed. In the DVD for treating an image, a voice, etc., the same data such as an unsound portion, etc., are often written in large quantities. To solve this problem, various devices were made so as not to set the writing data of the adjacent track to the same even when the same data were written in large quantities by a user.
[0005] For example, as shown in Japanese Patent Laid-Open No. 274885/1994, there is a method for changing the start of a sector every one track as to whether the sector is started from a mark or a portion constituting no mark. Further, as described in STANDARD-ECMA-272, the DVD-RAM adopts a method in which an Maximum length sequence (random series) is generated with ID information of each frame as an initial value (seed), and is added to user data and is then written to the disk, etc. Such randomization of the data is generally called scramble.
[0006] On the other hand, in the field of optical communication, a method called a guided scramble was used to make a run length limit code having flat frequency characteristics and suitable for the optical communication. In this method, data of many kinds are made by adding data having a sufficiently large space to the head of data desirous to make the run length limit code, and one of data close to required characteristics is selected from data made by randomizing these data of many kinds. For example, such a technique is described in detail in "CODES FOR MASS DATA STORAGE SYSTEMS" K. A. S. IMMINK, SHANNON FOUNDATION PUBLISHER, 1999. Further, such a technique is described in "POLYNOMIALS FOR GUIDED SCRAMBLING LINE CODE", IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, Vol. 13, NO. 3, APRIL, 1995, etc. in theses.
[0007] Further, a high density optical disk using a blue purple laser is proposed in recent years. For example, such a technique is described in "OPTICAL DISC SYSTEM FOR DIGITAL VIDEO RECORDING", TATSUYA NARAHARA JPN.J. APPL. PHYS. VOL. 39 (2000) PP. 912-919 PART 1, NO. 2B, FEBRUARY 2000, etc.
[0008] FIG. 10 shows a format method of the optical disk described in this thesis. User data are changed to an error correcting code in a unit of 64K bytes, and are written onto a disk medium. In the optical disk, data are read and written in a unit of 2048 bytes in the DVD-RAM, etc. in the present situation, and this is called a logic sector. An error check code EDC of 4 bytes is added to the inputted user data so that the user data become 2052 bytes. This logic sectors added with the EDC thereto are collected into groups of 8 sectors, and is divided into 76 pieces of 216
bytes each. Each piece is coded to [248, 216, 33] Reed Solomon code, and is collected as 8 sectors and is arranged in an area (38 bytes.times.496
bytes) of (A) 1001 shown by half-tone dot meshing in FIG. 10. This area of 38 bytes.times.496 bytes is called LDC. Similarly, each piece is collected as 8 sectors each, and the areas of (B) 1002, (C) 1003 and (D) 1004 are buried by the logic sectors. Hereinafter, the Reed Solomon code is called an RS code.
[0009] Next, addresses, copy protection information, substitution sector information, etc. of 8.times.4=32 sectors are divided of 30 bytes each, and are changed to twenty-four [62, 30, 33] RS codes. These RS codes are written to three BIS areas 1005 to 1007 in FIG. 10 of 8 RS codes each. Asynchronous signal 1008 is added to this format, and data are taken out of this format in the transversal direction and are written onto the optical disk medium as shown by an arrow 1009. At a data regenerating time, the data read from the optical disk medium are arranged in the order shown by the arrow 1009, and are also arranged so as to form the format shown in FIG. 10, and error correction processing, etc. are then performed.
[0010] In the above technique (Japanese Patent Laid-Open No. 150725/1991), while the recording place of data on the memory medium is shifted within a predetermined range and the data of an object on the memory medium are rewritten, these rewritten data are set to be not overlapped with data existing before and after these rewritten data on the memory medium. Therefore, at least an area of the above predetermined range is required. This causes the problem of a reduction in format efficiency of the memory device and the memory medium, in its turn, a reduction in memory capacity.
[0011] Further, when the number of rewritable times of the memory medium is further increased by applying the above technique, it is considered to increase the above predetermined range and a shifting kind. However, if the above predetermined range is increased, the format efficiency of the memory device and the memory medium is reduced. For example, there are four shifting kinds by shifting channel data of two bits each (200 nm in the case of e.g., a channel data bit pitch 100 nm) from 0 bit (0 nm in this case) of the channel data on the memory medium to 6 bits (600 nm in this case). The condition of these four shifting kinds is set to a condition of 8 shifting kinds in which the channel data are shifted of one bit each (100 nm) from 0 bit (0 nm) to 7 bits (700 nm). Thus, the shifting kinds are doubled so that the number of rewritable times of the memory medium is further increased on trial. However, the predetermined range is changed from 7 bits (O to 6 bits) to 8 bits (O to 7 bits) and is not greatly changed. Therefore, it is doubtful whether a notable improvement is obtained.
SUMMARY OF THE INVENTION
[0012] Since the optical disk is a commutative medium, interchangeability is important. When a new technique is introduced, it is necessary that reading and writing operations can be easily performed even when the conventional optical disk medium introducing no new technique thereto is used.
[0013] A main object of the present invention is to provide a scramble coding-decoding method to be executed in a memory device for recording data to a rewritable memory medium and regenerating the data from this memory medium, and its circuit. In the scramble coding-decoding method and its circuit, the number of rewritable times of the memory medium can be increased by a slight reduction in format efficiency. Even when there is an error in the data of an object in descramble, this error is diffused to only limited slight data by the descramble so that the scramble coding-decoding method and its circuit are cheaply provided in view of the calculating amount and the circuit scale in execution. Another main object of the present invention is to provide a recording-regenerating method and its device having such a scramble coding-decoding method or its circuit. A still another main object of the present invention is to provide a memory medium for storing data recorded by such a recording method or its device.
[0014] In the scramble method in the present invention, data are scrambled by using an arbitrary seed to solve the above problem. Arbitrary seed data for performing randomization are preferably added to the original data to be recorded onto the disk. Additional information such as a sector number, copy protection, etc. is more preferably added to the original data to be recorded onto the disk, and an address is together scrambled. Thus, if the seed is different even in the same data, the data after the scramble are different. Namely, even when the same data should be recorded, the data actually recorded are different when the seed is different. Accordingly, the number of rewritable times of the memory medium can be increased. The randomized data, the additional information and the seed data are changed to different error correcting codes. Since the size of the data is increased by the seed by the scramble, format efficiency is reduced, but this reduction is slight.
[0015] When the present invention is used in the next generation high density optical disk introduced in the prior art, data are divisionally stored to an LDC area and the additional information and the seed are divisionally stored to a BIS area. Further, in accordance with the scramble method of the present invention, the randomized data of 1 bit are determined by a calculation using the original data of 1 bit or the seed data and the past randomized data of plural bits. In accordance with another mode of the present invention, a descramble method requiring no seed data is provided. Concretely, the present invention is characterized in that randomization release data of 1 bit are determined by the calculation using the randomized data of plural bits at a data regenerating time. In accordance with another mode of the present invention, a descramble method requiring no seed data is provided. Concretely, the present invention is characterized in that the randomization release data of 1 bit are determined by the calculation using the randomized data of plural bits at the data regenerating time. Further, in accordance with another mode of the present invention, even when a randomized area and an unrandomized area are mixed and exist in one disk, reading and writing operations can be performed by the same device without any problem even in a disk corresponding to the randomization and a disk not corresponding to the randomization. Concretely, with respect to the reading operation, an error detection code of data, position information, etc. are detected. When an error is detected, it is judged that the scramble is performed, and the descramble is performed. With respect to the writing operation, an area for storing discriminating information is arranged within the disk. Further, an area to be written without performing the scramble and an area to be written by performing the scramble are arranged in the optical disk medium to get access in a device not corresponding to the scramble.
[0016] Further, to achieve such objects, in the scramble coding method and its circuit in the present invention, when the seed and the data to be recorded before the scramble are continuously connected and are interpreted as a polynomial expression and a polynomial divisional calculation is made with respect to this polynomial with a predetermined scramble polynomial as a divisional polynomial, a quotient polynomial of this calculation result is set to data after the scramble. Thus, even when an error exists in the data of a descramble object in the descramble, this error is diffused only until an order of said predetermined scramble polynomial at most.
[0017] Further, to achieve such objects, in the scramble coding method and its circuit of the present invention, when its order is set to M, a polynomial of xM+1 is used as the predetermined scramble polynomial. Here, xy shows the y-th power of x, and xM means the M-th power of x. Thus, the scramble is really performed by the polynomial divisional calculation as an accumulative calculation using an exclusive logical sum of bits each separated by M-bits. Thus, the present invention can be cheaply constructed in view of the calculating amount and the circuit scale in execution.
[0018] Further, the descramble (which is an operation reverse to the scramble and is scramble decoding) corresponding to the above scramble coding method or its circuit is performed to achieve such objects in the scramble decoding method and its circuit of the present invention. Further, the recording-regenerating method and its device of the present invention have the above scramble coding-decoding method or its device to achieve such objects. Further, the memory medium of the present invention stores data recorded by the above recording method or its device to achieve such objects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 is a view showing a scramble circuit of the present invention.
[0020] FIG. 2 is a view showing a descramble circuit of the present invention.
[0021] FIG. 3 is a schematic block diagram of a first embodiment mode of the present invention.
[0022] FIG. 4 is a detailed block diagram of the scramble circuit of the first embodiment mode of the present invention.
[0023] FIG. 5 is a detailed circuit diagram of an Maximum length sequence generator of the first embodiment mode of the present invention.
[0024] FIG. 6 is a detailed circuit diagram of a secondary scramble circuit of the first embodiment mode of the present invention.
[0025] FIG. 7 is a detailed block diagram of the descramble circuit of the first embodiment mode of the present invention.
[0026] FIG. 8 is a detailed circuit diagram of a secondary descramble circuit of the first embodiment mode of the present invention.
[0027] FIG. 9 is a conceptual view of the first embodiment mode of the present invention.
[0028] FIG. 10 is a recording format view of the next generation optical disk.
[0029] FIG. 11 is a data sector format view of a second embodiment mode of the present invention.
[0030] FIG. 12 is a recording format view of the second embodiment mode of the present invention.
[0031] FIG. 13 is a recording format view of a fourth embodiment mode of the present invention.
[0032] FIG. 14 is a system block diagram of the second embodiment mode of the present invention.
[0033] FIG. 15 is a processing flow chart at a recording time of the second embodiment mode of the present invention.
[0034] FIG. 16 is a processing flow chart at a regenerating time of the second embodiment mode of the present invention.
[0035] FIG. 17 is a schematic block diagram of the fourth embodiment mode of the present invention.
[0036] FIG. 18 is a block diagram of an optical disk system of the fourth embodiment mode of the present invention.
[0037] FIG. 19 is a detailed block diagram of a seed generator of the second embodiment mode of the present invention.
[0038] FIG. 20 is a block diagram of the scramble circuit of the second embodiment mode of the present invention.
[0039] FIG. 21 is a block diagram of the descramble circuit of the second embodiment mode of the present invention.
[0040] FIG. 22 is a view showing a recording format of a third embodiment mode of the present invention.
[0041] FIG. 23 is a block diagram of a rewriting number recording memory of the third embodiment mode of the present invention.
[0042] FIG. 24 is one portion of a processing flow chart at a recording time of the third embodiment mode of the present invention.
[0043] FIG. 25 is a processing flow-chart at a regenerating time of the third embodiment mode of the present invention.
[0044] FIG. 26 is a block diagram of an optical disk system of a fifth embodiment mode of the present invention.
[0045] FIG. 27 is a block diagram of an optical disk system of a sixth embodiment mode of the present invention.
[0046] FIG. 28 is a block diagram of an optical disk system of the third embodiment mode of the present invention.
[0047] FIG. 29 is a typical view of an optical disk medium of the second embodiment mode of the present invention.
[0048] FIG. 30 is a typical view of an optical disk medium of the third embodiment mode of the present invention.
[0049] FIG. 31 is a processing flow chart at a partial rewriting time of the second embodiment mode of the present invention.
[0050] FIG. 32 is a processing flow chart at a power turning-on time and an optical disk insertion time of the third embodiment mode of the present invention.
[0051] FIG. 33 is one portion of the processing flow chart at the recording time of the third embodiment mode of the present invention.
[0052] FIG. 34 is one portion of the processing flow chart at the recording time of the third embodiment mode of the present invention.
[0053] FIG. 35 is a block diagram of an optical disk system of a seventh embodiment mode of the present invention.
[0054] FIG. 36 is one portion of the processing flow chart at a power turning-off time and an optical disk taking out time of the third embodiment mode of the present invention.
[0055] FIG. 37 is a typical view of an optical disk medium of an eighth embodiment mode of the present invention.
[0056] FIG. 38 is a typical view of an optical disk medium of an eleventh embodiment mode of the present invention.
[0057] FIG. 39 is a block diagram of an optical disk system of each of the eighth to eleventh embodiment modes of the present invention.
[0058] FIG. 40 is a detailed block diagram of a seed generator of each of the eighth to eleventh embodiment modes of the present invention.
[0059] FIG. 41 is a flow chart showing processing at a recording time of the eighth embodiment mode of the present invention.
[0060] FIG. 42 is a typical view of an optical disk medium of a ninth embodiment mode of the present invention.
[0061] FIG. 43 is a flow chart showing processing at a power turning-on time or a disk exchanging time of a tenth embodiment mode of the present invention.
[0062] FIG. 44 is a flow chart showing processing at the power turning-on time or the disk exchanging time of the ninth embodiment mode of the present invention.
[0063] FIG. 45 is a detailed block diagram of a scrambler of each of the eighth to eleventh embodiment modes of the present invention.
[0064] FIG. 46 is a detailed block diagram of a descrambler of each of the eighth to eleventh embodiment modes of the present invention.
[0065] FIG. 47 is a block diagram showing the construction of a scramble coding circuit of a 1-bit input-output type in a twelfth embodiment mode of the present invention.
[0066] FIG. 48 is a block diagram showing the construction of the scramble coding circuit of an M-bit input-output type in the twelfth embodiment mode of the present invention.
[0067] FIG. 49 is a block diagram showing the construction of a scramble decoding circuit of a 1-bit input-output type in the twelfth embodiment mode of the present invention.
[0068] FIG. 50 is a block diagram showing the construction of the scramble decoding circuit of an M-bit input-output type in the twelfth embodiment mode of the present invention.
[0069] FIG. 51 is a view showing a memory medium of a disk type used in a memory device in the twelfth embodiment mode of the present invention.
[0070] FIG. 52 is a view showing the memory medium of an array type used in the memory device in the twelfth embodiment mode of the present invention.
[0071] FIG. 53 is a block diagram showing the construction of an optical disk device having a scramble coding-decoding section for storing host data in the twelfth embodiment mode of the present invention.
[0072] FIG. 54 is a view showing the transition of data generated in a recording process by a recorder in the twelfth embodiment mode of the present invention.
[0073] FIG. 55 is a block diagram showing the construction of the optical disk device in which a processor executes a scramble coding method and a scramble decoding method to store host data in the twelfth embodiment mode of the present invention.
[0074] FIG. 56 is a block diagram showing the construction of the optical disk device for storing data of a voice and a dynamic image in broadcast in the twelfth embodiment mode of the present invention.
[0075] FIG. 57 is a block diagram showing the construction of the optical disk device of a camera type for storing the voice dynamic image data in the twelfth embodiment mode of the present invention.
[0076] FIG. 58 is a view showing a data arrangement in the optical disk device of a first literature.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0077] With respect to the embodiment modes of the present invention, a first embodiment mode will first be explained by using FIGS. 3 to 9. FIG. 3 is a schematic block diagram showing the construction of an optical disk device of this embodiment mode. The embodiment modes explained below do not limit the present invention. There is also a case in which the optical disk device of the present invention is used as a recording regenerator such as a stationary type image and voice recording regenerator connected to a television, a portable video camera, a portable voice regenerator, etc. in addition to a memory device used in a computer system as in this embodiment mode.
[0078] In FIG. 3, a host interface (host I/F) 311 controls data transfer between the optical disk device and a host computer such as an unillustrated personal computer, etc. A scramble circuit 309 randomizes data. An error correction coding circuit 307 adds an error correcting code to the randomized data. A run length limit coding circuit 305
modulates the data added with the error correcting code thereto in accordance with a rule determined in advance, and converts the modulated data to data able to be recorded to an optical disk 301 as a recording medium. A recording-regenerating amplifier 303 receives the coded data from the run length limit coding circuit 305, and converts the coded data to a voltage waveform suitable for a recording-regenerating head 302. The recording-regenerating head 302 converts the received voltage waveform to a laser beam, and writes a mark onto the optical disk 301 by power of the laser beam. At a reading time of the data, the recording-regenerating head 302 irradiates the laser beam to the optical disk 301, and reads the data by reflected light by utilizing the difference in reflection intensity of the light between the mark and a non-mark, and converts the read information to an electric signal.
[0079] This electric signal is amplified to a suitable degree by the recording-regenerating amplifier 303, and is then outputted to a data regenerating circuit 304. The data regenerating circuit 304 converts the read analog signal to a digital information series of 0 and 1. The obtained data series is demodulated in a run length limit code decoding circuit 306 reversely to the run length limit coding circuit 305. In an error correcting circuit 308, an error position and an error value are calculated on the basis of the error correcting code added by the error correction coding circuit 307, and the error is corrected. The data corrected with respect to the error are restored to the original data in a descramble circuit 310. In the optical disk device, the data are recorded and regenerated by the above procedure.
[0080] The scramble circuit 309 will be explained in detail. FIG. 4 is a detailed block diagram of the scramble circuit 309. A fixing random series made by an Maximum length sequence generator 401 is added to user data sent from the host I/F 311 by an EOR circuit 402, and these user data are then inputted to a random seed scrambler 403. FIG. 5 is a detailed circuit diagram of the Maximum length sequence generator 401. Reference numerals 502 to 516 designate registers for storing data in one bit unit. These registers 502 to 516 perform a shift operation in synchronization with the inputted user data. Reference numeral 501
designates an exclusive logical sum circuit. In an initial state, only the register 516 is set to 1, and registers 502 to 515 are set to 0. In this embodiment mode, the Maximum length sequence generator using a 15-th order polynomial shown by the following formula 1 is supposed. Hereinafter, all the polynomials used in this embodiment mode are polynomials on Galois field (GF(2)), and "+" shows the exclusive logical sum.
[0081] [Formula 1]
x.sup.15+x.sup.4+1
[0082] The series generated by this Maximum length sequence generator 401
is a pseudo random series having a period of 215-1=32767. Here, ab is defined as the b-th power of a. In the following description, the b-th power of a is noted as ab. In this embodiment mode, no Maximum length sequence generator 401 is necessarily required, and only the random seed scrambler 403 may be arranged. However, in this embodiment mode, the Maximum length sequence generator 401 is also used to preferably give random performance.
[0083] In the random seed scrambler 403, data of 8 bits are first added to the head of data as shown in FIG. 9. These data of 8 bits are arbitrary data of 8 bits, and may be set to data made on the basis of a time for performing a writing operation, etc., and may be also a value incremented one by one by an increment counter of 8 bits at every one writing operation. These added bits of 8 bits are set to a seed for randomization. In this embodiment mode, since the data of 8 bits are added, the randomization of 28=256 combinations from "00000000" to "11111111" can be performed. Namely, when the same user data are physically recorded to the same place, the probability of setting the really written data to the same is 1/256. This probability is similarly formed when the same user data are written to an adjacent track. Thus, deterioration of the optical disk 301 can be avoided and a tracking error can be also reduced by performing such randomization. The added data are not necessarily set to 8 bits, but may be also set to bits greater or smaller than 8 bits. Further, the added bits (initial value) are not necessarily added to the head of the user data, but may be also inserted into any place of the user data. A portion after the added portion of the data (initial value) is generated as a series different at every initial value. In this embodiment mode, the added data are located in the head able to most efficiently perform the randomization.
[0084] FIG. 6 is a detailed circuit diagram of a secondary scramble circuit 405. Reference numerals 601 to 604 designate exclusive logical sum circuits. Reference numerals 605 to 612 designate registers for storing data in a one-bit unit. The registers 605 to 612 are set to 0 in the initial state. The secondary scramble circuit 405 performs the shift operation in synchronization with input data. The scramble shown by the following formula 2 is performed by this circuit.
[0085] [Formula 2]
c.sub.i=b.sub.i+c.sub.i-4+c.sub.1-5+c.sub.1-6+c.sub.1-8
[0086] Here, b.sub.i is i-th bit data are inputted to the secondary scramble circuit. C.sub.i-j is data located by j-bits before with respect to the i-th bit data outputted from the secondary scramble circuit. As can be seen from this formula, C.sub.i is made from data of 1 bit before the scramble, and past data of plural bits after the scramble. Thus, the data are scrambled in this way and are then sent to the error correction coding circuit 307.
[0087] The descramble circuit 310 will next be explained in detail. FIG. 7
is a detailed block diagram of the descramble circuit 310. FIG. 8 is a detailed circuit diagram of a secondary descramble circuit 704 of FIG. 7. Reference numerals 801 to 808 designate registers for storing data in a one-bit unit. Reference numerals 809 to 812 designate exclusive logical sum circuits. Similar to the secondary scramble circuit 405, the secondary descramble circuit 704 also performs the shift operation in synchronization with input data.
[0088] The operation of the descramble circuit 310 will next be explained. Data corrected by the error correcting circuit 308 with respect to an error are inputted to the secondary descramble circuit 704 of a random seed descrambler 703. The descramble shown by the following formula 3 is performed by the secondary descramble circuit 704.
[0089] [Formula 3]
b.sub.i=c.sub.i+c.sub.i-4+c.sub.i-5+c.sub.i-6+c.sub.i-8
[0090] Here, b.sub.i is descrambled user data of an i-th bit, and c.sub.i-j is data located by j-bits before with respect to the i-th bit inputted from the error correcting circuit 308. As can be seen from this formula, when the descramble is performed, the descramble can be performed even when no initial value of the scramble is already known. When an error unable to be corrected is generated in the error correcting circuit 308, the error is widened by 8 bits in the descrambled user data. However, the error is propagated by only 8 bits, but is not widened any more.
[0091] As shown in FIG. 9, the added bits of 8 bits added by a random data adding circuit 404 are next deleted by a random data deleting circuit 705.
[0092] An Maximum length sequence generator 701 is the same as the Maximum length sequence generator 401, and is shown in FIG. 5. The user data are decoded by adding the same object by an exclusive logical sum circuit 702.
[0093] In this embodiment mode, the scramble circuit is constructed by using the shift register for shifting bits, but may be also realized by an equivalent circuit operated in a byte unit.
[0094] In this embodiment mode, the random seed scramble is performed by using a primitive polynomial of 8 bits represented as follows.
[0095] [Formula 4]
x.sup.8+x.sup.4+x.sup.3+x.sup.2+1
[0096] However, any polynomial may be here used. The scramble circuit can be realized by FIG. 1 and the descramble circuit can be realized by FIG. 2 with respect to the following general formula of the polynomial.
[0097] [Formula 5] 1 i = 0 n a i x i
[0098] When the primitive polynomial is used in the polynomial, the period can be set to be long so that a more random series can be obtained. Here, a.sub.i is set to 1 or 0. When a.sub.i is 1, a signal line is connected. In contrast to this, when a.sub.i is 0, no signal line is connected. In this embodiment mode, the polynomial can be also expressed as the following primitive polynomial of 8 bits.
[0099] [Formula 6]
x.sup.8+x.sup.6+x.sup.5+x.sup.4+1
[0100] In this case, the scramble circuit can be realized by FIG. 1 and the descramble circuit can be realized by FIG. 2 with respect to the following general formula of the polynomial.
[0101] [Formula 7] 2 i = 0 n a i x n - i
[0102] Here, a.sub.i is set to 1 or 0. When a.sub.i is 1, the signal line is connected. In contrast to this, when a.sub.i is 0, no signal line is connected. The relation of formulas 5 and 7 is generally called a reciprocal polynomial. Since the reciprocal polynomial of the primitive polynomial is a primitive polynomial, there is particularly no problem in view of the use of the primitive polynomial. When the definition of the formula 7 is used, output data has a meaning in which output data is a quotient provided by dividing input data by the polynomial (here formula 7) for defining the scramble circuit. However, any one of the formulas 5
and 7 may be used in the definition.
[0103] In this embodiment mode, the scramble circuit 309/descramble circuit 310 in FIG. 3 are arranged between the error correction coding circuit 307/error correcting circuit 308 and the host I/F in the above explanation, but may be also arranged between the run length limit coding circuit 305/decoding circuit 306 and the error correction coding circuit 307/decoding circuit 308. Further, in FIGS. 4 and 7, in this embodiment mode, the Maximum length sequence generator 401/701 is arranged on the host I/F 311 side from the random seed scramble circuit 403/descramble circuit 703, but may be also arranged on the optical disk 301 side from the random seed scramble circuit 403/descramble circuit 703. The arrangement of the above scramble circuit 310 or the Maximum length sequence generator 401/701 is one embodiment, and the present invention is not limited to this arrangement. Namely, the scramble circuit 301 or the Maximum length sequence generator 401/701 can be arranged in an arbitrary position able to obtain the effects of the present invention. Further, in FIG. 3, all or one portion of the scramble circuit 309, the error correction coding circuit 307, the run length limit coding circuit 305, the descramble circuit 310, the error correcting circuit 308, the run length limit code decoding circuit 306, etc. can be constructed by one chip.
[0104] An application case of the random seed scramble explained in the first embodiment mode to the next generation DVD format will next be explained further in detail as a second embodiment mode. FIG. 14 is a schematic block diagram of a DVD device in this second embodiment mode. Reference numeral 311 designates an interface for performing input-output control of data with respect to an upper device. Reference numeral 1406
designates a microcomputer for generalizing a system. The microcomputer 146 is connected to a control circuit 1411 within the system. This control circuit 1411 controls the operations of a seed generator 2603, the error correction coding circuit 307, a scrambler 2601, etc. through an unillustrated control line. Reference numeral 1401 designates an ID adder for adding additional information such as ID, etc. required to make a record to the user data given by the interface 311. Reference numeral 1402 designates a memory (RAM) for temporarily storing data. Reference numeral 2601 designates a scrambler for randomizing data.
[0105] This scrambler is a scrambler shown in FIG. 20, and includes the random seed scrambler 403 explained in the first embodiment mode. Reference numeral 2603 designates a seed generator for giving a different seed to the random seed scrambler within the scrambler 2601 every writing. Reference numeral 307 designates an error correction coding circuit for adding an error correcting code to the scrambled user data. Reference numeral 305 designates a coding circuit for converting the user data adding the error correcting code thereto to a run length limit code suitable for the record to the optical disk 301. Reference numeral 302
designates a pickup for recording/regenerating data of the optical disk 301. Reference numeral 1403 designates a spindle motor for rotating the disk. Reference numeral 1404 designates a servo for controlling the operation of the optical pickup 302, etc. Reference numeral 304
designates a read channel for performing waveform equalization processing of an analog regenerating signal read from the optical disk 301, a binary operation and synchronous clock generation. Reference numeral 306
designates a decoder for decoding the read run length limit code. Reference numeral 308 designates an error detection-correction circuit for detecting an error on the basis of the error correcting code added by the error correction coding circuit 307, and correcting the error. Reference numeral 2602 designates a descramble circuit for releasing the randomization performed by the scrambler 2601 and returning the user data to the original user data and shown in FIG. 21. The descramble circuit 2602 includes the random seed descrambler 703 explained in the first embodiment mode. Reference numeral 1407 designates an ID deleting device for deleting the additional information required to record the ID, etc. added by the ID adder 1401, and setting the data to only the user data.
[0106] FIG. 19 is a view showing the seed generator 2603 of this second embodiment mode. Each of reference numerals. 1301, 1302 designates a 1-bit shift register, and reference numeral 1303 designates an exclusive logical sum circuit. A suitable value except for all zero is inputted to each 1-bit shift register 1301 in the initial state. When the seed is required at a data writing time, a clock (1305) is inputted and the values of the 1-bit shift registers 1301, 1302 are leftward shifted. An output value of the exclusive logical sum circuit 1303 is inputted to the 1-bit shift register 1302. Thereafter, 6 bits of the seed value inputted to the 1-bit shift registers 1301, 1302 and a sector ID (b7 and b8 of the sector number) (1901) given by the ID adder 1401 are outputted as the seed to the scramble circuit 2601 through a seed output line 1307. Here, b7 and b8 of the sector ID correspond to eighth and ninth bits from the lower order of the sector ID, and a bit for absolutely giving no same value in an adjacent track is selected.
[0107] The operation of the DVD device shown in FIG. 14 will next be explained. The operation of the DVD device at a recording time will first be explained with reference to the optical disk shown in FIG. 29, the format shown in FIG. 11 and the processing procedure shown in FIG. 15 at the recording time. In the optical disk shown in FIG. 29, scramble mode information showing whether this optical disk corresponds to a random seed scramble, is written to an innermost circumferential track 2901. The same information as 2902, 2903, 2904, 2905 is written to four places so as to provide reliability for the scramble mode information. As shown in this embodiment mode, the reliability of data can be highly held by writing the above information to the innermost circumference since no innermost circumference is easily damaged. This scramble mode information is read into the optical disk device at a power turning-on time of the optical disk device or an optical disk insertion time, and is stored into a mode bit 2001 within the scramble circuit 2601. When different information is obtained from the four places, a value largely read by decision by majority is written to the mode bit 2001. In this embodiment mode, the writing position of the scramble mode information is limited to only the inner circumference. However, when no track near the outer circumference or the center instead of the inner circumference is easily damaged, the writing position may be also arranged in the track near the outer circumference or the center.
[0108] Further, the writing operation may be also performed by dividing the track into plural tracks as in the innermost circumference and a circumference near the center. In this case, it takes time to read the scramble mode information, but the scramble mode information can be more reliably stored. Further, in this embodiment mode, the writing position of the scramble mode information is set to four places, but may be also set to places greater than four places. In this case, the scramble mode information can be more reliably stored. Further, the scramble mode information can be also written by adding a strong error correcting code to more reliably write the scramble mode information. When the writing position of the scramble mode information is set to odd places, but there is a merit in that the writing position is determined by decision by majority at any time and processing is easily performed. In accordance with the present invention, it is possible to provide a disk having the above characters and a device for recording data to this disk.
[0109] First, user data 1101 of 2048 bytes (corresponding to 1 logic sector) are inputted from the interface 311 (step 1501). In the ID adder 1401, an error detection code (EDC) 1107 of four bytes is added to the user data 1101 inputted from the interface 311 (step 1502), and these user data are written to an area A 1408 of a RAM 1402 (step 1503). It is then confirmed whether a file is terminated (step 1504). When it is the termination of the file, the remaining sectors constructed by dummy data are added so as to provide 32 sectors in total (step 1517). In contrast to this, when it is not the end of the file, it is confirmed whether the 32 sectors are completed (step 1505), and steps 1501 to 1505 are repeated until the 32 sectors are completed. When the 32 sectors are completed, additional information 719 byte 1115 such as identification address information of data such as ID, etc., copy protection information, reserve information, etc. is further added to the 32 logic sectors 1101
to 1106 and EDCs 1107 to 1112 in the ID adder 1401 as shown in FIG. 11
(step 1506). Next, a mode bit 2001 is inspected, and it is judged whether the disk to be written at present corresponds to the random seed scramble (step 1507).
[0110] When this disk does not correspond to the random seed scramble, a selector 2002 transfers unscrambled user data to the error correction-detection circuit. In contrast to this, when the disk corresponds to the random seed scramble, the scramble is performed by the scramble circuit 2601. In the scramble circuit 2601, a seed 1114 of 1
byte given by the seed generator 2603 is added to the head of the additional in-formation 719 byte (step 1508), and the random seed scramble explained in the first embodiment mode is performed (step 1509). As shown by an arrow 1116 of FIG. 11, the scramble is sequentially performed in the order of the seed 1114, the additional information 1115, the user data 110 from the left upper portion, and the scrambled data are transferred to the error correction coding circuit 307.
[0111] Next, in the error correction coding circuit 307, the scrambled data of the additional information 1115 of 719 bytes and the seed 1114 of 1 byte for the random seed scramble stored to an area A 1408 within the RAM 1402 are divided into 24 pieces of 30 bytes each. In the error correction coding circuit 307, these data of 30 bytes each are changed to [62, 30, 33] RS codes, and are respectively stored to three BIS areas 1005, 1006, 1007 within an area B(1409) of the RAM 1402 shown in FIG. 12
of 8 code words each. Next, the logic sectors added with the EDC are collected into groups of 8 sectors each, and is divided into 76 pieces of 216 bytes each. Each piece is changed to [248, 216, 33] RS codes, and is collected by 8 sectors, and these sectors are arranged in an LDC area 1001 (38 bytes.times.496 bytes) of (A) shown by half-tone dot meshing in FIG. 12. Similarly, the logic sectors are collected every 8 sectors, and the LDC areas of (B)1002, (C)1003 and (D)1004 are filled with these logic sectors (step 1510). Further, a synchronous signal (SYNC code) 1008 is added to the left-hand end (,step 1511).
[0112] Next, the coding circuit 305 reads data from an area B(1409).of the RAM 1402 in accordance with an arrow 1009 showing a recording-regenerating order in FIG. 12, and continuously reads 31 stages (one stage corresponds to 1 byte in the longitudinal direction) as a "physical sector" of 4 k bytes (step 1512), and performs run length limit coding (step 1513).
[0113] The run length limit coded sequence is then written to the optical disk 301 via an LD driver 1405 and the optical pickup 302 (step 1514). Thereafter., the written data are read and are compared with the data of the RAM so as to judge whether the data are normally written to the optical disk (step 1515). When the data of 1 ECC block are normally recorded to the optical disk 301, the processing is terminated. However, when it is unsuccessful in the record for a certain reason during the record of the data, the medium is deteriorated when the same data are written to the same place. Accordingly, when the disk corresponds to the random seed scramble, the scramble is again performed by changing the seed, and the data are rewritten. Namely, the data are rewritten from the step 1507. In this case, data stored to the area A 1408 of the RAM 1402
are scrambled in the scrambler 2602. The scrambled data are again stored to the RAM 1402, and the error correcting code is again added to these scrambled data by the error correction coding circuit 307. The data adding the error correcting code thereto are converted to a physical sector, and are changed to a run length limit code, and are then again written to the optical disk 301.
[0114] It is possible to omit the step 1515 and the rewriting step using the rescramble in a case such as an AV system in which speed is more important than reliability. As shown by 1201 of FIG. 12, seed 1 byte of the random seed scramble is written into the BIS area by performing the writing processing as in this embodiment mode. It is possible to prevent the same data as an adjacent track from being written by using a different bit at any time between adjacent tracks in one portion of the seed of the random seed scramble as in this embodiment mode even when no scramble using an Maximum length sequence additional calculation with ID, etc. as the seed is performed. Therefore, correlation with respect to the adjacent track can be reduced so that noises from a data area with respect to a servo, etc. can be reduced. In this second embodiment mode, b7 and b8 of the sector ID are used. However, any sector number may be used if it is guaranteed to take a different value between the adjacent tracks. If the track number, etc. exist within the ID, the track number, etc. may be also used. One portion of the ID, may be also used in one portion of the seed as a value giving track information as in the seed of the Maximum length sequence used in the scramble of the present DVD-RAM.
[0115] The processing procedure at a regenerating time will next be explained with reference to FIG. 16. At the regenerating time, data are read by the optical pickup 302, and a binary operation is performed and a synchronous clock is generated in the read channel 304 (step 1601). In the decoding circuit 306, the decoding operation is performed from a run length limit code (step 1602), and regenerating data are temporarily stored to the area B 1409 of the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12 (step 1603). The physical sector corresponding to 4
k bytes is collectively read by 16 sectors and is temporarily stored to the area B 1409 of the RAM 1402. The error detection/correction circuit 308 first performs error correction processing of the seed 1114 stored to the BIS area shown in FIG. 12 and the additional information 719 byte1115
such as ID, etc. (step 1604). Next, it is confirmed whether the ID written to the BIS area and performed with respect to the error correction processing is the ID of an ECC block intended to be regenerated (step 1605). If the ID is the ID of the. ECC block or the sector desirously read, the error correction processing of an LDC area is performed (step 1614). The additional information 719 byte1115 such as ID, etc. is deleted by the ID deleting circuit 1407 (step 1615), and it is jumped to a step 1611. In contrast to this, when no ID written to the BIS area and performed with respect to the error correction processing is the ID of the ECC block intended to be regenerated, the data of the BIS area terminated with respect to the error correction processing are transferred to the descramble circuit 2602 and are descrambled, and are temporarily stored to the area A1408 of the RAM 1402 (step 1606).
[0116] As shown in FIG. 21, this descramble circuit 2602 includes the random seed descramble circuit 703. All 1-bit shift registers 801 to 808
within the secondary descramble circuit 704 are cleared to "0" before the data of the BIS area are inputted. After the descramble of the BIS area is terminated, the values of the 1-bit shift registers 801 to 808 within the secondary descramble circuit 704 are held until the descramble of the LDC area is started. Next, it is confirmed whether the ID included in the descrambled BIS data is the ID of a sector desirously read (step 1607). When the read ID is different from the ID of the desired sector, it is again returned to the step 1601, and data are read from the medium. In contrast to this, when the read ID is the ID of the desired sector, the error correction processing of the user data stored to the LDC area is performed in the error detection/correction circuit 308 (step 1608). After the error correction processing is terminated, the data of the LDC area are transferred from the area B 1409 of the RAM 1402 to the descramble circuit 2602 and are descrambled, and are temporarily stored to the area A1408 of the RAM 1402 (step 1609). The descramble processing can be continuously performed since the values of the 1-bit shift registers 801 to 808 within the descramble circuit 310 are not changed as they are. After the descramble is terminated, the seed 1114 for the scramble and the additional information 1115 such as ID, etc. are deleted from the data stored to the area A1408 of the RAM 1402 by the ID deleting circuit 1407 (step 1610).
[0117] Thereafter, it is confirmed that there is no error in the user data 1101 to 1106 by using EDCs 1107 to 1112 (step 1611), and the EDCs 1107 to 1112 are deleted (step 1612), and the user data are outputted to the interface 311 (step 1613). Thus, since the scramble is released by using the construction of the second embodiment mode after the error correction processing is terminated, no deterioration of error correction ability due to error propagation of the random seed scramble is generated. In the second embodiment mode, the seed of 1 byte is added to 1 ECC block 64 K bytes, but the random seed scramble can be also performed every logic sector by adding the seed of logic sector 2 K bytes each. When the scramble is performed of logic sector each, a method for processing the random seed scramble by using the same seed in each logic sector in the 1
ECC block is considered.
[0118] Further, error propagation is generated in the random seed scramble. Accordingly, when it is considered to remedy data as much as possible in the case of error correction disability, it is desirable to perform the scramble processing on the user side from the error correction coding. As shown in this embodiment mode, it is desirable to descramble-process the additional information such as ID, etc. corresponding to the user data before the user data. Thus, the ID can be early confirmed so that are-reading operation can be rapidly performed when the ID is incorrect. When the ID is confirmed before the data descramble as shown in this embodiment mode, and the desirable ID is obtained here, data are regenerated without descrambling these data. In contrast to this, when no desirable ID is obtained, the ID is confirmed after the descramble is performed. After the desirable ID is thus obtained, the data are also descrambled and regenerated. Thus, the data can be regenerated without any care about a disk recorded by using the random seed scramble and a disk recorded without using the random seed scramble. If this system is used, the data can be regenerated without any care in a case in which the scrambled ECC block and the unscrambled ECC block are mixed within one disk instead of a disk unit. In accordance with the present invention, this disk and a device for regenerating this disk can be provided.
[0119] Further, in this embodiment mode, the judgment is made by only the EDC check result of one logic sector. However, it may be also judged that no data are scrambled when all the EDC check results of plural logic sectors or 1 ECC block are OK. In this case, it is possible to reduce the probability of a judgment mistake due to the error detection of the EDC.
[0120] The processing procedure in rewriting only the sector of one portion within the ECC block 64 K bytes will next be explained with reference to FIG. 31. First, user data 1101 of 2048 bytes (corresponding to 1 logic sector) to be rewritten are inputted from the interface 311
(step 3101). The ID adding circuit 1401 adds an error detection code (EDC) 1107 of 4 bytes to the user data 1101 inputted from the interface 311 (step 3102), and writes these user data to the area A1408 of the RAM 1402 (step 3103). It is then confirmed whether a file is terminated (step 3104). If no file is terminated, it is returned to the step 3101, and the data are read until the end of the file. In the case of the termination of the file, written data of the ECC block are read from the optical disk 301 (step 3105). In the decoding circuit 306, the decoding operation is performed from a run length limit code (step 3106), and regenerating data are temporarily stored to the area B1409 of the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12 (step 3107). The physical sector corresponding to 4 k bytes is collectively read by 16 sectors, and is temporarily stored to the area B1409 of the RAM 1402. The error detection/correction circuit 308 first performs the error detection processing of the seed 1114 stored to the BIS area shown in FIG. 12, and the additional information 791 byte1115 such as ID, etc. (step 3108). It is then conformed whether the ID terminated with respect to the error correction processing is the ID of the ECC block desirously written (step 3109). When the IDs are conformed to each other, the error correction processing of the LDC area is performed (step 3123), and it proceeds to a step 3114. In contrast to this, when no IDs are conformed to each other, the data of the BIS area terminated with respect to the error correction processing are transferred to the descramble circuit 2602 and are descrambled, and are temporarily stored to the area A1408 of the RAM 1402
(step 3110). Before the data of the BIS area are inputted, all the 1-bit shift registers 801 to 808 within the secondary descramble circuit 704
are cleared to "0".
[0121] After the descramble of the BIS area is terminated, the values of the 1-bit shift registers 801 to 808 within the secondary descramble circuit 704 are held until the descramble of the LDC area is started. Next, it is conformed whether the ID included in the descrambled BIS data is the ID of a sector desirously written (step 3111). When the read ID is different from the ID of the desired sector, it is again returned to the step 3105, and data are read from the medium. In contrast to this, when the read ID is the ID of the desired sector, the error correction processing of the user data stored to the LDC area is performed in the error detection/correction circuit 308 (step 3112). After the error correction processing is terminated, the data of the LDC area are transferred from the area B1409 of the RAM 1402 to the descramble circuit 310 and are descrambled (step 3113), and are temporarily stored to the area A1408 of the RAM 1402 with respect to only the sector unwritten in the step 3103 (step 3114).
[0122] Thus, the data of written 1 ECC block are completed. Next, in the scramble circuit 2601, it is first checked whether the inserted disk is a disk corresponding to the scramble (step 3115). If no inserted disk is the scramble corresponding disk, it proceeds to a step 3118. In contrast to this, when the inserted disk is the scramble corresponding disk, the random seed scramble is performed. A seed 1114 of 1 byte for the random seed scramble given by the seed generator 2603 is then added (step 3116), and the added data are scrambled (step 3117). As shown by an arrow 1116
of FIG. 11, the scramble is sequentially performed in the order of the seed 1114, the additional information 1115 and the user data 1101 from the left upper portion, and the scrambled data are transferred to the error correction coding circuit 307.
[0123] In the error correction coding circuit 307, the data scrambled with respect to the seed 1114 of 1 byte for the random seed scramble stored to the area A1408 within the RAM 1402 and the additional information 1115 of 719 bytes are changed to [62, 30, 33] RS codes of 30 bytes each, and are divided into 24 pieces. In the error correction coding circuit 307, these data of 30 bytes each are changed to [62, 30, 33] RS codes, and are respectively stored to three BIS areas 1005, 1006, 1007 within the area B1409 of the RAM 1402 shown in FIG. 12 by of 8 code words each. Next, the logic sector added with the EDC thereto is collected into groups of 8
sectors each, and is divided into 76 pieces of 216 bytes each. Each piece is changed to [248, 216, 33] RS codes, and is collected by 8 sectors, and is arranged in the LDC area 1001 (38 bytes.times.496 bytes) of (A) shown by half-tone dot meshing in FIG. 12. Similarly, the LDC areas of (B)1002, (C)1003 and (D)1004 are collectively filled with the pieces of 8 sectors each (step 3118).
[0124] Next, the coding circuit 305 reads data from the area B of the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12 and showing a recording-regenerating order, and continuously reads the data at 31
stages (one stage corresponds to 1 byte in the longitudinal direction) as a "physical sector" of 4 k bytes (step 3119), and changes these data to a run length limit code (step 3120). The data of 4 k bytes changed to the run length limit code are written to the optical disk 301 via the LD driver 1405 and the optical pickup 302 (step 3121). The remaining data changed to the error correcting code are similarly processed every "physical sector" of the 4 k bite unit and are written onto the optical disk. Thereafter, the written data are read and are compared with the data of the RAM as to whether the data are normally written to the optical disk (step 3122). When the data of 1 ECC block are normally recorded onto the optical disk 301, the processing is terminated. However, when it is unsuccessful in the record for a certain reason during the record of the data, deterioration of the medium is caused when the same data are written to the same place. Accordingly, when the disk corresponds to the random seed scramble, the scramble is again performed by changing the seed, and data are rewritten.
[0125] Namely, the data are rewritten from the step 3115. In this case, the data stored to the area A of the RAM 1402 are scrambled in the scramble 2602. The error correcting code is again added to the scrambled data in the error correction coding circuit 307. The data adding the error correcting code thereto are converted to a physical sector, and are changed to a run length limit code, and are then again written to the optical disk 301. It is possible to omit the step 3122 and the rewriting step using the rescramble in a case such as an AV system in which speed is more important than reliability.
[0126] A third embodiment mode will next be explained with reference to FIGS. 28 and 30. FIG. 30 shows an optical disk medium 301 used in this third embodiment mode. Reference numeral 3001 designates an innermost circumferential track of the optical disk 301, and a rewriting number of each ECC block is recorded to tracks 3001 to 3002. Data are written to the optical disk 301 of this third embodiment mode in accordance with the format shown in FIG. 22, and are also written to the innermost circumferential tracks 3001 to 3002 in accordance with the format shown in FIG. 22. In this embodiment mode, the reliability of a rewriting number recording area is raised by arranging the rewriting number recording area in the innermost circumference. In the format shown in FIG. 22, the data of 32 logic sectors (32*2048 bytes) can be stored as shown in FIG. 11. These 32*2048 bytes are divided into sizes of 17 bits each, and each size is set to the rewriting number recording area. This rewriting number recording area of these 17 bits corresponds to the ECC block for recording data in the entire disk one by one, and can be preferably counted until the rewriting of about 130,000 times. Number 1
is written as the rewriting number at a factory forwarding time of the optical disk. The data of 30480 ECC blocks can be managed in one ECC block. The rewriting number recording area of 12 ECC blocks is required to manage the optical disk of 22.5 G bytes. The tracks (until track 3002) of the 12 ECC blocks from the innermost circumferential track 3001 are prepared as the rewriting number recording area.
[0127] FIG. 28 is a schematic block diagram of a DVD device in this third embodiment mode. Reference numerals 311 and 1406 respectively designate an interface for performing input-output control of data with respect to an upper device, and a microcomputer for generalizing a system. The microcomputer 1406 is connected to a control circuit 1411 within a system, and the control circuit 1411 controls the operations of an error correction coding circuit 307, a scrambler 2601, etc. through an unillustrated control line. In the microcomputer 1406, there is an information bit 2805 showing whether the optical disk inserted at present corresponds to the random seed scramble with the rewriting number as one portion of the seed. Reference numeral 1401 designates an ID adder for adding additional information such as ID, etc. required to make a record to user data given by the interface 311. Reference numeral 1402
designates a memory (RAM) for temporarily storing data. Reference numeral 2601 designates a scrambler for randomizing data. This scrambler is explained in the first embodiment mode, and includes an Maximum length sequence generator of a fixing seed and a random seed scrambler. Reference numeral 307 designates an error correction coding circuit for adding an error correcting code to the scrambled user data. Reference numeral 305 is a coding circuit for converting the user data adding the error correcting code thereto to a run length limit code suitable for the record to the optical disk 301. Reference numerals 302 and 1403
respectively designate a pickup for recording/regenerating data of the optical disk 301, and a spindle motor for rotating the disk. Reference numeral 1404 designates a servo for controlling the operation of the optical pickup 302, etc. Reference numeral 304 designates a read channel for performing waveform equalization processing of an analog regenerating signal read from the optical disk 301, a binary operation and synchronous clock generation. Reference numeral 306, designates a decoder for decoding the read run length limit code. Reference numeral 308 designates an error detection-correction circuit for detecting an error on the basis of the error correcting code added by the error correction coding circuit 307, and correcting the error. Reference numeral 310 designates a descramble circuit for releasing the randomization performed by the scrambler 309 and returning the user data to the original user data and also shown in the first embodiment mode. The descramble circuit 310
includes the Maximum length sequence generator of a fixing seed and a random seed descrambler. Reference numeral 1407 designates an ID deleting device for deleting the additional information such as ID, etc. added by the ID adder 1401 and required to make a record, and setting only the user data.
[0128] As shown in FIG. 23, a memory 2604 is constructed by a memory 2301
for recording a rewriting number read from tracks 3001 to 3002 of the optical disk 301, a 1-bit register 2302 and an inverter 2303. When a seed for the random seed scramble is required at a writing time of data, CLOCK 2304 is inputted and the value of the 1-bit register 2302 is inverted. 8
bits provided by adding lower 7 bits of the rewriting number of a written ECC block recorded to the rewriting number recording memory 2301 and the value of the 1-bit register 2302 are outputted to the scramble circuit 2601 as the seed of the random seed scramble.
[0129] Next, in this third embodiment mode, the scramble is again performed by using a second seed to obtain a series of preferable run length limit codes. When the seed for the rescramble is required, the CLOCK 2304 is again-inputted, and the value of the 1-bit register 2302 is inverted. 8 bits provided by adding lower 7 bits of the rewriting number of the written ECC block recorded to the rewriting number recording memory 2301 and the value of the 1-bit register 2302 are outputted to the scramble circuit 2601 as the seed of the random seed scramble. The first seed and the second seed first given are inverted with respect to only a lower 1 bit. This seed generator is one example, and the seed of four or more combinations may be also able to be selected in one writing by setting the shift register 2302 to two bits or more.
[0130] The operation of the optical disk device shown in FIG. 28 will next be explained. This operation at a power turning-on time or an insertion time of the optical disk will first be explained on the basis of FIG. 32. First, when the power of the optical disk device is turned on (step 3201), the optical disk device 2801 confirms whether the optical disk 301
is inserted into this device (step 3202). If no optical disk 301 is inserted, the step 3202 is repeated and the optical disk device waits for the insertion of the optical disk 301. When the optical disk is inserted (step 3203), rewriting number information of the ECC block of the entire disk written to a rewriting number recording area (tracks 3001 to 3002) is read (step 3204). First, the run length limit code is decoded (step 3205), and is stored to the RAM 1402 (step 3206). An error correction of the BIS area is then made (step 3207), and ID written to the BIS area is confirmed (step 3208). In this third embodiment mode, since no BIS area is scrambled, no descramble processing is performed.
[0131] If the ID is that of the rewriting number recording area, the error correction of the LDC area is made (step 3209), and an error is detected by the EDC (step 3210). When no error is detected by the EDC, no inserted optical disk corresponds to the random seed scramble with the rewriting number as one portion of the seed so that an information bit 2805 is reset (step 3217) and it is terminated. In contrast to this, when the error is detected by the EDC, the data are descrambled (step 3211), and the error detection is again performed by the EDC (step 3212). When the error is detected by the EDC, the processing is again performed from the step 3204. In contrast to this, when no error is detected by the EDC, the added seed, ID information, etc. are deleted (step 3213), and the EDC is deleted (step 3214). Further, the information bit 2805 is set (step 3215), and the data of the rewriting number are stored to the memory 2604
(step 3216). The operation of the optical disk device at the power turning-on time or the disk insertion time is then terminated, and the optical disk device waits for the instruction of commands from the host interface.
[0132] The operation of the optical disk device at a recording time will next be explained with reference to the format shown in FIG. 22 and the processing procedures at the recording time shown in FIGS. 33, 34 and 24.
[0133] First, as shown in FIG. 33, when information about a written sector is given from the interface 311, the ID adding circuit 1401 generates additional information such as identification address information of data of ID, etc., copy protection information, reserve information, etc., and inputs the additional information to the error correction coding circuit 307. The ID adding circuit 1401 further stores the additional information to a storing place in the BIS area of areas A2802 and B2803 of the RAM 1402 (step 3301). As shown in FIG. 22, each of the areas A2802 and B2803
is divided so as to store data, and the additional information is stored to the BIS area shown by each of 1005, 1006 and 1007. A seed storing area 2201 for storing the seed of the random seed scramble is arranged in the BIS area, and is made such that the seed of 1 byte can be stored to two physical blocks. Next, if no optical disk intended to be written at present corresponds to the random seed scramble with reference to the information bit 2805 (step 3302), it proceeds to a step 2401 of FIG. 24. After the user data of 32 sectors are then read from the interface 311, a primary scramble using a fixing seed is performed (step 2402), and error correction coding is performed (step 2403). Thereafter, a writing operation to the RAM 1402 is performed (step 2404), and a synchronous signal is added (step 2405), and run length limit coding is then performed (step 2406). The run length limit code is then written to the optical disk 301 via the LD driver 1405 and the optical pickup 302 (step 2407).
[0134] Thereafter, the written data are read and compared with the data of the RAM as to whether the data are normally written to the optical disk (step 2408). When the data of 1 ECC block are normally recorded onto the optical disk 301, the processing is terminated. However, when it is unsuccessful in the record for a certain reason during the record of the data, the processing is again performed from the step 2406. Namely, the processing is again performed from the conversion of the data of the RAM 1402 to the run length limit code.
[0135] When the information bit 2805 is set and the optical disk 301
written at present corresponds to the random seed scramble, the rewriting number corresponding to the written ECC block is first read from the memory 2604 (step 3303), and "1" is added to the rewriting number and the added number is stored to the memory 2604 (step 3304). At this time, when the rewriting number exceeds a constant value, e.g., 80,000 times, replacement processing with a different physical sector is performed by supposing that reliability is reduced by deterioration of the medium. Therefore, replacing sector processing (step 3308) is performed, and it is again returned to the step 3301, and the ID, etc. are re-added and the record processing is again performed. When the rewriting number is a constant value or less, the user data of 32 logic sectors are read from the interface 311 (step 3306), and are first sent to the scramble circuit 2601, and the primary scramble is performed by adding an Maximum length sequence by the fixing seed using one portion of the ID, etc. (step 3307). The processing after the step 3309 is performed of two physical blocks each. One physical block shows 31 stages (one stage corresponds to 1 byte in the longitudinal direction) in FIG. 22.
[0136] The processing case of first two physical blocks will first be explained. A first seed constructed by lower 7 bits of the rewriting number added by "1" and the output of the 1-bit register 2302 is stored to a seed (uppermost seed) with the physical block processed at present as one of seeds 2201 shown in FIG. 22 within an area A2802 of the RAM 1402 (step 3309). Next, the data of the BIS area within the first two physical blocks processed at present are changed to [62, 30, 33] RS codes by the error correction coding circuit 307 (step 3310). Next, the shift register of the random seed scramble circuit is set by the first seed (step 3311). The user data of the first two physical blocks are then random-seed-scrambled. At this time, the random seed scramble is performed in the order of the arrow 1009 of the recording-regenerating order shown in FIG. 22 (step 3312). When the physical block being processed is seventh and eighth sectors or fifteenth and sixteenth sectors (step 3313), the user data are intermediately interrupted so that the user data are changed to [248, 216, 33] RS codes (step 3314) and are written to the area A2802 of the RAM 1402 (step 3315). A synchronous signal is then added (step 3316), and the run length limit coding is performed (step 3317).
[0137] Next, a second seed inverted in only a lower 1 bit with respect to the first seed is stored to the seed (uppermost seed) within the physical block processed at present as one of seeds 2201 shown in FIG. 22 within an area B2803 of the RAM 1402 (step 3318). The data of the BIS area within the first two physical blocks processed at present are changed to [62, 30, 33] RS codes by the error correction coding circuit 307 (step 3319). Next, a shift register of the random seed scramble circuit is set by the second seed (step 3320). The user data of the first two physical blocks are then random-seed-scrambled. At this time, the random seed scramble is performed in the order of the arrow 1009 of the recording-regenerating order shown in FIG. 22 (step 3321). When the physical block being processed is seventh and eighth sectors or fifteenth and sixteenth sectors (step 3322), the user data are intermediately interrupted so that the user data are changed to [248, 216, 33] RS codes (step 3323) and are written to the area B2803 of the RAM 1402 (step 3324). A synchronous signal is then added (step 3325), and the run length limit coding is performed (step 3326). A preferable sequence in nature among the sequences of the two run length limit codes made in the steps 3317 and 3326 is selected (step 3327), and is written to the optical disk 301 via the LD driver 1405 and the optical pickup 302 (step 3328).
[0138] Here, various methods such as the following three methods, etc. are considered as a selecting method of the preferable sequence in nature. (1) A sequence for providing small sizes of a maximum mark and a maximum space is selected. (2) A sequence for providing a low value of a low frequency component of the code is selected. (3) A sequence for providing small generation frequencies of a minimum mark and a minimum space is selected.
[0139] When the selected sequence is next generated from the second seed, the seed and the random-seed-scrambled sequence are next transferred from the area B2803 of the RAM 1402 to the area A2802. In contrast to this, when the selected sequence is generated from the first seed, the seed and the random-seed-scrambled sequence are transferred from the area A2802 of the RAM 1402 to the area B2803 (step 3329). This operation is repeated until the processing of 1 ECC block is terminated (step 3330). After the processing of the 1 ECC block is terminated, the written data are read and compared with the data of the RAM as to whether the data are normally written to the optical disk (step 3331). When the data of the 1 ECC block are normally recorded onto the optical disk 301, the processing is terminated.
[0140] However, when it is unsuccessful in the record for a certain reason during the record of the data, deterioration of the medium is caused when the same data are written to the same place. Accordingly, in this case, the scramble is again performed by changing the seed, and the data are rewritten. Namely, the processing shown in FIG. 34 is performed. First, the rewriting number of the corresponding ECC block stored to the memory 2604 is read (step 3401), and "1" is added to the rewriting number, and the added number is stored to the memory 2604 (step 3402). The first seed constructed by lower 7 bits of the rewriting number and the output of the 1-bit register 2302 is stored to a seed (uppermost seed) within the physical block processed at present as one of seeds 2201 shown in FIG. 22
within the area A2802 of the RAM 1402 (step 3403). At this time, since the rewriting number is added by one, the seed becomes a seed different from that at the first time at any time. Next, the data of the BIS area within the first two physical blocks processed at present are changed to [62, 30, 33] RS codes by the error correction coding circuit 307 (step 3404). Next, the random-seed-scrambled data of the first two physical blocks stored into the area A2802 of the RAM 1402 are descrambled (step 3405).
[0141] Next, the shift register of the random seed scramble circuit is set by the first seed (step 3406). Next, the descrambled user data are random-seed-scrambled. At this time, the random seed scramble is performed in the order of the arrow 1009 of the recording-regenerating order shown in FIG. 22 (step 3407). When the physical block being processed is seventh and eighth sectors or fifteenth and sixteenth sectors (step 3408), the user data are intermediately interrupted so that the user data are changed to [248, 216, 33] RS codes (step 3409) and are written to the area A2802 of the RAM 1402 (step 3410). Further, a synchronous signal is added (step 3411), and the run length limit coding is performed (step 3412). Next, a second seed inverted in only a lower 1
bit with respect to the first seed is stored to a seed (uppermost seed) within the physical block processed at present as one of seeds 2201 shown in FIG. 22 within the area B2803 of the RAM 1402 (step 3413).
[0142] Next, the data of the BIS area within the first two physical blocks processed at present are changed to [62, 30, 33] RS codes by the error correction coding circuit 307 (step 3414). Next, the shift register of the random seed scramble circuit is set by the second seed (step 3415). The user data obtained in the step 3405 is then random-seed-scrambled. At this time, the random seed scramble is performed in the order of the arrow of the recording-regenerating order shown in FIG. 22 (step 3416). When the physical block being processed is seventh and eighth sectors or fifteenth and sixteenth sectors (step 3417), the user data are intermediately interrupted so that the user data are changed to [248, 216, 33] RS codes (step 3418) and are written to the area B2803 of the RAM 1402 (step 3419). Further, a synchronous signal is added (step 3420), and the run length limit coding is performed (step 3421). A preferable sequence in nature among the sequences of the two run length limit codes made in the steps 3412 and 3421 is selected (step 3422), and is written to the optical disk 301 via the LD driver 1405 and the optical pickup 302
(step 3423).
[0143] Next, when the selected sequence is generated from the second seed, the seed and the random-seed-scrambled sequence are transferred from the area B2803 of the RAM 1402 to the area A2802. In contrast to this, when the selected sequence is generated from the first seed, the seed and the random-seed-scrambled sequence are transferred from the area A2802 of the RAM. 1402 to the area B2803 (step 3424). This operation is repeated until the processing is terminated by 1 ECC block (step 3425). When the processing is terminated by the 1 ECC block, the written data are read and compared with the data of the RAM as to whether the data are normally written to the optical disk (step 3426). When the data of the 1 ECC block are normally recorded onto the optical disk 301, the processing is terminated.
[0144] The operation of the optical disk device at a regenerating time will next be explained with reference to the processing procedure of FIG. 25. First, the optical disk device 2801 reads data from the optical disk (step 2501), and the run length limit code is first decoded (step 2502) and is stored to the RAM 1402 (step 2503). An error correction of the BIS area is then made (step 2504), and ID written to the BIS area is confirmed (step 2505). In this third embodiment mode, no descramble processing is performed since no BIS area is scrambled. If the ID is the ID of the ECC block in a reading request, the error correction of the LDC area is made (step 2506), and the error is detected by the EDC (step 2507). When no error is detected by the EDC, it proceeds to a step 2510. In contrast to this, when the error is detected by the EDC, the data are descrambled (step 2508), and the error detection is again performed by the EDC (step 2509). When the error is detected by the EDC, the processing is again performed from the step 2501. In contrast to this, when no error is detected by the EDC, added seed, ID information, etc. are deleted (step 2510), and the EDC is deleted (step 2511), and the user data decoded from the interface 311 are outputted (step 2512). When a random-seed-scrambled area and an area not random-seed-scrambled are mixed and exist in one disk, the reading operation can be simply performed by such control without particularly arranging a special bit, etc. in a format showing this mixture.
[0145] Next, the operation of the optical disk device at the power turning-off time and the optical disk fetching time will be explained with reference to the processing procedure shown in FIG. 36. At the generating time of power turning-off instructions or optical disk fetching instructions, the optical disk device 2801 first refers to an information bit 2805 (step 3603). When the information bit 2805 is cleared, it proceeds to a step 3606. In contrast to this, when the information bit 2805 is set, data of the memory 2604 are read (step 3604), and all rewriting number counts corresponding to the rewriting number recording area are counted up by one (step 3605). Thereafter, the rewriting number stored to the memory 2604 is written from a track 3001
of the disk 301 to a track 3002 in accordance with a writing sequence after the step 3307 of the writing sequence of FIG. 33 (step 3606). Thereafter, the optical disk is taken out and the power is turned off (step 3606).
[0146] As shown in this third embodiment mode, after plural RLL sequences are generated, one sequence having preferable characteristics is selected. Thus, a technique for making the disk from the sequence of good nature is particularly effective in a ROM disk making device. A construction similar to that in this third embodiment mode can be used in the ROM disk making device.
[0147] Further, in accordance with the third embodiment mode, a run length code sequence of better nature can be obtained by selecting this sequence from plural sequences.
[0148] Next, a fourth embodiment mode will be explained with reference to FIGS. 18 and 13. FIG. 18 is a schematic block diagram of an optical disk device 2801 shown in this fourth embodiment mode. Reference numeral 311
designates an interface for performing input-output control of data with respect to an upper device. Reference numeral 1406 designates a microcomputer for generalizing a system. The microcomputer 1406 is connected to a control circuit 1411 within the system. The control circuit 1411 controls the operations of a seed generator 2603, an error correction coding circuit 307, a scrambler 2601, etc. through an unillustrated control line. Reference numeral 1401 designates an ID adder for adding additional information such as ID, etc. required to make a record to user data given by the interface 311. Reference numeral 307
designates an error correction coding circuit for adding an error correcting code to the user data. Reference numeral 1402 designates a memory (RAM) for temporarily storing data. Reference numeral 2601
designates a scrambler for randomizing data. This scrambler is explained in the first embodiment mode, and includes an Maximum length sequence generator of a fixing seed and a random seed scrambler. Reference numeral 305 designates a coding circuit for converting the scrambled user data to a run length limit code suitable for the record to the optical disk 301. Reference numeral 302 designates a pickup for recording/regenerating data of the optical disk 301. Reference numeral 1403 designates a spindle motor for rotating the disk.
[0149] Reference numeral 1404 designates a servo for controlling the operation of the optical pickup 302, etc. Reference numeral 304
designates a read channel for performing waveform equalization processing of an analog regenerating signal read from the optical disk 301, a binary operation and synchronous clock generation. Reference numeral 306
designates a decoder for decoding a read run length limit code. Reference numeral 310 designates a descramble circuit for releasing the randomization performed by the scrambler 309 and returning user data to the original user data and also shown in the first embodiment mode. The descramble circuit 310 includes an Maximum length sequence generator of a fixing seed and a random seed descrambler. Reference numeral 308
designates an error detection-correction circuit for detecting an error on the basis of an error correcting code added by the error correction coding circuit 307, and correcting the error. Reference numeral 1407
designates an ID deleting circuit for deleting additional information such as ID, etc. required to make a record and added by the ID adder 1401, and setting only the user data. Reference numeral 2603 designates a seed generator for generating and giving a new seed to the scrambler 309
every writing processing.
[0150] The operation of the optical disk device shown in FIG. 18 will next be explained with reference to FIG. 17. First, at a recording time, additional information such as ID, etc. required to make a record is added to user data inputted from the host interface 311 by the ID adder 1401. Thereafter, the added user data are changed to an error correcting code by the error correction coding circuit 307, and are stored to the RAM 1402 in accordance with the format shown in FIG. 12. Thereafter, the stored data are read in the unit of a physical sector, and are scrambled by a fixing seed. Thereafter, the seed given from the seed generator 2603
is added to the head of the data read from the RAM, and the random seed scramble is performed. Run length limit coding is then performed by the run length limit coding circuit 305, and the run length limit code is written to the optical disk 301. Thereafter, it is confirmed by reading the data whether the data are normally written to the optical disk. When no data are normally written to the optical disk, the data stored to the RAM 1402 are again scrambled by using the fixing seed, and the random seed scramble is performed by changing the seed. The run length limit coding is then performed by the run length limit coding circuit 305, and the run length limit code is written to the optical disk 301. When the run length limit code is written to the optical disk, the run length limit code is written in accordance with the format shown in FIG. 13. Namely, seed 1 byte 3708 after the scramble is written to generate a sector after Header 3702 and Mirror 3703 formed on the optical disk, Gap 3704 for absorbing the shift of writing start timing, Guard 3705, VFO area 3706 for generating a regenerating clock, and PS 3707 for taking byte synchronization.
[0151] Thereafter, the user data are written in accordance with the format of FIG. 12. With respect to the storing place of the seed, the seed may be buried into an unused area among BIS areas 1005, 1006, 1007 shown in FIG. 12. Next, the operation of the optical disk device at the regenerating time will be explained. At the regenerating time, data read from the optical disk are first decoded by the run length limit code decoding circuit 306, and the seed is taken out of the head position 3708
of the data or the BIS areas 1005, 1006, 1007. The random seed descramble and the descramble of the fixing seed scramble are then performed by the descramble circuit 310, and the descrambled data are stored to the RAM 1402 (step 3206). Error correction processing is then performed by the error correcting circuit 308, and added ID information, etc. are deleted and the remaining data are outputted to the host interface.
[0152] As shown in this embodiment mode, error correction coding processing can be omitted in rewriting processing by performing the random seed scramble on the medium side from the error correcting circuit. Accordingly, the rewriting processing can be executed at high speed.
[0153] Next, a fifth embodiment mode will be explained with reference to FIG. 26. In the fifth, sixth and seventh embodiment modes, a method for applying the random seed scramble to the optical disk device controlled by the existing optical disk control LSI building-in the error correction coding circuit, etc. will be described. First, in the fifth embodiment mode, a scramble LSI 2605 for performing the random seed scramble processing is arranged on the host interface side from the optical disk control LSI 2611. The scramble LSI 2605 includes an interface 2610 for performing data input-output control with respect to the host computer, a scramble circuit 2607, a descramble circuit 2609, and an interface circuit 2608 for outputting a signal similar to that of the interface circuit of the host computer, and performing data input-output control with respect to the interface circuit 311 of the optical disk control LSI 2611. A seed generator 2613, the scramble circuit 2607 and the descramble circuit 2609 are the same as those explained in the second embodiment mode. A microcomputer 1406 is connected to a control circuit 2614 within the scramble LSI 2605, and this control circuit 2614 controls the operations of the seed generator 2613, the scramble circuit 2607, etc. through an unillustrated control line.
[0154] The operation of the optical disk device at the recording time will next be explained. When information such as the size of data, the ID of a recording place, etc. with respect to a written sector is first given from the interface 311, information given to the optical disk control LSI 2611 is transmitted as it is through the interface 2608. Next, when the user data of a first one logic sector (2048 bytes) is received from the interface 2610, the seed generator 2613 generates a new seed, and transmits this new seed to the scramble circuit 2607. The scramble circuit 2607 adds the seed to the head of the user data of one logic sector and performs the scramble. First 1 byte of the sequence after the scramble is read by the microcomputer 1406, and the subsequent sequence of 2048 bytes after the scramble is transferred to the optical disk control LSI 2611 through the interface 2608. Next, when the user data of a second 1 logic sector (2048 bytes) are received and this logic sector is data to be written to the same ECC block as the above first logic sector, no seed generator 2613 generates a new seed.
[0155] When this logic sector is data to be written to the ECC block different from the above first logic sector, the seed generator 2613
generates a new seed. Thus, the user data of 1 ECC block are read. The optical disk control LSI 2611 generates additional information 720 byte such as identification address information of data of ID, etc., copy protection information, reserve information, etc. from the above sector information by the ID adder 1401, and writes the generated additional information to the RAM 1402 in the format shown in FIG. 12. The additional information is written to three BIS areas 1005, 1006, 1007
shown in FIG. 12. The microcomputer 1406 writes first 1 byte of the sequence previously scrambled and read to a reserve area written by a fixing value within the above additional information 720 byte within the BIS areas 1005, 1006, 1007 of the RAM 1402. The additional information 720 byte including the 1 byte written by the microcomputer 1406 is divided into 24 pieces of 30 bytes each. The error correction coding circuit 307 changes these data of 30 bytes each to [62, 30, 33] RS codes, and stores the respective RS codes to the three BIS areas 1005, 1006, 1007 of the RAM 1402 shown in FIG. 12 of 8 code words each.
[0156] Next, the user data 1101 of 2048 bytes (corresponding to 1 logic sector) are read from the interface 311. The ID adder 1401 adds an error detection code (EDC) of 4 bytes to the user data inputted from the interface 311, and stores the added data to the RAM 1402. Next, these data are transferred to the error correction coding circuit 307, and are changed to [248, 216, 33] RS (Reed Solomon) codes of 216 bytes each, and are stored to four LDC areas 1001, 1002, 1003, 1004 of the RAM 1402 shown in FIG. 12. After the user data of 1 ECC block are read and the error correction coding is performed, a synchronous signal (SYNC code) 1008 is further added to the left-hand end of the error correction code. Next, the coding circuit 305 reads data from the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12 and showing the recording-regenerating order, and continuously reads data at 31 stages (one stage corresponds to 1 byte in the longitudinal direction) as a "physical sector" of 4 k bytes, and changes these data to a run length limit code. The run-length-limit-coded data of 4 k bytes are written to the optical disk 301 via the LD driver 1405 and the optical pickup 302.
[0157] Next, the processing procedure at the regenerating time will be explained. At the regenerating time, data are read from the optical pickup 302, and a binary operation is performed and a synchronous clock is generated in the read channel 304. In the decoding circuit 306, the decoding operation is performed from the run length limit code, and regenerated data are temporarily stored to the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12. The error detection/correction circuit 308 first performs error correction processing of additional information 720 byte such as ID, etc. including first 1 byte of a sequence scrambled and stored to the BIS area shown in FIG. 12. Next, it is confirmed whether the ID written to the BIS area performed with respect to the error correction processing is the ID of an ECC block intended to be regenerated. Here, if the ID is the ID of the ECC block or a sector desirously read, the microcomputer 1406 first reads the first 1
byte of the scrambled sequence stored to the BIS area, and returns the data of the RAM storing this 1 byte thereto to a fixing value of the reserve area. Then, the error correction processing of the LDC area is performed, and the additional information 720 byte such as ID, etc. is deleted by the ID deleting circuit 1407, and an error is checked by using the EDC. Thereafter, the user data 2048 byte are transferred to the descramble circuit 2609 via the interfaces 311, 2608. The microcomputer 1406 adds the first 1 byte of the scrambled sequence read from the BIS area to the head of the user data 2048 byte, and performs the descramble. The descrambled sequence is transferred from the interface 2610 to the host computer.
[0158] Thus, in accordance with the construction of the fifth embodiment mode, the scramble is released after the error correction processing is terminated. Accordingly, no deterioration of error correction ability due to error propagation of the random seed scramble is generated. Further, in the fifth embodiment mode, the random seed scramble processing is performed by using the same seed in each logic sector in the 1 ECC block. However, a method for continuously scrambling the 1 ECC block 64 Kbytes is also considered. Further, a method for performing the random seed scramble processing by using a different seed every logic sector is considered. In this case, it is necessary to secure an area of 32 bytes in the BIS area as an area for storing the head byte after the scramble.
[0159] Further, the error propagation is generated in the random seed scramble. Accordingly, when it is considered to remedy data as much as possible in the case of error correction disability, it is desirable to perform the scramble processing on the user side from the error correction coding.
[0160] Next, a sixth embodiment mode will be explained with reference to FIG. 27. In the sixth embodiment mode, a scramble LSI 2701 for performing the random seed scramble processing is arranged closer to the optical disk medium side than the optical disk control LSI 2611. The scramble LSI 2701 includes decoding circuits 2704, 2706 of a run length limit code, coding circuits 2702, 2705, a scramble circuit 2703, a descramble circuit 2707, and a seed generator 2708. The scramble circuit 2703 and the descramble circuit 2707 are the same as those explained in the third embodiment mode. The seed generator is the same as that explained in the second embodiment mode.
[0161] The operation of the optical disk device at the recording time will next be explained. When information about a written sector is first given from the interface 311, the optical disk control LSI 2611 generates additional information 720 byte such as identification address information of data of ID, etc., copy protection information, reserve information, etc. from information about the above sector by the ID adding circuit 1401, and writes this additional information to the RAM 1402 in the format shown in FIG. 12. The additional information is written to three BIS areas 1005, 1006, 1007 shown in FIG. 12. The additional information 720 byte generated in the ID adding circuit 1401
is changed to [62, 30, 33] RS codes of 30 bytes each, and is divided into 24 pieces. The error correction coding circuit 307 changes these data of 30 bytes each to [62, 30, 33] RS codes, and stores the respective RS codes to the three BIS areas 1005, 1006, 1007 of the RAM 1402 shown in FIG. 12 of 8 code words each.
[0162] Next, the user data 1101 of 2048 bytes (corresponding to 1 logic sector) are read from the interface 311. The ID adder 1401 adds an error detection code (EDC) of 4 bytes to the user data inputted from the interface 311, and stores the added data to the RAM 1402. Next, these data are transferred to the error correction coding circuit 307, and are changed to [248, 216, 33] RS codes of 216 bytes each, and are stored to four LDC areas 1001, 1002, 1003, 1004 of the RAM 1402 shown in FIG. 12. After the user data of 1 ECC block are read and the error correction coding is performed, a synchronous signal (SYNC code) 1008 is further added to the left-hand end of the error correcting code.
[0163] Next, the coding circuit 305 reads data from the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12 and showing the recording-regenerating order, and continuously reads data at 31 stages (one stage corresponds to 1 byte in the longitudinal direction) as a "physical sector" of 4 k bytes, and changes these data to a run length limit code. The run-length-limit-coded data of 4 k bytes are transferred to the scramble LSI 2701. The scramble LSI 2701 returns the run-length-limit-coded data of 4 k bytes to user data by the decoding circuit 2704. The seed of 1 byte generated by the seed generator 2708 is buried to a reserve area of the BIS area, and is used as a preset value of the random seed scrambler. The decoded user data are scrambled-processed by the scrambler 2703, and are then again changed to a run length limit code by the coding circuit 2702. The run length limit code is written to the optical disk 301 via the LD driver 1405 and the optical pickup 302.
[0164] Next, the processing procedure at the regenerating time will be explained. At the regenerating time, data are read from the optical pickup 302, and a binary operation is performed and a synchronous clock is generated in the read channel 304. In the decoding circuit 2706, the decoding operation is performed from the run length limit code, and the seed buried to the BIS area is taken out. The taken-out seed is used as a preset value of the random seed descrambler within the descramble circuit 2707. The descrambled sequence is again changed to a run length limit code by the coding circuit 2705, and is sent to the optical disk control LSI 2611. The optical disk control LSI 2611 again decodes the run length limit code, and temporarily stores regenerated data to the RAM 1402 in accordance with the arrow 1009 shown in FIG. 12. The error detection/correction circuit 308 first performs the error correction processing of additional information 720 byte such as ID, etc. stored to the BIS area shown in FIG. 12. Next, it is confirmed whether the ID written to the BIS area and performed with respect to the error correction processing is the ID of an ECC block intended to be regenerated.
[0165] Here, if the ID is the ID of the ECC block or a sector desirously read, the error correction processing of the LDC area is performed, and the additional information 719 byte such as ID, etc. is deleted by the ID deleting circuit 1407, and an error of the user data 2048 byte is checked by using the EDC. Thereafter, the user data 2048 byte are transferred to the host computer via the interface 311. Thus, in accordance with the construction of the sixth embodiment mode, the random seed scramble can be applied by adding the scramble LSI 2701 to the existing optical disk control LSI 2611.
[0166] Next, a seventh embodiment mode will be explained with reference to FIG. 35. In the seventh embodiment mode, the random seed scramble processing is performed in software by the microcomputer 1406.
[0167] The operation of the optical disk device at the recording time will next be explained. When information about a written sector is first given from the interface 311, the optical disk control LSI 2611 generates additional information 720 byte such as identification address information of data of ID, etc., copy protection information, reserve information, etc. from the information about the above sector by the ID adding circuit 1401. The microcomputer 1406 determines a seed by making a calculation shown by the following formula 8.
[0168] [Formula 8]
SD(k)=(SD(k-1)+n)mod256
[0169] Here, k shows k-th seed generation, and n is a suitable prime number with respect to 256. The seed of 1 byte generated by the microcomputer 1406 is written to the reserve area within 720 bytes generated by the ID adding circuit 1401 through a control line 3801. The 720 bytes are divided into 24 pieces of 30 bytes each. The error correction coding circuit 307 changes these data of 30 bytes each to [62, 30, 33] RS codes, and stores the respective RS codes to three BIS areas 1005, 1006, 1007 of the RAM 1402 shown in FIG. 12 of 8 code words each.
[0170] Next, the user data 1101 of 2048-bytes (corresponds to 1 logic sector) are read from the interface 311. The ID adder 1401 adds an error correction code (EDC) of 4 bytes to the user data inputted from the interface 311, and stores these data to the RAM 1402. Next, the microcomputer 1406 performs the scramble by making a calculation shown by the following formula 2 with respect to the data stored to the RAM through a control line 3802.
[0171] [Formula 2]
c.sub.i=b.sub.i+c.sub.i-4+c.sub.i-5+c.sub.i-6+c.sub.i-8
[0172] In this calculation, b.sub.i shows read i-th user data. The data are read from the head of the user data of the RAM 1402 every 1 bit, and the calculation is made by substituting these data for this b.sub.i. Reference numeral c.sub.i designates an i-th calculated result, and is a value after the scramble. The microcomputer 1406 writes the value of c.sub.i to the RAM. The seed of 1 byte generated by the microcomputer is