1. An apparatus for parallel data processing over a plurality of phases, comprising:
a plurality of processors, any one of said processors operative as a master processor, said master processor including means for generating interconnection switch configuration control signals;
a communication bus for interconnecting each of said processors, for exchange of at least control and synchronization information among each of said processors;
a plurality of multi-access memory modules;
an interconnection switch coupled to each of said processors and each of said multi-access memory modules, and responsive to said interconnection switch control signals from said master processor, for selectively interconnecting any one or more of said processors with one or more of said multi-access memory modules, and whereby any one of said multi-access memory modules is exclusively interconnected to only one of said processors during any given phase of processing;
each of said processors further including local memory, whereby one or more of said processors processes data in its local memory before, after, and during a phase of processing;
said master processor further including means for generating a processing phase commencement signal over said communication bus to the other of said processors, said commencement signal indicating the start of each of said plurality of phases of parallel data processing during which any one or more of said plurality of processors is exclusively interconnected to said one or more multi-access memory modules; and
each of said processors further including means for generating a completion signal over said communication bus to the other of said processors said completion signal indicating completion of each phase of processing.