|
| | |
|
Your search returned 551 patents.
( 716/7 in Current US Classification ) |
|
|
| 1 2 3 4 5 6 |
| Patent ID | Title | Date Filed |
| 7203917 | Efficient distributed SAT and SAT-based distributed bounded model checking
| March 9, 2004 |
| 7055126 | Renesting interaction map into design for efficient long range calculations
| October 27, 2003 |
| 7051307 | Autonomic graphical partitioning
| December 3, 2003 |
| 7051298 | Method and apparatus for specifying a distance between an external state and a set of states in space
| December 31, 2002 |
| 7051293 | Method and apparatus for creating an extraction model
| January 31, 2002 |
| 7047511 | Electronic circuit design
| September 26, 2003 |
| 7047510 | Method and system for partitioning an integrated circuit design
| April 23, 2003 |
| 7047506 | Method to identify geometrically non-overlapping optimization partitions for parallel timing closure
| November 19, 2003 |
| 7047162 | Computer assisted method for partitioning an electric circuit
| November 7, 1997 |
| 7043711 | System and method for defining semiconductor device layout parameters
| June 26, 2002 |
| 7039891 | Method of clock driven cell placement and clock tree synthesis for integrated circuit design
| August 27, 2003 |
| 7039887 | Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques
| October 15, 2002 |
| 7039883 | Derivation of circuit block constraints
| December 5, 2003 |
| 7039880 | Circuit design method, apparatus and program using polynomial primitive root
| November 12, 2003 |
| 7039576 | System verification equipment, system verification method and LSI manufacturing method using the system verification equipment
| November 14, 2001 |
| 1 2 3 4 5 6 |
|
|
|
|
|
|
|
|
|
|
|