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| Patent ID | Title | Date Filed |
| 7181704 | Method and system for designing integrated circuits using implementation directives
| August 6, 2004 |
| 7181703 | Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
| July 22, 2003 |
| 7178114 | Scripted, hierarchical template-based IC physical layout system
| June 7, 2004 |
| 7174519 | Vector Logic techniques for multilevel minimization
| September 5, 2003 |
| 7171637 | Translation generation for a mask pattern
| January 14, 2005 |
| 7171636 | Pass-transistor logic circuit and a method of designing thereof
| May 9, 2003 |
| 7171635 | Method and apparatus for routing
| December 31, 2002 |
| 7171632 | Apparatus, method and program for designing semiconductor integrated circuit
| May 24, 2004 |
| 7168061 | Method, system and program product for implementing a read-only dial in a configuration database of a digital design
| April 28, 2003 |
| 7165230 | Switch methodology for mask-programmable logic devices
| June 2, 2004 |
| 7162707 | Scan path timing optimizing apparatus determining connection order of scan path circuits to realize optimum signal timings
| May 28, 2003 |
| 7159202 | Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages
| July 29, 2003 |
| 7159201 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification
| July 23, 2004 |
| 7159196 | System and method for providing interface compatibility between two hierarchical collections of IC design objects
| February 4, 2004 |
| 7158401 | Methods for machine detection of at least one aspect of an object, methods for machine identification of a person, and methods of forming electronic systems
| November 30, 2004 |
| 7155688 | Memory generation and placement
| November 17, 2004 |
| 7155687 | Methods and apparatus for scan insertion
| May 4, 2004 |
| 7152214 | Recognition of a state machine in high-level integrated circuit description language code
| December 15, 2003 |
| 7149675 | System and method for automatically mapping state elements for equivalence verification
| March 9, 2001 |
| 7146591 | Method of selecting cells in logic restructuring
| November 19, 2004 |
| 7146584 | Scan diagnosis system and method
| October 30, 2001 |
| 7146583 | Method and system for implementing a circuit design in a tree representation
| August 6, 2004 |
| 7146302 | Method, system and program product that utilize a configuration database to configure a hardware digital system having an arbitrary system size and component set
| April 28, 2003 |
| 7143388 | Method of transforming software language constructs to functional hardware equivalents
| February 17, 2005 |
| 7143375 | Logical equivalence verifying device, method and computer readable medium thereof
| November 12, 2003 |
| 7143329 | FPGA configuration memory with built-in error correction mechanism
| March 9, 2004 |
| 7143020 | Method and system for generic inference of sequential elements
| October 7, 1999 |
| 7137082 | Reduced architecture processing paths
| March 29, 2004 |
| 7137079 | Memory compiler with ultra low power feature and method of use
| January 6, 2004 |
| 7136947 | System and method for automatically synthesizing interfaces between incompatible protocols
| June 10, 1999 |
| 7134105 | Multiple level transistor abstraction for dynamic circuits
| December 9, 2003 |
| 7134104 | Method of selectively building redundant logic structures to improve fault tolerance
| December 5, 2003 |
| 7131087 | Multi-cycle path analyzing method
| November 13, 2003 |
| 7131079 | Method of generating protected standard delay format file
| May 4, 2004 |
| 7131078 | Method and apparatus for circuit design and synthesis
| August 21, 2003 |
| 7131077 | Using an embedded processor to implement a finite state machine
| March 28, 2003 |
| 7130787 | Functional replicator of a specific integrated circuit and its use as an emulation device
| October 30, 2000 |
| 7127692 | Timing abstraction and partitioning strategy
| June 27, 2002 |
| 7124385 | Method for automated transistor folding
| September 8, 2003 |
| 7124381 | Method of estimating crosstalk noise in lumped RLC coupled interconnects
| May 25, 2004 |
| 7120894 | Pass-transistor logic circuit and a method of designing thereof
| May 9, 2003 |
| 7117465 | Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs
| June 30, 2003 |
| 7117463 | Verification of digital circuitry using range generators
| November 6, 2002 |
| 7117140 | Method of evaluating the exposure property of data to wafer
| April 23, 2002 |
| 7114134 | Automatic circuit design method with a cell library providing transistor size information
| May 27, 2004 |
| 7114133 | Broken symmetry for optimization of resource fabric in a sea-of-platform architecture
| March 25, 2004 |
| 7111267 | Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths
| August 27, 2004 |
| 7111224 | FPGA configuration memory with built-in error correction mechanism
| February 28, 2001 |
| 7110929 | System and method of providing additional circuit analysis using simulation templates
| November 12, 1999 |
| 7107568 | System and method for reducing wire delay or congestion during synthesis of hardware solvers
| October 7, 2002 |
| 7107567 | Electronic design protection circuit
| April 6, 2004 |
| 7107557 | Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit
| April 1, 2003 |
| 7107553 | Method and apparatus for solving constraints
| August 18, 2003 |
| 7107201 | Simulating a logic design
| August 29, 2001 |
| 7103858 | Process and apparatus for characterizing intellectual property for integration into an IC platform environment
| April 14, 2004 |
| 7103620 | Method and apparatus for verification of digital arithmetic circuits by means of an equivalence comparison
| October 22, 2002 |
| 7100144 | System and method for topology selection to minimize leakage power during synthesis
| December 9, 2003 |
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