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Your search returned 459 patents.
( 716/14 in Current US Classification ) |
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| Patent ID | Title | Date Filed |
| 7114141 | Method and apparatus for decomposing a design layout
| August 14, 2002 |
| 7109751 | Methods of implementing phase shift mask compliant static memory cell circuits
| June 2, 2004 |
| 7107564 | Method and apparatus for routing a set of nets
| January 31, 2002 |
| 7107556 | Method and system for implementing an analytical wirelength formulation for unavailability of routing directions
| December 29, 2004 |
| 7103864 | Semiconductor device, and design method, inspection method, and design program therefor
| October 8, 2003 |
| 7096449 | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
| August 26, 2002 |
| 7096448 | Method and apparatus for diagonal routing by using several sets of lines
| January 5, 2002 |
| 7096443 | Method for determining the critical path of an integrated circuit
| July 15, 2003 |
| 7093223 | Noise analysis for an integrated circuit model
| November 26, 2002 |
| 7093222 | Power supply wiring method for semiconductor integrated circuit and semiconductor integrated circuit
| September 4, 2003 |
| 7093221 | Method and apparatus for identifying a group of routes for a set of nets
| December 31, 2002 |
| 7089526 | Maximum flow analysis for electronic circuit design
| January 14, 2003 |
| 7089524 | Topological vias route wherein the topological via does not have a coordinate within the region
| August 28, 2002 |
| 7086024 | Methods and apparatus for defining power grid structures having diagonal stripes
| June 1, 2003 |
| 7086015 | Method of optimizing RTL code for multiplex structures
| May 12, 2004 |
| 7082590 | Three-dimensional wire harness assembly models from three-dimensional zone models
| October 23, 2003 |
| 7082581 | Integrated circuit with layout matched high speed lines
| February 19, 2003 |
| 7080342 | Method and apparatus for computing capacity of a region for non-Manhattan routing
| December 31, 2002 |
| 7080341 | Apparatus and method for integrated circuit power management
| September 9, 2004 |
| 7080331 | Method and system for automatic recognition of simulation configurations of an integrated circuit
| July 28, 2003 |
| 7076760 | Method and apparatus for specifying encoded sub-networks
| January 31, 2002 |
| 7076756 | Layout design method of semiconductor integrated circuit, and semiconductor integrated circuit, with high integration level of multiple level metalization
| November 4, 2003 |
| 7073155 | Method for computing and using future costing data in signal routing
| December 21, 2004 |
| 7073154 | Apparatus and methods for interconnect zones and associated cells in integrated circuits
| May 21, 2002 |
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