| 1 2 3 4 5 6 7 8 9 |
| Patent ID | Title | Date Filed |
| 7191415 | Clearance inspection apparatus and clearance inspection method
| April 13, 2005 |
| 7191412 | Method and apparatus for processing a circuit description for logic simulation
| September 28, 2005 |
| 7191380 | Defect-tolerant and fault-tolerant circuit interconnections
| September 10, 2003 |
| 7185304 | System and method for VLSI CAD design
| October 14, 2004 |
| 7185296 | Method of extraction of wire capacitances in LSI device having diagonal wires and extraction program for same
| July 27, 2004 |
| 7184919 | Dynamic routing for a measurement system
| August 30, 2002 |
| 7181711 | Prioritizing of nets for coupled noise analysis
| April 27, 2005 |
| 7181359 | Method and system of generic implementation of sharing test pins with I/O cells
| November 12, 2004 |
| 7178125 | Method for modeling triangle meshed interconnect structures using an electrically equivalent three rectangle combination for each triangle in the triangle mesh
| July 7, 2004 |
| 7178124 | Methods, algorithms, software, architectures and system for placing clocked components and routing timing signals in a circuit and/or layout
| May 30, 2003 |
| 7178123 | Schematic diagram generation and display system
| October 27, 2004 |
| 7178121 | Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design
| June 24, 2005 |
| 7174529 | Acute angle avoidance during routing
| February 14, 2004 |
| 7174528 | Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure
| October 10, 2003 |
| 7168053 | Method and system for implementing an analytical wirelength formulation
| December 29, 2004 |
| 7166492 | Integrated circuit carrier apparatus method and system
| November 14, 2003 |
| 7162704 | Method and apparatus for circuit design and retiming
| May 9, 2003 |
| 7155697 | Routing method and apparatus
| January 13, 2002 |
| 7155696 | Interconnection routing method
| May 17, 2004 |
| 7155695 | Signal shielding technique using active shields for non-interacting driver design
| February 6, 2002 |
| 7155693 | Floorplanning a hierarchical physical design to improve placement and routing
| April 23, 2004 |
| 7155684 | Integrated circuit device and method for forming the same
| June 30, 2004 |
| 7152217 | Alleviating timing based congestion within circuit designs
| April 20, 2004 |
| 7149995 | Graphical interface to layout processing components and connections
| June 25, 2004 |
| 7149666 | Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures
| May 30, 2002 |
| 7146597 | CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for executing the CAD method
| September 27, 2004 |
| 7146596 | Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid
| August 29, 2003 |
| 7146592 | Integrated logic circuit and hierarchical design method thereof
| January 26, 2005 |
| 7143389 | Systems and methods for generating node level bypass capacitor models
| July 28, 2004 |
| 7143385 | Wiring design method and system for electronic wiring boards
| March 19, 2004 |
| 7143384 | Methods of routing programmable logic devices to minimize programming time
| November 18, 2003 |
| 7143383 | Method for layout of gridless non manhattan integrated circuits with tile based router
| December 31, 2002 |
| 7143382 | Method and apparatus for storing routes
| January 4, 2002 |
| 7143378 | Method and apparatus for timing characterization of integrated circuit designs
| November 18, 2003 |
| 7143367 | Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information
| December 28, 2001 |
| 7139995 | Integration of a run-time parameterizable core with a static circuit design
| March 19, 2002 |
| 7139993 | Method and apparatus for routing differential signals across a semiconductor chip
| March 26, 2004 |
| 7139992 | Short path search using tiles and piecewise linear cost propagation
| November 30, 2001 |
| 7139991 | Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
| April 14, 2005 |
| 7137097 | Constraint-based global router for routing high performance designs
| June 25, 2004 |
| 7137096 | Interconnect structure of a chip and a configuration method thereof
| March 10, 2004 |
| 7137095 | Freeway routing system for a gate array
| February 15, 2002 |
| 7137094 | Method for reducing layers revision in engineering change order
| April 16, 2004 |
| 7134112 | Incremental routing in integrated circuit design
| July 21, 2003 |
| 7134109 | Parameter oriented graphical representation of hardware timing and triggering capabilities with contextual information
| February 10, 2003 |
| 7134108 | Method for checking an IC layout
| August 24, 2004 |
| 1 2 3 4 5 6 7 8 9 |