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Your search returned 767 patents.
( 716/11 in Current US Classification ) |
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| Patent ID | Title | Date Filed |
| 7139990 | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction
| March 23, 2004 |
| 7137094 | Method for reducing layers revision in engineering change order
| April 16, 2004 |
| 7137089 | Systems and methods for reducing IR-drop noise
| September 1, 2004 |
| 7134111 | Layout method and apparatus for arrangement of a via offset from a center axis of a conductor and semiconductor device thereof
| May 21, 2004 |
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