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| Patent ID | Title | Date Filed |
| 7168024 | Data processing system and method
| October 3, 2003 |
| 7168013 | Memory with element redundancy
| September 2, 2004 |
| 7164728 | Method and device for forming transport frames from coded-signal frames and device for extracting coded signal frames
| July 21, 2000 |
| 7162682 | Method of error control coding and decoding of messages in a packet-based data transmission system
| November 7, 2003 |
| 7162678 | Extended error correction codes
| March 14, 2003 |
| 7162677 | Device and method for coding data with a fire code
| August 27, 1999 |
| 7159139 | Digital data storage subsystem including directory for efficiently providing formatting information for stopped records and utilization of a check value for verifying that a record is from a particular storage location
| September 30, 2003 |
| 7158595 | Apparatus and method for acquiring frame synchronization in a mobile communication system
| April 3, 2002 |
| 7155659 | Error detection and correction circuit
| March 23, 2001 |
| 7155654 | Low complexity error concealment for wireless transmission
| May 10, 2003 |
| 7152198 | Encoding/decoding device and encoding/decoding method
| April 20, 2001 |
| 7149947 | Method of and system for validating an error correction code and parity information associated with a data word
| September 4, 2003 |
| 7149946 | Systems and methods for enhanced stored data verification utilizing pageable pool memory
| June 13, 2003 |
| 7149945 | Systems and methods for providing error correction code testing functionality
| May 9, 2003 |
| 7146557 | Encoding/decoding apparatus and method in a CDMA mobile communication system
| May 9, 2002 |
| 7143332 | Methods and structures for providing programmable width and error correction in memory arrays in programmable logic devices
| December 16, 2003 |
| 7143329 | FPGA configuration memory with built-in error correction mechanism
| March 9, 2004 |
| 7139964 | Variable modulation with LDPC (low density parity check) coding
| September 23, 2003 |
| 7139963 | Methods and apparatus to support error-checking of variable length data packets using a multi-stage process
| May 15, 2003 |
| 7139962 | System for encoding digital data and method of the same
| April 9, 2003 |
| 7137060 | Forward error correction apparatus and method in a high-speed data transmission system
| June 11, 2003 |
| 7137056 | Low error propagation rate 32/34 trellis code
| September 25, 2002 |
| 7136929 | Broadcast in a wireless communications system
| January 24, 2002 |
| 7131039 | Repair techniques for memory with multiple redundancy
| December 11, 2002 |
| 7127659 | Memory efficient LDPC decoding methods and apparatus
| August 2, 2004 |
| 7127443 | Adaptive turbo-coding and decoding
| March 9, 2001 |
| 7124351 | Software instructions utilizing a hardwired circuit
| December 4, 2003 |
| 7124346 | Apparatus for transmitting and receiving wireless data and method thereof
| February 15, 2001 |
| 7119712 | Data recovery scheme in thermometer system
| September 19, 2003 |
| 7117428 | Redundancy register architecture for soft-error tolerance and methods of making the same
| November 8, 2005 |
| 7117419 | Reliable communication between multi-processor clusters of multi-cluster computer systems
| August 5, 2003 |
| 7117323 | Cyclic redundancy checking for managing the coherency of mirrored storage volumes
| October 23, 2001 |
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