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| Patent ID | Title | Date Filed |
| 6868545 | Method for re-using system-on-chip verification software in an operating system
| January 31, 2000 |
| 6857090 | System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices
| October 9, 2001 |
| 6856950 | Abstract verification environment
| October 15, 1999 |
| 6845480 | Test pattern generator and test pattern generation
| January 28, 2002 |
| 6845479 | Method for testing for the presence of faults in digital circuits
| March 14, 2001 |
| 6836867 | Method of generating a pattern for testing a logic circuit and apparatus for doing the same
| September 13, 2001 |
| 6820047 | Method and system for simulating an operation of a memory
| September 11, 2000 |
| 6807647 | IC test system and storage medium for the same
| September 5, 2001 |
| 6795942 | Built-in redundancy analysis for memories with row and column repair
| July 6, 2000 |
| 6782518 | System and method for facilitating coverage feedback testcase generation reproducibility
| March 28, 2002 |
| 6782499 | Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium
| November 1, 2002 |
| 6766473 | Test pattern selection apparatus for selecting test pattern from a plurality of check patterns
| March 26, 2001 |
| 6728914 | Random path delay testing methodology
| December 22, 2000 |
| 6728667 | Multiple instantiation system
| October 20, 1998 |
| 6721676 | Testing of semiconductor device and a fabrication process of a semiconductor device including a testing process
| April 22, 1999 |
| 6718498 | Method and apparatus for the real time manipulation of a test vector to access the microprocessor state machine information using the integrated debug trigger
| June 4, 2001 |
| 6715119 | Test data generating system and method to test high-speed actual operation
| July 7, 2000 |
| 6708306 | Method for diagnosing failures using invariant analysis
| December 18, 2000 |
| 6704675 | Method of detecting an integrated circuit in failure among integrated circuits, apparatus of doing the same, and recording medium storing program for doing the same
| June 29, 2000 |
| 6698004 | Pin toggling using an object oriented programming language
| June 20, 2002 |
| 6697773 | Using assignment decision diagrams with control nodes for sequential review during behavioral simulation
| March 24, 1999 |
| 6691270 | Integrated circuit and method of operation of such a circuit employing serial test scan chains
| December 22, 2000 |
| 6684359 | System and method for test generation with dynamic constraints using static analysis
| March 6, 2001 |
| 6681357 | MISR simulation tool for memory BIST application
| May 31, 2001 |
| 6678645 | Method and apparatus for SoC design validation
| October 28, 1999 |
| 6675138 | System and method for measuring temporal coverage detection
| June 8, 1999 |
| 6671846 | Method of automatically generating schematic and waveform diagrams for isolating faults from multiple failing paths in a circuit using input signal predictors and transition times
| October 6, 2000 |
| 6662327 | Method for clustered test pattern generation
| May 13, 1999 |
| 6654919 | Automated system for inserting and reading of probe points in silicon embedded testbenches
| April 17, 2000 |
| 6651206 | Method of design for testability, test sequence generation method and semiconductor integrated circuit
| March 27, 2001 |
| 6636995 | Method of automatic latch insertion for testing application specific integrated circuits
| July 13, 2000 |
| 6631344 | Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation
| March 26, 1999 |
| 6625771 | Tool to reconfigure pin connections between a DUT and a tester
| March 22, 2001 |
| 6625770 | Method of automatically generating schematic and waveform diagrams for relevant logic cells of a circuit using input signal predictors and transition times
| June 20, 2000 |
| 6611936 | Programmable delay elements for source synchronous link function design verification through simulation
| April 28, 2000 |
| 6601205 | Method to descramble the data mapping in memory circuits
| September 29, 2000 |
| 6598191 | Verification of asynchronous boundary behavior
| November 23, 1999 |
| 6567961 | Method for detecting lack of synchronism in VLSI designs during high level simulation
| December 4, 2001 |
| 6567946 | Evaluation device of weighted fault coverage and evaluation method of the same
| March 22, 2000 |
| 6553514 | Digital circuit verification
| September 23, 1999 |
| 6546514 | Integrated circuit analysis and design involving defective circuit element replacement on a netlist
| December 13, 1999 |
| 6539498 | Method of detecting cause of failure in computer
| January 10, 2000 |
| 6499132 | System and method for analyzing temporal expressions
| June 15, 2001 |
| 6493841 | Method and apparatus for determining expected values during circuit design verification
| March 31, 1999 |
| 6484280 | Scan path test support
| September 30, 1999 |
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