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| Patent ID | Title | Date Filed |
| 7024598 | Nonvolatile semiconductor memory device with a fail bit detecting scheme and method for counting the number of fail bits
| October 30, 2001 |
| 7013416 | IC with expected data memory coupled to scan data register
| July 7, 2005 |
| 6996761 | IC with protocol selection memory coupled to serial scan path
| October 20, 2003 |
| 6988232 | Method and apparatus for optimized parallel testing and access of electronic circuits
| April 9, 2002 |
| 6983404 | Method and apparatus for checking the resistance of programmable elements
| February 5, 2001 |
| 6961880 | Recording test information to identify memory cell errors
| July 30, 2001 |
| 6948107 | Method and installation for fast fault localization in an integrated circuit
| May 10, 2001 |
| 6941498 | Technique for debugging an integrated circuit having a parallel scan-chain architecture
| March 7, 2002 |
| 6941494 | Built-in test for multiple memory circuits
| December 21, 2001 |
| 6934900 | Test pattern generator for SRAM and DRAM
| June 25, 2001 |
| 6912680 | Memory system with dynamic timing correction
| February 11, 1997 |
| 6901545 | Testing method for permanent electrical removal of an integrated circuit output after packaging
| February 11, 2003 |
| 6901542 | Internal cache for on chip test data storage
| August 9, 2001 |
| 6880120 | Sequence-based verification method and system
| January 18, 2001 |
| 6874111 | System initialization of microcode-based memory built-in self-test
| July 26, 2000 |
| 6857094 | Method and system for inferring fault propagation paths in combinational logic circuit
| February 12, 2002 |
| 6857092 | Method and apparatus to facilitate self-testing of a system on a chip
| May 25, 2001 |
| 6857089 | Differential receiver architecture
| May 9, 2001 |
| 6842712 | Method for testing an electronic component; computer program product, computer readable medium, and computer embodying the method; and method for downloading the program embodying the method
| May 8, 2003 |
| 6839648 | Systems for providing zero latency, non-modulo looping and branching of test pattern data for automatic test equipment
| May 1, 2003 |
| 6831588 | Range recognizer employing a single range internally partitioned by monotonically increasing boundary values
| September 17, 2002 |
| 6813740 | Method for the testing of electronic components
| October 19, 2000 |
| 6807646 | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test
| March 4, 2002 |
| 6802046 | Time domain measurement systems and methods
| May 1, 2002 |
| 6795944 | Testing regularly structured logic circuits in integrated circuit devices
| May 10, 2001 |
| 6789220 | Method and apparatus for vector processing
| May 3, 2001 |
| 6789219 | Arrangement and method of testing an integrated circuit
| August 7, 2001 |
| 6779139 | Circuit for reducing test time and semiconductor memory device including the circuit
| May 1, 2001 |
| 6772381 | Programmable logic device verification system and method
| January 17, 2002 |
| 6769082 | Delay device, semiconductor testing device, semiconductor device, and oscilloscope
| November 9, 1999 |
| 6766483 | Semiconductor test apparatus
| July 26, 2001 |
| 6766452 | Method of checking the authenticity of an electric circuit arrangement
| April 29, 1999 |
| 6762608 | Apparatus and method for testing fuses
| June 25, 2002 |
| 6754866 | Testing of integrated circuit devices
| September 28, 2001 |
| 6754865 | Integrated circuit
| December 15, 2000 |
| 6754861 | Circuitry for and system and substrate with circuitry for aligning output signals in massively parallel testers and other electronic devices
| June 6, 2002 |
| 6751766 | Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
| May 20, 2002 |
| 6742153 | Test configuration and method for testing a digital electronic filter
| July 21, 2000 |
| 6718276 | Method and apparatus for characterizing frequency response on an error performance analyzer
| November 29, 2000 |
| 6704904 | Method and apparatus for permuting code sequences and initial context of code sequences for improved electrical verification
| April 3, 2000 |
| 6697981 | System and method for evaluating the location of a failure in a logic circuit, and machine-readable recording medium having a recorded program
| January 29, 2001 |
| 6694464 | Method and apparatus for dynamically testing electrical interconnect
| October 23, 2000 |
| 6691271 | Built-in self-test apparatus
| June 9, 2000 |
| 6684357 | Chip testing apparatus and method
| December 13, 2000 |
| 6681361 | Semiconductor device inspection apparatus and semiconductor device inspection method
| May 5, 2000 |
| 6678645 | Method and apparatus for SoC design validation
| October 28, 1999 |
| 6671844 | Memory tester tests multiple DUT's per test site
| October 2, 2000 |
| 6662133 | JTAG-based software to perform cumulative array repair
| March 1, 2001 |
| 6654905 | Method and apparatus for detecting a fault condition in a computer processor
| April 19, 2000 |
| 6647524 | Built-in-self-test circuit for RAMBUS direct RDRAM
| April 30, 1999 |
| 6636996 | Method and apparatus for testing pipelined dynamic logic
| December 5, 2000 |
| 6615379 | Method and apparatus for testing a logic device
| December 8, 1999 |
| 6611935 | Method and system for efficiently testing circuitry
| August 31, 2000 |
| 6587983 | Apparatus and method of testing a semiconductor device
| April 3, 2000 |
| 6587976 | Semiconductor device tester for measuring skew between output pins of a semiconductor device
| December 3, 1999 |
| 6581018 | Multiplexer select line exclusivity check method and apparatus
| July 26, 2000 |
| 6578169 | Data failure memory compaction for semiconductor test system
| April 8, 2000 |
| 6571364 | Semiconductor integrated circuit device with fault analysis function
| December 9, 1999 |
| 6571363 | Single event upset tolerant microprocessor architecture
| December 15, 1999 |
| 6560724 | Random message verification technique
| September 29, 1999 |
| 6559671 | Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
| July 29, 2002 |
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