| 1 2 3 4 5 |
| Patent ID | Title | Date Filed |
| 7032151 | Systems and methods for testing integrated circuits
| November 13, 2002 |
| 7032148 | Mask network design for scan-based integrated circuits
| June 28, 2004 |
| 7032147 | Boundary scan circuit
| April 3, 2003 |
| 7032146 | Boundary scan apparatus and interconnect test method
| October 29, 2002 |
| 7028238 | Input/output characterization chain for an integrated circuit
| April 18, 2002 |
| 7024606 | Method of generating test pattern for integrated circuit
| December 16, 2003 |
| 7024346 | Automatic ATAP test bench generator
| May 17, 2000 |
| 7020819 | Semiconductor integrated circuit with local monitor circuits
| November 8, 2001 |
| 7020818 | Method and apparatus for PVT controller for programmable on die termination
| March 8, 2004 |
| 7010722 | Embedded symmetric multiprocessor system debug
| September 27, 2002 |
| 7003707 | IC tap/scan test port access with tap lock circuitry
| April 30, 2001 |
| 7000163 | Optimized buffering for JTAG boundary scan nets
| February 25, 2002 |
| 6999900 | Testing memory access signal connections
| March 30, 2004 |
| 6996758 | Apparatus for testing an interconnecting logic fabric
| November 16, 2001 |
| 6996032 | BIST circuit for measuring path delay in an IC
| July 28, 2003 |
| 6990618 | Boundary scan register for differential chip core
| December 3, 2002 |
| 6988230 | Test arrangement for assemblages of intergrated circuit blocks
| September 17, 2002 |
| 6988229 | Method and apparatus for monitoring and controlling boundary scan enabled devices
| February 11, 2002 |
| 6986090 | Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit
| February 20, 2002 |
| 6976200 | Semiconductor integrated circuit having bonding optional function
| November 20, 1998 |
| 6975980 | Hierarchical linking module connection to access ports of embedded cores
| June 14, 2002 |
| 6973606 | Partially distributed control mechanism for scanout incorporating flexible debug triggering
| December 28, 2000 |
| 6973588 | Disaster recovery port in a portable computer
| November 27, 2002 |
| 6964001 | On-chip service processor
| January 30, 2004 |
| 6961885 | System and method for testing video devices using a test fixture
| November 26, 2001 |
| 6954888 | Arithmetic built-in self-test of multiple scan-based integrated circuits
| February 10, 2004 |
| 6947884 | Scan interface with TDM feature for permitting signal overlay
| March 2, 2001 |
| 6938194 | Integrated circuit testing method and system
| February 26, 2002 |
| 6937493 | Programming flash memory via a boundary scan register
| September 24, 2003 |
| 6934898 | Test circuit topology reconfiguration and utilization techniques
| November 30, 2001 |
| 6915495 | Process and system for management of test access port (TAP) functions
| January 31, 2002 |
| 6909303 | Multichip module and testing method thereof
| July 18, 2003 |
| 6901544 | Scan chain testing of integrated circuits with hard-cores
| October 24, 2001 |
| 6900661 | Repairable finite state machines
| June 25, 2003 |
| 6895542 | Data recovery circuit and method and data receiving system using the same
| November 4, 2003 |
| 6886122 | Method for testing integrated circuits with memory element access
| January 25, 2002 |
| 6886117 | Field repairable embedded memory in system-on-a-chip
| November 20, 2001 |
| 6886110 | Multiple device scan chain emulation/debugging
| August 2, 2001 |
| 6883151 | Method and device for IC identification
| May 13, 2003 |
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