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| Patent ID | Title | Date Filed |
| 7110446 | Method and apparatus for reducing effect of jitter
| July 26, 2002 |
| 7107477 | Programmable logic devices with skewed clocking signals
| January 31, 2003 |
| 7107424 | Memory read strobe pulse optimization training system
| March 25, 2004 |
| 7103792 | Information processing system has clock lines which are electrically isolated from another clock line electrically connected to clock buffer and termination voltage
| December 16, 2002 |
| 7103791 | Interleaved delay line for phase locked and delay locked loops
| November 3, 2005 |
| 7100067 | Data transmission error reduction via automatic data sampling timing adjustment
| March 19, 2003 |
| 7100066 | Clock distribution device and method in compact PCI based multi-processing system
| December 27, 2002 |
| 7095817 | Method and apparatus for compensating for timing variances in digital data transmission channels
| May 3, 2002 |
| 7093150 | Wavefront clock synchronization
| December 30, 2002 |
| 7092478 | Local timer which is used in wireless LAN
| November 24, 2004 |
| 7089444 | Clock and data recovery circuits
| September 24, 2003 |
| 7089440 | Skew compensation for a multi-agent shared bus
| November 24, 2003 |
| 7085951 | Method for generating a signal pulse sequence with a predetermined stable fundamental frequency
| January 24, 2003 |
| 7085950 | Parallel data communication realignment of data sent in multiple groups
| September 28, 2001 |
| 7082175 | Method for controlled synchronization to an astable clock system, and reception unit corresponding thereto
| May 15, 2001 |
| 7076680 | Method and apparatus for providing skew compensation using a self-timed source-synchronous network
| June 10, 2003 |
| 7076678 | Method and apparatus for data transfer
| February 11, 2002 |
| 7073085 | Semiconductor circuit device
| July 2, 2003 |
| 7069463 | Bus clock controlling apparatus and method
| December 20, 2001 |
| 7069460 | Method and apparatus for image processing with an effective line noise correction
| March 15, 2002 |
| 7069459 | Clock skew reduction technique based on distributed process monitors
| March 10, 2003 |
| 7058840 | Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock
| May 10, 2002 |
| 7055050 | Network synchronization technique
| June 14, 2002 |
| 7051225 | Memory system, module and register
| April 30, 2003 |
| 7047384 | Method and apparatus for dynamic timing of memory interface signals
| June 27, 2002 |
| 7043657 | Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle
| October 8, 2003 |
| 7043656 | Methods and apparatus for extending a phase on an interconnect
| January 28, 2003 |
| 7043654 | Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal
| December 31, 2002 |
| 7043653 | Method and apparatus for synchronous signal transmission between at least two logic or memory components
| August 8, 2002 |
| 7043652 | Calibration method and memory system
| August 1, 2002 |
| 7036037 | Multi-bit deskewing of bus signals using a training pattern
| August 13, 2002 |
| 7032122 | Data transfer system capable of transferring data at high transfer speed
| June 17, 2003 |
| 7028210 | System and method for automatically correcting timers
| May 20, 2003 |
| 7028205 | Techniques to monitor transition density of an input signal
| July 25, 2002 |
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