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Your search returned 542 patents.
( 713/401 in Current US Classification ) |
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| Patent ID | Title | Date Filed |
| 7103694 | Method and apparatus implementing a tuned stub SCSI topology
| September 7, 2001 |
| 7098696 | Logic circuit and semiconductor integrated circuit
| July 23, 2004 |
| 7096376 | Device and method for ensuring that a signal always reaches its destination after a fixed number of clock cycles
| June 7, 2002 |
| 7096375 | Data transfer circuit between different clock regions
| November 19, 2002 |
| 7093150 | Wavefront clock synchronization
| December 30, 2002 |
| 7089440 | Skew compensation for a multi-agent shared bus
| November 24, 2003 |
| 7089439 | Architecture and method for output clock generation on a high speed memory device
| September 3, 2003 |
| 7089437 | Apparatus for determining power consumed by a bus of a digital signal processor using counted number of logic state transitions on bus
| August 1, 2001 |
| 7085948 | Method, apparatus, and computer program product for implementing time synchronization correction in computer systems
| April 24, 2003 |
| 7080275 | Method and apparatus using parasitic capacitance for synchronizing signals a device
| August 12, 2002 |
| 7076680 | Method and apparatus for providing skew compensation using a self-timed source-synchronous network
| June 10, 2003 |
| 7076678 | Method and apparatus for data transfer
| February 11, 2002 |
| 7076677 | Same edge strobing for source synchronous bus systems
| December 30, 2002 |
| 7075336 | Method for distributing clock signals to flip-flop circuits
| June 28, 2002 |
| 7073086 | System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit
| November 27, 2002 |
| 7073085 | Semiconductor circuit device
| July 2, 2003 |
| 7072433 | Delay locked loop fine tune
| July 11, 2001 |
| 7069459 | Clock skew reduction technique based on distributed process monitors
| March 10, 2003 |
| 7069458 | Parallel data interface and method for high-speed timing adjustment
| August 16, 2002 |
| 7064994 | Dynamic memory throttling for power and thermal limitations
| January 30, 2004 |
| 7064590 | Option for independently adjusting the timing of the forward and reverse direction of bi-directional digital signals
| August 30, 2002 |
| 7058837 | Method and system for providing a message-time-ordering facility
| May 12, 2003 |
| 7058799 | Apparatus and method for clock domain crossing with integrated decode
| June 19, 2001 |
| 7051225 | Memory system, module and register
| April 30, 2003 |
| 7051224 | Method and apparatus for configuring a clock timing feedback path
| March 18, 2002 |
| 7050512 | Receiver architecture
| January 8, 2001 |
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