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Your search returned 137 patents.
( 712/41 in Current US Classification ) |
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| Patent ID | Title | Date Filed |
| 5887160 | Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor
| December 17, 1996 |
| 5854939 | Eight-bit microcontroller having a risc architecture
| November 7, 1996 |
| 5826074 | Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
| November 22, 1996 |
| 5812845 | Method for generating an object code for a pipeline computer process to reduce swapping instruction set
| September 25, 1996 |
| 5805918 | Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set
| October 24, 1995 |
| 5802288 | Integrated communications for pipelined computers
| January 23, 1996 |
| 5790872 | Interrupt control handler for a RISC-type microprocessor
| September 18, 1997 |
| 5790822 | Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor
| March 21, 1996 |
| 5774710 | Cache line branch prediction scheme that shares among sets of a set associative cache
| September 19, 1996 |
| 5774709 | Enhanced branch delay slot handling with single exception program counter
| December 6, 1995 |
| 5764943 | Data path circuitry for processor having multiple instruction pipelines
| December 28, 1995 |
| 5761713 | Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank
| March 1, 1996 |
| 5761524 | Method and apparatus for performing and operation multiple times in response to a single instruction
| March 15, 1996 |
| 5761449 | Bus system providing dynamic control of pipeline depth for a multi-agent computer
| June 6, 1997 |
| 5751982 | Software emulation system with dynamic translation of emulated instructions for increased processing speed
| March 31, 1995 |
| 5748950 | Method and apparatus for providing an optimized compare-and-branch instruction
| March 20, 1997 |
| 5740461 | Data processing with multiple instruction sets
| October 22, 1996 |
| 5737625 | Selectable processing registers and method
| October 31, 1996 |
| 5732278 | Data memory and processor bus
| January 19, 1996 |
| 5713038 | Microprocessor having register file
| August 14, 1995 |
| 5713035 | Linking program access register number with millicode operand access
| March 31, 1995 |
| 5706459 | Processor having a variable number of stages in a pipeline
| December 30, 1994 |
| 5704054 | Counterflow pipeline processor architecture for semi-custom application specific IC's
| May 9, 1995 |
| 5685009 | Shared floating-point registers and register port-pairing in a dual-architecture CPU
| November 29, 1995 |
| 5682545 | Microcomputer having 16 bit fixed length instruction format
| June 7, 1995 |
| 5682493 | Scoreboard table for a counterflow pipeline processor with instruction packages and result packages
| August 26, 1995 |
| 5664215 | Data processor with an execution unit for performing load instructions and method of operation
| March 27, 1996 |
| 5664159 | Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register
| May 8, 1995 |
| 5659782 | System and method for handling load and/or store operations in a superscalar microprocessor
| September 16, 1994 |
| 5642523 | Microprocessor with variable size register windowing
| August 9, 1994 |
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