|
| | |
|
Your search returned 486 patents.
( 712/244 in Current US Classification ) |
|
|
| 1 2 3 4 5 |
| Patent ID | Title | Date Filed |
| 6934832 | Exception mechanism for a computer
| September 21, 2000 |
| 6934738 | Message processing apparatus
| March 10, 2000 |
| 6931635 | Program optimization
| October 29, 2001 |
| 6928582 | Method for fast exception handling
| January 4, 2002 |
| 6925591 | Method and apparatus for providing full accessibility to instruction cache and microcode ROM
| May 21, 2004 |
| 6925552 | Method and system with multiple exception handlers in a processor
| June 19, 2001 |
| 6920515 | Early exception detection
| March 29, 2001 |
| 6917608 | Microsequencer microcode bank switched architecture
| December 22, 2000 |
| 6910122 | Method and apparatus for preserving pipeline data during a pipeline stall and for recovering from the pipeline stall
| February 18, 2000 |
| 6904517 | Data processing apparatus and method for saving return state
| November 2, 2001 |
| 6898700 | Efficient saving and restoring state in task switching
| March 31, 1998 |
| 6895527 | Error recovery for speculative memory accesses
| September 30, 2000 |
| 6895460 | Synchronization of asynchronous emulated interrupts
| July 19, 2002 |
| 6892260 | Interrupt processing in a data processing system
| November 30, 2001 |
| 6889167 | Diagnostic exerciser and methods therefor
| February 27, 2003 |
| 6886094 | Apparatus and method for detecting and handling exceptions
| September 28, 2000 |
| 6880072 | Pipelined processor and method using a profile register storing the return from exception address of an executed instruction supplied by an exception program counter chain for code profiling
| May 8, 2001 |
| 6880071 | Selective signalling of later reserve location memory fault in compound compare and swap
| April 9, 2001 |
| 6874049 | Semaphores with interrupt mechanism
| February 1, 2002 |
| 6871173 | Method and apparatus for handling masked exceptions in an instruction interpreter
| September 13, 2000 |
| 6857064 | Method and apparatus for processing events in a multithreaded processor
| November 30, 2001 |
| 6845443 | Method of processing a repeat block efficiently in a processor wherein the repeat count is not decremented in a specific case to prevent error in execution
| December 29, 2000 |
| 6839834 | Microprocessor protected against parasitic interrupt signals
| April 3, 2001 |
| 6829719 | Method and apparatus for handling nested faults
| March 30, 2001 |
| 6829684 | Applications of operating mode dependent error signal generation upon real address range checking prior to translation
| June 20, 2002 |
| 6826682 | Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state
| June 26, 2000 |
| 6823448 | Exception handling using an exception pipeline in a pipelined processor
| December 15, 2000 |
| 6820190 | Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions
| February 2, 2000 |
| 6807628 | System and method for supporting precise exceptions in a data processor having a clustered architecture
| December 29, 2000 |
| 6807621 | Pipelined microprocessor and a method relating thereto
| September 27, 2001 |
| 6799269 | Virtual shadow registers and virtual register windows
| October 28, 2002 |
| 6792525 | Input replicator for interrupts in a simultaneous and redundantly threaded processor
| April 19, 2001 |
| 1 2 3 4 5 |
|
|
|
|
|
|
|
|
|
|
|